isa.hh revision 7393:8330b0b08daa
112952Sgabeblack@google.com/* 212952Sgabeblack@google.com * Copyright (c) 2010 ARM Limited 312952Sgabeblack@google.com * All rights reserved 412952Sgabeblack@google.com * 512952Sgabeblack@google.com * The license below extends only to copyright in the software and shall 612952Sgabeblack@google.com * not be construed as granting a license to any other intellectual 712952Sgabeblack@google.com * property including but not limited to intellectual property relating 812952Sgabeblack@google.com * to a hardware implementation of the functionality of the software 912952Sgabeblack@google.com * licensed hereunder. You may use the software subject to the license 1012952Sgabeblack@google.com * terms below provided that you ensure that this notice is replicated 1112952Sgabeblack@google.com * unmodified and in its entirety in all distributions of the software, 1212952Sgabeblack@google.com * modified or unmodified, in source code or in binary form. 1312952Sgabeblack@google.com * 1412952Sgabeblack@google.com * Copyright (c) 2009 The Regents of The University of Michigan 1512952Sgabeblack@google.com * All rights reserved. 1612952Sgabeblack@google.com * 1712952Sgabeblack@google.com * Redistribution and use in source and binary forms, with or without 1812952Sgabeblack@google.com * modification, are permitted provided that the following conditions are 1912952Sgabeblack@google.com * met: redistributions of source code must retain the above copyright 2012952Sgabeblack@google.com * notice, this list of conditions and the following disclaimer; 2112952Sgabeblack@google.com * redistributions in binary form must reproduce the above copyright 2212952Sgabeblack@google.com * notice, this list of conditions and the following disclaimer in the 2312952Sgabeblack@google.com * documentation and/or other materials provided with the distribution; 2412952Sgabeblack@google.com * neither the name of the copyright holders nor the names of its 2512952Sgabeblack@google.com * contributors may be used to endorse or promote products derived from 2612952Sgabeblack@google.com * this software without specific prior written permission. 2712952Sgabeblack@google.com * 2812952Sgabeblack@google.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2912952Sgabeblack@google.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3012952Sgabeblack@google.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3112957Sgabeblack@google.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3212957Sgabeblack@google.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3312957Sgabeblack@google.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3412953Sgabeblack@google.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3513196Sgabeblack@google.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3613102Sgabeblack@google.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3712998Sgabeblack@google.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3812998Sgabeblack@google.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3912952Sgabeblack@google.com * 4012952Sgabeblack@google.com * Authors: Gabe Black 4112952Sgabeblack@google.com */ 4212952Sgabeblack@google.com 4312952Sgabeblack@google.com#ifndef __ARCH_ARM_ISA_HH__ 4412952Sgabeblack@google.com#define __ARCH_MRM_ISA_HH__ 4512952Sgabeblack@google.com 4612995Sgabeblack@google.com#include "arch/arm/registers.hh" 4712952Sgabeblack@google.com#include "arch/arm/types.hh" 4812952Sgabeblack@google.com 4912952Sgabeblack@google.comclass ThreadContext; 5012952Sgabeblack@google.comclass Checkpoint; 5112952Sgabeblack@google.comclass EventManager; 5212995Sgabeblack@google.com 5312952Sgabeblack@google.comnamespace ArmISA 5412952Sgabeblack@google.com{ 5512952Sgabeblack@google.com class ISA 5612952Sgabeblack@google.com { 5712952Sgabeblack@google.com protected: 5812952Sgabeblack@google.com MiscReg miscRegs[NumMiscRegs]; 5912952Sgabeblack@google.com const IntRegIndex *intRegMap; 6012952Sgabeblack@google.com 6112952Sgabeblack@google.com void 6212952Sgabeblack@google.com updateRegMap(CPSR cpsr) 6312952Sgabeblack@google.com { 6412952Sgabeblack@google.com switch (cpsr.mode) { 6512952Sgabeblack@google.com case MODE_USER: 6612952Sgabeblack@google.com case MODE_SYSTEM: 6712952Sgabeblack@google.com intRegMap = IntRegUsrMap; 6812952Sgabeblack@google.com break; 6912952Sgabeblack@google.com case MODE_FIQ: 7012952Sgabeblack@google.com intRegMap = IntRegFiqMap; 7112952Sgabeblack@google.com break; 7212952Sgabeblack@google.com case MODE_IRQ: 7312952Sgabeblack@google.com intRegMap = IntRegIrqMap; 7412952Sgabeblack@google.com break; 7512952Sgabeblack@google.com case MODE_SVC: 7612952Sgabeblack@google.com intRegMap = IntRegSvcMap; 7712952Sgabeblack@google.com break; 7812952Sgabeblack@google.com case MODE_MON: 7912952Sgabeblack@google.com intRegMap = IntRegMonMap; 8012952Sgabeblack@google.com break; 8112952Sgabeblack@google.com case MODE_ABORT: 8212952Sgabeblack@google.com intRegMap = IntRegAbtMap; 8312952Sgabeblack@google.com break; 8412952Sgabeblack@google.com case MODE_UNDEFINED: 8513133Sgabeblack@google.com intRegMap = IntRegUndMap; 8612952Sgabeblack@google.com break; 8713133Sgabeblack@google.com default: 8813133Sgabeblack@google.com panic("Unrecognized mode setting in CPSR.\n"); 8913133Sgabeblack@google.com } 9013133Sgabeblack@google.com } 9113133Sgabeblack@google.com 9213133Sgabeblack@google.com public: 9313133Sgabeblack@google.com void clear() 9413133Sgabeblack@google.com { 9512952Sgabeblack@google.com memset(miscRegs, 0, sizeof(miscRegs)); 9612952Sgabeblack@google.com CPSR cpsr = 0; 9712952Sgabeblack@google.com cpsr.mode = MODE_USER; 9812952Sgabeblack@google.com miscRegs[MISCREG_CPSR] = cpsr; 9912952Sgabeblack@google.com updateRegMap(cpsr); 10012952Sgabeblack@google.com 10112952Sgabeblack@google.com SCTLR sctlr = 0; 10212952Sgabeblack@google.com sctlr.nmfi = 1; 10312952Sgabeblack@google.com sctlr.rao1 = 1; 10412952Sgabeblack@google.com sctlr.rao2 = 1; 10512952Sgabeblack@google.com sctlr.rao3 = 1; 10612959Sgabeblack@google.com sctlr.rao4 = 1; 10713133Sgabeblack@google.com miscRegs[MISCREG_SCTLR] = sctlr; 10812959Sgabeblack@google.com 10912952Sgabeblack@google.com /* 11012952Sgabeblack@google.com * Technically this should be 0, but we don't support those 11112952Sgabeblack@google.com * settings. 11212952Sgabeblack@google.com */ 11312952Sgabeblack@google.com CPACR cpacr = 0; 11412952Sgabeblack@google.com // Enable CP 10, 11 11512952Sgabeblack@google.com cpacr.cp10 = 0x3; 11612952Sgabeblack@google.com cpacr.cp11 = 0x3; 11712952Sgabeblack@google.com miscRegs[MISCREG_CPACR] = cpacr; 11812999Sgabeblack@google.com 11913206Sgabeblack@google.com /* Start with an event in the mailbox */ 12012999Sgabeblack@google.com miscRegs[MISCREG_SEV_MAILBOX] = 1; 12112999Sgabeblack@google.com 12212999Sgabeblack@google.com /* 12312999Sgabeblack@google.com * Implemented = '5' from "M5", 12412999Sgabeblack@google.com * Variant = 0, 12512999Sgabeblack@google.com */ 12612952Sgabeblack@google.com miscRegs[MISCREG_MIDR] = 12712952Sgabeblack@google.com (0x35 << 24) | //Implementor is '5' from "M5" 12812952Sgabeblack@google.com (0 << 20) | //Variant 12912952Sgabeblack@google.com (0xf << 16) | //Architecture from CPUID scheme 13012952Sgabeblack@google.com (0 << 4) | //Primary part number 13112952Sgabeblack@google.com (0 << 0) | //Revision 13212952Sgabeblack@google.com 0; 13312952Sgabeblack@google.com 13412952Sgabeblack@google.com // Separate Instruction and Data TLBs. 13512952Sgabeblack@google.com miscRegs[MISCREG_TLBTR] = 1; 13612952Sgabeblack@google.com 13712952Sgabeblack@google.com MVFR0 mvfr0 = 0; 13812952Sgabeblack@google.com mvfr0.advSimdRegisters = 2; 13912952Sgabeblack@google.com mvfr0.singlePrecision = 2; 14012952Sgabeblack@google.com mvfr0.doublePrecision = 2; 14112952Sgabeblack@google.com mvfr0.vfpExceptionTrapping = 0; 14213102Sgabeblack@google.com mvfr0.divide = 1; 14313102Sgabeblack@google.com mvfr0.squareRoot = 1; 14413102Sgabeblack@google.com mvfr0.shortVectors = 1; 14513102Sgabeblack@google.com mvfr0.roundingModes = 1; 14613102Sgabeblack@google.com miscRegs[MISCREG_MVFR0] = mvfr0; 14713102Sgabeblack@google.com 14812952Sgabeblack@google.com MVFR1 mvfr1 = 0; 14912952Sgabeblack@google.com mvfr1.flushToZero = 1; 15012952Sgabeblack@google.com mvfr1.defaultNaN = 1; 15112952Sgabeblack@google.com mvfr1.advSimdLoadStore = 1; 15212952Sgabeblack@google.com mvfr1.advSimdInteger = 1; 15312952Sgabeblack@google.com mvfr1.advSimdSinglePrecision = 1; 15412952Sgabeblack@google.com mvfr1.advSimdHalfPrecision = 1; 15512952Sgabeblack@google.com mvfr1.vfpHalfPrecision = 1; 15612995Sgabeblack@google.com miscRegs[MISCREG_MVFR1] = mvfr1; 15712998Sgabeblack@google.com 15812995Sgabeblack@google.com miscRegs[MISCREG_MPIDR] = 0; 15912995Sgabeblack@google.com 16012998Sgabeblack@google.com //XXX We need to initialize the rest of the state. 16112998Sgabeblack@google.com } 16212998Sgabeblack@google.com 16312998Sgabeblack@google.com MiscReg 16412998Sgabeblack@google.com readMiscRegNoEffect(int misc_reg) 16512998Sgabeblack@google.com { 16612952Sgabeblack@google.com assert(misc_reg < NumMiscRegs); 16712952Sgabeblack@google.com if (misc_reg == MISCREG_SPSR) { 16812952Sgabeblack@google.com CPSR cpsr = miscRegs[MISCREG_CPSR]; 16912952Sgabeblack@google.com switch (cpsr.mode) { 17012952Sgabeblack@google.com case MODE_USER: 17113102Sgabeblack@google.com return miscRegs[MISCREG_SPSR]; 17213102Sgabeblack@google.com case MODE_FIQ: 17313102Sgabeblack@google.com return miscRegs[MISCREG_SPSR_FIQ]; 17413102Sgabeblack@google.com case MODE_IRQ: 17513102Sgabeblack@google.com return miscRegs[MISCREG_SPSR_IRQ]; 17613102Sgabeblack@google.com case MODE_SVC: 17712952Sgabeblack@google.com return miscRegs[MISCREG_SPSR_SVC]; 17812952Sgabeblack@google.com case MODE_MON: 17912952Sgabeblack@google.com return miscRegs[MISCREG_SPSR_MON]; 18012952Sgabeblack@google.com case MODE_ABORT: 18112952Sgabeblack@google.com return miscRegs[MISCREG_SPSR_ABT]; 18212952Sgabeblack@google.com case MODE_UNDEFINED: 18312952Sgabeblack@google.com return miscRegs[MISCREG_SPSR_UND]; 18412952Sgabeblack@google.com default: 18512995Sgabeblack@google.com return miscRegs[MISCREG_SPSR]; 18613261Sgabeblack@google.com } 18713261Sgabeblack@google.com } 18812998Sgabeblack@google.com return miscRegs[misc_reg]; 18912998Sgabeblack@google.com } 19012998Sgabeblack@google.com 19112998Sgabeblack@google.com MiscReg 19212998Sgabeblack@google.com readMiscReg(int misc_reg, ThreadContext *tc) 19312998Sgabeblack@google.com { 19412952Sgabeblack@google.com if (misc_reg == MISCREG_CPSR) { 19512952Sgabeblack@google.com CPSR cpsr = miscRegs[misc_reg]; 19612952Sgabeblack@google.com Addr pc = tc->readPC(); 19712952Sgabeblack@google.com if (pc & (ULL(1) << PcJBitShift)) 19812952Sgabeblack@google.com cpsr.j = 1; 19913102Sgabeblack@google.com else 20013102Sgabeblack@google.com cpsr.j = 0; 20113102Sgabeblack@google.com if (pc & (ULL(1) << PcTBitShift)) 20213102Sgabeblack@google.com cpsr.t = 1; 20313102Sgabeblack@google.com else 20413102Sgabeblack@google.com cpsr.t = 0; 20512952Sgabeblack@google.com return cpsr; 20612952Sgabeblack@google.com } 20712998Sgabeblack@google.com if (misc_reg >= MISCREG_CP15_UNIMP_START && 20812998Sgabeblack@google.com misc_reg < MISCREG_CP15_END) { 20912998Sgabeblack@google.com panic("Unimplemented CP15 register %s read.\n", 21012998Sgabeblack@google.com miscRegName[misc_reg]); 21112952Sgabeblack@google.com } 21212952Sgabeblack@google.com switch (misc_reg) { 21312952Sgabeblack@google.com case MISCREG_CLIDR: 21412952Sgabeblack@google.com warn("The clidr register always reports 0 caches.\n"); 21512952Sgabeblack@google.com break; 21612952Sgabeblack@google.com case MISCREG_CCSIDR: 21712995Sgabeblack@google.com warn("The ccsidr register isn't implemented and " 21812952Sgabeblack@google.com "always reads as 0.\n"); 21912952Sgabeblack@google.com break; 22012952Sgabeblack@google.com } 22112952Sgabeblack@google.com return readMiscRegNoEffect(misc_reg); 22212952Sgabeblack@google.com } 22312952Sgabeblack@google.com 22412952Sgabeblack@google.com void 22512952Sgabeblack@google.com setMiscRegNoEffect(int misc_reg, const MiscReg &val) 22612952Sgabeblack@google.com { 22712952Sgabeblack@google.com assert(misc_reg < NumMiscRegs); 22812952Sgabeblack@google.com if (misc_reg == MISCREG_SPSR) { 22912952Sgabeblack@google.com CPSR cpsr = miscRegs[MISCREG_CPSR]; 23012952Sgabeblack@google.com switch (cpsr.mode) { 23112952Sgabeblack@google.com case MODE_USER: 23212952Sgabeblack@google.com miscRegs[MISCREG_SPSR] = val; 23312952Sgabeblack@google.com return; 23412952Sgabeblack@google.com case MODE_FIQ: 23512952Sgabeblack@google.com miscRegs[MISCREG_SPSR_FIQ] = val; 23612952Sgabeblack@google.com return; 23712952Sgabeblack@google.com case MODE_IRQ: 23812952Sgabeblack@google.com miscRegs[MISCREG_SPSR_IRQ] = val; 23913260Sgabeblack@google.com return; 24013260Sgabeblack@google.com case MODE_SVC: 24113260Sgabeblack@google.com miscRegs[MISCREG_SPSR_SVC] = val; 24213260Sgabeblack@google.com return; 24313260Sgabeblack@google.com case MODE_MON: 24413260Sgabeblack@google.com miscRegs[MISCREG_SPSR_MON] = val; 24513260Sgabeblack@google.com return; 24613260Sgabeblack@google.com case MODE_ABORT: 24713260Sgabeblack@google.com miscRegs[MISCREG_SPSR_ABT] = val; 24813260Sgabeblack@google.com return; 24913260Sgabeblack@google.com case MODE_UNDEFINED: 25013260Sgabeblack@google.com miscRegs[MISCREG_SPSR_UND] = val; 25113260Sgabeblack@google.com return; 25213260Sgabeblack@google.com default: 25313260Sgabeblack@google.com miscRegs[MISCREG_SPSR] = val; 25413260Sgabeblack@google.com return; 25513260Sgabeblack@google.com } 25613260Sgabeblack@google.com } 25713260Sgabeblack@google.com miscRegs[misc_reg] = val; 25813260Sgabeblack@google.com } 25913260Sgabeblack@google.com 26012953Sgabeblack@google.com void 26112952Sgabeblack@google.com setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 26212953Sgabeblack@google.com { 26312953Sgabeblack@google.com MiscReg newVal = val; 26412953Sgabeblack@google.com if (misc_reg == MISCREG_CPSR) { 26512953Sgabeblack@google.com updateRegMap(val); 26612953Sgabeblack@google.com CPSR cpsr = val; 26713175Sgabeblack@google.com DPRINTF(Arm, "Updating CPSR to %#x f:%d i:%d a:%d mode:%#x\n", 26813175Sgabeblack@google.com cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 26912995Sgabeblack@google.com Addr npc = tc->readNextPC() & ~PcModeMask; 27012953Sgabeblack@google.com if (cpsr.j) 27112995Sgabeblack@google.com npc = npc | (ULL(1) << PcJBitShift); 27213182Sgabeblack@google.com if (cpsr.t) 27313182Sgabeblack@google.com npc = npc | (ULL(1) << PcTBitShift); 27412953Sgabeblack@google.com 27512953Sgabeblack@google.com tc->setNextPC(npc); 27613093Sgabeblack@google.com } 27712953Sgabeblack@google.com if (misc_reg >= MISCREG_CP15_UNIMP_START && 27812952Sgabeblack@google.com misc_reg < MISCREG_CP15_END) { 27912957Sgabeblack@google.com panic("Unimplemented CP15 register %s wrote with %#x.\n", 28013206Sgabeblack@google.com miscRegName[misc_reg], val); 28112957Sgabeblack@google.com } 28213206Sgabeblack@google.com switch (misc_reg) { 28312957Sgabeblack@google.com case MISCREG_CPACR: 28412957Sgabeblack@google.com { 28512957Sgabeblack@google.com CPACR newCpacr = 0; 28613206Sgabeblack@google.com CPACR valCpacr = val; 28712957Sgabeblack@google.com newCpacr.cp10 = valCpacr.cp10; 28813206Sgabeblack@google.com newCpacr.cp11 = valCpacr.cp11; 28913206Sgabeblack@google.com if (newCpacr.cp10 != 0x3 || newCpacr.cp11 != 3) { 29013206Sgabeblack@google.com panic("Disabling coprocessors isn't implemented.\n"); 29113206Sgabeblack@google.com } 29212957Sgabeblack@google.com newVal = newCpacr; 29313206Sgabeblack@google.com } 29413206Sgabeblack@google.com break; 29513206Sgabeblack@google.com case MISCREG_CSSELR: 29613260Sgabeblack@google.com warn("The csselr register isn't implemented.\n"); 29713260Sgabeblack@google.com break; 29813260Sgabeblack@google.com case MISCREG_FPSCR: 29913260Sgabeblack@google.com { 30013260Sgabeblack@google.com const uint32_t ones = (uint32_t)(-1); 30113260Sgabeblack@google.com FPSCR fpscrMask = 0; 30213206Sgabeblack@google.com fpscrMask.ioc = ones; 30313206Sgabeblack@google.com fpscrMask.dzc = ones; 30413206Sgabeblack@google.com fpscrMask.ofc = ones; 30513206Sgabeblack@google.com fpscrMask.ufc = ones; 30613206Sgabeblack@google.com fpscrMask.ixc = ones; 30713206Sgabeblack@google.com fpscrMask.idc = ones; 30813206Sgabeblack@google.com fpscrMask.len = ones; 30913206Sgabeblack@google.com fpscrMask.stride = ones; 31013206Sgabeblack@google.com fpscrMask.rMode = ones; 31113206Sgabeblack@google.com fpscrMask.fz = ones; 31213206Sgabeblack@google.com fpscrMask.dn = ones; 31313206Sgabeblack@google.com fpscrMask.ahp = ones; 31413206Sgabeblack@google.com fpscrMask.qc = ones; 31513206Sgabeblack@google.com fpscrMask.v = ones; 31613206Sgabeblack@google.com fpscrMask.c = ones; 31713206Sgabeblack@google.com fpscrMask.z = ones; 31813206Sgabeblack@google.com fpscrMask.n = ones; 31913206Sgabeblack@google.com newVal = (newVal & (uint32_t)fpscrMask) | 32013206Sgabeblack@google.com (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask); 32113206Sgabeblack@google.com } 32213206Sgabeblack@google.com break; 32313206Sgabeblack@google.com case MISCREG_FPEXC: 32413206Sgabeblack@google.com { 32513206Sgabeblack@google.com const uint32_t fpexcMask = 0x60000000; 32613206Sgabeblack@google.com newVal = (newVal & fpexcMask) | 32712957Sgabeblack@google.com (miscRegs[MISCREG_FPEXC] & ~fpexcMask); 32812957Sgabeblack@google.com } 32912959Sgabeblack@google.com break; 33012959Sgabeblack@google.com case MISCREG_TLBTR: 33112959Sgabeblack@google.com case MISCREG_MVFR0: 33213260Sgabeblack@google.com case MISCREG_MVFR1: 33313260Sgabeblack@google.com case MISCREG_MPIDR: 33413260Sgabeblack@google.com case MISCREG_FPSID: 33513260Sgabeblack@google.com return; 33613260Sgabeblack@google.com } 33712959Sgabeblack@google.com return setMiscRegNoEffect(misc_reg, newVal); 33813206Sgabeblack@google.com } 33913206Sgabeblack@google.com 34012959Sgabeblack@google.com int 34113206Sgabeblack@google.com flattenIntIndex(int reg) 34212959Sgabeblack@google.com { 34313206Sgabeblack@google.com assert(reg >= 0); 34413206Sgabeblack@google.com if (reg < NUM_ARCH_INTREGS) { 34513206Sgabeblack@google.com return intRegMap[reg]; 34613206Sgabeblack@google.com } else if (reg < NUM_INTREGS) { 34713206Sgabeblack@google.com return reg; 34813206Sgabeblack@google.com } else { 34912959Sgabeblack@google.com int mode = reg / intRegsPerMode; 35012959Sgabeblack@google.com reg = reg % intRegsPerMode; 35112959Sgabeblack@google.com switch (mode) { 35212959Sgabeblack@google.com case MODE_USER: 35312959Sgabeblack@google.com case MODE_SYSTEM: 35412959Sgabeblack@google.com return INTREG_USR(reg); 35512996Sgabeblack@google.com case MODE_FIQ: 35612996Sgabeblack@google.com return INTREG_FIQ(reg); 35712959Sgabeblack@google.com case MODE_IRQ: 35812959Sgabeblack@google.com return INTREG_IRQ(reg); 35912959Sgabeblack@google.com case MODE_SVC: 36012959Sgabeblack@google.com return INTREG_SVC(reg); 36112959Sgabeblack@google.com case MODE_MON: 36212959Sgabeblack@google.com return INTREG_MON(reg); 36312997Sgabeblack@google.com case MODE_ABORT: 36412997Sgabeblack@google.com return INTREG_ABT(reg); 36512997Sgabeblack@google.com case MODE_UNDEFINED: 36612997Sgabeblack@google.com return INTREG_UND(reg); 36712997Sgabeblack@google.com default: 36812997Sgabeblack@google.com panic("Flattening into an unknown mode.\n"); 36912997Sgabeblack@google.com } 37012997Sgabeblack@google.com } 37112997Sgabeblack@google.com } 37212997Sgabeblack@google.com 37312997Sgabeblack@google.com int 37412997Sgabeblack@google.com flattenFloatIndex(int reg) 37512997Sgabeblack@google.com { 37613180Sgabeblack@google.com return reg; 37713206Sgabeblack@google.com } 37813206Sgabeblack@google.com 37913206Sgabeblack@google.com void serialize(EventManager *em, std::ostream &os) 38013194Sgabeblack@google.com {} 38113260Sgabeblack@google.com void unserialize(EventManager *em, Checkpoint *cp, 38213260Sgabeblack@google.com const std::string §ion) 38313189Sgabeblack@google.com {} 38412953Sgabeblack@google.com 38513131Sgabeblack@google.com ISA() 38613131Sgabeblack@google.com { 38713131Sgabeblack@google.com clear(); 38812953Sgabeblack@google.com } 38912953Sgabeblack@google.com }; 39012952Sgabeblack@google.com} 39112998Sgabeblack@google.com 39212998Sgabeblack@google.com#endif 39312998Sgabeblack@google.com