isa.hh revision 7287:25c1718b819a
12810SN/A/* 22810SN/A * Copyright (c) 2010 ARM Limited 32810SN/A * All rights reserved 42810SN/A * 52810SN/A * The license below extends only to copyright in the software and shall 62810SN/A * not be construed as granting a license to any other intellectual 72810SN/A * property including but not limited to intellectual property relating 82810SN/A * to a hardware implementation of the functionality of the software 92810SN/A * licensed hereunder. You may use the software subject to the license 102810SN/A * terms below provided that you ensure that this notice is replicated 112810SN/A * unmodified and in its entirety in all distributions of the software, 122810SN/A * modified or unmodified, in source code or in binary form. 132810SN/A * 142810SN/A * Copyright (c) 2009 The Regents of The University of Michigan 152810SN/A * All rights reserved. 162810SN/A * 172810SN/A * Redistribution and use in source and binary forms, with or without 182810SN/A * modification, are permitted provided that the following conditions are 192810SN/A * met: redistributions of source code must retain the above copyright 202810SN/A * notice, this list of conditions and the following disclaimer; 212810SN/A * redistributions in binary form must reproduce the above copyright 222810SN/A * notice, this list of conditions and the following disclaimer in the 232810SN/A * documentation and/or other materials provided with the distribution; 242810SN/A * neither the name of the copyright holders nor the names of its 252810SN/A * contributors may be used to endorse or promote products derived from 262810SN/A * this software without specific prior written permission. 272810SN/A * 282810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 294458SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 304458SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810SN/A * 402810SN/A * Authors: Gabe Black 417676Snate@binkert.org */ 427676Snate@binkert.org 437676Snate@binkert.org#ifndef __ARCH_ARM_ISA_HH__ 442810SN/A#define __ARCH_MRM_ISA_HH__ 452810SN/A 462825SN/A#include "arch/arm/registers.hh" 472810SN/A#include "arch/arm/types.hh" 482810SN/A 496215Snate@binkert.orgclass ThreadContext; 506978SLisa.Hsu@amd.comclass Checkpoint; 518232Snate@binkert.orgclass EventManager; 528232Snate@binkert.org 535338Sstever@gmail.comnamespace ArmISA 542810SN/A{ 552810SN/A class ISA 568229Snate@binkert.org { 574626SN/A protected: 585034SN/A MiscReg miscRegs[NumMiscRegs]; 592811SN/A const IntRegIndex *intRegMap; 604626SN/A 612810SN/A void 623194SN/A updateRegMap(CPSR cpsr) 632810SN/A { 642810SN/A switch (cpsr.mode) { 652810SN/A case MODE_USER: 662810SN/A case MODE_SYSTEM: 672810SN/A intRegMap = IntRegUsrMap; 684628SN/A break; 694628SN/A case MODE_FIQ: 704628SN/A intRegMap = IntRegFiqMap; 714628SN/A break; 724628SN/A case MODE_IRQ: 734628SN/A intRegMap = IntRegIrqMap; 744628SN/A break; 754628SN/A case MODE_SVC: 768737Skoansin.tan@gmail.com intRegMap = IntRegSvcMap; 774628SN/A break; 784628SN/A case MODE_MON: 794628SN/A intRegMap = IntRegMonMap; 804628SN/A break; 814628SN/A case MODE_ABORT: 824628SN/A intRegMap = IntRegAbtMap; 834628SN/A break; 844628SN/A case MODE_UNDEFINED: 854628SN/A intRegMap = IntRegUndMap; 864628SN/A break; 874628SN/A default: 884628SN/A panic("Unrecognized mode setting in CPSR.\n"); 894628SN/A } 904628SN/A } 914628SN/A 924628SN/A public: 934628SN/A void clear() 944628SN/A { 954628SN/A memset(miscRegs, 0, sizeof(miscRegs)); 964628SN/A CPSR cpsr = 0; 978737Skoansin.tan@gmail.com cpsr.mode = MODE_USER; 984628SN/A miscRegs[MISCREG_CPSR] = cpsr; 994626SN/A updateRegMap(cpsr); 1002810SN/A 1012844SN/A SCTLR sctlr = 0; 1022810SN/A sctlr.nmfi = 1; 1032810SN/A sctlr.rao1 = 1; 1043738SN/A sctlr.rao2 = 1; 1054965SN/A sctlr.rao3 = 1; 1066122SSteve.Reinhardt@amd.com sctlr.rao4 = 1; 1074458SN/A miscRegs[MISCREG_SCTLR] = sctlr; 1086227Snate@binkert.org 1092810SN/A /* 1104458SN/A * Technically this should be 0, but we don't support those 1113013SN/A * settings. 1124666SN/A */ 1134666SN/A miscRegs[MISCREG_CPACR] = 0x0fffffff; 1144666SN/A 1155314SN/A //XXX We need to initialize the rest of the state. 1165314SN/A } 1172811SN/A 1182810SN/A MiscReg 1192810SN/A readMiscRegNoEffect(int misc_reg) 1202810SN/A { 1212810SN/A assert(misc_reg < NumMiscRegs); 1225314SN/A if (misc_reg == MISCREG_SPSR) { 1233606SN/A CPSR cpsr = miscRegs[MISCREG_CPSR]; 1242810SN/A switch (cpsr.mode) { 1252810SN/A case MODE_USER: 1262897SN/A return miscRegs[MISCREG_SPSR]; 1272897SN/A case MODE_FIQ: 1284458SN/A return miscRegs[MISCREG_SPSR_FIQ]; 1294458SN/A case MODE_IRQ: 1304888SN/A return miscRegs[MISCREG_SPSR_IRQ]; 1314666SN/A case MODE_SVC: 1324666SN/A return miscRegs[MISCREG_SPSR_SVC]; 1334458SN/A case MODE_MON: 1344458SN/A return miscRegs[MISCREG_SPSR_MON]; 1354458SN/A case MODE_ABORT: 1364626SN/A return miscRegs[MISCREG_SPSR_ABT]; 1374626SN/A case MODE_UNDEFINED: 1384626SN/A return miscRegs[MISCREG_SPSR_UND]; 1392811SN/A default: 1402810SN/A return miscRegs[MISCREG_SPSR]; 1413338SN/A } 1423738SN/A } 1433338SN/A return miscRegs[misc_reg]; 1444626SN/A } 1454626SN/A 1464626SN/A MiscReg 1474626SN/A readMiscReg(int misc_reg, ThreadContext *tc) 1484626SN/A { 1494626SN/A if (misc_reg == MISCREG_CPSR) { 1504626SN/A CPSR cpsr = miscRegs[misc_reg]; 1514626SN/A Addr pc = tc->readPC(); 1524628SN/A if (pc & (ULL(1) << PcJBitShift)) 1534628SN/A cpsr.j = 1; 1544628SN/A else 1554666SN/A cpsr.j = 0; 1564628SN/A if (pc & (ULL(1) << PcTBitShift)) 1574628SN/A cpsr.t = 1; 1584628SN/A else 1594628SN/A cpsr.t = 0; 1604628SN/A return cpsr; 1614628SN/A } 1624628SN/A if (misc_reg >= MISCREG_CP15_UNIMP_START && 1634628SN/A misc_reg < MISCREG_CP15_END) { 1644628SN/A panic("Unimplemented CP15 register %s read.\n", 1654628SN/A miscRegName[misc_reg]); 1664628SN/A } 1674628SN/A switch (misc_reg) { 1687667Ssteve.reinhardt@amd.com case MISCREG_CLIDR: 1694628SN/A warn("The clidr register always reports 0 caches.\n"); 1704628SN/A break; 1714628SN/A case MISCREG_CCSIDR: 1727667Ssteve.reinhardt@amd.com warn("The ccsidr register isn't implemented and " 1734628SN/A "always reads as 0.\n"); 1744628SN/A break; 1754628SN/A } 1764628SN/A return readMiscRegNoEffect(misc_reg); 1774628SN/A } 1784626SN/A 1796227Snate@binkert.org void 1804626SN/A setMiscRegNoEffect(int misc_reg, const MiscReg &val) 1814630SN/A { 1824630SN/A assert(misc_reg < NumMiscRegs); 1834630SN/A if (misc_reg == MISCREG_SPSR) { 1844630SN/A CPSR cpsr = miscRegs[MISCREG_CPSR]; 1854630SN/A switch (cpsr.mode) { 1864626SN/A case MODE_USER: 1874626SN/A miscRegs[MISCREG_SPSR] = val; 1884626SN/A return; 1896122SSteve.Reinhardt@amd.com case MODE_FIQ: 1906122SSteve.Reinhardt@amd.com miscRegs[MISCREG_SPSR_FIQ] = val; 1914626SN/A return; 1928134SAli.Saidi@ARM.com case MODE_IRQ: 1938134SAli.Saidi@ARM.com miscRegs[MISCREG_SPSR_IRQ] = val; 1948134SAli.Saidi@ARM.com return; 1958134SAli.Saidi@ARM.com case MODE_SVC: 1968134SAli.Saidi@ARM.com miscRegs[MISCREG_SPSR_SVC] = val; 1972810SN/A return; 1982810SN/A case MODE_MON: 1992810SN/A miscRegs[MISCREG_SPSR_MON] = val; 2002810SN/A return; 2012810SN/A case MODE_ABORT: 2022810SN/A miscRegs[MISCREG_SPSR_ABT] = val; 2036122SSteve.Reinhardt@amd.com return; 2046122SSteve.Reinhardt@amd.com case MODE_UNDEFINED: 2056122SSteve.Reinhardt@amd.com miscRegs[MISCREG_SPSR_UND] = val; 2062810SN/A return; 2072810SN/A default: 2082810SN/A miscRegs[MISCREG_SPSR] = val; 2094626SN/A return; 2104626SN/A } 2112810SN/A } 2122810SN/A miscRegs[misc_reg] = val; 2132810SN/A } 2142810SN/A 2153503SN/A void 2163503SN/A setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 2173503SN/A { 2186122SSteve.Reinhardt@amd.com MiscReg newVal = val; 2196122SSteve.Reinhardt@amd.com if (misc_reg == MISCREG_CPSR) { 2206122SSteve.Reinhardt@amd.com updateRegMap(val); 2216122SSteve.Reinhardt@amd.com CPSR cpsr = val; 2226122SSteve.Reinhardt@amd.com Addr npc = tc->readNextPC() & ~PcModeMask; 2236978SLisa.Hsu@amd.com if (cpsr.j) 2246978SLisa.Hsu@amd.com npc = npc | (ULL(1) << PcJBitShift); 2256978SLisa.Hsu@amd.com if (cpsr.t) 2262810SN/A npc = npc | (ULL(1) << PcTBitShift); 2276978SLisa.Hsu@amd.com 2282810SN/A tc->setNextPC(npc); 2292810SN/A } 2302810SN/A if (misc_reg >= MISCREG_CP15_UNIMP_START && 2312810SN/A misc_reg < MISCREG_CP15_END) { 2322810SN/A panic("Unimplemented CP15 register %s wrote with %#x.\n", 2332810SN/A miscRegName[misc_reg], val); 2342810SN/A } 2355999Snate@binkert.org switch (misc_reg) { 2362810SN/A case MISCREG_CPACR: 2372810SN/A newVal = bits(val, 27, 0); 2382810SN/A if (newVal != 0x0fffffff) { 2392810SN/A panic("Disabling coprocessors isn't implemented.\n"); 2402810SN/A } 2412810SN/A break; 2425999Snate@binkert.org case MISCREG_CSSELR: 2432810SN/A warn("The csselr register isn't implemented.\n"); 2442810SN/A break; 2452810SN/A } 2462810SN/A return setMiscRegNoEffect(misc_reg, newVal); 2472810SN/A } 2482810SN/A 2492810SN/A int 2502810SN/A flattenIntIndex(int reg) 2512810SN/A { 2525999Snate@binkert.org assert(reg >= 0); 2532810SN/A if (reg < NUM_ARCH_INTREGS) { 2542810SN/A return intRegMap[reg]; 2552810SN/A } else if (reg < NUM_INTREGS) { 2562810SN/A return reg; 2572810SN/A } else { 2582810SN/A reg -= NUM_INTREGS; 2594022SN/A assert(reg < NUM_ARCH_INTREGS); 2602810SN/A return reg; 2612810SN/A } 2622810SN/A } 2632810SN/A 2642810SN/A int 2652810SN/A flattenFloatIndex(int reg) 2664022SN/A { 2672810SN/A return reg; 2682810SN/A } 2692810SN/A 2702810SN/A void serialize(EventManager *em, std::ostream &os) 2712810SN/A {} 2722810SN/A void unserialize(EventManager *em, Checkpoint *cp, 2734022SN/A const std::string §ion) 2742810SN/A {} 2752810SN/A 2762810SN/A ISA() 2772810SN/A { 2782810SN/A clear(); 2792810SN/A } 2805999Snate@binkert.org }; 2812810SN/A} 2825999Snate@binkert.org 2832810SN/A#endif 2842810SN/A