isa.hh revision 6806 
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_ARM_ISA_HH__
32#define __ARCH_MRM_ISA_HH__
33
34#include "arch/arm/registers.hh"
35#include "arch/arm/types.hh"
36
37class ThreadContext;
38class Checkpoint;
39class EventManager;
40
41namespace ArmISA
42{
43    class ISA
44    {
45      protected:
46        MiscReg miscRegs[NumMiscRegs];
47        const IntRegIndex *intRegMap;
48
49        void
50        updateRegMap(CPSR cpsr)
51        {
52            switch (cpsr.mode) {
53              case MODE_USER:
54              case MODE_SYSTEM:
55                intRegMap = IntRegUsrMap;
56                break;
57              case MODE_FIQ:
58                intRegMap = IntRegFiqMap;
59                break;
60              case MODE_IRQ:
61                intRegMap = IntRegIrqMap;
62                break;
63              case MODE_SVC:
64                intRegMap = IntRegSvcMap;
65                break;
66              case MODE_MON:
67                intRegMap = IntRegMonMap;
68                break;
69              case MODE_ABORT:
70                intRegMap = IntRegAbtMap;
71                break;
72              case MODE_UNDEFINED:
73                intRegMap = IntRegUndMap;
74                break;
75              default:
76                panic("Unrecognized mode setting in CPSR.\n");
77            }
78        }
79
80      public:
81        void clear()
82        {
83            memset(miscRegs, 0, sizeof(miscRegs));
84            CPSR cpsr = 0;
85            cpsr.mode = MODE_USER;
86            miscRegs[MISCREG_CPSR] = cpsr;
87            updateRegMap(cpsr);
88
89            SCTLR sctlr = 0;
90            sctlr.nmfi = 1;
91            sctlr.rao1 = 1;
92            sctlr.rao2 = 1;
93            sctlr.rao3 = 1;
94            sctlr.rao4 = 1;
95
96            //XXX We need to initialize the rest of the state.
97        }
98
99        MiscReg
100        readMiscRegNoEffect(int misc_reg)
101        {
102            assert(misc_reg < NumMiscRegs);
103            if (misc_reg == MISCREG_SPSR) {
104                CPSR cpsr = miscRegs[MISCREG_CPSR];
105                switch (cpsr.mode) {
106                  case MODE_USER:
107                    return miscRegs[MISCREG_SPSR];
108                  case MODE_FIQ:
109                    return miscRegs[MISCREG_SPSR_FIQ];
110                  case MODE_IRQ:
111                    return miscRegs[MISCREG_SPSR_IRQ];
112                  case MODE_SVC:
113                    return miscRegs[MISCREG_SPSR_SVC];
114                  case MODE_MON:
115                    return miscRegs[MISCREG_SPSR_MON];
116                  case MODE_ABORT:
117                    return miscRegs[MISCREG_SPSR_ABT];
118                  case MODE_UNDEFINED:
119                    return miscRegs[MISCREG_SPSR_UND];
120                  default:
121                    return miscRegs[MISCREG_SPSR];
122                }
123            }
124            return miscRegs[misc_reg];
125        }
126
127        MiscReg
128        readMiscReg(int misc_reg, ThreadContext *tc)
129        {
130            return readMiscRegNoEffect(misc_reg);
131        }
132
133        void
134        setMiscRegNoEffect(int misc_reg, const MiscReg &val)
135        {
136            assert(misc_reg < NumMiscRegs);
137            if (misc_reg == MISCREG_SPSR) {
138                CPSR cpsr = miscRegs[MISCREG_CPSR];
139                switch (cpsr.mode) {
140                  case MODE_USER:
141                    miscRegs[MISCREG_SPSR] = val;
142                    return;
143                  case MODE_FIQ:
144                    miscRegs[MISCREG_SPSR_FIQ] = val;
145                    return;
146                  case MODE_IRQ:
147                    miscRegs[MISCREG_SPSR_IRQ] = val;
148                    return;
149                  case MODE_SVC:
150                    miscRegs[MISCREG_SPSR_SVC] = val;
151                    return;
152                  case MODE_MON:
153                    miscRegs[MISCREG_SPSR_MON] = val;
154                    return;
155                  case MODE_ABORT:
156                    miscRegs[MISCREG_SPSR_ABT] = val;
157                    return;
158                  case MODE_UNDEFINED:
159                    miscRegs[MISCREG_SPSR_UND] = val;
160                    return;
161                  default:
162                    miscRegs[MISCREG_SPSR] = val;
163                    return;
164                }
165            }
166            miscRegs[misc_reg] = val;
167        }
168
169        void
170        setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
171        {
172            if (misc_reg == MISCREG_CPSR) {
173                updateRegMap(val);
174            }
175            return setMiscRegNoEffect(misc_reg, val);
176        }
177
178        int
179        flattenIntIndex(int reg)
180        {
181            assert(reg >= 0);
182            if (reg < NUM_ARCH_INTREGS) {
183                return intRegMap[reg];
184            } else if (reg < NUM_INTREGS) {
185                return reg;
186            } else {
187                reg -= NUM_INTREGS;
188                assert(reg < NUM_ARCH_INTREGS);
189                return reg;
190            }
191        }
192
193        int
194        flattenFloatIndex(int reg)
195        {
196            return reg;
197        }
198
199        void serialize(EventManager *em, std::ostream &os)
200        {}
201        void unserialize(EventManager *em, Checkpoint *cp,
202                const std::string &section)
203        {}
204
205        ISA()
206        {
207            clear();
208        }
209    };
210}
211
212#endif
213