isa.hh revision 6745:cdc62b81747e
112SN/A/* 21762SN/A * Copyright (c) 2009 The Regents of The University of Michigan 312SN/A * All rights reserved. 412SN/A * 512SN/A * Redistribution and use in source and binary forms, with or without 612SN/A * modification, are permitted provided that the following conditions are 712SN/A * met: redistributions of source code must retain the above copyright 812SN/A * notice, this list of conditions and the following disclaimer; 912SN/A * redistributions in binary form must reproduce the above copyright 1012SN/A * notice, this list of conditions and the following disclaimer in the 1112SN/A * documentation and/or other materials provided with the distribution; 1212SN/A * neither the name of the copyright holders nor the names of its 1312SN/A * contributors may be used to endorse or promote products derived from 1412SN/A * this software without specific prior written permission. 1512SN/A * 1612SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1712SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1812SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1912SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2012SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2112SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2212SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2312SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2412SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2512SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2612SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Gabe Black 2912SN/A */ 3012SN/A 3112SN/A#ifndef __ARCH_ARM_ISA_HH__ 3212SN/A#define __ARCH_MRM_ISA_HH__ 3356SN/A 348229Snate@binkert.org#include "arch/arm/registers.hh" 3556SN/A#include "arch/arm/types.hh" 367676Snate@binkert.org 378232Snate@binkert.orgclass ThreadContext; 3812SN/Aclass Checkpoint; 3912SN/Aclass EventManager; 4012SN/A 4112SN/Anamespace ArmISA 4212SN/A{ 4312SN/A class ISA 4412SN/A { 45360SN/A protected: 46360SN/A MiscReg miscRegs[NumMiscRegs]; 47360SN/A const IntRegIndex *intRegMap; 4812SN/A 4912SN/A void 5012SN/A updateRegMap(CPSR cpsr) 5112SN/A { 5212SN/A switch (cpsr.mode) { 5312SN/A case MODE_USER: 5412SN/A case MODE_SYSTEM: 5512SN/A intRegMap = IntRegUsrMap; 56360SN/A break; 57360SN/A case MODE_FIQ: 58360SN/A intRegMap = IntRegFiqMap; 5912SN/A break; 6012SN/A case MODE_IRQ: 6112SN/A intRegMap = IntRegIrqMap; 6212SN/A break; 6312SN/A case MODE_SVC: 6412SN/A intRegMap = IntRegSvcMap; 6512SN/A break; 662420SN/A case MODE_MON: 6712SN/A intRegMap = IntRegMonMap; 6812SN/A break; 6912SN/A case MODE_ABORT: 702420SN/A intRegMap = IntRegAbtMap; 7112SN/A break; 7212SN/A case MODE_UNDEFINED: 7312SN/A intRegMap = IntRegUndMap; 742420SN/A break; 7512SN/A default: 7612SN/A panic("Unrecognized mode setting in CPSR.\n"); 7712SN/A } 7812SN/A } 7912SN/A 8012SN/A public: 8112SN/A void clear() 8212SN/A { 833812Ssaidi@eecs.umich.edu memset(miscRegs, 0, sizeof(miscRegs)); 8412SN/A CPSR cpsr = 0; 8512SN/A cpsr.mode = MODE_USER; 8612SN/A miscRegs[MISCREG_CPSR] = cpsr; 8712SN/A updateRegMap(cpsr); 8812SN/A 8912SN/A SCTLR sctlr = 0; 903812Ssaidi@eecs.umich.edu sctlr.nmfi = 1; 9112SN/A sctlr.rao1 = 1; 9212SN/A sctlr.rao2 = 1; 9312SN/A sctlr.rao3 = 1; 9412SN/A sctlr.rao4 = 1; 95 96 //XXX We need to initialize the rest of the state. 97 } 98 99 MiscReg 100 readMiscRegNoEffect(int misc_reg) 101 { 102 assert(misc_reg < NumMiscRegs); 103 if (misc_reg == MISCREG_SPSR) { 104 CPSR cpsr = miscRegs[MISCREG_CPSR]; 105 switch (cpsr.mode) { 106 case MODE_USER: 107 return miscRegs[MISCREG_SPSR]; 108 case MODE_FIQ: 109 return miscRegs[MISCREG_SPSR_FIQ]; 110 case MODE_IRQ: 111 return miscRegs[MISCREG_SPSR_IRQ]; 112 case MODE_SVC: 113 return miscRegs[MISCREG_SPSR_SVC]; 114 case MODE_MON: 115 return miscRegs[MISCREG_SPSR_MON]; 116 case MODE_ABORT: 117 return miscRegs[MISCREG_SPSR_ABT]; 118 case MODE_UNDEFINED: 119 return miscRegs[MISCREG_SPSR_UND]; 120 default: 121 return miscRegs[MISCREG_SPSR]; 122 } 123 } 124 return miscRegs[misc_reg]; 125 } 126 127 MiscReg 128 readMiscReg(int misc_reg, ThreadContext *tc) 129 { 130 return readMiscRegNoEffect(misc_reg); 131 } 132 133 void 134 setMiscRegNoEffect(int misc_reg, const MiscReg &val) 135 { 136 assert(misc_reg < NumMiscRegs); 137 if (misc_reg == MISCREG_SPSR) { 138 CPSR cpsr = miscRegs[MISCREG_CPSR]; 139 switch (cpsr.mode) { 140 case MODE_USER: 141 miscRegs[MISCREG_SPSR] = val; 142 return; 143 case MODE_FIQ: 144 miscRegs[MISCREG_SPSR_FIQ] = val; 145 return; 146 case MODE_IRQ: 147 miscRegs[MISCREG_SPSR_IRQ] = val; 148 return; 149 case MODE_SVC: 150 miscRegs[MISCREG_SPSR_SVC] = val; 151 return; 152 case MODE_MON: 153 miscRegs[MISCREG_SPSR_MON] = val; 154 return; 155 case MODE_ABORT: 156 miscRegs[MISCREG_SPSR_ABT] = val; 157 return; 158 case MODE_UNDEFINED: 159 miscRegs[MISCREG_SPSR_UND] = val; 160 return; 161 default: 162 miscRegs[MISCREG_SPSR] = val; 163 return; 164 } 165 } 166 miscRegs[misc_reg] = val; 167 } 168 169 void 170 setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 171 { 172 if (misc_reg == MISCREG_CPSR) { 173 updateRegMap(val); 174 } 175 return setMiscRegNoEffect(misc_reg, val); 176 } 177 178 int 179 flattenIntIndex(int reg) 180 { 181 assert(reg >= 0); 182 if (reg < NUM_ARCH_INTREGS) { 183 return intRegMap[reg]; 184 } else if (reg < NUM_INTREGS) { 185 return reg; 186 } else { 187 reg -= NUM_INTREGS; 188 assert(reg < NUM_ARCH_INTREGS); 189 return reg; 190 } 191 } 192 193 int 194 flattenFloatIndex(int reg) 195 { 196 return reg; 197 } 198 199 void serialize(EventManager *em, std::ostream &os) 200 {} 201 void unserialize(EventManager *em, Checkpoint *cp, 202 const std::string §ion) 203 {} 204 205 ISA() 206 { 207 clear(); 208 } 209 }; 210} 211 212#endif 213