isa.hh revision 6723:ea7c71a3433a 
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_ARM_ISA_HH__
32#define __ARCH_MRM_ISA_HH__
33
34#include "arch/arm/registers.hh"
35#include "arch/arm/types.hh"
36
37class ThreadContext;
38class Checkpoint;
39class EventManager;
40
41namespace ArmISA
42{
43    class ISA
44    {
45      protected:
46        MiscReg miscRegs[NumMiscRegs];
47        const IntRegIndex *intRegMap;
48
49        void
50        updateRegMap(CPSR cpsr)
51        {
52            switch (cpsr.mode) {
53              case MODE_USER:
54              case MODE_SYSTEM:
55                intRegMap = IntRegUsrMap;
56                break;
57              case MODE_FIQ:
58                intRegMap = IntRegFiqMap;
59                break;
60              case MODE_IRQ:
61                intRegMap = IntRegIrqMap;
62                break;
63              case MODE_SVC:
64                intRegMap = IntRegSvcMap;
65                break;
66              case MODE_MON:
67                intRegMap = IntRegMonMap;
68                break;
69              case MODE_ABORT:
70                intRegMap = IntRegAbtMap;
71                break;
72              case MODE_UNDEFINED:
73                intRegMap = IntRegUndMap;
74                break;
75              default:
76                panic("Unrecognized mode setting in CPSR.\n");
77            }
78        }
79
80      public:
81        void clear()
82        {
83            memset(miscRegs, 0, sizeof(miscRegs));
84            CPSR cpsr = 0;
85            cpsr.mode = MODE_USER;
86            miscRegs[MISCREG_CPSR] = cpsr;
87            updateRegMap(cpsr);
88            //XXX We need to initialize the rest of the state.
89        }
90
91        MiscReg
92        readMiscRegNoEffect(int misc_reg)
93        {
94            assert(misc_reg < NumMiscRegs);
95            return miscRegs[misc_reg];
96        }
97
98        MiscReg
99        readMiscReg(int misc_reg, ThreadContext *tc)
100        {
101            assert(misc_reg < NumMiscRegs);
102            return miscRegs[misc_reg];
103        }
104
105        void
106        setMiscRegNoEffect(int misc_reg, const MiscReg &val)
107        {
108            assert(misc_reg < NumMiscRegs);
109            miscRegs[misc_reg] = val;
110        }
111
112        void
113        setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
114        {
115            if (misc_reg == MISCREG_CPSR) {
116                updateRegMap(val);
117            }
118            assert(misc_reg < NumMiscRegs);
119            miscRegs[misc_reg] = val;
120        }
121
122        int
123        flattenIntIndex(int reg)
124        {
125            assert(reg >= 0);
126            if (reg < NUM_ARCH_INTREGS) {
127                return intRegMap[reg];
128            } else {
129                assert(reg < NUM_INTREGS);
130                return reg;
131            }
132        }
133
134        int
135        flattenFloatIndex(int reg)
136        {
137            return reg;
138        }
139
140        void serialize(EventManager *em, std::ostream &os)
141        {}
142        void unserialize(EventManager *em, Checkpoint *cp,
143                const std::string &section)
144        {}
145
146        ISA()
147        {
148            clear();
149        }
150    };
151}
152
153#endif
154