isa.hh revision 13601:f5c84915eb7f
17139Sgblack@eecs.umich.edu/* 27139Sgblack@eecs.umich.edu * Copyright (c) 2010, 2012-2018 ARM Limited 37139Sgblack@eecs.umich.edu * All rights reserved 47139Sgblack@eecs.umich.edu * 57139Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67139Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77139Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87139Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97139Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107139Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117139Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127139Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137139Sgblack@eecs.umich.edu * 147139Sgblack@eecs.umich.edu * Copyright (c) 2009 The Regents of The University of Michigan 157139Sgblack@eecs.umich.edu * All rights reserved. 167139Sgblack@eecs.umich.edu * 177139Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 187139Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 197139Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 207139Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 217139Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 227139Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 237139Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 247139Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 257139Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 267139Sgblack@eecs.umich.edu * this software without specific prior written permission. 277139Sgblack@eecs.umich.edu * 287139Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 297139Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 307139Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 317139Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 327139Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 337139Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 347139Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 357139Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 367139Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 377139Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 387139Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 397188Sgblack@eecs.umich.edu * 407188Sgblack@eecs.umich.edu * Authors: Gabe Black 417188Sgblack@eecs.umich.edu */ 427188Sgblack@eecs.umich.edu 437188Sgblack@eecs.umich.edu#ifndef __ARCH_ARM_ISA_HH__ 447139Sgblack@eecs.umich.edu#define __ARCH_ARM_ISA_HH__ 457139Sgblack@eecs.umich.edu 467139Sgblack@eecs.umich.edu#include "arch/arm/isa_device.hh" 477139Sgblack@eecs.umich.edu#include "arch/arm/miscregs.hh" 487188Sgblack@eecs.umich.edu#include "arch/arm/registers.hh" 497188Sgblack@eecs.umich.edu#include "arch/arm/system.hh" 507188Sgblack@eecs.umich.edu#include "arch/arm/tlb.hh" 517188Sgblack@eecs.umich.edu#include "arch/arm/types.hh" 527188Sgblack@eecs.umich.edu#include "arch/generic/traits.hh" 537188Sgblack@eecs.umich.edu#include "debug/Checkpoint.hh" 547139Sgblack@eecs.umich.edu#include "enums/VecRegRenameMode.hh" 557146Sgblack@eecs.umich.edu#include "sim/sim_object.hh" 567141Sgblack@eecs.umich.edu#include "enums/DecoderFlavour.hh" 577139Sgblack@eecs.umich.edu 587139Sgblack@eecs.umich.edustruct ArmISAParams; 597139Sgblack@eecs.umich.edustruct DummyArmISADeviceParams; 607146Sgblack@eecs.umich.educlass ThreadContext; 617141Sgblack@eecs.umich.educlass Checkpoint; 627139Sgblack@eecs.umich.educlass EventManager; 637146Sgblack@eecs.umich.edu 647141Sgblack@eecs.umich.edunamespace ArmISA 657139Sgblack@eecs.umich.edu{ 667139Sgblack@eecs.umich.edu class ISA : public SimObject 677139Sgblack@eecs.umich.edu { 687139Sgblack@eecs.umich.edu protected: 697139Sgblack@eecs.umich.edu // Parent system 707188Sgblack@eecs.umich.edu ArmSystem *system; 717188Sgblack@eecs.umich.edu 727188Sgblack@eecs.umich.edu // Micro Architecture 737188Sgblack@eecs.umich.edu const Enums::DecoderFlavour _decoderFlavour; 747188Sgblack@eecs.umich.edu const Enums::VecRegRenameMode _vecRegRenameMode; 757188Sgblack@eecs.umich.edu 767188Sgblack@eecs.umich.edu /** Dummy device for to handle non-existing ISA devices */ 777188Sgblack@eecs.umich.edu DummyISADevice dummyDevice; 787188Sgblack@eecs.umich.edu 797188Sgblack@eecs.umich.edu // PMU belonging to this ISA 807188Sgblack@eecs.umich.edu BaseISADevice *pmu; 817188Sgblack@eecs.umich.edu 827188Sgblack@eecs.umich.edu // Generic timer interface belonging to this ISA 837188Sgblack@eecs.umich.edu std::unique_ptr<BaseISADevice> timer; 847188Sgblack@eecs.umich.edu 857188Sgblack@eecs.umich.edu // GICv3 CPU interface belonging to this ISA 867188Sgblack@eecs.umich.edu std::unique_ptr<BaseISADevice> gicv3CpuInterface; 877188Sgblack@eecs.umich.edu 887188Sgblack@eecs.umich.edu // Cached copies of system-level properties 897188Sgblack@eecs.umich.edu bool highestELIs64; 907139Sgblack@eecs.umich.edu bool haveSecurity; 917139Sgblack@eecs.umich.edu bool haveLPAE; 927139Sgblack@eecs.umich.edu bool haveVirtualization; 937139Sgblack@eecs.umich.edu bool haveCrypto; 947139Sgblack@eecs.umich.edu bool haveLargeAsid64; 957139Sgblack@eecs.umich.edu bool haveGICv3CPUInterface; 967139Sgblack@eecs.umich.edu uint8_t physAddrRange; 977139Sgblack@eecs.umich.edu 987139Sgblack@eecs.umich.edu /** 997139Sgblack@eecs.umich.edu * If true, accesses to IMPLEMENTATION DEFINED registers are treated 1007139Sgblack@eecs.umich.edu * as NOP hence not causing UNDEFINED INSTRUCTION. 1017139Sgblack@eecs.umich.edu */ 1027139Sgblack@eecs.umich.edu bool impdefAsNop; 1037139Sgblack@eecs.umich.edu 1047139Sgblack@eecs.umich.edu /** MiscReg metadata **/ 1057139Sgblack@eecs.umich.edu struct MiscRegLUTEntry { 1067139Sgblack@eecs.umich.edu uint32_t lower; // Lower half mapped to this register 1077139Sgblack@eecs.umich.edu uint32_t upper; // Upper half mapped to this register 1087139Sgblack@eecs.umich.edu uint64_t _reset; // value taken on reset (i.e. initialization) 1097139Sgblack@eecs.umich.edu uint64_t _res0; // reserved 1107139Sgblack@eecs.umich.edu uint64_t _res1; // reserved 1117188Sgblack@eecs.umich.edu uint64_t _raz; // read as zero (fixed at 0) 1127188Sgblack@eecs.umich.edu uint64_t _rao; // read as one (fixed at 1) 1137188Sgblack@eecs.umich.edu public: 1147188Sgblack@eecs.umich.edu MiscRegLUTEntry() : 1157139Sgblack@eecs.umich.edu lower(0), upper(0), 1167188Sgblack@eecs.umich.edu _reset(0), _res0(0), _res1(0), _raz(0), _rao(0) {} 1177139Sgblack@eecs.umich.edu uint64_t reset() const { return _reset; } 1187188Sgblack@eecs.umich.edu uint64_t res0() const { return _res0; } 1197139Sgblack@eecs.umich.edu uint64_t res1() const { return _res1; } 1207139Sgblack@eecs.umich.edu uint64_t raz() const { return _raz; } 1217139Sgblack@eecs.umich.edu uint64_t rao() const { return _rao; } 1227139Sgblack@eecs.umich.edu // raz/rao implies writes ignored 1237139Sgblack@eecs.umich.edu uint64_t wi() const { return _raz | _rao; } 1247139Sgblack@eecs.umich.edu }; 1257139Sgblack@eecs.umich.edu 1267139Sgblack@eecs.umich.edu /** Metadata table accessible via the value of the register */ 1277210Sgblack@eecs.umich.edu static std::vector<struct MiscRegLUTEntry> lookUpMiscReg; 1287210Sgblack@eecs.umich.edu 1297210Sgblack@eecs.umich.edu class MiscRegLUTEntryInitializer { 1307210Sgblack@eecs.umich.edu struct MiscRegLUTEntry &entry; 1317210Sgblack@eecs.umich.edu std::bitset<NUM_MISCREG_INFOS> &info; 1327210Sgblack@eecs.umich.edu typedef const MiscRegLUTEntryInitializer& chain; 1337210Sgblack@eecs.umich.edu public: 1347210Sgblack@eecs.umich.edu chain mapsTo(uint32_t l, uint32_t u = 0) const { 1357210Sgblack@eecs.umich.edu entry.lower = l; 1367210Sgblack@eecs.umich.edu entry.upper = u; 1377210Sgblack@eecs.umich.edu return *this; 1387210Sgblack@eecs.umich.edu } 1397210Sgblack@eecs.umich.edu chain res0(uint64_t mask) const { 1407210Sgblack@eecs.umich.edu entry._res0 = mask; 1417210Sgblack@eecs.umich.edu return *this; 1427210Sgblack@eecs.umich.edu } 1437210Sgblack@eecs.umich.edu chain res1(uint64_t mask) const { 1447210Sgblack@eecs.umich.edu entry._res1 = mask; 1457210Sgblack@eecs.umich.edu return *this; 1467210Sgblack@eecs.umich.edu } 1477210Sgblack@eecs.umich.edu chain raz(uint64_t mask) const { 1487210Sgblack@eecs.umich.edu entry._raz = mask; 1497210Sgblack@eecs.umich.edu return *this; 1507210Sgblack@eecs.umich.edu } 1517210Sgblack@eecs.umich.edu chain rao(uint64_t mask) const { 1527210Sgblack@eecs.umich.edu entry._rao = mask; 1537210Sgblack@eecs.umich.edu return *this; 1547210Sgblack@eecs.umich.edu } 1557210Sgblack@eecs.umich.edu chain implemented(bool v = true) const { 1567210Sgblack@eecs.umich.edu info[MISCREG_IMPLEMENTED] = v; 1577210Sgblack@eecs.umich.edu return *this; 1587210Sgblack@eecs.umich.edu } 1597210Sgblack@eecs.umich.edu chain unimplemented() const { 1607210Sgblack@eecs.umich.edu return implemented(false); 1617210Sgblack@eecs.umich.edu } 1627210Sgblack@eecs.umich.edu chain unverifiable(bool v = true) const { 1637210Sgblack@eecs.umich.edu info[MISCREG_UNVERIFIABLE] = v; 1647210Sgblack@eecs.umich.edu return *this; 1657210Sgblack@eecs.umich.edu } 1667210Sgblack@eecs.umich.edu chain warnNotFail(bool v = true) const { 1677210Sgblack@eecs.umich.edu info[MISCREG_WARN_NOT_FAIL] = v; 1687211Sgblack@eecs.umich.edu return *this; 1697211Sgblack@eecs.umich.edu } 1707211Sgblack@eecs.umich.edu chain mutex(bool v = true) const { 1717210Sgblack@eecs.umich.edu info[MISCREG_MUTEX] = v; 1727210Sgblack@eecs.umich.edu return *this; 1737210Sgblack@eecs.umich.edu } 1747210Sgblack@eecs.umich.edu chain banked(bool v = true) const { 1757210Sgblack@eecs.umich.edu info[MISCREG_BANKED] = v; 1767210Sgblack@eecs.umich.edu return *this; 1777210Sgblack@eecs.umich.edu } 1787211Sgblack@eecs.umich.edu chain bankedChild(bool v = true) const { 1797211Sgblack@eecs.umich.edu info[MISCREG_BANKED_CHILD] = v; 1807211Sgblack@eecs.umich.edu return *this; 1817210Sgblack@eecs.umich.edu } 1827210Sgblack@eecs.umich.edu chain userNonSecureRead(bool v = true) const { 1837210Sgblack@eecs.umich.edu info[MISCREG_USR_NS_RD] = v; 1847210Sgblack@eecs.umich.edu return *this; 1857210Sgblack@eecs.umich.edu } 1867210Sgblack@eecs.umich.edu chain userNonSecureWrite(bool v = true) const { 1877210Sgblack@eecs.umich.edu info[MISCREG_USR_NS_WR] = v; 1887210Sgblack@eecs.umich.edu return *this; 1897210Sgblack@eecs.umich.edu } 1907210Sgblack@eecs.umich.edu chain userSecureRead(bool v = true) const { 1917210Sgblack@eecs.umich.edu info[MISCREG_USR_S_RD] = v; 1927210Sgblack@eecs.umich.edu return *this; 1937210Sgblack@eecs.umich.edu } 1947210Sgblack@eecs.umich.edu chain userSecureWrite(bool v = true) const { 1957210Sgblack@eecs.umich.edu info[MISCREG_USR_S_WR] = v; 1967210Sgblack@eecs.umich.edu return *this; 1977210Sgblack@eecs.umich.edu } 1987210Sgblack@eecs.umich.edu chain user(bool v = true) const { 1997210Sgblack@eecs.umich.edu userNonSecureRead(v); 2007210Sgblack@eecs.umich.edu userNonSecureWrite(v); 2017210Sgblack@eecs.umich.edu userSecureRead(v); 2027210Sgblack@eecs.umich.edu userSecureWrite(v); 2037210Sgblack@eecs.umich.edu return *this; 2047210Sgblack@eecs.umich.edu } 2057210Sgblack@eecs.umich.edu chain privNonSecureRead(bool v = true) const { 2067210Sgblack@eecs.umich.edu info[MISCREG_PRI_NS_RD] = v; 2077210Sgblack@eecs.umich.edu return *this; 2087210Sgblack@eecs.umich.edu } 2097210Sgblack@eecs.umich.edu chain privNonSecureWrite(bool v = true) const { 2107210Sgblack@eecs.umich.edu info[MISCREG_PRI_NS_WR] = v; 2117210Sgblack@eecs.umich.edu return *this; 2127210Sgblack@eecs.umich.edu } 2137211Sgblack@eecs.umich.edu chain privNonSecure(bool v = true) const { 2147211Sgblack@eecs.umich.edu privNonSecureRead(v); 2157211Sgblack@eecs.umich.edu privNonSecureWrite(v); 2167210Sgblack@eecs.umich.edu return *this; 2177210Sgblack@eecs.umich.edu } 2187210Sgblack@eecs.umich.edu chain privSecureRead(bool v = true) const { 2197210Sgblack@eecs.umich.edu info[MISCREG_PRI_S_RD] = v; 2207210Sgblack@eecs.umich.edu return *this; 2217210Sgblack@eecs.umich.edu } 2227210Sgblack@eecs.umich.edu chain privSecureWrite(bool v = true) const { 2237210Sgblack@eecs.umich.edu info[MISCREG_PRI_S_WR] = v; 2247194Sgblack@eecs.umich.edu return *this; 2257194Sgblack@eecs.umich.edu } 2267194Sgblack@eecs.umich.edu chain privSecure(bool v = true) const { 2277194Sgblack@eecs.umich.edu privSecureRead(v); 2287194Sgblack@eecs.umich.edu privSecureWrite(v); 2297194Sgblack@eecs.umich.edu return *this; 2307194Sgblack@eecs.umich.edu } 2317194Sgblack@eecs.umich.edu chain priv(bool v = true) const { 2327194Sgblack@eecs.umich.edu privSecure(v); 2337194Sgblack@eecs.umich.edu privNonSecure(v); 2347194Sgblack@eecs.umich.edu return *this; 2357194Sgblack@eecs.umich.edu } 2367194Sgblack@eecs.umich.edu chain privRead(bool v = true) const { 2377194Sgblack@eecs.umich.edu privSecureRead(v); 2387194Sgblack@eecs.umich.edu privNonSecureRead(v); 2397194Sgblack@eecs.umich.edu return *this; 2407194Sgblack@eecs.umich.edu } 2417194Sgblack@eecs.umich.edu chain hypRead(bool v = true) const { 2427194Sgblack@eecs.umich.edu info[MISCREG_HYP_RD] = v; 2437194Sgblack@eecs.umich.edu return *this; 2447194Sgblack@eecs.umich.edu } 2457194Sgblack@eecs.umich.edu chain hypWrite(bool v = true) const { 2467194Sgblack@eecs.umich.edu info[MISCREG_HYP_WR] = v; 2477194Sgblack@eecs.umich.edu return *this; 2487194Sgblack@eecs.umich.edu } 2497194Sgblack@eecs.umich.edu chain hyp(bool v = true) const { 2507194Sgblack@eecs.umich.edu hypRead(v); 2517194Sgblack@eecs.umich.edu hypWrite(v); 2527194Sgblack@eecs.umich.edu return *this; 2537194Sgblack@eecs.umich.edu } 2547194Sgblack@eecs.umich.edu chain monSecureRead(bool v = true) const { 2557194Sgblack@eecs.umich.edu info[MISCREG_MON_NS0_RD] = v; 2567194Sgblack@eecs.umich.edu return *this; 2577194Sgblack@eecs.umich.edu } 2587194Sgblack@eecs.umich.edu chain monSecureWrite(bool v = true) const { 2597194Sgblack@eecs.umich.edu info[MISCREG_MON_NS0_WR] = v; 2607194Sgblack@eecs.umich.edu return *this; 2617194Sgblack@eecs.umich.edu } 2627194Sgblack@eecs.umich.edu chain monNonSecureRead(bool v = true) const { 2637194Sgblack@eecs.umich.edu info[MISCREG_MON_NS1_RD] = v; 2647194Sgblack@eecs.umich.edu return *this; 2657194Sgblack@eecs.umich.edu } 2667194Sgblack@eecs.umich.edu chain monNonSecureWrite(bool v = true) const { 2677194Sgblack@eecs.umich.edu info[MISCREG_MON_NS1_WR] = v; 2687194Sgblack@eecs.umich.edu return *this; 2697194Sgblack@eecs.umich.edu } 2707194Sgblack@eecs.umich.edu chain mon(bool v = true) const { 2717194Sgblack@eecs.umich.edu monSecureRead(v); 2727194Sgblack@eecs.umich.edu monSecureWrite(v); 2737194Sgblack@eecs.umich.edu monNonSecureRead(v); 2747194Sgblack@eecs.umich.edu monNonSecureWrite(v); 2757194Sgblack@eecs.umich.edu return *this; 2767194Sgblack@eecs.umich.edu } 2777194Sgblack@eecs.umich.edu chain monSecure(bool v = true) const { 2787194Sgblack@eecs.umich.edu monSecureRead(v); 2797194Sgblack@eecs.umich.edu monSecureWrite(v); 2807194Sgblack@eecs.umich.edu return *this; 2817194Sgblack@eecs.umich.edu } 2827194Sgblack@eecs.umich.edu chain monNonSecure(bool v = true) const { 2837194Sgblack@eecs.umich.edu monNonSecureRead(v); 2847194Sgblack@eecs.umich.edu monNonSecureWrite(v); 2857194Sgblack@eecs.umich.edu return *this; 2867194Sgblack@eecs.umich.edu } 2877194Sgblack@eecs.umich.edu chain allPrivileges(bool v = true) const { 2887194Sgblack@eecs.umich.edu userNonSecureRead(v); 2897194Sgblack@eecs.umich.edu userNonSecureWrite(v); 2907194Sgblack@eecs.umich.edu userSecureRead(v); 2917194Sgblack@eecs.umich.edu userSecureWrite(v); 2927194Sgblack@eecs.umich.edu privNonSecureRead(v); 2937194Sgblack@eecs.umich.edu privNonSecureWrite(v); 2947194Sgblack@eecs.umich.edu privSecureRead(v); 2957194Sgblack@eecs.umich.edu privSecureWrite(v); 2967194Sgblack@eecs.umich.edu hypRead(v); 2977194Sgblack@eecs.umich.edu hypWrite(v); 2987194Sgblack@eecs.umich.edu monSecureRead(v); 2997194Sgblack@eecs.umich.edu monSecureWrite(v); 3007194Sgblack@eecs.umich.edu monNonSecureRead(v); 3017194Sgblack@eecs.umich.edu monNonSecureWrite(v); 3027194Sgblack@eecs.umich.edu return *this; 3037194Sgblack@eecs.umich.edu } 3047194Sgblack@eecs.umich.edu chain nonSecure(bool v = true) const { 3057194Sgblack@eecs.umich.edu userNonSecureRead(v); 3067194Sgblack@eecs.umich.edu userNonSecureWrite(v); 3077194Sgblack@eecs.umich.edu privNonSecureRead(v); 3087194Sgblack@eecs.umich.edu privNonSecureWrite(v); 3097194Sgblack@eecs.umich.edu hypRead(v); 3107194Sgblack@eecs.umich.edu hypWrite(v); 3117194Sgblack@eecs.umich.edu monNonSecureRead(v); 3127194Sgblack@eecs.umich.edu monNonSecureWrite(v); 3137194Sgblack@eecs.umich.edu return *this; 3147194Sgblack@eecs.umich.edu } 3157194Sgblack@eecs.umich.edu chain secure(bool v = true) const { 3167194Sgblack@eecs.umich.edu userSecureRead(v); 3177194Sgblack@eecs.umich.edu userSecureWrite(v); 3187194Sgblack@eecs.umich.edu privSecureRead(v); 3197194Sgblack@eecs.umich.edu privSecureWrite(v); 3207194Sgblack@eecs.umich.edu monSecureRead(v); 3217194Sgblack@eecs.umich.edu monSecureWrite(v); 3227194Sgblack@eecs.umich.edu return *this; 3237194Sgblack@eecs.umich.edu } 3247194Sgblack@eecs.umich.edu chain reads(bool v) const { 3257194Sgblack@eecs.umich.edu userNonSecureRead(v); 3267194Sgblack@eecs.umich.edu userSecureRead(v); 3277194Sgblack@eecs.umich.edu privNonSecureRead(v); 3287194Sgblack@eecs.umich.edu privSecureRead(v); 3297194Sgblack@eecs.umich.edu hypRead(v); 3307194Sgblack@eecs.umich.edu monSecureRead(v); 3317194Sgblack@eecs.umich.edu monNonSecureRead(v); 3327194Sgblack@eecs.umich.edu return *this; 3337194Sgblack@eecs.umich.edu } 3347194Sgblack@eecs.umich.edu chain writes(bool v) const { 3357194Sgblack@eecs.umich.edu userNonSecureWrite(v); 3367194Sgblack@eecs.umich.edu userSecureWrite(v); 3377194Sgblack@eecs.umich.edu privNonSecureWrite(v); 3387194Sgblack@eecs.umich.edu privSecureWrite(v); 3397194Sgblack@eecs.umich.edu hypWrite(v); 3407139Sgblack@eecs.umich.edu monSecureWrite(v); 3417188Sgblack@eecs.umich.edu monNonSecureWrite(v); 3427188Sgblack@eecs.umich.edu return *this; 3437188Sgblack@eecs.umich.edu } 3447188Sgblack@eecs.umich.edu chain exceptUserMode() const { 3457188Sgblack@eecs.umich.edu user(0); 3467188Sgblack@eecs.umich.edu return *this; 3477188Sgblack@eecs.umich.edu } 3487188Sgblack@eecs.umich.edu MiscRegLUTEntryInitializer(struct MiscRegLUTEntry &e, 3497139Sgblack@eecs.umich.edu std::bitset<NUM_MISCREG_INFOS> &i) 3507188Sgblack@eecs.umich.edu : entry(e), 3517139Sgblack@eecs.umich.edu info(i) 3527188Sgblack@eecs.umich.edu { 3537188Sgblack@eecs.umich.edu // force unimplemented registers to be thusly declared 3547188Sgblack@eecs.umich.edu implemented(1); 3557188Sgblack@eecs.umich.edu } 3567188Sgblack@eecs.umich.edu }; 3577188Sgblack@eecs.umich.edu 3587139Sgblack@eecs.umich.edu const MiscRegLUTEntryInitializer InitReg(uint32_t reg) { 3597188Sgblack@eecs.umich.edu return MiscRegLUTEntryInitializer(lookUpMiscReg[reg], 3607188Sgblack@eecs.umich.edu miscRegInfo[reg]); 3617188Sgblack@eecs.umich.edu } 3627188Sgblack@eecs.umich.edu 3637188Sgblack@eecs.umich.edu void initializeMiscRegMetadata(); 3647188Sgblack@eecs.umich.edu 3657139Sgblack@eecs.umich.edu RegVal miscRegs[NumMiscRegs]; 3667139Sgblack@eecs.umich.edu const IntRegIndex *intRegMap; 3677139Sgblack@eecs.umich.edu 3687139Sgblack@eecs.umich.edu void 3697188Sgblack@eecs.umich.edu updateRegMap(CPSR cpsr) 3707188Sgblack@eecs.umich.edu { 3717188Sgblack@eecs.umich.edu if (cpsr.width == 0) { 3727188Sgblack@eecs.umich.edu intRegMap = IntReg64Map; 3737188Sgblack@eecs.umich.edu } else { 3747188Sgblack@eecs.umich.edu switch (cpsr.mode) { 3757188Sgblack@eecs.umich.edu case MODE_USER: 3767188Sgblack@eecs.umich.edu case MODE_SYSTEM: 3777188Sgblack@eecs.umich.edu intRegMap = IntRegUsrMap; 3787188Sgblack@eecs.umich.edu break; 3797188Sgblack@eecs.umich.edu case MODE_FIQ: 3807188Sgblack@eecs.umich.edu intRegMap = IntRegFiqMap; 3817188Sgblack@eecs.umich.edu break; 3827188Sgblack@eecs.umich.edu case MODE_IRQ: 3837188Sgblack@eecs.umich.edu intRegMap = IntRegIrqMap; 3847188Sgblack@eecs.umich.edu break; 3857188Sgblack@eecs.umich.edu case MODE_SVC: 3867188Sgblack@eecs.umich.edu intRegMap = IntRegSvcMap; 3877188Sgblack@eecs.umich.edu break; 3887188Sgblack@eecs.umich.edu case MODE_MON: 3897188Sgblack@eecs.umich.edu intRegMap = IntRegMonMap; 3907188Sgblack@eecs.umich.edu break; 3917188Sgblack@eecs.umich.edu case MODE_ABORT: 3927185Sgblack@eecs.umich.edu intRegMap = IntRegAbtMap; 3937188Sgblack@eecs.umich.edu break; 3947188Sgblack@eecs.umich.edu case MODE_HYP: 3957188Sgblack@eecs.umich.edu intRegMap = IntRegHypMap; 3967188Sgblack@eecs.umich.edu break; 3977188Sgblack@eecs.umich.edu case MODE_UNDEFINED: 3987188Sgblack@eecs.umich.edu intRegMap = IntRegUndMap; 3997188Sgblack@eecs.umich.edu break; 4007188Sgblack@eecs.umich.edu default: 4017188Sgblack@eecs.umich.edu panic("Unrecognized mode setting in CPSR.\n"); 4027188Sgblack@eecs.umich.edu } 4037188Sgblack@eecs.umich.edu } 4047188Sgblack@eecs.umich.edu } 4057139Sgblack@eecs.umich.edu 4067139Sgblack@eecs.umich.edu BaseISADevice &getGenericTimer(ThreadContext *tc); 4077139Sgblack@eecs.umich.edu BaseISADevice &getGICv3CPUInterface(ThreadContext *tc); 4087139Sgblack@eecs.umich.edu 4097139Sgblack@eecs.umich.edu 4107139Sgblack@eecs.umich.edu private: 4117139Sgblack@eecs.umich.edu inline void assert32(ThreadContext *tc) { 4127139Sgblack@eecs.umich.edu CPSR cpsr M5_VAR_USED = readMiscReg(MISCREG_CPSR, tc); 4137139Sgblack@eecs.umich.edu assert(cpsr.width); 4147139Sgblack@eecs.umich.edu } 4157139Sgblack@eecs.umich.edu 4167139Sgblack@eecs.umich.edu inline void assert64(ThreadContext *tc) { 4177139Sgblack@eecs.umich.edu CPSR cpsr M5_VAR_USED = readMiscReg(MISCREG_CPSR, tc); 4187139Sgblack@eecs.umich.edu assert(!cpsr.width); 4197185Sgblack@eecs.umich.edu } 4207139Sgblack@eecs.umich.edu 4217185Sgblack@eecs.umich.edu public: 4227139Sgblack@eecs.umich.edu void clear(); 4237139Sgblack@eecs.umich.edu 4247139Sgblack@eecs.umich.edu protected: 4257188Sgblack@eecs.umich.edu void clear32(const ArmISAParams *p, const SCTLR &sctlr_rst); 4267188Sgblack@eecs.umich.edu void clear64(const ArmISAParams *p); 4277188Sgblack@eecs.umich.edu void initID32(const ArmISAParams *p); 4287188Sgblack@eecs.umich.edu void initID64(const ArmISAParams *p); 4297139Sgblack@eecs.umich.edu 4307188Sgblack@eecs.umich.edu public: 4317139Sgblack@eecs.umich.edu RegVal readMiscRegNoEffect(int misc_reg) const; 4327188Sgblack@eecs.umich.edu RegVal readMiscReg(int misc_reg, ThreadContext *tc); 4337139Sgblack@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, RegVal val); 4347139Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, RegVal val, ThreadContext *tc); 4357139Sgblack@eecs.umich.edu 4367139Sgblack@eecs.umich.edu RegId 4377139Sgblack@eecs.umich.edu flattenRegId(const RegId& regId) const 4387139Sgblack@eecs.umich.edu { 4397139Sgblack@eecs.umich.edu switch (regId.classValue()) { 4407141Sgblack@eecs.umich.edu case IntRegClass: 4417195Sgblack@eecs.umich.edu return RegId(IntRegClass, flattenIntIndex(regId.index())); 4427195Sgblack@eecs.umich.edu case FloatRegClass: 4437195Sgblack@eecs.umich.edu return RegId(FloatRegClass, flattenFloatIndex(regId.index())); 4447195Sgblack@eecs.umich.edu case VecRegClass: 4457195Sgblack@eecs.umich.edu return RegId(VecRegClass, flattenVecIndex(regId.index())); 4467195Sgblack@eecs.umich.edu case VecElemClass: 4477195Sgblack@eecs.umich.edu return RegId(VecElemClass, flattenVecElemIndex(regId.index()), 4487195Sgblack@eecs.umich.edu regId.elemIndex()); 4497195Sgblack@eecs.umich.edu case CCRegClass: 4507195Sgblack@eecs.umich.edu return RegId(CCRegClass, flattenCCIndex(regId.index())); 4517195Sgblack@eecs.umich.edu case MiscRegClass: 4527195Sgblack@eecs.umich.edu return RegId(MiscRegClass, flattenMiscIndex(regId.index())); 4537195Sgblack@eecs.umich.edu } 4547195Sgblack@eecs.umich.edu return RegId(); 4557195Sgblack@eecs.umich.edu } 4567195Sgblack@eecs.umich.edu 4577195Sgblack@eecs.umich.edu int 4587195Sgblack@eecs.umich.edu flattenIntIndex(int reg) const 4597195Sgblack@eecs.umich.edu { 4607195Sgblack@eecs.umich.edu assert(reg >= 0); 4617195Sgblack@eecs.umich.edu if (reg < NUM_ARCH_INTREGS) { 4627195Sgblack@eecs.umich.edu return intRegMap[reg]; 4637141Sgblack@eecs.umich.edu } else if (reg < NUM_INTREGS) { 4647141Sgblack@eecs.umich.edu return reg; 4657141Sgblack@eecs.umich.edu } else if (reg == INTREG_SPX) { 4667141Sgblack@eecs.umich.edu CPSR cpsr = miscRegs[MISCREG_CPSR]; 4677141Sgblack@eecs.umich.edu ExceptionLevel el = opModeToEL( 4687141Sgblack@eecs.umich.edu (OperatingMode) (uint8_t) cpsr.mode); 4697141Sgblack@eecs.umich.edu if (!cpsr.sp && el != EL0) 4707141Sgblack@eecs.umich.edu return INTREG_SP0; 4717141Sgblack@eecs.umich.edu switch (el) { 4727141Sgblack@eecs.umich.edu case EL3: 4737141Sgblack@eecs.umich.edu return INTREG_SP3; 4747141Sgblack@eecs.umich.edu case EL2: 4757183Sgblack@eecs.umich.edu return INTREG_SP2; 4767141Sgblack@eecs.umich.edu case EL1: 4777183Sgblack@eecs.umich.edu return INTREG_SP1; 4787141Sgblack@eecs.umich.edu case EL0: 4797183Sgblack@eecs.umich.edu return INTREG_SP0; 4807141Sgblack@eecs.umich.edu default: 4817141Sgblack@eecs.umich.edu panic("Invalid exception level"); 4827141Sgblack@eecs.umich.edu return 0; // Never happens. 4837183Sgblack@eecs.umich.edu } 4847141Sgblack@eecs.umich.edu } else { 4857183Sgblack@eecs.umich.edu return flattenIntRegModeIndex(reg); 4867141Sgblack@eecs.umich.edu } 4877183Sgblack@eecs.umich.edu } 4887141Sgblack@eecs.umich.edu 4897183Sgblack@eecs.umich.edu int 4907141Sgblack@eecs.umich.edu flattenFloatIndex(int reg) const 4917141Sgblack@eecs.umich.edu { 4927183Sgblack@eecs.umich.edu assert(reg >= 0); 4937141Sgblack@eecs.umich.edu return reg; 4947146Sgblack@eecs.umich.edu } 4957141Sgblack@eecs.umich.edu 4967183Sgblack@eecs.umich.edu int 4977141Sgblack@eecs.umich.edu flattenVecIndex(int reg) const 4987183Sgblack@eecs.umich.edu { 4997141Sgblack@eecs.umich.edu assert(reg >= 0); 5007141Sgblack@eecs.umich.edu return reg; 5017141Sgblack@eecs.umich.edu } 5027141Sgblack@eecs.umich.edu 5037141Sgblack@eecs.umich.edu int 5047141Sgblack@eecs.umich.edu flattenVecElemIndex(int reg) const 5057141Sgblack@eecs.umich.edu { 5067141Sgblack@eecs.umich.edu assert(reg >= 0); 5077141Sgblack@eecs.umich.edu return reg; 5087141Sgblack@eecs.umich.edu } 5097141Sgblack@eecs.umich.edu 5107141Sgblack@eecs.umich.edu int 5117183Sgblack@eecs.umich.edu flattenCCIndex(int reg) const 5127141Sgblack@eecs.umich.edu { 5137183Sgblack@eecs.umich.edu assert(reg >= 0); 5147141Sgblack@eecs.umich.edu return reg; 5157183Sgblack@eecs.umich.edu } 5167141Sgblack@eecs.umich.edu 5177183Sgblack@eecs.umich.edu int 5187141Sgblack@eecs.umich.edu flattenMiscIndex(int reg) const 5197183Sgblack@eecs.umich.edu { 5207141Sgblack@eecs.umich.edu assert(reg >= 0); 5217183Sgblack@eecs.umich.edu int flat_idx = reg; 5227141Sgblack@eecs.umich.edu 5237183Sgblack@eecs.umich.edu if (reg == MISCREG_SPSR) { 5247141Sgblack@eecs.umich.edu CPSR cpsr = miscRegs[MISCREG_CPSR]; 5257183Sgblack@eecs.umich.edu switch (cpsr.mode) { 5267141Sgblack@eecs.umich.edu case MODE_EL0T: 5277183Sgblack@eecs.umich.edu warn("User mode does not have SPSR\n"); 5287141Sgblack@eecs.umich.edu flat_idx = MISCREG_SPSR; 5297183Sgblack@eecs.umich.edu break; 5307141Sgblack@eecs.umich.edu case MODE_EL1T: 5317183Sgblack@eecs.umich.edu case MODE_EL1H: 5327141Sgblack@eecs.umich.edu flat_idx = MISCREG_SPSR_EL1; 5337183Sgblack@eecs.umich.edu break; 5347141Sgblack@eecs.umich.edu case MODE_EL2T: 5357183Sgblack@eecs.umich.edu case MODE_EL2H: 5367141Sgblack@eecs.umich.edu flat_idx = MISCREG_SPSR_EL2; 5377183Sgblack@eecs.umich.edu break; 5387141Sgblack@eecs.umich.edu case MODE_EL3T: 5397183Sgblack@eecs.umich.edu case MODE_EL3H: 5407141Sgblack@eecs.umich.edu flat_idx = MISCREG_SPSR_EL3; 5417183Sgblack@eecs.umich.edu break; 5427141Sgblack@eecs.umich.edu case MODE_USER: 5437141Sgblack@eecs.umich.edu warn("User mode does not have SPSR\n"); 5447141Sgblack@eecs.umich.edu flat_idx = MISCREG_SPSR; 5457141Sgblack@eecs.umich.edu break; 5467141Sgblack@eecs.umich.edu case MODE_FIQ: 5477141Sgblack@eecs.umich.edu flat_idx = MISCREG_SPSR_FIQ; 5487141Sgblack@eecs.umich.edu break; 5497141Sgblack@eecs.umich.edu case MODE_IRQ: 5507141Sgblack@eecs.umich.edu flat_idx = MISCREG_SPSR_IRQ; 5517141Sgblack@eecs.umich.edu break; 5527141Sgblack@eecs.umich.edu case MODE_SVC: 5537141Sgblack@eecs.umich.edu flat_idx = MISCREG_SPSR_SVC; 5547141Sgblack@eecs.umich.edu break; 5557141Sgblack@eecs.umich.edu case MODE_MON: 5567146Sgblack@eecs.umich.edu flat_idx = MISCREG_SPSR_MON; 5577141Sgblack@eecs.umich.edu break; 5587183Sgblack@eecs.umich.edu case MODE_ABORT: 5597141Sgblack@eecs.umich.edu flat_idx = MISCREG_SPSR_ABT; 5607146Sgblack@eecs.umich.edu break; 5617141Sgblack@eecs.umich.edu case MODE_HYP: 5627154Sgblack@eecs.umich.edu flat_idx = MISCREG_SPSR_HYP; 5637154Sgblack@eecs.umich.edu break; 5647154Sgblack@eecs.umich.edu case MODE_UNDEFINED: 5657154Sgblack@eecs.umich.edu flat_idx = MISCREG_SPSR_UND; 5667154Sgblack@eecs.umich.edu break; 5677154Sgblack@eecs.umich.edu default: 5687154Sgblack@eecs.umich.edu warn("Trying to access SPSR in an invalid mode: %d\n", 5697154Sgblack@eecs.umich.edu cpsr.mode); 5707154Sgblack@eecs.umich.edu flat_idx = MISCREG_SPSR; 5717141Sgblack@eecs.umich.edu break; 5727141Sgblack@eecs.umich.edu } 5737141Sgblack@eecs.umich.edu } else if (miscRegInfo[reg][MISCREG_MUTEX]) { 5747141Sgblack@eecs.umich.edu // Mutually exclusive CP15 register 5757141Sgblack@eecs.umich.edu switch (reg) { 5767141Sgblack@eecs.umich.edu case MISCREG_PRRR_MAIR0: 5777141Sgblack@eecs.umich.edu case MISCREG_PRRR_MAIR0_NS: 5787141Sgblack@eecs.umich.edu case MISCREG_PRRR_MAIR0_S: 5797141Sgblack@eecs.umich.edu { 5807141Sgblack@eecs.umich.edu TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 5817185Sgblack@eecs.umich.edu // If the muxed reg has been flattened, work out the 5827141Sgblack@eecs.umich.edu // offset and apply it to the unmuxed reg 5837141Sgblack@eecs.umich.edu int idxOffset = reg - MISCREG_PRRR_MAIR0; 5847141Sgblack@eecs.umich.edu if (ttbcr.eae) 5857141Sgblack@eecs.umich.edu flat_idx = flattenMiscIndex(MISCREG_MAIR0 + 5867141Sgblack@eecs.umich.edu idxOffset); 5877141Sgblack@eecs.umich.edu else 5887141Sgblack@eecs.umich.edu flat_idx = flattenMiscIndex(MISCREG_PRRR + 5897141Sgblack@eecs.umich.edu idxOffset); 5907141Sgblack@eecs.umich.edu } 5917146Sgblack@eecs.umich.edu break; 5927141Sgblack@eecs.umich.edu case MISCREG_NMRR_MAIR1: 5937141Sgblack@eecs.umich.edu case MISCREG_NMRR_MAIR1_NS: 5947141Sgblack@eecs.umich.edu case MISCREG_NMRR_MAIR1_S: 5957141Sgblack@eecs.umich.edu { 5967141Sgblack@eecs.umich.edu TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 5977141Sgblack@eecs.umich.edu // If the muxed reg has been flattened, work out the 5987141Sgblack@eecs.umich.edu // offset and apply it to the unmuxed reg 5997141Sgblack@eecs.umich.edu int idxOffset = reg - MISCREG_NMRR_MAIR1; 6007141Sgblack@eecs.umich.edu if (ttbcr.eae) 6017141Sgblack@eecs.umich.edu flat_idx = flattenMiscIndex(MISCREG_MAIR1 + 6027146Sgblack@eecs.umich.edu idxOffset); 6037141Sgblack@eecs.umich.edu else 6047141Sgblack@eecs.umich.edu flat_idx = flattenMiscIndex(MISCREG_NMRR + 6057146Sgblack@eecs.umich.edu idxOffset); 6067141Sgblack@eecs.umich.edu } 6077141Sgblack@eecs.umich.edu break; 6087141Sgblack@eecs.umich.edu case MISCREG_PMXEVTYPER_PMCCFILTR: 6097154Sgblack@eecs.umich.edu { 6107154Sgblack@eecs.umich.edu PMSELR pmselr = miscRegs[MISCREG_PMSELR]; 6117154Sgblack@eecs.umich.edu if (pmselr.sel == 31) 6127154Sgblack@eecs.umich.edu flat_idx = flattenMiscIndex(MISCREG_PMCCFILTR); 6137141Sgblack@eecs.umich.edu else 6147141Sgblack@eecs.umich.edu flat_idx = flattenMiscIndex(MISCREG_PMXEVTYPER); 6157141Sgblack@eecs.umich.edu } 6167141Sgblack@eecs.umich.edu break; 6177141Sgblack@eecs.umich.edu default: 6187141Sgblack@eecs.umich.edu panic("Unrecognized misc. register.\n"); 6197141Sgblack@eecs.umich.edu break; 6207141Sgblack@eecs.umich.edu } 6217141Sgblack@eecs.umich.edu } else { 6227141Sgblack@eecs.umich.edu if (miscRegInfo[reg][MISCREG_BANKED]) { 6237141Sgblack@eecs.umich.edu bool secureReg = haveSecurity && !highestELIs64 && 6247141Sgblack@eecs.umich.edu inSecureState(miscRegs[MISCREG_SCR], 6257154Sgblack@eecs.umich.edu miscRegs[MISCREG_CPSR]); 6267154Sgblack@eecs.umich.edu flat_idx += secureReg ? 2 : 1; 6277154Sgblack@eecs.umich.edu } 6287154Sgblack@eecs.umich.edu } 6297141Sgblack@eecs.umich.edu return flat_idx; 6307141Sgblack@eecs.umich.edu } 6317201Sgblack@eecs.umich.edu 6327201Sgblack@eecs.umich.edu std::pair<int,int> getMiscIndices(int misc_reg) const 6337201Sgblack@eecs.umich.edu { 6347201Sgblack@eecs.umich.edu // Note: indexes of AArch64 registers are left unchanged 6357201Sgblack@eecs.umich.edu int flat_idx = flattenMiscIndex(misc_reg); 6367201Sgblack@eecs.umich.edu 6377141Sgblack@eecs.umich.edu if (lookUpMiscReg[flat_idx].lower == 0) { 6387141Sgblack@eecs.umich.edu return std::make_pair(flat_idx, 0); 6397141Sgblack@eecs.umich.edu } 6407141Sgblack@eecs.umich.edu 6417141Sgblack@eecs.umich.edu // do additional S/NS flattenings if mapped to NS while in S 6427141Sgblack@eecs.umich.edu bool S = haveSecurity && !highestELIs64 && 6437141Sgblack@eecs.umich.edu inSecureState(miscRegs[MISCREG_SCR], 6447141Sgblack@eecs.umich.edu miscRegs[MISCREG_CPSR]); 6457141Sgblack@eecs.umich.edu int lower = lookUpMiscReg[flat_idx].lower; 6467141Sgblack@eecs.umich.edu int upper = lookUpMiscReg[flat_idx].upper; 6477154Sgblack@eecs.umich.edu // upper == 0, which is CPSR, is not MISCREG_BANKED_CHILD (no-op) 6487154Sgblack@eecs.umich.edu lower += S && miscRegInfo[lower][MISCREG_BANKED_CHILD]; 6497154Sgblack@eecs.umich.edu upper += S && miscRegInfo[upper][MISCREG_BANKED_CHILD]; 6507154Sgblack@eecs.umich.edu return std::make_pair(lower, upper); 6517141Sgblack@eecs.umich.edu } 6527212Sgblack@eecs.umich.edu 6537212Sgblack@eecs.umich.edu void serialize(CheckpointOut &cp) const 6547212Sgblack@eecs.umich.edu { 6557212Sgblack@eecs.umich.edu DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n"); 6567212Sgblack@eecs.umich.edu SERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS); 6577212Sgblack@eecs.umich.edu 6587212Sgblack@eecs.umich.edu SERIALIZE_SCALAR(highestELIs64); 6597212Sgblack@eecs.umich.edu SERIALIZE_SCALAR(haveSecurity); 6607212Sgblack@eecs.umich.edu SERIALIZE_SCALAR(haveLPAE); 6617212Sgblack@eecs.umich.edu SERIALIZE_SCALAR(haveVirtualization); 6627212Sgblack@eecs.umich.edu SERIALIZE_SCALAR(haveLargeAsid64); 6637212Sgblack@eecs.umich.edu SERIALIZE_SCALAR(physAddrRange); 6647212Sgblack@eecs.umich.edu } 6657141Sgblack@eecs.umich.edu void unserialize(CheckpointIn &cp) 6667141Sgblack@eecs.umich.edu { 6677141Sgblack@eecs.umich.edu DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n"); 6687154Sgblack@eecs.umich.edu UNSERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS); 6697154Sgblack@eecs.umich.edu CPSR tmp_cpsr = miscRegs[MISCREG_CPSR]; 6707154Sgblack@eecs.umich.edu updateRegMap(tmp_cpsr); 6717154Sgblack@eecs.umich.edu 6727141Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(highestELIs64); 6737141Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(haveSecurity); 6747201Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(haveLPAE); 6757201Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(haveVirtualization); 6767201Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(haveLargeAsid64); 6777201Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(physAddrRange); 6787201Sgblack@eecs.umich.edu } 6797201Sgblack@eecs.umich.edu 6807141Sgblack@eecs.umich.edu void startup(ThreadContext *tc); 6817141Sgblack@eecs.umich.edu 6827141Sgblack@eecs.umich.edu Enums::DecoderFlavour decoderFlavour() const { return _decoderFlavour; } 6837141Sgblack@eecs.umich.edu 6847141Sgblack@eecs.umich.edu Enums::VecRegRenameMode 6857141Sgblack@eecs.umich.edu vecRegRenameMode() const 6867141Sgblack@eecs.umich.edu { 6877141Sgblack@eecs.umich.edu return _vecRegRenameMode; 6887141Sgblack@eecs.umich.edu } 6897141Sgblack@eecs.umich.edu 6907141Sgblack@eecs.umich.edu /// Explicitly import the otherwise hidden startup 6917141Sgblack@eecs.umich.edu using SimObject::startup; 6927141Sgblack@eecs.umich.edu 6937141Sgblack@eecs.umich.edu typedef ArmISAParams Params; 6947141Sgblack@eecs.umich.edu 6957141Sgblack@eecs.umich.edu const Params *params() const; 6967141Sgblack@eecs.umich.edu 6977141Sgblack@eecs.umich.edu ISA(Params *p); 6987141Sgblack@eecs.umich.edu }; 6997141Sgblack@eecs.umich.edu} 7007141Sgblack@eecs.umich.edu 7017141Sgblack@eecs.umich.edutemplate<> 7027141Sgblack@eecs.umich.edustruct RenameMode<ArmISA::ISA> 7037141Sgblack@eecs.umich.edu{ 7047141Sgblack@eecs.umich.edu static Enums::VecRegRenameMode 7057141Sgblack@eecs.umich.edu init(const ArmISA::ISA* isa) 7067141Sgblack@eecs.umich.edu { 7077141Sgblack@eecs.umich.edu return isa->vecRegRenameMode(); 7087141Sgblack@eecs.umich.edu } 7097141Sgblack@eecs.umich.edu 7107141Sgblack@eecs.umich.edu static Enums::VecRegRenameMode 7117141Sgblack@eecs.umich.edu mode(const ArmISA::PCState& pc) 7127146Sgblack@eecs.umich.edu { 7137183Sgblack@eecs.umich.edu if (pc.aarch64()) { 7147141Sgblack@eecs.umich.edu return Enums::Full; 7157146Sgblack@eecs.umich.edu } else { 7167183Sgblack@eecs.umich.edu return Enums::Elem; 7177141Sgblack@eecs.umich.edu } 7187141Sgblack@eecs.umich.edu } 7197141Sgblack@eecs.umich.edu 7207141Sgblack@eecs.umich.edu static bool 7217141Sgblack@eecs.umich.edu equalsInit(const ArmISA::ISA* isa1, const ArmISA::ISA* isa2) 7227141Sgblack@eecs.umich.edu { 7237141Sgblack@eecs.umich.edu return init(isa1) == init(isa2); 7247141Sgblack@eecs.umich.edu } 7257141Sgblack@eecs.umich.edu}; 7267141Sgblack@eecs.umich.edu 7277141Sgblack@eecs.umich.edu#endif 7287183Sgblack@eecs.umich.edu