isa.hh revision 7404
16313Sgblack@eecs.umich.edu/* 27093Sgblack@eecs.umich.edu * Copyright (c) 2010 ARM Limited 37093Sgblack@eecs.umich.edu * All rights reserved 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67093Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77093Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87093Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97093Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107093Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117093Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127093Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137093Sgblack@eecs.umich.edu * 146313Sgblack@eecs.umich.edu * Copyright (c) 2009 The Regents of The University of Michigan 156313Sgblack@eecs.umich.edu * All rights reserved. 166313Sgblack@eecs.umich.edu * 176313Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 186313Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 196313Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 206313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 216313Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 226313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 236313Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 246313Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 256313Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 266313Sgblack@eecs.umich.edu * this software without specific prior written permission. 276313Sgblack@eecs.umich.edu * 286313Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296313Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306313Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316313Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326313Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336313Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346313Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356313Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366313Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376313Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386313Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396313Sgblack@eecs.umich.edu * 406313Sgblack@eecs.umich.edu * Authors: Gabe Black 416313Sgblack@eecs.umich.edu */ 426313Sgblack@eecs.umich.edu 436313Sgblack@eecs.umich.edu#ifndef __ARCH_ARM_ISA_HH__ 447404SAli.Saidi@ARM.com#define __ARCH_ARM_ISA_HH__ 456313Sgblack@eecs.umich.edu 466333Sgblack@eecs.umich.edu#include "arch/arm/registers.hh" 477404SAli.Saidi@ARM.com#include "arch/arm/tlb.hh" 486313Sgblack@eecs.umich.edu#include "arch/arm/types.hh" 496313Sgblack@eecs.umich.edu 506333Sgblack@eecs.umich.educlass ThreadContext; 516313Sgblack@eecs.umich.educlass Checkpoint; 526313Sgblack@eecs.umich.educlass EventManager; 536313Sgblack@eecs.umich.edu 546313Sgblack@eecs.umich.edunamespace ArmISA 556313Sgblack@eecs.umich.edu{ 566313Sgblack@eecs.umich.edu class ISA 576313Sgblack@eecs.umich.edu { 586313Sgblack@eecs.umich.edu protected: 596333Sgblack@eecs.umich.edu MiscReg miscRegs[NumMiscRegs]; 606718Sgblack@eecs.umich.edu const IntRegIndex *intRegMap; 616718Sgblack@eecs.umich.edu 626718Sgblack@eecs.umich.edu void 636718Sgblack@eecs.umich.edu updateRegMap(CPSR cpsr) 646718Sgblack@eecs.umich.edu { 656718Sgblack@eecs.umich.edu switch (cpsr.mode) { 666718Sgblack@eecs.umich.edu case MODE_USER: 676718Sgblack@eecs.umich.edu case MODE_SYSTEM: 686718Sgblack@eecs.umich.edu intRegMap = IntRegUsrMap; 696718Sgblack@eecs.umich.edu break; 706718Sgblack@eecs.umich.edu case MODE_FIQ: 716718Sgblack@eecs.umich.edu intRegMap = IntRegFiqMap; 726718Sgblack@eecs.umich.edu break; 736718Sgblack@eecs.umich.edu case MODE_IRQ: 746718Sgblack@eecs.umich.edu intRegMap = IntRegIrqMap; 756718Sgblack@eecs.umich.edu break; 766718Sgblack@eecs.umich.edu case MODE_SVC: 776718Sgblack@eecs.umich.edu intRegMap = IntRegSvcMap; 786718Sgblack@eecs.umich.edu break; 796723Sgblack@eecs.umich.edu case MODE_MON: 806723Sgblack@eecs.umich.edu intRegMap = IntRegMonMap; 816723Sgblack@eecs.umich.edu break; 826718Sgblack@eecs.umich.edu case MODE_ABORT: 836718Sgblack@eecs.umich.edu intRegMap = IntRegAbtMap; 846718Sgblack@eecs.umich.edu break; 856718Sgblack@eecs.umich.edu case MODE_UNDEFINED: 866718Sgblack@eecs.umich.edu intRegMap = IntRegUndMap; 876718Sgblack@eecs.umich.edu break; 886718Sgblack@eecs.umich.edu default: 896718Sgblack@eecs.umich.edu panic("Unrecognized mode setting in CPSR.\n"); 906718Sgblack@eecs.umich.edu } 916718Sgblack@eecs.umich.edu } 926313Sgblack@eecs.umich.edu 936313Sgblack@eecs.umich.edu public: 946333Sgblack@eecs.umich.edu void clear() 956333Sgblack@eecs.umich.edu { 967400SAli.Saidi@ARM.com SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 977400SAli.Saidi@ARM.com 986401Sgblack@eecs.umich.edu memset(miscRegs, 0, sizeof(miscRegs)); 996401Sgblack@eecs.umich.edu CPSR cpsr = 0; 1006719Sgblack@eecs.umich.edu cpsr.mode = MODE_USER; 1016401Sgblack@eecs.umich.edu miscRegs[MISCREG_CPSR] = cpsr; 1026718Sgblack@eecs.umich.edu updateRegMap(cpsr); 1036735Sgblack@eecs.umich.edu 1046735Sgblack@eecs.umich.edu SCTLR sctlr = 0; 1057400SAli.Saidi@ARM.com sctlr.nmfi = (bool)sctlr_rst.nmfi; 1067400SAli.Saidi@ARM.com sctlr.v = (bool)sctlr_rst.v; 1077400SAli.Saidi@ARM.com sctlr.u = 1; 1086735Sgblack@eecs.umich.edu sctlr.rao1 = 1; 1096735Sgblack@eecs.umich.edu sctlr.rao2 = 1; 1106735Sgblack@eecs.umich.edu sctlr.rao3 = 1; 1116735Sgblack@eecs.umich.edu sctlr.rao4 = 1; 1127270Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR] = sctlr; 1137400SAli.Saidi@ARM.com miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 1147400SAli.Saidi@ARM.com 1156735Sgblack@eecs.umich.edu 1167271Sgblack@eecs.umich.edu /* 1177271Sgblack@eecs.umich.edu * Technically this should be 0, but we don't support those 1187271Sgblack@eecs.umich.edu * settings. 1197271Sgblack@eecs.umich.edu */ 1207320Sgblack@eecs.umich.edu CPACR cpacr = 0; 1217320Sgblack@eecs.umich.edu // Enable CP 10, 11 1227320Sgblack@eecs.umich.edu cpacr.cp10 = 0x3; 1237320Sgblack@eecs.umich.edu cpacr.cp11 = 0x3; 1247320Sgblack@eecs.umich.edu miscRegs[MISCREG_CPACR] = cpacr; 1257271Sgblack@eecs.umich.edu 1267350SAli.Saidi@ARM.com /* Start with an event in the mailbox */ 1277350SAli.Saidi@ARM.com miscRegs[MISCREG_SEV_MAILBOX] = 1; 1287350SAli.Saidi@ARM.com 1297298Sgblack@eecs.umich.edu /* 1307298Sgblack@eecs.umich.edu * Implemented = '5' from "M5", 1317298Sgblack@eecs.umich.edu * Variant = 0, 1327298Sgblack@eecs.umich.edu */ 1337298Sgblack@eecs.umich.edu miscRegs[MISCREG_MIDR] = 1347298Sgblack@eecs.umich.edu (0x35 << 24) | //Implementor is '5' from "M5" 1357298Sgblack@eecs.umich.edu (0 << 20) | //Variant 1367298Sgblack@eecs.umich.edu (0xf << 16) | //Architecture from CPUID scheme 1377298Sgblack@eecs.umich.edu (0 << 4) | //Primary part number 1387298Sgblack@eecs.umich.edu (0 << 0) | //Revision 1397298Sgblack@eecs.umich.edu 0; 1407298Sgblack@eecs.umich.edu 1417354Sgblack@eecs.umich.edu // Separate Instruction and Data TLBs. 1427354Sgblack@eecs.umich.edu miscRegs[MISCREG_TLBTR] = 1; 1437354Sgblack@eecs.umich.edu 1447383Sgblack@eecs.umich.edu MVFR0 mvfr0 = 0; 1457383Sgblack@eecs.umich.edu mvfr0.advSimdRegisters = 2; 1467383Sgblack@eecs.umich.edu mvfr0.singlePrecision = 2; 1477383Sgblack@eecs.umich.edu mvfr0.doublePrecision = 2; 1487383Sgblack@eecs.umich.edu mvfr0.vfpExceptionTrapping = 0; 1497383Sgblack@eecs.umich.edu mvfr0.divide = 1; 1507383Sgblack@eecs.umich.edu mvfr0.squareRoot = 1; 1517383Sgblack@eecs.umich.edu mvfr0.shortVectors = 1; 1527383Sgblack@eecs.umich.edu mvfr0.roundingModes = 1; 1537383Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR0] = mvfr0; 1547383Sgblack@eecs.umich.edu 1557383Sgblack@eecs.umich.edu MVFR1 mvfr1 = 0; 1567383Sgblack@eecs.umich.edu mvfr1.flushToZero = 1; 1577383Sgblack@eecs.umich.edu mvfr1.defaultNaN = 1; 1587383Sgblack@eecs.umich.edu mvfr1.advSimdLoadStore = 1; 1597383Sgblack@eecs.umich.edu mvfr1.advSimdInteger = 1; 1607383Sgblack@eecs.umich.edu mvfr1.advSimdSinglePrecision = 1; 1617383Sgblack@eecs.umich.edu mvfr1.advSimdHalfPrecision = 1; 1627383Sgblack@eecs.umich.edu mvfr1.vfpHalfPrecision = 1; 1637383Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR1] = mvfr1; 1647383Sgblack@eecs.umich.edu 1657390Sgblack@eecs.umich.edu miscRegs[MISCREG_MPIDR] = 0; 1667390Sgblack@eecs.umich.edu 1676401Sgblack@eecs.umich.edu //XXX We need to initialize the rest of the state. 1686333Sgblack@eecs.umich.edu } 1696313Sgblack@eecs.umich.edu 1706333Sgblack@eecs.umich.edu MiscReg 1716333Sgblack@eecs.umich.edu readMiscRegNoEffect(int misc_reg) 1726333Sgblack@eecs.umich.edu { 1736333Sgblack@eecs.umich.edu assert(misc_reg < NumMiscRegs); 1746745Sgblack@eecs.umich.edu if (misc_reg == MISCREG_SPSR) { 1756745Sgblack@eecs.umich.edu CPSR cpsr = miscRegs[MISCREG_CPSR]; 1766745Sgblack@eecs.umich.edu switch (cpsr.mode) { 1776745Sgblack@eecs.umich.edu case MODE_USER: 1786745Sgblack@eecs.umich.edu return miscRegs[MISCREG_SPSR]; 1796745Sgblack@eecs.umich.edu case MODE_FIQ: 1806745Sgblack@eecs.umich.edu return miscRegs[MISCREG_SPSR_FIQ]; 1816745Sgblack@eecs.umich.edu case MODE_IRQ: 1826745Sgblack@eecs.umich.edu return miscRegs[MISCREG_SPSR_IRQ]; 1836745Sgblack@eecs.umich.edu case MODE_SVC: 1846745Sgblack@eecs.umich.edu return miscRegs[MISCREG_SPSR_SVC]; 1856745Sgblack@eecs.umich.edu case MODE_MON: 1866745Sgblack@eecs.umich.edu return miscRegs[MISCREG_SPSR_MON]; 1876745Sgblack@eecs.umich.edu case MODE_ABORT: 1886745Sgblack@eecs.umich.edu return miscRegs[MISCREG_SPSR_ABT]; 1896745Sgblack@eecs.umich.edu case MODE_UNDEFINED: 1906745Sgblack@eecs.umich.edu return miscRegs[MISCREG_SPSR_UND]; 1916745Sgblack@eecs.umich.edu default: 1926745Sgblack@eecs.umich.edu return miscRegs[MISCREG_SPSR]; 1936745Sgblack@eecs.umich.edu } 1946745Sgblack@eecs.umich.edu } 1956333Sgblack@eecs.umich.edu return miscRegs[misc_reg]; 1966333Sgblack@eecs.umich.edu } 1976313Sgblack@eecs.umich.edu 1986333Sgblack@eecs.umich.edu MiscReg 1996333Sgblack@eecs.umich.edu readMiscReg(int misc_reg, ThreadContext *tc) 2006333Sgblack@eecs.umich.edu { 2017093Sgblack@eecs.umich.edu if (misc_reg == MISCREG_CPSR) { 2027093Sgblack@eecs.umich.edu CPSR cpsr = miscRegs[misc_reg]; 2037093Sgblack@eecs.umich.edu Addr pc = tc->readPC(); 2047093Sgblack@eecs.umich.edu if (pc & (ULL(1) << PcJBitShift)) 2057093Sgblack@eecs.umich.edu cpsr.j = 1; 2067093Sgblack@eecs.umich.edu else 2077093Sgblack@eecs.umich.edu cpsr.j = 0; 2087093Sgblack@eecs.umich.edu if (pc & (ULL(1) << PcTBitShift)) 2097093Sgblack@eecs.umich.edu cpsr.t = 1; 2107093Sgblack@eecs.umich.edu else 2117093Sgblack@eecs.umich.edu cpsr.t = 0; 2127093Sgblack@eecs.umich.edu return cpsr; 2137093Sgblack@eecs.umich.edu } 2147259Sgblack@eecs.umich.edu if (misc_reg >= MISCREG_CP15_UNIMP_START && 2157259Sgblack@eecs.umich.edu misc_reg < MISCREG_CP15_END) { 2167259Sgblack@eecs.umich.edu panic("Unimplemented CP15 register %s read.\n", 2177259Sgblack@eecs.umich.edu miscRegName[misc_reg]); 2187259Sgblack@eecs.umich.edu } 2197273Sgblack@eecs.umich.edu switch (misc_reg) { 2207273Sgblack@eecs.umich.edu case MISCREG_CLIDR: 2217273Sgblack@eecs.umich.edu warn("The clidr register always reports 0 caches.\n"); 2227273Sgblack@eecs.umich.edu break; 2237287Sgblack@eecs.umich.edu case MISCREG_CCSIDR: 2247287Sgblack@eecs.umich.edu warn("The ccsidr register isn't implemented and " 2257287Sgblack@eecs.umich.edu "always reads as 0.\n"); 2267287Sgblack@eecs.umich.edu break; 2277404SAli.Saidi@ARM.com case MISCREG_ID_PFR0: 2287404SAli.Saidi@ARM.com return 0x1031; // ThumbEE | !Jazelle | Thumb | ARM 2297273Sgblack@eecs.umich.edu } 2306745Sgblack@eecs.umich.edu return readMiscRegNoEffect(misc_reg); 2316333Sgblack@eecs.umich.edu } 2326333Sgblack@eecs.umich.edu 2336333Sgblack@eecs.umich.edu void 2346333Sgblack@eecs.umich.edu setMiscRegNoEffect(int misc_reg, const MiscReg &val) 2356333Sgblack@eecs.umich.edu { 2366333Sgblack@eecs.umich.edu assert(misc_reg < NumMiscRegs); 2376745Sgblack@eecs.umich.edu if (misc_reg == MISCREG_SPSR) { 2386745Sgblack@eecs.umich.edu CPSR cpsr = miscRegs[MISCREG_CPSR]; 2396745Sgblack@eecs.umich.edu switch (cpsr.mode) { 2406745Sgblack@eecs.umich.edu case MODE_USER: 2416745Sgblack@eecs.umich.edu miscRegs[MISCREG_SPSR] = val; 2426745Sgblack@eecs.umich.edu return; 2436745Sgblack@eecs.umich.edu case MODE_FIQ: 2446745Sgblack@eecs.umich.edu miscRegs[MISCREG_SPSR_FIQ] = val; 2456745Sgblack@eecs.umich.edu return; 2466745Sgblack@eecs.umich.edu case MODE_IRQ: 2476745Sgblack@eecs.umich.edu miscRegs[MISCREG_SPSR_IRQ] = val; 2486745Sgblack@eecs.umich.edu return; 2496745Sgblack@eecs.umich.edu case MODE_SVC: 2506745Sgblack@eecs.umich.edu miscRegs[MISCREG_SPSR_SVC] = val; 2516745Sgblack@eecs.umich.edu return; 2526745Sgblack@eecs.umich.edu case MODE_MON: 2536745Sgblack@eecs.umich.edu miscRegs[MISCREG_SPSR_MON] = val; 2546745Sgblack@eecs.umich.edu return; 2556745Sgblack@eecs.umich.edu case MODE_ABORT: 2566745Sgblack@eecs.umich.edu miscRegs[MISCREG_SPSR_ABT] = val; 2576745Sgblack@eecs.umich.edu return; 2586745Sgblack@eecs.umich.edu case MODE_UNDEFINED: 2596745Sgblack@eecs.umich.edu miscRegs[MISCREG_SPSR_UND] = val; 2606745Sgblack@eecs.umich.edu return; 2616745Sgblack@eecs.umich.edu default: 2626745Sgblack@eecs.umich.edu miscRegs[MISCREG_SPSR] = val; 2636745Sgblack@eecs.umich.edu return; 2646745Sgblack@eecs.umich.edu } 2656745Sgblack@eecs.umich.edu } 2666333Sgblack@eecs.umich.edu miscRegs[misc_reg] = val; 2676333Sgblack@eecs.umich.edu } 2686333Sgblack@eecs.umich.edu 2696333Sgblack@eecs.umich.edu void 2706333Sgblack@eecs.umich.edu setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 2716333Sgblack@eecs.umich.edu { 2727271Sgblack@eecs.umich.edu MiscReg newVal = val; 2736718Sgblack@eecs.umich.edu if (misc_reg == MISCREG_CPSR) { 2746718Sgblack@eecs.umich.edu updateRegMap(val); 2757093Sgblack@eecs.umich.edu CPSR cpsr = val; 2767348SAli.Saidi@ARM.com DPRINTF(Arm, "Updating CPSR to %#x f:%d i:%d a:%d mode:%#x\n", 2777348SAli.Saidi@ARM.com cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 2787093Sgblack@eecs.umich.edu Addr npc = tc->readNextPC() & ~PcModeMask; 2797093Sgblack@eecs.umich.edu if (cpsr.j) 2807093Sgblack@eecs.umich.edu npc = npc | (ULL(1) << PcJBitShift); 2817093Sgblack@eecs.umich.edu if (cpsr.t) 2827093Sgblack@eecs.umich.edu npc = npc | (ULL(1) << PcTBitShift); 2837093Sgblack@eecs.umich.edu 2847093Sgblack@eecs.umich.edu tc->setNextPC(npc); 2856718Sgblack@eecs.umich.edu } 2867259Sgblack@eecs.umich.edu if (misc_reg >= MISCREG_CP15_UNIMP_START && 2877259Sgblack@eecs.umich.edu misc_reg < MISCREG_CP15_END) { 2887259Sgblack@eecs.umich.edu panic("Unimplemented CP15 register %s wrote with %#x.\n", 2897259Sgblack@eecs.umich.edu miscRegName[misc_reg], val); 2907259Sgblack@eecs.umich.edu } 2917271Sgblack@eecs.umich.edu switch (misc_reg) { 2927271Sgblack@eecs.umich.edu case MISCREG_CPACR: 2937320Sgblack@eecs.umich.edu { 2947320Sgblack@eecs.umich.edu CPACR newCpacr = 0; 2957320Sgblack@eecs.umich.edu CPACR valCpacr = val; 2967320Sgblack@eecs.umich.edu newCpacr.cp10 = valCpacr.cp10; 2977320Sgblack@eecs.umich.edu newCpacr.cp11 = valCpacr.cp11; 2987320Sgblack@eecs.umich.edu if (newCpacr.cp10 != 0x3 || newCpacr.cp11 != 3) { 2997320Sgblack@eecs.umich.edu panic("Disabling coprocessors isn't implemented.\n"); 3007320Sgblack@eecs.umich.edu } 3017320Sgblack@eecs.umich.edu newVal = newCpacr; 3027271Sgblack@eecs.umich.edu } 3037271Sgblack@eecs.umich.edu break; 3047287Sgblack@eecs.umich.edu case MISCREG_CSSELR: 3057287Sgblack@eecs.umich.edu warn("The csselr register isn't implemented.\n"); 3067287Sgblack@eecs.umich.edu break; 3077393Sgblack@eecs.umich.edu case MISCREG_FPSCR: 3087393Sgblack@eecs.umich.edu { 3097393Sgblack@eecs.umich.edu const uint32_t ones = (uint32_t)(-1); 3107393Sgblack@eecs.umich.edu FPSCR fpscrMask = 0; 3117393Sgblack@eecs.umich.edu fpscrMask.ioc = ones; 3127393Sgblack@eecs.umich.edu fpscrMask.dzc = ones; 3137393Sgblack@eecs.umich.edu fpscrMask.ofc = ones; 3147393Sgblack@eecs.umich.edu fpscrMask.ufc = ones; 3157393Sgblack@eecs.umich.edu fpscrMask.ixc = ones; 3167393Sgblack@eecs.umich.edu fpscrMask.idc = ones; 3177393Sgblack@eecs.umich.edu fpscrMask.len = ones; 3187393Sgblack@eecs.umich.edu fpscrMask.stride = ones; 3197393Sgblack@eecs.umich.edu fpscrMask.rMode = ones; 3207393Sgblack@eecs.umich.edu fpscrMask.fz = ones; 3217393Sgblack@eecs.umich.edu fpscrMask.dn = ones; 3227393Sgblack@eecs.umich.edu fpscrMask.ahp = ones; 3237393Sgblack@eecs.umich.edu fpscrMask.qc = ones; 3247393Sgblack@eecs.umich.edu fpscrMask.v = ones; 3257393Sgblack@eecs.umich.edu fpscrMask.c = ones; 3267393Sgblack@eecs.umich.edu fpscrMask.z = ones; 3277393Sgblack@eecs.umich.edu fpscrMask.n = ones; 3287393Sgblack@eecs.umich.edu newVal = (newVal & (uint32_t)fpscrMask) | 3297393Sgblack@eecs.umich.edu (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask); 3307393Sgblack@eecs.umich.edu } 3317393Sgblack@eecs.umich.edu break; 3327393Sgblack@eecs.umich.edu case MISCREG_FPEXC: 3337393Sgblack@eecs.umich.edu { 3347393Sgblack@eecs.umich.edu const uint32_t fpexcMask = 0x60000000; 3357393Sgblack@eecs.umich.edu newVal = (newVal & fpexcMask) | 3367393Sgblack@eecs.umich.edu (miscRegs[MISCREG_FPEXC] & ~fpexcMask); 3377393Sgblack@eecs.umich.edu } 3387393Sgblack@eecs.umich.edu break; 3397400SAli.Saidi@ARM.com case MISCREG_SCTLR: 3407400SAli.Saidi@ARM.com { 3417400SAli.Saidi@ARM.com SCTLR sctlr = miscRegs[MISCREG_SCTLR]; 3427400SAli.Saidi@ARM.com SCTLR new_sctlr = newVal; 3437400SAli.Saidi@ARM.com new_sctlr.nmfi = (bool)sctlr.nmfi; 3447400SAli.Saidi@ARM.com miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr; 3457400SAli.Saidi@ARM.com return; 3467400SAli.Saidi@ARM.com } 3477354Sgblack@eecs.umich.edu case MISCREG_TLBTR: 3487383Sgblack@eecs.umich.edu case MISCREG_MVFR0: 3497383Sgblack@eecs.umich.edu case MISCREG_MVFR1: 3507390Sgblack@eecs.umich.edu case MISCREG_MPIDR: 3517393Sgblack@eecs.umich.edu case MISCREG_FPSID: 3527354Sgblack@eecs.umich.edu return; 3537404SAli.Saidi@ARM.com case MISCREG_TLBIALLIS: 3547404SAli.Saidi@ARM.com case MISCREG_TLBIALL: 3557404SAli.Saidi@ARM.com warn("Need to flush all TLBs in MP\n"); 3567404SAli.Saidi@ARM.com tc->getITBPtr()->flushAll(); 3577404SAli.Saidi@ARM.com tc->getDTBPtr()->flushAll(); 3587404SAli.Saidi@ARM.com return; 3597404SAli.Saidi@ARM.com case MISCREG_ITLBIALL: 3607404SAli.Saidi@ARM.com tc->getITBPtr()->flushAll(); 3617404SAli.Saidi@ARM.com return; 3627404SAli.Saidi@ARM.com case MISCREG_DTLBIALL: 3637404SAli.Saidi@ARM.com tc->getDTBPtr()->flushAll(); 3647404SAli.Saidi@ARM.com return; 3657404SAli.Saidi@ARM.com case MISCREG_TLBIMVAIS: 3667404SAli.Saidi@ARM.com case MISCREG_TLBIMVA: 3677404SAli.Saidi@ARM.com warn("Need to flush all TLBs in MP\n"); 3687404SAli.Saidi@ARM.com tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 3697404SAli.Saidi@ARM.com bits(newVal, 7,0)); 3707404SAli.Saidi@ARM.com tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 3717404SAli.Saidi@ARM.com bits(newVal, 7,0)); 3727404SAli.Saidi@ARM.com return; 3737404SAli.Saidi@ARM.com case MISCREG_TLBIASIDIS: 3747404SAli.Saidi@ARM.com case MISCREG_TLBIASID: 3757404SAli.Saidi@ARM.com warn("Need to flush all TLBs in MP\n"); 3767404SAli.Saidi@ARM.com tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 3777404SAli.Saidi@ARM.com tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 3787404SAli.Saidi@ARM.com return; 3797404SAli.Saidi@ARM.com case MISCREG_TLBIMVAAIS: 3807404SAli.Saidi@ARM.com case MISCREG_TLBIMVAA: 3817404SAli.Saidi@ARM.com warn("Need to flush all TLBs in MP\n"); 3827404SAli.Saidi@ARM.com tc->getITBPtr()->flushMva(mbits(newVal, 31,12)); 3837404SAli.Saidi@ARM.com tc->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 3847404SAli.Saidi@ARM.com return; 3857404SAli.Saidi@ARM.com case MISCREG_ITLBIMVA: 3867404SAli.Saidi@ARM.com tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 3877404SAli.Saidi@ARM.com bits(newVal, 7,0)); 3887404SAli.Saidi@ARM.com return; 3897404SAli.Saidi@ARM.com case MISCREG_DTLBIMVA: 3907404SAli.Saidi@ARM.com tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 3917404SAli.Saidi@ARM.com bits(newVal, 7,0)); 3927404SAli.Saidi@ARM.com return; 3937404SAli.Saidi@ARM.com case MISCREG_ITLBIASID: 3947404SAli.Saidi@ARM.com tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 3957404SAli.Saidi@ARM.com return; 3967404SAli.Saidi@ARM.com case MISCREG_DTLBIASID: 3977404SAli.Saidi@ARM.com tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 3987404SAli.Saidi@ARM.com return; 3997271Sgblack@eecs.umich.edu } 4007400SAli.Saidi@ARM.com setMiscRegNoEffect(misc_reg, newVal); 4016333Sgblack@eecs.umich.edu } 4026313Sgblack@eecs.umich.edu 4036313Sgblack@eecs.umich.edu int 4046313Sgblack@eecs.umich.edu flattenIntIndex(int reg) 4056313Sgblack@eecs.umich.edu { 4066718Sgblack@eecs.umich.edu assert(reg >= 0); 4076718Sgblack@eecs.umich.edu if (reg < NUM_ARCH_INTREGS) { 4086718Sgblack@eecs.umich.edu return intRegMap[reg]; 4096726Sgblack@eecs.umich.edu } else if (reg < NUM_INTREGS) { 4106726Sgblack@eecs.umich.edu return reg; 4116718Sgblack@eecs.umich.edu } else { 4127310Sgblack@eecs.umich.edu int mode = reg / intRegsPerMode; 4137310Sgblack@eecs.umich.edu reg = reg % intRegsPerMode; 4147310Sgblack@eecs.umich.edu switch (mode) { 4157310Sgblack@eecs.umich.edu case MODE_USER: 4167310Sgblack@eecs.umich.edu case MODE_SYSTEM: 4177310Sgblack@eecs.umich.edu return INTREG_USR(reg); 4187310Sgblack@eecs.umich.edu case MODE_FIQ: 4197310Sgblack@eecs.umich.edu return INTREG_FIQ(reg); 4207310Sgblack@eecs.umich.edu case MODE_IRQ: 4217310Sgblack@eecs.umich.edu return INTREG_IRQ(reg); 4227310Sgblack@eecs.umich.edu case MODE_SVC: 4237310Sgblack@eecs.umich.edu return INTREG_SVC(reg); 4247310Sgblack@eecs.umich.edu case MODE_MON: 4257310Sgblack@eecs.umich.edu return INTREG_MON(reg); 4267310Sgblack@eecs.umich.edu case MODE_ABORT: 4277310Sgblack@eecs.umich.edu return INTREG_ABT(reg); 4287310Sgblack@eecs.umich.edu case MODE_UNDEFINED: 4297310Sgblack@eecs.umich.edu return INTREG_UND(reg); 4307310Sgblack@eecs.umich.edu default: 4317310Sgblack@eecs.umich.edu panic("Flattening into an unknown mode.\n"); 4327310Sgblack@eecs.umich.edu } 4336718Sgblack@eecs.umich.edu } 4346313Sgblack@eecs.umich.edu } 4356313Sgblack@eecs.umich.edu 4366313Sgblack@eecs.umich.edu int 4376313Sgblack@eecs.umich.edu flattenFloatIndex(int reg) 4386313Sgblack@eecs.umich.edu { 4396313Sgblack@eecs.umich.edu return reg; 4406313Sgblack@eecs.umich.edu } 4416313Sgblack@eecs.umich.edu 4426678Sgblack@eecs.umich.edu void serialize(EventManager *em, std::ostream &os) 4436333Sgblack@eecs.umich.edu {} 4446678Sgblack@eecs.umich.edu void unserialize(EventManager *em, Checkpoint *cp, 4456678Sgblack@eecs.umich.edu const std::string §ion) 4466333Sgblack@eecs.umich.edu {} 4476313Sgblack@eecs.umich.edu 4486313Sgblack@eecs.umich.edu ISA() 4496313Sgblack@eecs.umich.edu { 4507400SAli.Saidi@ARM.com SCTLR sctlr; 4517400SAli.Saidi@ARM.com sctlr = 0; 4527400SAli.Saidi@ARM.com miscRegs[MISCREG_SCTLR_RST] = sctlr; 4537400SAli.Saidi@ARM.com 4546313Sgblack@eecs.umich.edu clear(); 4556313Sgblack@eecs.umich.edu } 4566313Sgblack@eecs.umich.edu }; 4576313Sgblack@eecs.umich.edu} 4586313Sgblack@eecs.umich.edu 4596313Sgblack@eecs.umich.edu#endif 460