isa.hh revision 7393
16313Sgblack@eecs.umich.edu/* 27093Sgblack@eecs.umich.edu * Copyright (c) 2010 ARM Limited 37093Sgblack@eecs.umich.edu * All rights reserved 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67093Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77093Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87093Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97093Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107093Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117093Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127093Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137093Sgblack@eecs.umich.edu * 146313Sgblack@eecs.umich.edu * Copyright (c) 2009 The Regents of The University of Michigan 156313Sgblack@eecs.umich.edu * All rights reserved. 166313Sgblack@eecs.umich.edu * 176313Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 186313Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 196313Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 206313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 216313Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 226313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 236313Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 246313Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 256313Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 266313Sgblack@eecs.umich.edu * this software without specific prior written permission. 276313Sgblack@eecs.umich.edu * 286313Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296313Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306313Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316313Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326313Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336313Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346313Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356313Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366313Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376313Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386313Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396313Sgblack@eecs.umich.edu * 406313Sgblack@eecs.umich.edu * Authors: Gabe Black 416313Sgblack@eecs.umich.edu */ 426313Sgblack@eecs.umich.edu 436313Sgblack@eecs.umich.edu#ifndef __ARCH_ARM_ISA_HH__ 446313Sgblack@eecs.umich.edu#define __ARCH_MRM_ISA_HH__ 456313Sgblack@eecs.umich.edu 466333Sgblack@eecs.umich.edu#include "arch/arm/registers.hh" 476313Sgblack@eecs.umich.edu#include "arch/arm/types.hh" 486313Sgblack@eecs.umich.edu 496333Sgblack@eecs.umich.educlass ThreadContext; 506313Sgblack@eecs.umich.educlass Checkpoint; 516313Sgblack@eecs.umich.educlass EventManager; 526313Sgblack@eecs.umich.edu 536313Sgblack@eecs.umich.edunamespace ArmISA 546313Sgblack@eecs.umich.edu{ 556313Sgblack@eecs.umich.edu class ISA 566313Sgblack@eecs.umich.edu { 576313Sgblack@eecs.umich.edu protected: 586333Sgblack@eecs.umich.edu MiscReg miscRegs[NumMiscRegs]; 596718Sgblack@eecs.umich.edu const IntRegIndex *intRegMap; 606718Sgblack@eecs.umich.edu 616718Sgblack@eecs.umich.edu void 626718Sgblack@eecs.umich.edu updateRegMap(CPSR cpsr) 636718Sgblack@eecs.umich.edu { 646718Sgblack@eecs.umich.edu switch (cpsr.mode) { 656718Sgblack@eecs.umich.edu case MODE_USER: 666718Sgblack@eecs.umich.edu case MODE_SYSTEM: 676718Sgblack@eecs.umich.edu intRegMap = IntRegUsrMap; 686718Sgblack@eecs.umich.edu break; 696718Sgblack@eecs.umich.edu case MODE_FIQ: 706718Sgblack@eecs.umich.edu intRegMap = IntRegFiqMap; 716718Sgblack@eecs.umich.edu break; 726718Sgblack@eecs.umich.edu case MODE_IRQ: 736718Sgblack@eecs.umich.edu intRegMap = IntRegIrqMap; 746718Sgblack@eecs.umich.edu break; 756718Sgblack@eecs.umich.edu case MODE_SVC: 766718Sgblack@eecs.umich.edu intRegMap = IntRegSvcMap; 776718Sgblack@eecs.umich.edu break; 786723Sgblack@eecs.umich.edu case MODE_MON: 796723Sgblack@eecs.umich.edu intRegMap = IntRegMonMap; 806723Sgblack@eecs.umich.edu break; 816718Sgblack@eecs.umich.edu case MODE_ABORT: 826718Sgblack@eecs.umich.edu intRegMap = IntRegAbtMap; 836718Sgblack@eecs.umich.edu break; 846718Sgblack@eecs.umich.edu case MODE_UNDEFINED: 856718Sgblack@eecs.umich.edu intRegMap = IntRegUndMap; 866718Sgblack@eecs.umich.edu break; 876718Sgblack@eecs.umich.edu default: 886718Sgblack@eecs.umich.edu panic("Unrecognized mode setting in CPSR.\n"); 896718Sgblack@eecs.umich.edu } 906718Sgblack@eecs.umich.edu } 916313Sgblack@eecs.umich.edu 926313Sgblack@eecs.umich.edu public: 936333Sgblack@eecs.umich.edu void clear() 946333Sgblack@eecs.umich.edu { 956401Sgblack@eecs.umich.edu memset(miscRegs, 0, sizeof(miscRegs)); 966401Sgblack@eecs.umich.edu CPSR cpsr = 0; 976719Sgblack@eecs.umich.edu cpsr.mode = MODE_USER; 986401Sgblack@eecs.umich.edu miscRegs[MISCREG_CPSR] = cpsr; 996718Sgblack@eecs.umich.edu updateRegMap(cpsr); 1006735Sgblack@eecs.umich.edu 1016735Sgblack@eecs.umich.edu SCTLR sctlr = 0; 1026735Sgblack@eecs.umich.edu sctlr.nmfi = 1; 1036735Sgblack@eecs.umich.edu sctlr.rao1 = 1; 1046735Sgblack@eecs.umich.edu sctlr.rao2 = 1; 1056735Sgblack@eecs.umich.edu sctlr.rao3 = 1; 1066735Sgblack@eecs.umich.edu sctlr.rao4 = 1; 1077270Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR] = sctlr; 1086735Sgblack@eecs.umich.edu 1097271Sgblack@eecs.umich.edu /* 1107271Sgblack@eecs.umich.edu * Technically this should be 0, but we don't support those 1117271Sgblack@eecs.umich.edu * settings. 1127271Sgblack@eecs.umich.edu */ 1137320Sgblack@eecs.umich.edu CPACR cpacr = 0; 1147320Sgblack@eecs.umich.edu // Enable CP 10, 11 1157320Sgblack@eecs.umich.edu cpacr.cp10 = 0x3; 1167320Sgblack@eecs.umich.edu cpacr.cp11 = 0x3; 1177320Sgblack@eecs.umich.edu miscRegs[MISCREG_CPACR] = cpacr; 1187271Sgblack@eecs.umich.edu 1197350SAli.Saidi@ARM.com /* Start with an event in the mailbox */ 1207350SAli.Saidi@ARM.com miscRegs[MISCREG_SEV_MAILBOX] = 1; 1217350SAli.Saidi@ARM.com 1227298Sgblack@eecs.umich.edu /* 1237298Sgblack@eecs.umich.edu * Implemented = '5' from "M5", 1247298Sgblack@eecs.umich.edu * Variant = 0, 1257298Sgblack@eecs.umich.edu */ 1267298Sgblack@eecs.umich.edu miscRegs[MISCREG_MIDR] = 1277298Sgblack@eecs.umich.edu (0x35 << 24) | //Implementor is '5' from "M5" 1287298Sgblack@eecs.umich.edu (0 << 20) | //Variant 1297298Sgblack@eecs.umich.edu (0xf << 16) | //Architecture from CPUID scheme 1307298Sgblack@eecs.umich.edu (0 << 4) | //Primary part number 1317298Sgblack@eecs.umich.edu (0 << 0) | //Revision 1327298Sgblack@eecs.umich.edu 0; 1337298Sgblack@eecs.umich.edu 1347354Sgblack@eecs.umich.edu // Separate Instruction and Data TLBs. 1357354Sgblack@eecs.umich.edu miscRegs[MISCREG_TLBTR] = 1; 1367354Sgblack@eecs.umich.edu 1377383Sgblack@eecs.umich.edu MVFR0 mvfr0 = 0; 1387383Sgblack@eecs.umich.edu mvfr0.advSimdRegisters = 2; 1397383Sgblack@eecs.umich.edu mvfr0.singlePrecision = 2; 1407383Sgblack@eecs.umich.edu mvfr0.doublePrecision = 2; 1417383Sgblack@eecs.umich.edu mvfr0.vfpExceptionTrapping = 0; 1427383Sgblack@eecs.umich.edu mvfr0.divide = 1; 1437383Sgblack@eecs.umich.edu mvfr0.squareRoot = 1; 1447383Sgblack@eecs.umich.edu mvfr0.shortVectors = 1; 1457383Sgblack@eecs.umich.edu mvfr0.roundingModes = 1; 1467383Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR0] = mvfr0; 1477383Sgblack@eecs.umich.edu 1487383Sgblack@eecs.umich.edu MVFR1 mvfr1 = 0; 1497383Sgblack@eecs.umich.edu mvfr1.flushToZero = 1; 1507383Sgblack@eecs.umich.edu mvfr1.defaultNaN = 1; 1517383Sgblack@eecs.umich.edu mvfr1.advSimdLoadStore = 1; 1527383Sgblack@eecs.umich.edu mvfr1.advSimdInteger = 1; 1537383Sgblack@eecs.umich.edu mvfr1.advSimdSinglePrecision = 1; 1547383Sgblack@eecs.umich.edu mvfr1.advSimdHalfPrecision = 1; 1557383Sgblack@eecs.umich.edu mvfr1.vfpHalfPrecision = 1; 1567383Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR1] = mvfr1; 1577383Sgblack@eecs.umich.edu 1587390Sgblack@eecs.umich.edu miscRegs[MISCREG_MPIDR] = 0; 1597390Sgblack@eecs.umich.edu 1606401Sgblack@eecs.umich.edu //XXX We need to initialize the rest of the state. 1616333Sgblack@eecs.umich.edu } 1626313Sgblack@eecs.umich.edu 1636333Sgblack@eecs.umich.edu MiscReg 1646333Sgblack@eecs.umich.edu readMiscRegNoEffect(int misc_reg) 1656333Sgblack@eecs.umich.edu { 1666333Sgblack@eecs.umich.edu assert(misc_reg < NumMiscRegs); 1676745Sgblack@eecs.umich.edu if (misc_reg == MISCREG_SPSR) { 1686745Sgblack@eecs.umich.edu CPSR cpsr = miscRegs[MISCREG_CPSR]; 1696745Sgblack@eecs.umich.edu switch (cpsr.mode) { 1706745Sgblack@eecs.umich.edu case MODE_USER: 1716745Sgblack@eecs.umich.edu return miscRegs[MISCREG_SPSR]; 1726745Sgblack@eecs.umich.edu case MODE_FIQ: 1736745Sgblack@eecs.umich.edu return miscRegs[MISCREG_SPSR_FIQ]; 1746745Sgblack@eecs.umich.edu case MODE_IRQ: 1756745Sgblack@eecs.umich.edu return miscRegs[MISCREG_SPSR_IRQ]; 1766745Sgblack@eecs.umich.edu case MODE_SVC: 1776745Sgblack@eecs.umich.edu return miscRegs[MISCREG_SPSR_SVC]; 1786745Sgblack@eecs.umich.edu case MODE_MON: 1796745Sgblack@eecs.umich.edu return miscRegs[MISCREG_SPSR_MON]; 1806745Sgblack@eecs.umich.edu case MODE_ABORT: 1816745Sgblack@eecs.umich.edu return miscRegs[MISCREG_SPSR_ABT]; 1826745Sgblack@eecs.umich.edu case MODE_UNDEFINED: 1836745Sgblack@eecs.umich.edu return miscRegs[MISCREG_SPSR_UND]; 1846745Sgblack@eecs.umich.edu default: 1856745Sgblack@eecs.umich.edu return miscRegs[MISCREG_SPSR]; 1866745Sgblack@eecs.umich.edu } 1876745Sgblack@eecs.umich.edu } 1886333Sgblack@eecs.umich.edu return miscRegs[misc_reg]; 1896333Sgblack@eecs.umich.edu } 1906313Sgblack@eecs.umich.edu 1916333Sgblack@eecs.umich.edu MiscReg 1926333Sgblack@eecs.umich.edu readMiscReg(int misc_reg, ThreadContext *tc) 1936333Sgblack@eecs.umich.edu { 1947093Sgblack@eecs.umich.edu if (misc_reg == MISCREG_CPSR) { 1957093Sgblack@eecs.umich.edu CPSR cpsr = miscRegs[misc_reg]; 1967093Sgblack@eecs.umich.edu Addr pc = tc->readPC(); 1977093Sgblack@eecs.umich.edu if (pc & (ULL(1) << PcJBitShift)) 1987093Sgblack@eecs.umich.edu cpsr.j = 1; 1997093Sgblack@eecs.umich.edu else 2007093Sgblack@eecs.umich.edu cpsr.j = 0; 2017093Sgblack@eecs.umich.edu if (pc & (ULL(1) << PcTBitShift)) 2027093Sgblack@eecs.umich.edu cpsr.t = 1; 2037093Sgblack@eecs.umich.edu else 2047093Sgblack@eecs.umich.edu cpsr.t = 0; 2057093Sgblack@eecs.umich.edu return cpsr; 2067093Sgblack@eecs.umich.edu } 2077259Sgblack@eecs.umich.edu if (misc_reg >= MISCREG_CP15_UNIMP_START && 2087259Sgblack@eecs.umich.edu misc_reg < MISCREG_CP15_END) { 2097259Sgblack@eecs.umich.edu panic("Unimplemented CP15 register %s read.\n", 2107259Sgblack@eecs.umich.edu miscRegName[misc_reg]); 2117259Sgblack@eecs.umich.edu } 2127273Sgblack@eecs.umich.edu switch (misc_reg) { 2137273Sgblack@eecs.umich.edu case MISCREG_CLIDR: 2147273Sgblack@eecs.umich.edu warn("The clidr register always reports 0 caches.\n"); 2157273Sgblack@eecs.umich.edu break; 2167287Sgblack@eecs.umich.edu case MISCREG_CCSIDR: 2177287Sgblack@eecs.umich.edu warn("The ccsidr register isn't implemented and " 2187287Sgblack@eecs.umich.edu "always reads as 0.\n"); 2197287Sgblack@eecs.umich.edu break; 2207273Sgblack@eecs.umich.edu } 2216745Sgblack@eecs.umich.edu return readMiscRegNoEffect(misc_reg); 2226333Sgblack@eecs.umich.edu } 2236333Sgblack@eecs.umich.edu 2246333Sgblack@eecs.umich.edu void 2256333Sgblack@eecs.umich.edu setMiscRegNoEffect(int misc_reg, const MiscReg &val) 2266333Sgblack@eecs.umich.edu { 2276333Sgblack@eecs.umich.edu assert(misc_reg < NumMiscRegs); 2286745Sgblack@eecs.umich.edu if (misc_reg == MISCREG_SPSR) { 2296745Sgblack@eecs.umich.edu CPSR cpsr = miscRegs[MISCREG_CPSR]; 2306745Sgblack@eecs.umich.edu switch (cpsr.mode) { 2316745Sgblack@eecs.umich.edu case MODE_USER: 2326745Sgblack@eecs.umich.edu miscRegs[MISCREG_SPSR] = val; 2336745Sgblack@eecs.umich.edu return; 2346745Sgblack@eecs.umich.edu case MODE_FIQ: 2356745Sgblack@eecs.umich.edu miscRegs[MISCREG_SPSR_FIQ] = val; 2366745Sgblack@eecs.umich.edu return; 2376745Sgblack@eecs.umich.edu case MODE_IRQ: 2386745Sgblack@eecs.umich.edu miscRegs[MISCREG_SPSR_IRQ] = val; 2396745Sgblack@eecs.umich.edu return; 2406745Sgblack@eecs.umich.edu case MODE_SVC: 2416745Sgblack@eecs.umich.edu miscRegs[MISCREG_SPSR_SVC] = val; 2426745Sgblack@eecs.umich.edu return; 2436745Sgblack@eecs.umich.edu case MODE_MON: 2446745Sgblack@eecs.umich.edu miscRegs[MISCREG_SPSR_MON] = val; 2456745Sgblack@eecs.umich.edu return; 2466745Sgblack@eecs.umich.edu case MODE_ABORT: 2476745Sgblack@eecs.umich.edu miscRegs[MISCREG_SPSR_ABT] = val; 2486745Sgblack@eecs.umich.edu return; 2496745Sgblack@eecs.umich.edu case MODE_UNDEFINED: 2506745Sgblack@eecs.umich.edu miscRegs[MISCREG_SPSR_UND] = val; 2516745Sgblack@eecs.umich.edu return; 2526745Sgblack@eecs.umich.edu default: 2536745Sgblack@eecs.umich.edu miscRegs[MISCREG_SPSR] = val; 2546745Sgblack@eecs.umich.edu return; 2556745Sgblack@eecs.umich.edu } 2566745Sgblack@eecs.umich.edu } 2576333Sgblack@eecs.umich.edu miscRegs[misc_reg] = val; 2586333Sgblack@eecs.umich.edu } 2596333Sgblack@eecs.umich.edu 2606333Sgblack@eecs.umich.edu void 2616333Sgblack@eecs.umich.edu setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 2626333Sgblack@eecs.umich.edu { 2637271Sgblack@eecs.umich.edu MiscReg newVal = val; 2646718Sgblack@eecs.umich.edu if (misc_reg == MISCREG_CPSR) { 2656718Sgblack@eecs.umich.edu updateRegMap(val); 2667093Sgblack@eecs.umich.edu CPSR cpsr = val; 2677348SAli.Saidi@ARM.com DPRINTF(Arm, "Updating CPSR to %#x f:%d i:%d a:%d mode:%#x\n", 2687348SAli.Saidi@ARM.com cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 2697093Sgblack@eecs.umich.edu Addr npc = tc->readNextPC() & ~PcModeMask; 2707093Sgblack@eecs.umich.edu if (cpsr.j) 2717093Sgblack@eecs.umich.edu npc = npc | (ULL(1) << PcJBitShift); 2727093Sgblack@eecs.umich.edu if (cpsr.t) 2737093Sgblack@eecs.umich.edu npc = npc | (ULL(1) << PcTBitShift); 2747093Sgblack@eecs.umich.edu 2757093Sgblack@eecs.umich.edu tc->setNextPC(npc); 2766718Sgblack@eecs.umich.edu } 2777259Sgblack@eecs.umich.edu if (misc_reg >= MISCREG_CP15_UNIMP_START && 2787259Sgblack@eecs.umich.edu misc_reg < MISCREG_CP15_END) { 2797259Sgblack@eecs.umich.edu panic("Unimplemented CP15 register %s wrote with %#x.\n", 2807259Sgblack@eecs.umich.edu miscRegName[misc_reg], val); 2817259Sgblack@eecs.umich.edu } 2827271Sgblack@eecs.umich.edu switch (misc_reg) { 2837271Sgblack@eecs.umich.edu case MISCREG_CPACR: 2847320Sgblack@eecs.umich.edu { 2857320Sgblack@eecs.umich.edu CPACR newCpacr = 0; 2867320Sgblack@eecs.umich.edu CPACR valCpacr = val; 2877320Sgblack@eecs.umich.edu newCpacr.cp10 = valCpacr.cp10; 2887320Sgblack@eecs.umich.edu newCpacr.cp11 = valCpacr.cp11; 2897320Sgblack@eecs.umich.edu if (newCpacr.cp10 != 0x3 || newCpacr.cp11 != 3) { 2907320Sgblack@eecs.umich.edu panic("Disabling coprocessors isn't implemented.\n"); 2917320Sgblack@eecs.umich.edu } 2927320Sgblack@eecs.umich.edu newVal = newCpacr; 2937271Sgblack@eecs.umich.edu } 2947271Sgblack@eecs.umich.edu break; 2957287Sgblack@eecs.umich.edu case MISCREG_CSSELR: 2967287Sgblack@eecs.umich.edu warn("The csselr register isn't implemented.\n"); 2977287Sgblack@eecs.umich.edu break; 2987393Sgblack@eecs.umich.edu case MISCREG_FPSCR: 2997393Sgblack@eecs.umich.edu { 3007393Sgblack@eecs.umich.edu const uint32_t ones = (uint32_t)(-1); 3017393Sgblack@eecs.umich.edu FPSCR fpscrMask = 0; 3027393Sgblack@eecs.umich.edu fpscrMask.ioc = ones; 3037393Sgblack@eecs.umich.edu fpscrMask.dzc = ones; 3047393Sgblack@eecs.umich.edu fpscrMask.ofc = ones; 3057393Sgblack@eecs.umich.edu fpscrMask.ufc = ones; 3067393Sgblack@eecs.umich.edu fpscrMask.ixc = ones; 3077393Sgblack@eecs.umich.edu fpscrMask.idc = ones; 3087393Sgblack@eecs.umich.edu fpscrMask.len = ones; 3097393Sgblack@eecs.umich.edu fpscrMask.stride = ones; 3107393Sgblack@eecs.umich.edu fpscrMask.rMode = ones; 3117393Sgblack@eecs.umich.edu fpscrMask.fz = ones; 3127393Sgblack@eecs.umich.edu fpscrMask.dn = ones; 3137393Sgblack@eecs.umich.edu fpscrMask.ahp = ones; 3147393Sgblack@eecs.umich.edu fpscrMask.qc = ones; 3157393Sgblack@eecs.umich.edu fpscrMask.v = ones; 3167393Sgblack@eecs.umich.edu fpscrMask.c = ones; 3177393Sgblack@eecs.umich.edu fpscrMask.z = ones; 3187393Sgblack@eecs.umich.edu fpscrMask.n = ones; 3197393Sgblack@eecs.umich.edu newVal = (newVal & (uint32_t)fpscrMask) | 3207393Sgblack@eecs.umich.edu (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask); 3217393Sgblack@eecs.umich.edu } 3227393Sgblack@eecs.umich.edu break; 3237393Sgblack@eecs.umich.edu case MISCREG_FPEXC: 3247393Sgblack@eecs.umich.edu { 3257393Sgblack@eecs.umich.edu const uint32_t fpexcMask = 0x60000000; 3267393Sgblack@eecs.umich.edu newVal = (newVal & fpexcMask) | 3277393Sgblack@eecs.umich.edu (miscRegs[MISCREG_FPEXC] & ~fpexcMask); 3287393Sgblack@eecs.umich.edu } 3297393Sgblack@eecs.umich.edu break; 3307354Sgblack@eecs.umich.edu case MISCREG_TLBTR: 3317383Sgblack@eecs.umich.edu case MISCREG_MVFR0: 3327383Sgblack@eecs.umich.edu case MISCREG_MVFR1: 3337390Sgblack@eecs.umich.edu case MISCREG_MPIDR: 3347393Sgblack@eecs.umich.edu case MISCREG_FPSID: 3357354Sgblack@eecs.umich.edu return; 3367271Sgblack@eecs.umich.edu } 3377271Sgblack@eecs.umich.edu return setMiscRegNoEffect(misc_reg, newVal); 3386333Sgblack@eecs.umich.edu } 3396313Sgblack@eecs.umich.edu 3406313Sgblack@eecs.umich.edu int 3416313Sgblack@eecs.umich.edu flattenIntIndex(int reg) 3426313Sgblack@eecs.umich.edu { 3436718Sgblack@eecs.umich.edu assert(reg >= 0); 3446718Sgblack@eecs.umich.edu if (reg < NUM_ARCH_INTREGS) { 3456718Sgblack@eecs.umich.edu return intRegMap[reg]; 3466726Sgblack@eecs.umich.edu } else if (reg < NUM_INTREGS) { 3476726Sgblack@eecs.umich.edu return reg; 3486718Sgblack@eecs.umich.edu } else { 3497310Sgblack@eecs.umich.edu int mode = reg / intRegsPerMode; 3507310Sgblack@eecs.umich.edu reg = reg % intRegsPerMode; 3517310Sgblack@eecs.umich.edu switch (mode) { 3527310Sgblack@eecs.umich.edu case MODE_USER: 3537310Sgblack@eecs.umich.edu case MODE_SYSTEM: 3547310Sgblack@eecs.umich.edu return INTREG_USR(reg); 3557310Sgblack@eecs.umich.edu case MODE_FIQ: 3567310Sgblack@eecs.umich.edu return INTREG_FIQ(reg); 3577310Sgblack@eecs.umich.edu case MODE_IRQ: 3587310Sgblack@eecs.umich.edu return INTREG_IRQ(reg); 3597310Sgblack@eecs.umich.edu case MODE_SVC: 3607310Sgblack@eecs.umich.edu return INTREG_SVC(reg); 3617310Sgblack@eecs.umich.edu case MODE_MON: 3627310Sgblack@eecs.umich.edu return INTREG_MON(reg); 3637310Sgblack@eecs.umich.edu case MODE_ABORT: 3647310Sgblack@eecs.umich.edu return INTREG_ABT(reg); 3657310Sgblack@eecs.umich.edu case MODE_UNDEFINED: 3667310Sgblack@eecs.umich.edu return INTREG_UND(reg); 3677310Sgblack@eecs.umich.edu default: 3687310Sgblack@eecs.umich.edu panic("Flattening into an unknown mode.\n"); 3697310Sgblack@eecs.umich.edu } 3706718Sgblack@eecs.umich.edu } 3716313Sgblack@eecs.umich.edu } 3726313Sgblack@eecs.umich.edu 3736313Sgblack@eecs.umich.edu int 3746313Sgblack@eecs.umich.edu flattenFloatIndex(int reg) 3756313Sgblack@eecs.umich.edu { 3766313Sgblack@eecs.umich.edu return reg; 3776313Sgblack@eecs.umich.edu } 3786313Sgblack@eecs.umich.edu 3796678Sgblack@eecs.umich.edu void serialize(EventManager *em, std::ostream &os) 3806333Sgblack@eecs.umich.edu {} 3816678Sgblack@eecs.umich.edu void unserialize(EventManager *em, Checkpoint *cp, 3826678Sgblack@eecs.umich.edu const std::string §ion) 3836333Sgblack@eecs.umich.edu {} 3846313Sgblack@eecs.umich.edu 3856313Sgblack@eecs.umich.edu ISA() 3866313Sgblack@eecs.umich.edu { 3876313Sgblack@eecs.umich.edu clear(); 3886313Sgblack@eecs.umich.edu } 3896313Sgblack@eecs.umich.edu }; 3906313Sgblack@eecs.umich.edu} 3916313Sgblack@eecs.umich.edu 3926313Sgblack@eecs.umich.edu#endif 393