isa.hh revision 7298
16313Sgblack@eecs.umich.edu/* 27093Sgblack@eecs.umich.edu * Copyright (c) 2010 ARM Limited 37093Sgblack@eecs.umich.edu * All rights reserved 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67093Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77093Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87093Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97093Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107093Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117093Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127093Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137093Sgblack@eecs.umich.edu * 146313Sgblack@eecs.umich.edu * Copyright (c) 2009 The Regents of The University of Michigan 156313Sgblack@eecs.umich.edu * All rights reserved. 166313Sgblack@eecs.umich.edu * 176313Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 186313Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 196313Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 206313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 216313Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 226313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 236313Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 246313Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 256313Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 266313Sgblack@eecs.umich.edu * this software without specific prior written permission. 276313Sgblack@eecs.umich.edu * 286313Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296313Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306313Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316313Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326313Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336313Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346313Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356313Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366313Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376313Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386313Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396313Sgblack@eecs.umich.edu * 406313Sgblack@eecs.umich.edu * Authors: Gabe Black 416313Sgblack@eecs.umich.edu */ 426313Sgblack@eecs.umich.edu 436313Sgblack@eecs.umich.edu#ifndef __ARCH_ARM_ISA_HH__ 446313Sgblack@eecs.umich.edu#define __ARCH_MRM_ISA_HH__ 456313Sgblack@eecs.umich.edu 466333Sgblack@eecs.umich.edu#include "arch/arm/registers.hh" 476313Sgblack@eecs.umich.edu#include "arch/arm/types.hh" 486313Sgblack@eecs.umich.edu 496333Sgblack@eecs.umich.educlass ThreadContext; 506313Sgblack@eecs.umich.educlass Checkpoint; 516313Sgblack@eecs.umich.educlass EventManager; 526313Sgblack@eecs.umich.edu 536313Sgblack@eecs.umich.edunamespace ArmISA 546313Sgblack@eecs.umich.edu{ 556313Sgblack@eecs.umich.edu class ISA 566313Sgblack@eecs.umich.edu { 576313Sgblack@eecs.umich.edu protected: 586333Sgblack@eecs.umich.edu MiscReg miscRegs[NumMiscRegs]; 596718Sgblack@eecs.umich.edu const IntRegIndex *intRegMap; 606718Sgblack@eecs.umich.edu 616718Sgblack@eecs.umich.edu void 626718Sgblack@eecs.umich.edu updateRegMap(CPSR cpsr) 636718Sgblack@eecs.umich.edu { 646718Sgblack@eecs.umich.edu switch (cpsr.mode) { 656718Sgblack@eecs.umich.edu case MODE_USER: 666718Sgblack@eecs.umich.edu case MODE_SYSTEM: 676718Sgblack@eecs.umich.edu intRegMap = IntRegUsrMap; 686718Sgblack@eecs.umich.edu break; 696718Sgblack@eecs.umich.edu case MODE_FIQ: 706718Sgblack@eecs.umich.edu intRegMap = IntRegFiqMap; 716718Sgblack@eecs.umich.edu break; 726718Sgblack@eecs.umich.edu case MODE_IRQ: 736718Sgblack@eecs.umich.edu intRegMap = IntRegIrqMap; 746718Sgblack@eecs.umich.edu break; 756718Sgblack@eecs.umich.edu case MODE_SVC: 766718Sgblack@eecs.umich.edu intRegMap = IntRegSvcMap; 776718Sgblack@eecs.umich.edu break; 786723Sgblack@eecs.umich.edu case MODE_MON: 796723Sgblack@eecs.umich.edu intRegMap = IntRegMonMap; 806723Sgblack@eecs.umich.edu break; 816718Sgblack@eecs.umich.edu case MODE_ABORT: 826718Sgblack@eecs.umich.edu intRegMap = IntRegAbtMap; 836718Sgblack@eecs.umich.edu break; 846718Sgblack@eecs.umich.edu case MODE_UNDEFINED: 856718Sgblack@eecs.umich.edu intRegMap = IntRegUndMap; 866718Sgblack@eecs.umich.edu break; 876718Sgblack@eecs.umich.edu default: 886718Sgblack@eecs.umich.edu panic("Unrecognized mode setting in CPSR.\n"); 896718Sgblack@eecs.umich.edu } 906718Sgblack@eecs.umich.edu } 916313Sgblack@eecs.umich.edu 926313Sgblack@eecs.umich.edu public: 936333Sgblack@eecs.umich.edu void clear() 946333Sgblack@eecs.umich.edu { 956401Sgblack@eecs.umich.edu memset(miscRegs, 0, sizeof(miscRegs)); 966401Sgblack@eecs.umich.edu CPSR cpsr = 0; 976719Sgblack@eecs.umich.edu cpsr.mode = MODE_USER; 986401Sgblack@eecs.umich.edu miscRegs[MISCREG_CPSR] = cpsr; 996718Sgblack@eecs.umich.edu updateRegMap(cpsr); 1006735Sgblack@eecs.umich.edu 1016735Sgblack@eecs.umich.edu SCTLR sctlr = 0; 1026735Sgblack@eecs.umich.edu sctlr.nmfi = 1; 1036735Sgblack@eecs.umich.edu sctlr.rao1 = 1; 1046735Sgblack@eecs.umich.edu sctlr.rao2 = 1; 1056735Sgblack@eecs.umich.edu sctlr.rao3 = 1; 1066735Sgblack@eecs.umich.edu sctlr.rao4 = 1; 1077270Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR] = sctlr; 1086735Sgblack@eecs.umich.edu 1097271Sgblack@eecs.umich.edu /* 1107271Sgblack@eecs.umich.edu * Technically this should be 0, but we don't support those 1117271Sgblack@eecs.umich.edu * settings. 1127271Sgblack@eecs.umich.edu */ 1137271Sgblack@eecs.umich.edu miscRegs[MISCREG_CPACR] = 0x0fffffff; 1147271Sgblack@eecs.umich.edu 1157298Sgblack@eecs.umich.edu /* One region, unified map. */ 1167298Sgblack@eecs.umich.edu miscRegs[MISCREG_MPUIR] = 0x100; 1177298Sgblack@eecs.umich.edu 1187298Sgblack@eecs.umich.edu /* 1197298Sgblack@eecs.umich.edu * Implemented = '5' from "M5", 1207298Sgblack@eecs.umich.edu * Variant = 0, 1217298Sgblack@eecs.umich.edu */ 1227298Sgblack@eecs.umich.edu miscRegs[MISCREG_MIDR] = 1237298Sgblack@eecs.umich.edu (0x35 << 24) | //Implementor is '5' from "M5" 1247298Sgblack@eecs.umich.edu (0 << 20) | //Variant 1257298Sgblack@eecs.umich.edu (0xf << 16) | //Architecture from CPUID scheme 1267298Sgblack@eecs.umich.edu (0 << 4) | //Primary part number 1277298Sgblack@eecs.umich.edu (0 << 0) | //Revision 1287298Sgblack@eecs.umich.edu 0; 1297298Sgblack@eecs.umich.edu 1306401Sgblack@eecs.umich.edu //XXX We need to initialize the rest of the state. 1316333Sgblack@eecs.umich.edu } 1326313Sgblack@eecs.umich.edu 1336333Sgblack@eecs.umich.edu MiscReg 1346333Sgblack@eecs.umich.edu readMiscRegNoEffect(int misc_reg) 1356333Sgblack@eecs.umich.edu { 1366333Sgblack@eecs.umich.edu assert(misc_reg < NumMiscRegs); 1376745Sgblack@eecs.umich.edu if (misc_reg == MISCREG_SPSR) { 1386745Sgblack@eecs.umich.edu CPSR cpsr = miscRegs[MISCREG_CPSR]; 1396745Sgblack@eecs.umich.edu switch (cpsr.mode) { 1406745Sgblack@eecs.umich.edu case MODE_USER: 1416745Sgblack@eecs.umich.edu return miscRegs[MISCREG_SPSR]; 1426745Sgblack@eecs.umich.edu case MODE_FIQ: 1436745Sgblack@eecs.umich.edu return miscRegs[MISCREG_SPSR_FIQ]; 1446745Sgblack@eecs.umich.edu case MODE_IRQ: 1456745Sgblack@eecs.umich.edu return miscRegs[MISCREG_SPSR_IRQ]; 1466745Sgblack@eecs.umich.edu case MODE_SVC: 1476745Sgblack@eecs.umich.edu return miscRegs[MISCREG_SPSR_SVC]; 1486745Sgblack@eecs.umich.edu case MODE_MON: 1496745Sgblack@eecs.umich.edu return miscRegs[MISCREG_SPSR_MON]; 1506745Sgblack@eecs.umich.edu case MODE_ABORT: 1516745Sgblack@eecs.umich.edu return miscRegs[MISCREG_SPSR_ABT]; 1526745Sgblack@eecs.umich.edu case MODE_UNDEFINED: 1536745Sgblack@eecs.umich.edu return miscRegs[MISCREG_SPSR_UND]; 1546745Sgblack@eecs.umich.edu default: 1556745Sgblack@eecs.umich.edu return miscRegs[MISCREG_SPSR]; 1566745Sgblack@eecs.umich.edu } 1576745Sgblack@eecs.umich.edu } 1586333Sgblack@eecs.umich.edu return miscRegs[misc_reg]; 1596333Sgblack@eecs.umich.edu } 1606313Sgblack@eecs.umich.edu 1616333Sgblack@eecs.umich.edu MiscReg 1626333Sgblack@eecs.umich.edu readMiscReg(int misc_reg, ThreadContext *tc) 1636333Sgblack@eecs.umich.edu { 1647093Sgblack@eecs.umich.edu if (misc_reg == MISCREG_CPSR) { 1657093Sgblack@eecs.umich.edu CPSR cpsr = miscRegs[misc_reg]; 1667093Sgblack@eecs.umich.edu Addr pc = tc->readPC(); 1677093Sgblack@eecs.umich.edu if (pc & (ULL(1) << PcJBitShift)) 1687093Sgblack@eecs.umich.edu cpsr.j = 1; 1697093Sgblack@eecs.umich.edu else 1707093Sgblack@eecs.umich.edu cpsr.j = 0; 1717093Sgblack@eecs.umich.edu if (pc & (ULL(1) << PcTBitShift)) 1727093Sgblack@eecs.umich.edu cpsr.t = 1; 1737093Sgblack@eecs.umich.edu else 1747093Sgblack@eecs.umich.edu cpsr.t = 0; 1757093Sgblack@eecs.umich.edu return cpsr; 1767093Sgblack@eecs.umich.edu } 1777259Sgblack@eecs.umich.edu if (misc_reg >= MISCREG_CP15_UNIMP_START && 1787259Sgblack@eecs.umich.edu misc_reg < MISCREG_CP15_END) { 1797259Sgblack@eecs.umich.edu panic("Unimplemented CP15 register %s read.\n", 1807259Sgblack@eecs.umich.edu miscRegName[misc_reg]); 1817259Sgblack@eecs.umich.edu } 1827273Sgblack@eecs.umich.edu switch (misc_reg) { 1837273Sgblack@eecs.umich.edu case MISCREG_CLIDR: 1847273Sgblack@eecs.umich.edu warn("The clidr register always reports 0 caches.\n"); 1857273Sgblack@eecs.umich.edu break; 1867287Sgblack@eecs.umich.edu case MISCREG_CCSIDR: 1877287Sgblack@eecs.umich.edu warn("The ccsidr register isn't implemented and " 1887287Sgblack@eecs.umich.edu "always reads as 0.\n"); 1897287Sgblack@eecs.umich.edu break; 1907273Sgblack@eecs.umich.edu } 1916745Sgblack@eecs.umich.edu return readMiscRegNoEffect(misc_reg); 1926333Sgblack@eecs.umich.edu } 1936333Sgblack@eecs.umich.edu 1946333Sgblack@eecs.umich.edu void 1956333Sgblack@eecs.umich.edu setMiscRegNoEffect(int misc_reg, const MiscReg &val) 1966333Sgblack@eecs.umich.edu { 1976333Sgblack@eecs.umich.edu assert(misc_reg < NumMiscRegs); 1986745Sgblack@eecs.umich.edu if (misc_reg == MISCREG_SPSR) { 1996745Sgblack@eecs.umich.edu CPSR cpsr = miscRegs[MISCREG_CPSR]; 2006745Sgblack@eecs.umich.edu switch (cpsr.mode) { 2016745Sgblack@eecs.umich.edu case MODE_USER: 2026745Sgblack@eecs.umich.edu miscRegs[MISCREG_SPSR] = val; 2036745Sgblack@eecs.umich.edu return; 2046745Sgblack@eecs.umich.edu case MODE_FIQ: 2056745Sgblack@eecs.umich.edu miscRegs[MISCREG_SPSR_FIQ] = val; 2066745Sgblack@eecs.umich.edu return; 2076745Sgblack@eecs.umich.edu case MODE_IRQ: 2086745Sgblack@eecs.umich.edu miscRegs[MISCREG_SPSR_IRQ] = val; 2096745Sgblack@eecs.umich.edu return; 2106745Sgblack@eecs.umich.edu case MODE_SVC: 2116745Sgblack@eecs.umich.edu miscRegs[MISCREG_SPSR_SVC] = val; 2126745Sgblack@eecs.umich.edu return; 2136745Sgblack@eecs.umich.edu case MODE_MON: 2146745Sgblack@eecs.umich.edu miscRegs[MISCREG_SPSR_MON] = val; 2156745Sgblack@eecs.umich.edu return; 2166745Sgblack@eecs.umich.edu case MODE_ABORT: 2176745Sgblack@eecs.umich.edu miscRegs[MISCREG_SPSR_ABT] = val; 2186745Sgblack@eecs.umich.edu return; 2196745Sgblack@eecs.umich.edu case MODE_UNDEFINED: 2206745Sgblack@eecs.umich.edu miscRegs[MISCREG_SPSR_UND] = val; 2216745Sgblack@eecs.umich.edu return; 2226745Sgblack@eecs.umich.edu default: 2236745Sgblack@eecs.umich.edu miscRegs[MISCREG_SPSR] = val; 2246745Sgblack@eecs.umich.edu return; 2256745Sgblack@eecs.umich.edu } 2266745Sgblack@eecs.umich.edu } 2276333Sgblack@eecs.umich.edu miscRegs[misc_reg] = val; 2286333Sgblack@eecs.umich.edu } 2296333Sgblack@eecs.umich.edu 2306333Sgblack@eecs.umich.edu void 2316333Sgblack@eecs.umich.edu setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 2326333Sgblack@eecs.umich.edu { 2337271Sgblack@eecs.umich.edu MiscReg newVal = val; 2346718Sgblack@eecs.umich.edu if (misc_reg == MISCREG_CPSR) { 2356718Sgblack@eecs.umich.edu updateRegMap(val); 2367093Sgblack@eecs.umich.edu CPSR cpsr = val; 2377093Sgblack@eecs.umich.edu Addr npc = tc->readNextPC() & ~PcModeMask; 2387093Sgblack@eecs.umich.edu if (cpsr.j) 2397093Sgblack@eecs.umich.edu npc = npc | (ULL(1) << PcJBitShift); 2407093Sgblack@eecs.umich.edu if (cpsr.t) 2417093Sgblack@eecs.umich.edu npc = npc | (ULL(1) << PcTBitShift); 2427093Sgblack@eecs.umich.edu 2437093Sgblack@eecs.umich.edu tc->setNextPC(npc); 2446718Sgblack@eecs.umich.edu } 2457259Sgblack@eecs.umich.edu if (misc_reg >= MISCREG_CP15_UNIMP_START && 2467259Sgblack@eecs.umich.edu misc_reg < MISCREG_CP15_END) { 2477259Sgblack@eecs.umich.edu panic("Unimplemented CP15 register %s wrote with %#x.\n", 2487259Sgblack@eecs.umich.edu miscRegName[misc_reg], val); 2497259Sgblack@eecs.umich.edu } 2507271Sgblack@eecs.umich.edu switch (misc_reg) { 2517271Sgblack@eecs.umich.edu case MISCREG_CPACR: 2527271Sgblack@eecs.umich.edu newVal = bits(val, 27, 0); 2537271Sgblack@eecs.umich.edu if (newVal != 0x0fffffff) { 2547271Sgblack@eecs.umich.edu panic("Disabling coprocessors isn't implemented.\n"); 2557271Sgblack@eecs.umich.edu } 2567271Sgblack@eecs.umich.edu break; 2577287Sgblack@eecs.umich.edu case MISCREG_CSSELR: 2587287Sgblack@eecs.umich.edu warn("The csselr register isn't implemented.\n"); 2597287Sgblack@eecs.umich.edu break; 2607271Sgblack@eecs.umich.edu } 2617271Sgblack@eecs.umich.edu return setMiscRegNoEffect(misc_reg, newVal); 2626333Sgblack@eecs.umich.edu } 2636313Sgblack@eecs.umich.edu 2646313Sgblack@eecs.umich.edu int 2656313Sgblack@eecs.umich.edu flattenIntIndex(int reg) 2666313Sgblack@eecs.umich.edu { 2676718Sgblack@eecs.umich.edu assert(reg >= 0); 2686718Sgblack@eecs.umich.edu if (reg < NUM_ARCH_INTREGS) { 2696718Sgblack@eecs.umich.edu return intRegMap[reg]; 2706726Sgblack@eecs.umich.edu } else if (reg < NUM_INTREGS) { 2716726Sgblack@eecs.umich.edu return reg; 2726718Sgblack@eecs.umich.edu } else { 2736726Sgblack@eecs.umich.edu reg -= NUM_INTREGS; 2746726Sgblack@eecs.umich.edu assert(reg < NUM_ARCH_INTREGS); 2756718Sgblack@eecs.umich.edu return reg; 2766718Sgblack@eecs.umich.edu } 2776313Sgblack@eecs.umich.edu } 2786313Sgblack@eecs.umich.edu 2796313Sgblack@eecs.umich.edu int 2806313Sgblack@eecs.umich.edu flattenFloatIndex(int reg) 2816313Sgblack@eecs.umich.edu { 2826313Sgblack@eecs.umich.edu return reg; 2836313Sgblack@eecs.umich.edu } 2846313Sgblack@eecs.umich.edu 2856678Sgblack@eecs.umich.edu void serialize(EventManager *em, std::ostream &os) 2866333Sgblack@eecs.umich.edu {} 2876678Sgblack@eecs.umich.edu void unserialize(EventManager *em, Checkpoint *cp, 2886678Sgblack@eecs.umich.edu const std::string §ion) 2896333Sgblack@eecs.umich.edu {} 2906313Sgblack@eecs.umich.edu 2916313Sgblack@eecs.umich.edu ISA() 2926313Sgblack@eecs.umich.edu { 2936313Sgblack@eecs.umich.edu clear(); 2946313Sgblack@eecs.umich.edu } 2956313Sgblack@eecs.umich.edu }; 2966313Sgblack@eecs.umich.edu} 2976313Sgblack@eecs.umich.edu 2986313Sgblack@eecs.umich.edu#endif 299