isa.hh revision 6718
16821SN/A/* 26821SN/A * Copyright (c) 2009 The Regents of The University of Michigan 36821SN/A * All rights reserved. 46821SN/A * 56821SN/A * Redistribution and use in source and binary forms, with or without 66821SN/A * modification, are permitted provided that the following conditions are 76821SN/A * met: redistributions of source code must retain the above copyright 86821SN/A * notice, this list of conditions and the following disclaimer; 96821SN/A * redistributions in binary form must reproduce the above copyright 106821SN/A * notice, this list of conditions and the following disclaimer in the 116821SN/A * documentation and/or other materials provided with the distribution; 126821SN/A * neither the name of the copyright holders nor the names of its 136821SN/A * contributors may be used to endorse or promote products derived from 146821SN/A * this software without specific prior written permission. 156821SN/A * 166821SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176821SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186821SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196821SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206821SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216821SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226821SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236821SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246821SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256821SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266821SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276821SN/A * 286818SN/A * Authors: Gabe Black 296818SN/A */ 306818SN/A 316818SN/A#ifndef __ARCH_ARM_ISA_HH__ 326818SN/A#define __ARCH_MRM_ISA_HH__ 336818SN/A 346818SN/A#include "arch/arm/registers.hh" 356818SN/A#include "arch/arm/types.hh" 366818SN/A 376818SN/Aclass ThreadContext; 386818SN/Aclass Checkpoint; 396818SN/Aclass EventManager; 406818SN/A 416818SN/Anamespace ArmISA 426818SN/A{ 436818SN/A class ISA 446818SN/A { 456818SN/A protected: 466818SN/A MiscReg miscRegs[NumMiscRegs]; 476818SN/A const IntRegIndex *intRegMap; 486818SN/A 496818SN/A void 506818SN/A updateRegMap(CPSR cpsr) 516818SN/A { 526818SN/A switch (cpsr.mode) { 536818SN/A case MODE_USER: 546818SN/A case MODE_SYSTEM: 556818SN/A intRegMap = IntRegUsrMap; 566818SN/A break; 576818SN/A case MODE_FIQ: 586818SN/A intRegMap = IntRegFiqMap; 596818SN/A break; 606818SN/A case MODE_IRQ: 616818SN/A intRegMap = IntRegIrqMap; 626818SN/A break; 636818SN/A case MODE_SVC: 647443SLisa.Hsu@amd.com intRegMap = IntRegSvcMap; 657443SLisa.Hsu@amd.com break; 667443SLisa.Hsu@amd.com case MODE_ABORT: 677443SLisa.Hsu@amd.com intRegMap = IntRegAbtMap; 686818SN/A break; 696818SN/A case MODE_UNDEFINED: 706818SN/A intRegMap = IntRegUndMap; 716818SN/A break; 726818SN/A default: 736818SN/A panic("Unrecognized mode setting in CPSR.\n"); 746818SN/A } 757443SLisa.Hsu@amd.com } 766818SN/A 776818SN/A public: 786818SN/A void clear() 796818SN/A { 806818SN/A memset(miscRegs, 0, sizeof(miscRegs)); 816818SN/A CPSR cpsr = 0; 826818SN/A cpsr.mode = MODE_SYSTEM; 836820SN/A miscRegs[MISCREG_CPSR] = cpsr; 846820SN/A updateRegMap(cpsr); 856818SN/A //XXX We need to initialize the rest of the state. 866818SN/A } 876818SN/A 886818SN/A MiscReg 896818SN/A readMiscRegNoEffect(int misc_reg) 906818SN/A { 916818SN/A assert(misc_reg < NumMiscRegs); 926818SN/A return miscRegs[misc_reg]; 936818SN/A } 946818SN/A 956818SN/A MiscReg 966818SN/A readMiscReg(int misc_reg, ThreadContext *tc) 976818SN/A { 986818SN/A assert(misc_reg < NumMiscRegs); 996818SN/A return miscRegs[misc_reg]; 1006818SN/A } 1016818SN/A 1026818SN/A void 1036818SN/A setMiscRegNoEffect(int misc_reg, const MiscReg &val) 1046818SN/A { 1056818SN/A assert(misc_reg < NumMiscRegs); 1066818SN/A miscRegs[misc_reg] = val; 1076818SN/A } 1086818SN/A 1096818SN/A void 1106818SN/A setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 1116818SN/A { 1126818SN/A if (misc_reg == MISCREG_CPSR) { 1136818SN/A updateRegMap(val); 1146818SN/A } 1156818SN/A assert(misc_reg < NumMiscRegs); 1166818SN/A miscRegs[misc_reg] = val; 1176818SN/A } 1186818SN/A 1196818SN/A int 1206818SN/A flattenIntIndex(int reg) 1216818SN/A { 1226818SN/A assert(reg >= 0); 1236818SN/A if (reg < NUM_ARCH_INTREGS) { 1246818SN/A return intRegMap[reg]; 1257443SLisa.Hsu@amd.com } else { 1267443SLisa.Hsu@amd.com assert(reg < NUM_INTREGS); 1276818SN/A return reg; 1287443SLisa.Hsu@amd.com } 1297443SLisa.Hsu@amd.com } 1307443SLisa.Hsu@amd.com 1317443SLisa.Hsu@amd.com int 1327443SLisa.Hsu@amd.com flattenFloatIndex(int reg) 1336818SN/A { 1346818SN/A return reg; 1356818SN/A } 1366818SN/A 1376818SN/A void serialize(EventManager *em, std::ostream &os) 1386818SN/A {} 1396818SN/A void unserialize(EventManager *em, Checkpoint *cp, 1406818SN/A const std::string §ion) 1416818SN/A {} 1426818SN/A 1436818SN/A ISA() 1446818SN/A { 1456818SN/A clear(); 1466818SN/A } 1476818SN/A }; 1486818SN/A} 1496818SN/A 1506818SN/A#endif 1516818SN/A