isa.hh revision 12714 
12501SN/A/*
22501SN/A * Copyright (c) 2010, 2012-2018 ARM Limited
32501SN/A * All rights reserved
42501SN/A *
52501SN/A * The license below extends only to copyright in the software and shall
62501SN/A * not be construed as granting a license to any other intellectual
72501SN/A * property including but not limited to intellectual property relating
82501SN/A * to a hardware implementation of the functionality of the software
92501SN/A * licensed hereunder.  You may use the software subject to the license
102501SN/A * terms below provided that you ensure that this notice is replicated
112501SN/A * unmodified and in its entirety in all distributions of the software,
122501SN/A * modified or unmodified, in source code or in binary form.
132501SN/A *
142501SN/A * Copyright (c) 2009 The Regents of The University of Michigan
152501SN/A * All rights reserved.
162501SN/A *
172501SN/A * Redistribution and use in source and binary forms, with or without
182501SN/A * modification, are permitted provided that the following conditions are
192501SN/A * met: redistributions of source code must retain the above copyright
202501SN/A * notice, this list of conditions and the following disclaimer;
212501SN/A * redistributions in binary form must reproduce the above copyright
222501SN/A * notice, this list of conditions and the following disclaimer in the
232501SN/A * documentation and/or other materials provided with the distribution;
242501SN/A * neither the name of the copyright holders nor the names of its
252501SN/A * contributors may be used to endorse or promote products derived from
262501SN/A * this software without specific prior written permission.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
292501SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
302501SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
312501SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
322501SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
332501SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
342501SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
356335Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
363603Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
378229Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
382501SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
397720Sgblack@eecs.umich.edu *
403272Sgblack@eecs.umich.edu * Authors: Gabe Black
417878Sgblack@eecs.umich.edu */
428767Sgblack@eecs.umich.edu
432501SN/A#ifndef __ARCH_ARM_ISA_HH__
442501SN/A#define __ARCH_ARM_ISA_HH__
452501SN/A
467720Sgblack@eecs.umich.edu#include "arch/arm/isa_device.hh"
477741Sgblack@eecs.umich.edu#include "arch/arm/miscregs.hh"
487741Sgblack@eecs.umich.edu#include "arch/arm/registers.hh"
497741Sgblack@eecs.umich.edu#include "arch/arm/system.hh"
507741Sgblack@eecs.umich.edu#include "arch/arm/tlb.hh"
517741Sgblack@eecs.umich.edu#include "arch/arm/types.hh"
527741Sgblack@eecs.umich.edu#include "arch/generic/traits.hh"
537741Sgblack@eecs.umich.edu#include "debug/Checkpoint.hh"
547741Sgblack@eecs.umich.edu#include "enums/VecRegRenameMode.hh"
557720Sgblack@eecs.umich.edu#include "sim/sim_object.hh"
567741Sgblack@eecs.umich.edu#include "enums/DecoderFlavour.hh"
574826Ssaidi@eecs.umich.edu
587741Sgblack@eecs.umich.edustruct ArmISAParams;
597741Sgblack@eecs.umich.edustruct DummyArmISADeviceParams;
607741Sgblack@eecs.umich.educlass ThreadContext;
618829Sgblack@eecs.umich.educlass Checkpoint;
628829Sgblack@eecs.umich.educlass EventManager;
638829Sgblack@eecs.umich.edu
647741Sgblack@eecs.umich.edunamespace ArmISA
653577Sgblack@eecs.umich.edu{
667741Sgblack@eecs.umich.edu    class ISA : public SimObject
677741Sgblack@eecs.umich.edu    {
687741Sgblack@eecs.umich.edu      protected:
697741Sgblack@eecs.umich.edu        // Parent system
707741Sgblack@eecs.umich.edu        ArmSystem *system;
717741Sgblack@eecs.umich.edu
722501SN/A        // Micro Architecture
737741Sgblack@eecs.umich.edu        const Enums::DecoderFlavour _decoderFlavour;
744194Ssaidi@eecs.umich.edu        const Enums::VecRegRenameMode _vecRegRenameMode;
757741Sgblack@eecs.umich.edu
767741Sgblack@eecs.umich.edu        /** Dummy device for to handle non-existing ISA devices */
777741Sgblack@eecs.umich.edu        DummyISADevice dummyDevice;
787741Sgblack@eecs.umich.edu
798767Sgblack@eecs.umich.edu        // PMU belonging to this ISA
807741Sgblack@eecs.umich.edu        BaseISADevice *pmu;
817741Sgblack@eecs.umich.edu
823528Sgblack@eecs.umich.edu        // Generic timer interface belonging to this ISA
837741Sgblack@eecs.umich.edu        std::unique_ptr<BaseISADevice> timer;
846329Sgblack@eecs.umich.edu
857741Sgblack@eecs.umich.edu        // Cached copies of system-level properties
866329Sgblack@eecs.umich.edu        bool highestELIs64;
877741Sgblack@eecs.umich.edu        bool haveSecurity;
887693SAli.Saidi@ARM.com        bool haveLPAE;
897741Sgblack@eecs.umich.edu        bool haveVirtualization;
907741Sgblack@eecs.umich.edu        bool haveLargeAsid64;
917741Sgblack@eecs.umich.edu        uint8_t physAddrRange64;
927741Sgblack@eecs.umich.edu
937741Sgblack@eecs.umich.edu        /**
947720Sgblack@eecs.umich.edu         * If true, accesses to IMPLEMENTATION DEFINED registers are treated
958300Schander.sudanthi@arm.com         * as NOP hence not causing UNDEFINED INSTRUCTION.
968300Schander.sudanthi@arm.com         */
978300Schander.sudanthi@arm.com        bool impdefAsNop;
988300Schander.sudanthi@arm.com
998300Schander.sudanthi@arm.com        /** MiscReg metadata **/
1008300Schander.sudanthi@arm.com        struct MiscRegLUTEntry {
1012501SN/A            uint32_t lower;  // Lower half mapped to this register
1022501SN/A            uint32_t upper;  // Upper half mapped to this register
1032501SN/A            uint64_t _reset; // value taken on reset (i.e. initialization)
104            uint64_t _res0;  // reserved
105            uint64_t _res1;  // reserved
106            uint64_t _raz;   // read as zero (fixed at 0)
107            uint64_t _rao;   // read as one (fixed at 1)
108          public:
109            MiscRegLUTEntry() :
110              lower(0), upper(0),
111              _reset(0), _res0(0), _res1(0), _raz(0), _rao(0) {}
112            uint64_t reset() const { return _reset; }
113            uint64_t res0()  const { return _res0; }
114            uint64_t res1()  const { return _res1; }
115            uint64_t raz()   const { return _raz; }
116            uint64_t rao()   const { return _rao; }
117            // raz/rao implies writes ignored
118            uint64_t wi()    const { return _raz | _rao; }
119        };
120
121        /** Metadata table accessible via the value of the register */
122        static std::vector<struct MiscRegLUTEntry> lookUpMiscReg;
123
124        class MiscRegLUTEntryInitializer {
125            struct MiscRegLUTEntry &entry;
126            std::bitset<NUM_MISCREG_INFOS> &info;
127            typedef const MiscRegLUTEntryInitializer& chain;
128          public:
129            chain mapsTo(uint32_t l, uint32_t u = 0) const {
130                entry.lower = l;
131                entry.upper = u;
132                return *this;
133            }
134            chain res0(uint64_t mask) const {
135                entry._res0 = mask;
136                return *this;
137            }
138            chain res1(uint64_t mask) const {
139                entry._res1 = mask;
140                return *this;
141            }
142            chain raz(uint64_t mask) const {
143                entry._raz  = mask;
144                return *this;
145            }
146            chain rao(uint64_t mask) const {
147                entry._rao  = mask;
148                return *this;
149            }
150            chain implemented(bool v = true) const {
151                info[MISCREG_IMPLEMENTED] = v;
152                return *this;
153            }
154            chain unimplemented() const {
155                return implemented(false);
156            }
157            chain unverifiable(bool v = true) const {
158                info[MISCREG_UNVERIFIABLE] = v;
159                return *this;
160            }
161            chain warnNotFail(bool v = true) const {
162                info[MISCREG_WARN_NOT_FAIL] = v;
163                return *this;
164            }
165            chain mutex(bool v = true) const {
166                info[MISCREG_MUTEX] = v;
167                return *this;
168            }
169            chain banked(bool v = true) const {
170                info[MISCREG_BANKED] = v;
171                return *this;
172            }
173            chain bankedChild(bool v = true) const {
174                info[MISCREG_BANKED_CHILD] = v;
175                return *this;
176            }
177            chain userNonSecureRead(bool v = true) const {
178                info[MISCREG_USR_NS_RD] = v;
179                return *this;
180            }
181            chain userNonSecureWrite(bool v = true) const {
182                info[MISCREG_USR_NS_WR] = v;
183                return *this;
184            }
185            chain userSecureRead(bool v = true) const {
186                info[MISCREG_USR_S_RD] = v;
187                return *this;
188            }
189            chain userSecureWrite(bool v = true) const {
190                info[MISCREG_USR_S_WR] = v;
191                return *this;
192            }
193            chain user(bool v = true) const {
194                userNonSecureRead(v);
195                userNonSecureWrite(v);
196                userSecureRead(v);
197                userSecureWrite(v);
198                return *this;
199            }
200            chain privNonSecureRead(bool v = true) const {
201                info[MISCREG_PRI_NS_RD] = v;
202                return *this;
203            }
204            chain privNonSecureWrite(bool v = true) const {
205                info[MISCREG_PRI_NS_WR] = v;
206                return *this;
207            }
208            chain privNonSecure(bool v = true) const {
209                privNonSecureRead(v);
210                privNonSecureWrite(v);
211                return *this;
212            }
213            chain privSecureRead(bool v = true) const {
214                info[MISCREG_PRI_S_RD] = v;
215                return *this;
216            }
217            chain privSecureWrite(bool v = true) const {
218                info[MISCREG_PRI_S_WR] = v;
219                return *this;
220            }
221            chain privSecure(bool v = true) const {
222                privSecureRead(v);
223                privSecureWrite(v);
224                return *this;
225            }
226            chain priv(bool v = true) const {
227                privSecure(v);
228                privNonSecure(v);
229                return *this;
230            }
231            chain hypRead(bool v = true) const {
232                info[MISCREG_HYP_RD] = v;
233                return *this;
234            }
235            chain hypWrite(bool v = true) const {
236                info[MISCREG_HYP_WR] = v;
237                return *this;
238            }
239            chain hyp(bool v = true) const {
240                hypRead(v);
241                hypWrite(v);
242                return *this;
243            }
244            chain monSecureRead(bool v = true) const {
245                info[MISCREG_MON_NS0_RD] = v;
246                return *this;
247            }
248            chain monSecureWrite(bool v = true) const {
249                info[MISCREG_MON_NS0_WR] = v;
250                return *this;
251            }
252            chain monNonSecureRead(bool v = true) const {
253                info[MISCREG_MON_NS1_RD] = v;
254                return *this;
255            }
256            chain monNonSecureWrite(bool v = true) const {
257                info[MISCREG_MON_NS1_WR] = v;
258                return *this;
259            }
260            chain mon(bool v = true) const {
261                monSecureRead(v);
262                monSecureWrite(v);
263                monNonSecureRead(v);
264                monNonSecureWrite(v);
265                return *this;
266            }
267            chain monSecure(bool v = true) const {
268                monSecureRead(v);
269                monSecureWrite(v);
270                return *this;
271            }
272            chain monNonSecure(bool v = true) const {
273                monNonSecureRead(v);
274                monNonSecureWrite(v);
275                return *this;
276            }
277            chain allPrivileges(bool v = true) const {
278                userNonSecureRead(v);
279                userNonSecureWrite(v);
280                userSecureRead(v);
281                userSecureWrite(v);
282                privNonSecureRead(v);
283                privNonSecureWrite(v);
284                privSecureRead(v);
285                privSecureWrite(v);
286                hypRead(v);
287                hypWrite(v);
288                monSecureRead(v);
289                monSecureWrite(v);
290                monNonSecureRead(v);
291                monNonSecureWrite(v);
292                return *this;
293            }
294            chain nonSecure(bool v = true) const {
295                userNonSecureRead(v);
296                userNonSecureWrite(v);
297                privNonSecureRead(v);
298                privNonSecureWrite(v);
299                hypRead(v);
300                hypWrite(v);
301                monNonSecureRead(v);
302                monNonSecureWrite(v);
303                return *this;
304            }
305            chain secure(bool v = true) const {
306                userSecureRead(v);
307                userSecureWrite(v);
308                privSecureRead(v);
309                privSecureWrite(v);
310                monSecureRead(v);
311                monSecureWrite(v);
312                return *this;
313            }
314            chain reads(bool v) const {
315                userNonSecureRead(v);
316                userSecureRead(v);
317                privNonSecureRead(v);
318                privSecureRead(v);
319                hypRead(v);
320                monSecureRead(v);
321                monNonSecureRead(v);
322                return *this;
323            }
324            chain writes(bool v) const {
325                userNonSecureWrite(v);
326                userSecureWrite(v);
327                privNonSecureWrite(v);
328                privSecureWrite(v);
329                hypWrite(v);
330                monSecureWrite(v);
331                monNonSecureWrite(v);
332                return *this;
333            }
334            chain exceptUserMode() const {
335                user(0);
336                return *this;
337            }
338            MiscRegLUTEntryInitializer(struct MiscRegLUTEntry &e,
339                                       std::bitset<NUM_MISCREG_INFOS> &i)
340              : entry(e),
341                info(i)
342            {
343                // force unimplemented registers to be thusly declared
344                implemented(1);
345            }
346        };
347
348        const MiscRegLUTEntryInitializer InitReg(uint32_t reg) {
349            return MiscRegLUTEntryInitializer(lookUpMiscReg[reg],
350                                              miscRegInfo[reg]);
351        }
352
353        void initializeMiscRegMetadata();
354
355        MiscReg miscRegs[NumMiscRegs];
356        const IntRegIndex *intRegMap;
357
358        void
359        updateRegMap(CPSR cpsr)
360        {
361            if (cpsr.width == 0) {
362                intRegMap = IntReg64Map;
363            } else {
364                switch (cpsr.mode) {
365                  case MODE_USER:
366                  case MODE_SYSTEM:
367                    intRegMap = IntRegUsrMap;
368                    break;
369                  case MODE_FIQ:
370                    intRegMap = IntRegFiqMap;
371                    break;
372                  case MODE_IRQ:
373                    intRegMap = IntRegIrqMap;
374                    break;
375                  case MODE_SVC:
376                    intRegMap = IntRegSvcMap;
377                    break;
378                  case MODE_MON:
379                    intRegMap = IntRegMonMap;
380                    break;
381                  case MODE_ABORT:
382                    intRegMap = IntRegAbtMap;
383                    break;
384                  case MODE_HYP:
385                    intRegMap = IntRegHypMap;
386                    break;
387                  case MODE_UNDEFINED:
388                    intRegMap = IntRegUndMap;
389                    break;
390                  default:
391                    panic("Unrecognized mode setting in CPSR.\n");
392                }
393            }
394        }
395
396        BaseISADevice &getGenericTimer(ThreadContext *tc);
397
398
399      private:
400        inline void assert32(ThreadContext *tc) {
401            CPSR cpsr M5_VAR_USED = readMiscReg(MISCREG_CPSR, tc);
402            assert(cpsr.width);
403        }
404
405        inline void assert64(ThreadContext *tc) {
406            CPSR cpsr M5_VAR_USED = readMiscReg(MISCREG_CPSR, tc);
407            assert(!cpsr.width);
408        }
409
410      public:
411        void clear();
412        void clear64(const ArmISAParams *p);
413
414        MiscReg readMiscRegNoEffect(int misc_reg) const;
415        MiscReg readMiscReg(int misc_reg, ThreadContext *tc);
416        void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
417        void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
418
419        RegId
420        flattenRegId(const RegId& regId) const
421        {
422            switch (regId.classValue()) {
423              case IntRegClass:
424                return RegId(IntRegClass, flattenIntIndex(regId.index()));
425              case FloatRegClass:
426                return RegId(FloatRegClass, flattenFloatIndex(regId.index()));
427              case VecRegClass:
428                return RegId(VecRegClass, flattenVecIndex(regId.index()));
429              case VecElemClass:
430                return RegId(VecElemClass, flattenVecElemIndex(regId.index()));
431              case CCRegClass:
432                return RegId(CCRegClass, flattenCCIndex(regId.index()));
433              case MiscRegClass:
434                return RegId(MiscRegClass, flattenMiscIndex(regId.index()));
435            }
436            return RegId();
437        }
438
439        int
440        flattenIntIndex(int reg) const
441        {
442            assert(reg >= 0);
443            if (reg < NUM_ARCH_INTREGS) {
444                return intRegMap[reg];
445            } else if (reg < NUM_INTREGS) {
446                return reg;
447            } else if (reg == INTREG_SPX) {
448                CPSR cpsr = miscRegs[MISCREG_CPSR];
449                ExceptionLevel el = opModeToEL(
450                    (OperatingMode) (uint8_t) cpsr.mode);
451                if (!cpsr.sp && el != EL0)
452                    return INTREG_SP0;
453                switch (el) {
454                  case EL3:
455                    return INTREG_SP3;
456                  case EL2:
457                    return INTREG_SP2;
458                  case EL1:
459                    return INTREG_SP1;
460                  case EL0:
461                    return INTREG_SP0;
462                  default:
463                    panic("Invalid exception level");
464                    break;
465                }
466            } else {
467                return flattenIntRegModeIndex(reg);
468            }
469        }
470
471        int
472        flattenFloatIndex(int reg) const
473        {
474            assert(reg >= 0);
475            return reg;
476        }
477
478        int
479        flattenVecIndex(int reg) const
480        {
481            assert(reg >= 0);
482            return reg;
483        }
484
485        int
486        flattenVecElemIndex(int reg) const
487        {
488            assert(reg >= 0);
489            return reg;
490        }
491
492        int
493        flattenCCIndex(int reg) const
494        {
495            assert(reg >= 0);
496            return reg;
497        }
498
499        int
500        flattenMiscIndex(int reg) const
501        {
502            assert(reg >= 0);
503            int flat_idx = reg;
504
505            if (reg == MISCREG_SPSR) {
506                CPSR cpsr = miscRegs[MISCREG_CPSR];
507                switch (cpsr.mode) {
508                  case MODE_EL0T:
509                    warn("User mode does not have SPSR\n");
510                    flat_idx = MISCREG_SPSR;
511                    break;
512                  case MODE_EL1T:
513                  case MODE_EL1H:
514                    flat_idx = MISCREG_SPSR_EL1;
515                    break;
516                  case MODE_EL2T:
517                  case MODE_EL2H:
518                    flat_idx = MISCREG_SPSR_EL2;
519                    break;
520                  case MODE_EL3T:
521                  case MODE_EL3H:
522                    flat_idx = MISCREG_SPSR_EL3;
523                    break;
524                  case MODE_USER:
525                    warn("User mode does not have SPSR\n");
526                    flat_idx = MISCREG_SPSR;
527                    break;
528                  case MODE_FIQ:
529                    flat_idx = MISCREG_SPSR_FIQ;
530                    break;
531                  case MODE_IRQ:
532                    flat_idx = MISCREG_SPSR_IRQ;
533                    break;
534                  case MODE_SVC:
535                    flat_idx = MISCREG_SPSR_SVC;
536                    break;
537                  case MODE_MON:
538                    flat_idx = MISCREG_SPSR_MON;
539                    break;
540                  case MODE_ABORT:
541                    flat_idx = MISCREG_SPSR_ABT;
542                    break;
543                  case MODE_HYP:
544                    flat_idx = MISCREG_SPSR_HYP;
545                    break;
546                  case MODE_UNDEFINED:
547                    flat_idx = MISCREG_SPSR_UND;
548                    break;
549                  default:
550                    warn("Trying to access SPSR in an invalid mode: %d\n",
551                         cpsr.mode);
552                    flat_idx = MISCREG_SPSR;
553                    break;
554                }
555            } else if (miscRegInfo[reg][MISCREG_MUTEX]) {
556                // Mutually exclusive CP15 register
557                switch (reg) {
558                  case MISCREG_PRRR_MAIR0:
559                  case MISCREG_PRRR_MAIR0_NS:
560                  case MISCREG_PRRR_MAIR0_S:
561                    {
562                        TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
563                        // If the muxed reg has been flattened, work out the
564                        // offset and apply it to the unmuxed reg
565                        int idxOffset = reg - MISCREG_PRRR_MAIR0;
566                        if (ttbcr.eae)
567                            flat_idx = flattenMiscIndex(MISCREG_MAIR0 +
568                                                        idxOffset);
569                        else
570                            flat_idx = flattenMiscIndex(MISCREG_PRRR +
571                                                        idxOffset);
572                    }
573                    break;
574                  case MISCREG_NMRR_MAIR1:
575                  case MISCREG_NMRR_MAIR1_NS:
576                  case MISCREG_NMRR_MAIR1_S:
577                    {
578                        TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
579                        // If the muxed reg has been flattened, work out the
580                        // offset and apply it to the unmuxed reg
581                        int idxOffset = reg - MISCREG_NMRR_MAIR1;
582                        if (ttbcr.eae)
583                            flat_idx = flattenMiscIndex(MISCREG_MAIR1 +
584                                                        idxOffset);
585                        else
586                            flat_idx = flattenMiscIndex(MISCREG_NMRR +
587                                                        idxOffset);
588                    }
589                    break;
590                  case MISCREG_PMXEVTYPER_PMCCFILTR:
591                    {
592                        PMSELR pmselr = miscRegs[MISCREG_PMSELR];
593                        if (pmselr.sel == 31)
594                            flat_idx = flattenMiscIndex(MISCREG_PMCCFILTR);
595                        else
596                            flat_idx = flattenMiscIndex(MISCREG_PMXEVTYPER);
597                    }
598                    break;
599                  default:
600                    panic("Unrecognized misc. register.\n");
601                    break;
602                }
603            } else {
604                if (miscRegInfo[reg][MISCREG_BANKED]) {
605                    bool secureReg = haveSecurity && !highestELIs64 &&
606                                     inSecureState(miscRegs[MISCREG_SCR],
607                                                   miscRegs[MISCREG_CPSR]);
608                    flat_idx += secureReg ? 2 : 1;
609                }
610            }
611            return flat_idx;
612        }
613
614        std::pair<int,int> getMiscIndices(int misc_reg) const
615        {
616            // Note: indexes of AArch64 registers are left unchanged
617            int flat_idx = flattenMiscIndex(misc_reg);
618
619            if (lookUpMiscReg[flat_idx].lower == 0) {
620                return std::make_pair(flat_idx, 0);
621            }
622
623            // do additional S/NS flattenings if mapped to NS while in S
624            bool S = haveSecurity && !highestELIs64 &&
625                     inSecureState(miscRegs[MISCREG_SCR],
626                                   miscRegs[MISCREG_CPSR]);
627            int lower = lookUpMiscReg[flat_idx].lower;
628            int upper = lookUpMiscReg[flat_idx].upper;
629            // upper == 0, which is CPSR, is not MISCREG_BANKED_CHILD (no-op)
630            lower += S && miscRegInfo[lower][MISCREG_BANKED_CHILD];
631            upper += S && miscRegInfo[upper][MISCREG_BANKED_CHILD];
632            return std::make_pair(lower, upper);
633        }
634
635        void serialize(CheckpointOut &cp) const
636        {
637            DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
638            SERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
639
640            SERIALIZE_SCALAR(highestELIs64);
641            SERIALIZE_SCALAR(haveSecurity);
642            SERIALIZE_SCALAR(haveLPAE);
643            SERIALIZE_SCALAR(haveVirtualization);
644            SERIALIZE_SCALAR(haveLargeAsid64);
645            SERIALIZE_SCALAR(physAddrRange64);
646        }
647        void unserialize(CheckpointIn &cp)
648        {
649            DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
650            UNSERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
651            CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
652            updateRegMap(tmp_cpsr);
653
654            UNSERIALIZE_SCALAR(highestELIs64);
655            UNSERIALIZE_SCALAR(haveSecurity);
656            UNSERIALIZE_SCALAR(haveLPAE);
657            UNSERIALIZE_SCALAR(haveVirtualization);
658            UNSERIALIZE_SCALAR(haveLargeAsid64);
659            UNSERIALIZE_SCALAR(physAddrRange64);
660        }
661
662        void startup(ThreadContext *tc) {}
663
664        Enums::DecoderFlavour decoderFlavour() const { return _decoderFlavour; }
665
666        Enums::VecRegRenameMode
667        vecRegRenameMode() const
668        {
669            return _vecRegRenameMode;
670        }
671
672        /// Explicitly import the otherwise hidden startup
673        using SimObject::startup;
674
675        typedef ArmISAParams Params;
676
677        const Params *params() const;
678
679        ISA(Params *p);
680    };
681}
682
683template<>
684struct initRenameMode<ArmISA::ISA>
685{
686    static Enums::VecRegRenameMode mode(const ArmISA::ISA* isa)
687    {
688        return isa->vecRegRenameMode();
689    }
690    static bool equals(const ArmISA::ISA* isa1, const ArmISA::ISA* isa2)
691    {
692        return mode(isa1) == mode(isa2);
693    }
694};
695
696#endif
697