isa.hh revision 11165
16313Sgblack@eecs.umich.edu/* 210844Sandreas.sandberg@arm.com * Copyright (c) 2010, 2012-2015 ARM Limited 37093Sgblack@eecs.umich.edu * All rights reserved 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67093Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77093Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87093Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97093Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107093Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117093Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127093Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137093Sgblack@eecs.umich.edu * 146313Sgblack@eecs.umich.edu * Copyright (c) 2009 The Regents of The University of Michigan 156313Sgblack@eecs.umich.edu * All rights reserved. 166313Sgblack@eecs.umich.edu * 176313Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 186313Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 196313Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 206313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 216313Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 226313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 236313Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 246313Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 256313Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 266313Sgblack@eecs.umich.edu * this software without specific prior written permission. 276313Sgblack@eecs.umich.edu * 286313Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296313Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306313Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316313Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326313Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336313Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346313Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356313Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366313Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376313Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386313Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396313Sgblack@eecs.umich.edu * 406313Sgblack@eecs.umich.edu * Authors: Gabe Black 416313Sgblack@eecs.umich.edu */ 426313Sgblack@eecs.umich.edu 436313Sgblack@eecs.umich.edu#ifndef __ARCH_ARM_ISA_HH__ 447404SAli.Saidi@ARM.com#define __ARCH_ARM_ISA_HH__ 456313Sgblack@eecs.umich.edu 4610461SAndreas.Sandberg@ARM.com#include "arch/arm/isa_device.hh" 476333Sgblack@eecs.umich.edu#include "arch/arm/registers.hh" 4810037SARM gem5 Developers#include "arch/arm/system.hh" 497404SAli.Saidi@ARM.com#include "arch/arm/tlb.hh" 506313Sgblack@eecs.umich.edu#include "arch/arm/types.hh" 518232Snate@binkert.org#include "debug/Checkpoint.hh" 529384SAndreas.Sandberg@arm.com#include "sim/sim_object.hh" 5311165SRekai.GonzalezAlberquilla@arm.com#include "enums/DecoderFlavour.hh" 546313Sgblack@eecs.umich.edu 559384SAndreas.Sandberg@arm.comstruct ArmISAParams; 5610461SAndreas.Sandberg@ARM.comstruct DummyArmISADeviceParams; 576333Sgblack@eecs.umich.educlass ThreadContext; 586313Sgblack@eecs.umich.educlass Checkpoint; 596313Sgblack@eecs.umich.educlass EventManager; 606313Sgblack@eecs.umich.edu 616313Sgblack@eecs.umich.edunamespace ArmISA 626313Sgblack@eecs.umich.edu{ 6310037SARM gem5 Developers 6410037SARM gem5 Developers /** 6510037SARM gem5 Developers * At the moment there are 57 registers which need to be aliased/ 6610037SARM gem5 Developers * translated with other registers in the ISA. This enum helps with that 6710037SARM gem5 Developers * translation. 6810037SARM gem5 Developers */ 6910037SARM gem5 Developers enum translateTable { 7010037SARM gem5 Developers miscRegTranslateCSSELR_EL1, 7110037SARM gem5 Developers miscRegTranslateSCTLR_EL1, 7210037SARM gem5 Developers miscRegTranslateSCTLR_EL2, 7310037SARM gem5 Developers miscRegTranslateACTLR_EL1, 7410037SARM gem5 Developers miscRegTranslateACTLR_EL2, 7510037SARM gem5 Developers miscRegTranslateCPACR_EL1, 7610037SARM gem5 Developers miscRegTranslateCPTR_EL2, 7710037SARM gem5 Developers miscRegTranslateHCR_EL2, 7810037SARM gem5 Developers miscRegTranslateMDCR_EL2, 7910037SARM gem5 Developers miscRegTranslateHSTR_EL2, 8010037SARM gem5 Developers miscRegTranslateHACR_EL2, 8110037SARM gem5 Developers miscRegTranslateTTBR0_EL1, 8210037SARM gem5 Developers miscRegTranslateTTBR1_EL1, 8310037SARM gem5 Developers miscRegTranslateTTBR0_EL2, 8410037SARM gem5 Developers miscRegTranslateVTTBR_EL2, 8510037SARM gem5 Developers miscRegTranslateTCR_EL1, 8610037SARM gem5 Developers miscRegTranslateTCR_EL2, 8710037SARM gem5 Developers miscRegTranslateVTCR_EL2, 8810037SARM gem5 Developers miscRegTranslateAFSR0_EL1, 8910037SARM gem5 Developers miscRegTranslateAFSR1_EL1, 9010037SARM gem5 Developers miscRegTranslateAFSR0_EL2, 9110037SARM gem5 Developers miscRegTranslateAFSR1_EL2, 9210037SARM gem5 Developers miscRegTranslateESR_EL2, 9310037SARM gem5 Developers miscRegTranslateFAR_EL1, 9410037SARM gem5 Developers miscRegTranslateFAR_EL2, 9510037SARM gem5 Developers miscRegTranslateHPFAR_EL2, 9610037SARM gem5 Developers miscRegTranslatePAR_EL1, 9710037SARM gem5 Developers miscRegTranslateMAIR_EL1, 9810037SARM gem5 Developers miscRegTranslateMAIR_EL2, 9910037SARM gem5 Developers miscRegTranslateAMAIR_EL1, 10010037SARM gem5 Developers miscRegTranslateVBAR_EL1, 10110037SARM gem5 Developers miscRegTranslateVBAR_EL2, 10210037SARM gem5 Developers miscRegTranslateCONTEXTIDR_EL1, 10310037SARM gem5 Developers miscRegTranslateTPIDR_EL0, 10410037SARM gem5 Developers miscRegTranslateTPIDRRO_EL0, 10510037SARM gem5 Developers miscRegTranslateTPIDR_EL1, 10610037SARM gem5 Developers miscRegTranslateTPIDR_EL2, 10710037SARM gem5 Developers miscRegTranslateTEECR32_EL1, 10810037SARM gem5 Developers miscRegTranslateCNTFRQ_EL0, 10910037SARM gem5 Developers miscRegTranslateCNTPCT_EL0, 11010037SARM gem5 Developers miscRegTranslateCNTVCT_EL0, 11110037SARM gem5 Developers miscRegTranslateCNTVOFF_EL2, 11210037SARM gem5 Developers miscRegTranslateCNTKCTL_EL1, 11310037SARM gem5 Developers miscRegTranslateCNTHCTL_EL2, 11410037SARM gem5 Developers miscRegTranslateCNTP_TVAL_EL0, 11510037SARM gem5 Developers miscRegTranslateCNTP_CTL_EL0, 11610037SARM gem5 Developers miscRegTranslateCNTP_CVAL_EL0, 11710037SARM gem5 Developers miscRegTranslateCNTV_TVAL_EL0, 11810037SARM gem5 Developers miscRegTranslateCNTV_CTL_EL0, 11910037SARM gem5 Developers miscRegTranslateCNTV_CVAL_EL0, 12010037SARM gem5 Developers miscRegTranslateCNTHP_TVAL_EL2, 12110037SARM gem5 Developers miscRegTranslateCNTHP_CTL_EL2, 12210037SARM gem5 Developers miscRegTranslateCNTHP_CVAL_EL2, 12310037SARM gem5 Developers miscRegTranslateDACR32_EL2, 12410037SARM gem5 Developers miscRegTranslateIFSR32_EL2, 12510037SARM gem5 Developers miscRegTranslateTEEHBR32_EL1, 12610037SARM gem5 Developers miscRegTranslateSDER32_EL3, 12710037SARM gem5 Developers miscRegTranslateMax 12810037SARM gem5 Developers }; 12910037SARM gem5 Developers 1309384SAndreas.Sandberg@arm.com class ISA : public SimObject 1316313Sgblack@eecs.umich.edu { 1326313Sgblack@eecs.umich.edu protected: 13310037SARM gem5 Developers // Parent system 13410037SARM gem5 Developers ArmSystem *system; 13510037SARM gem5 Developers 13611165SRekai.GonzalezAlberquilla@arm.com // Micro Architecture 13711165SRekai.GonzalezAlberquilla@arm.com const Enums::DecoderFlavour _decoderFlavour; 13811165SRekai.GonzalezAlberquilla@arm.com 13910461SAndreas.Sandberg@ARM.com /** Dummy device for to handle non-existing ISA devices */ 14010461SAndreas.Sandberg@ARM.com DummyISADevice dummyDevice; 14110461SAndreas.Sandberg@ARM.com 14210461SAndreas.Sandberg@ARM.com // PMU belonging to this ISA 14310461SAndreas.Sandberg@ARM.com BaseISADevice *pmu; 14410461SAndreas.Sandberg@ARM.com 14510844Sandreas.sandberg@arm.com // Generic timer interface belonging to this ISA 14610844Sandreas.sandberg@arm.com std::unique_ptr<BaseISADevice> timer; 14710844Sandreas.sandberg@arm.com 14810037SARM gem5 Developers // Cached copies of system-level properties 14910037SARM gem5 Developers bool haveSecurity; 15010037SARM gem5 Developers bool haveLPAE; 15110037SARM gem5 Developers bool haveVirtualization; 15210037SARM gem5 Developers bool haveLargeAsid64; 15310037SARM gem5 Developers uint8_t physAddrRange64; 15410037SARM gem5 Developers 15510037SARM gem5 Developers /** Register translation entry used in lookUpMiscReg */ 15610037SARM gem5 Developers struct MiscRegLUTEntry { 15710037SARM gem5 Developers uint32_t lower; 15810037SARM gem5 Developers uint32_t upper; 15910037SARM gem5 Developers }; 16010037SARM gem5 Developers 16110037SARM gem5 Developers struct MiscRegInitializerEntry { 16210037SARM gem5 Developers uint32_t index; 16310037SARM gem5 Developers struct MiscRegLUTEntry entry; 16410037SARM gem5 Developers }; 16510037SARM gem5 Developers 16610037SARM gem5 Developers /** Register table noting all translations */ 16710037SARM gem5 Developers static const struct MiscRegInitializerEntry 16810037SARM gem5 Developers MiscRegSwitch[miscRegTranslateMax]; 16910037SARM gem5 Developers 17010037SARM gem5 Developers /** Translation table accessible via the value of the register */ 17110037SARM gem5 Developers std::vector<struct MiscRegLUTEntry> lookUpMiscReg; 17210037SARM gem5 Developers 1736333Sgblack@eecs.umich.edu MiscReg miscRegs[NumMiscRegs]; 1746718Sgblack@eecs.umich.edu const IntRegIndex *intRegMap; 1756718Sgblack@eecs.umich.edu 1766718Sgblack@eecs.umich.edu void 1776718Sgblack@eecs.umich.edu updateRegMap(CPSR cpsr) 1786718Sgblack@eecs.umich.edu { 17910037SARM gem5 Developers if (cpsr.width == 0) { 18010037SARM gem5 Developers intRegMap = IntReg64Map; 18110037SARM gem5 Developers } else { 18210037SARM gem5 Developers switch (cpsr.mode) { 18310037SARM gem5 Developers case MODE_USER: 18410037SARM gem5 Developers case MODE_SYSTEM: 18510037SARM gem5 Developers intRegMap = IntRegUsrMap; 18610037SARM gem5 Developers break; 18710037SARM gem5 Developers case MODE_FIQ: 18810037SARM gem5 Developers intRegMap = IntRegFiqMap; 18910037SARM gem5 Developers break; 19010037SARM gem5 Developers case MODE_IRQ: 19110037SARM gem5 Developers intRegMap = IntRegIrqMap; 19210037SARM gem5 Developers break; 19310037SARM gem5 Developers case MODE_SVC: 19410037SARM gem5 Developers intRegMap = IntRegSvcMap; 19510037SARM gem5 Developers break; 19610037SARM gem5 Developers case MODE_MON: 19710037SARM gem5 Developers intRegMap = IntRegMonMap; 19810037SARM gem5 Developers break; 19910037SARM gem5 Developers case MODE_ABORT: 20010037SARM gem5 Developers intRegMap = IntRegAbtMap; 20110037SARM gem5 Developers break; 20210037SARM gem5 Developers case MODE_HYP: 20310037SARM gem5 Developers intRegMap = IntRegHypMap; 20410037SARM gem5 Developers break; 20510037SARM gem5 Developers case MODE_UNDEFINED: 20610037SARM gem5 Developers intRegMap = IntRegUndMap; 20710037SARM gem5 Developers break; 20810037SARM gem5 Developers default: 20910037SARM gem5 Developers panic("Unrecognized mode setting in CPSR.\n"); 21010037SARM gem5 Developers } 2116718Sgblack@eecs.umich.edu } 2126718Sgblack@eecs.umich.edu } 2136313Sgblack@eecs.umich.edu 21410844Sandreas.sandberg@arm.com BaseISADevice &getGenericTimer(ThreadContext *tc); 21510037SARM gem5 Developers 21610037SARM gem5 Developers 21710037SARM gem5 Developers private: 21810037SARM gem5 Developers inline void assert32(ThreadContext *tc) { 21910037SARM gem5 Developers CPSR cpsr M5_VAR_USED = readMiscReg(MISCREG_CPSR, tc); 22010037SARM gem5 Developers assert(cpsr.width); 22110037SARM gem5 Developers } 22210037SARM gem5 Developers 22310037SARM gem5 Developers inline void assert64(ThreadContext *tc) { 22410037SARM gem5 Developers CPSR cpsr M5_VAR_USED = readMiscReg(MISCREG_CPSR, tc); 22510037SARM gem5 Developers assert(!cpsr.width); 22610037SARM gem5 Developers } 22710037SARM gem5 Developers 22810709SAndreas.Sandberg@ARM.com void tlbiVA(ThreadContext *tc, MiscReg newVal, uint16_t asid, 22910037SARM gem5 Developers bool secure_lookup, uint8_t target_el); 23010037SARM gem5 Developers 23110037SARM gem5 Developers void tlbiALL(ThreadContext *tc, bool secure_lookup, uint8_t target_el); 23210037SARM gem5 Developers 23310037SARM gem5 Developers void tlbiALLN(ThreadContext *tc, bool hyp, uint8_t target_el); 23410037SARM gem5 Developers 23510037SARM gem5 Developers void tlbiMVA(ThreadContext *tc, MiscReg newVal, bool secure_lookup, 23610037SARM gem5 Developers bool hyp, uint8_t target_el); 23710037SARM gem5 Developers 2386313Sgblack@eecs.umich.edu public: 2397427Sgblack@eecs.umich.edu void clear(); 24010037SARM gem5 Developers void clear64(const ArmISAParams *p); 2416313Sgblack@eecs.umich.edu 24210035Sandreas.hansson@arm.com MiscReg readMiscRegNoEffect(int misc_reg) const; 2437405SAli.Saidi@ARM.com MiscReg readMiscReg(int misc_reg, ThreadContext *tc); 2447405SAli.Saidi@ARM.com void setMiscRegNoEffect(int misc_reg, const MiscReg &val); 2457405SAli.Saidi@ARM.com void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc); 2466313Sgblack@eecs.umich.edu 2476313Sgblack@eecs.umich.edu int 24810035Sandreas.hansson@arm.com flattenIntIndex(int reg) const 2496313Sgblack@eecs.umich.edu { 2506718Sgblack@eecs.umich.edu assert(reg >= 0); 2516718Sgblack@eecs.umich.edu if (reg < NUM_ARCH_INTREGS) { 2526718Sgblack@eecs.umich.edu return intRegMap[reg]; 2536726Sgblack@eecs.umich.edu } else if (reg < NUM_INTREGS) { 2546726Sgblack@eecs.umich.edu return reg; 25510037SARM gem5 Developers } else if (reg == INTREG_SPX) { 25610037SARM gem5 Developers CPSR cpsr = miscRegs[MISCREG_CPSR]; 25710037SARM gem5 Developers ExceptionLevel el = opModeToEL( 25810037SARM gem5 Developers (OperatingMode) (uint8_t) cpsr.mode); 25910037SARM gem5 Developers if (!cpsr.sp && el != EL0) 26010037SARM gem5 Developers return INTREG_SP0; 26110037SARM gem5 Developers switch (el) { 26210037SARM gem5 Developers case EL3: 26310037SARM gem5 Developers return INTREG_SP3; 26410037SARM gem5 Developers // @todo: uncomment this to enable Virtualization 26510037SARM gem5 Developers // case EL2: 26610037SARM gem5 Developers // return INTREG_SP2; 26710037SARM gem5 Developers case EL1: 26810037SARM gem5 Developers return INTREG_SP1; 26910037SARM gem5 Developers case EL0: 27010037SARM gem5 Developers return INTREG_SP0; 27110037SARM gem5 Developers default: 27210037SARM gem5 Developers panic("Invalid exception level"); 27310037SARM gem5 Developers break; 27410037SARM gem5 Developers } 2756718Sgblack@eecs.umich.edu } else { 27610037SARM gem5 Developers return flattenIntRegModeIndex(reg); 2776718Sgblack@eecs.umich.edu } 2786313Sgblack@eecs.umich.edu } 2796313Sgblack@eecs.umich.edu 2806313Sgblack@eecs.umich.edu int 28110035Sandreas.hansson@arm.com flattenFloatIndex(int reg) const 2826313Sgblack@eecs.umich.edu { 28310338SCurtis.Dunham@arm.com assert(reg >= 0); 2846313Sgblack@eecs.umich.edu return reg; 2856313Sgblack@eecs.umich.edu } 2866313Sgblack@eecs.umich.edu 2879920Syasuko.eckert@amd.com int 28810035Sandreas.hansson@arm.com flattenCCIndex(int reg) const 2899920Syasuko.eckert@amd.com { 29010338SCurtis.Dunham@arm.com assert(reg >= 0); 2919920Syasuko.eckert@amd.com return reg; 2929920Syasuko.eckert@amd.com } 2939920Syasuko.eckert@amd.com 2947614Sminkyu.jeong@arm.com int 29510035Sandreas.hansson@arm.com flattenMiscIndex(int reg) const 2967614Sminkyu.jeong@arm.com { 29710338SCurtis.Dunham@arm.com assert(reg >= 0); 29810037SARM gem5 Developers int flat_idx = reg; 29910037SARM gem5 Developers 3007614Sminkyu.jeong@arm.com if (reg == MISCREG_SPSR) { 3017614Sminkyu.jeong@arm.com CPSR cpsr = miscRegs[MISCREG_CPSR]; 3027614Sminkyu.jeong@arm.com switch (cpsr.mode) { 30310037SARM gem5 Developers case MODE_EL0T: 30410037SARM gem5 Developers warn("User mode does not have SPSR\n"); 30510037SARM gem5 Developers flat_idx = MISCREG_SPSR; 30610037SARM gem5 Developers break; 30710037SARM gem5 Developers case MODE_EL1T: 30810037SARM gem5 Developers case MODE_EL1H: 30910037SARM gem5 Developers flat_idx = MISCREG_SPSR_EL1; 31010037SARM gem5 Developers break; 31110037SARM gem5 Developers case MODE_EL2T: 31210037SARM gem5 Developers case MODE_EL2H: 31310037SARM gem5 Developers flat_idx = MISCREG_SPSR_EL2; 31410037SARM gem5 Developers break; 31510037SARM gem5 Developers case MODE_EL3T: 31610037SARM gem5 Developers case MODE_EL3H: 31710037SARM gem5 Developers flat_idx = MISCREG_SPSR_EL3; 31810037SARM gem5 Developers break; 3197614Sminkyu.jeong@arm.com case MODE_USER: 3207614Sminkyu.jeong@arm.com warn("User mode does not have SPSR\n"); 32110037SARM gem5 Developers flat_idx = MISCREG_SPSR; 3227614Sminkyu.jeong@arm.com break; 3237614Sminkyu.jeong@arm.com case MODE_FIQ: 32410037SARM gem5 Developers flat_idx = MISCREG_SPSR_FIQ; 3257614Sminkyu.jeong@arm.com break; 3267614Sminkyu.jeong@arm.com case MODE_IRQ: 32710037SARM gem5 Developers flat_idx = MISCREG_SPSR_IRQ; 3287614Sminkyu.jeong@arm.com break; 3297614Sminkyu.jeong@arm.com case MODE_SVC: 33010037SARM gem5 Developers flat_idx = MISCREG_SPSR_SVC; 3317614Sminkyu.jeong@arm.com break; 3327614Sminkyu.jeong@arm.com case MODE_MON: 33310037SARM gem5 Developers flat_idx = MISCREG_SPSR_MON; 3347614Sminkyu.jeong@arm.com break; 3357614Sminkyu.jeong@arm.com case MODE_ABORT: 33610037SARM gem5 Developers flat_idx = MISCREG_SPSR_ABT; 33710037SARM gem5 Developers break; 33810037SARM gem5 Developers case MODE_HYP: 33910037SARM gem5 Developers flat_idx = MISCREG_SPSR_HYP; 3407614Sminkyu.jeong@arm.com break; 3417614Sminkyu.jeong@arm.com case MODE_UNDEFINED: 34210037SARM gem5 Developers flat_idx = MISCREG_SPSR_UND; 3437614Sminkyu.jeong@arm.com break; 3447614Sminkyu.jeong@arm.com default: 3457614Sminkyu.jeong@arm.com warn("Trying to access SPSR in an invalid mode: %d\n", 3467614Sminkyu.jeong@arm.com cpsr.mode); 34710037SARM gem5 Developers flat_idx = MISCREG_SPSR; 3487614Sminkyu.jeong@arm.com break; 3497614Sminkyu.jeong@arm.com } 35010037SARM gem5 Developers } else if (miscRegInfo[reg][MISCREG_MUTEX]) { 35110037SARM gem5 Developers // Mutually exclusive CP15 register 35210037SARM gem5 Developers switch (reg) { 35310037SARM gem5 Developers case MISCREG_PRRR_MAIR0: 35410037SARM gem5 Developers case MISCREG_PRRR_MAIR0_NS: 35510037SARM gem5 Developers case MISCREG_PRRR_MAIR0_S: 35610037SARM gem5 Developers { 35710037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 35810037SARM gem5 Developers // If the muxed reg has been flattened, work out the 35910037SARM gem5 Developers // offset and apply it to the unmuxed reg 36010037SARM gem5 Developers int idxOffset = reg - MISCREG_PRRR_MAIR0; 36110037SARM gem5 Developers if (ttbcr.eae) 36210037SARM gem5 Developers flat_idx = flattenMiscIndex(MISCREG_MAIR0 + 36310037SARM gem5 Developers idxOffset); 36410037SARM gem5 Developers else 36510037SARM gem5 Developers flat_idx = flattenMiscIndex(MISCREG_PRRR + 36610037SARM gem5 Developers idxOffset); 36710037SARM gem5 Developers } 36810037SARM gem5 Developers break; 36910037SARM gem5 Developers case MISCREG_NMRR_MAIR1: 37010037SARM gem5 Developers case MISCREG_NMRR_MAIR1_NS: 37110037SARM gem5 Developers case MISCREG_NMRR_MAIR1_S: 37210037SARM gem5 Developers { 37310037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 37410037SARM gem5 Developers // If the muxed reg has been flattened, work out the 37510037SARM gem5 Developers // offset and apply it to the unmuxed reg 37610037SARM gem5 Developers int idxOffset = reg - MISCREG_NMRR_MAIR1; 37710037SARM gem5 Developers if (ttbcr.eae) 37810037SARM gem5 Developers flat_idx = flattenMiscIndex(MISCREG_MAIR1 + 37910037SARM gem5 Developers idxOffset); 38010037SARM gem5 Developers else 38110037SARM gem5 Developers flat_idx = flattenMiscIndex(MISCREG_NMRR + 38210037SARM gem5 Developers idxOffset); 38310037SARM gem5 Developers } 38410037SARM gem5 Developers break; 38510037SARM gem5 Developers case MISCREG_PMXEVTYPER_PMCCFILTR: 38610037SARM gem5 Developers { 38710037SARM gem5 Developers PMSELR pmselr = miscRegs[MISCREG_PMSELR]; 38810037SARM gem5 Developers if (pmselr.sel == 31) 38910037SARM gem5 Developers flat_idx = flattenMiscIndex(MISCREG_PMCCFILTR); 39010037SARM gem5 Developers else 39110037SARM gem5 Developers flat_idx = flattenMiscIndex(MISCREG_PMXEVTYPER); 39210037SARM gem5 Developers } 39310037SARM gem5 Developers break; 39410037SARM gem5 Developers default: 39510037SARM gem5 Developers panic("Unrecognized misc. register.\n"); 39610037SARM gem5 Developers break; 39710037SARM gem5 Developers } 39810037SARM gem5 Developers } else { 39910037SARM gem5 Developers if (miscRegInfo[reg][MISCREG_BANKED]) { 40010037SARM gem5 Developers bool secureReg = haveSecurity && 40110037SARM gem5 Developers inSecureState(miscRegs[MISCREG_SCR], 40210037SARM gem5 Developers miscRegs[MISCREG_CPSR]); 40310037SARM gem5 Developers flat_idx += secureReg ? 2 : 1; 40410037SARM gem5 Developers } 4057614Sminkyu.jeong@arm.com } 40610037SARM gem5 Developers return flat_idx; 4077614Sminkyu.jeong@arm.com } 4087614Sminkyu.jeong@arm.com 40910905Sandreas.sandberg@arm.com void serialize(CheckpointOut &cp) const 4107733SAli.Saidi@ARM.com { 4117733SAli.Saidi@ARM.com DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n"); 4127733SAli.Saidi@ARM.com SERIALIZE_ARRAY(miscRegs, NumMiscRegs); 41310037SARM gem5 Developers 41410037SARM gem5 Developers SERIALIZE_SCALAR(haveSecurity); 41510037SARM gem5 Developers SERIALIZE_SCALAR(haveLPAE); 41610037SARM gem5 Developers SERIALIZE_SCALAR(haveVirtualization); 41710037SARM gem5 Developers SERIALIZE_SCALAR(haveLargeAsid64); 41810037SARM gem5 Developers SERIALIZE_SCALAR(physAddrRange64); 4197733SAli.Saidi@ARM.com } 42010905Sandreas.sandberg@arm.com void unserialize(CheckpointIn &cp) 4217733SAli.Saidi@ARM.com { 4227733SAli.Saidi@ARM.com DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n"); 4237733SAli.Saidi@ARM.com UNSERIALIZE_ARRAY(miscRegs, NumMiscRegs); 4247733SAli.Saidi@ARM.com CPSR tmp_cpsr = miscRegs[MISCREG_CPSR]; 4257733SAli.Saidi@ARM.com updateRegMap(tmp_cpsr); 42610037SARM gem5 Developers 42710037SARM gem5 Developers UNSERIALIZE_SCALAR(haveSecurity); 42810037SARM gem5 Developers UNSERIALIZE_SCALAR(haveLPAE); 42910037SARM gem5 Developers UNSERIALIZE_SCALAR(haveVirtualization); 43010037SARM gem5 Developers UNSERIALIZE_SCALAR(haveLargeAsid64); 43110037SARM gem5 Developers UNSERIALIZE_SCALAR(physAddrRange64); 4327733SAli.Saidi@ARM.com } 4336313Sgblack@eecs.umich.edu 4349461Snilay@cs.wisc.edu void startup(ThreadContext *tc) {} 4359461Snilay@cs.wisc.edu 43611165SRekai.GonzalezAlberquilla@arm.com Enums::DecoderFlavour decoderFlavour() const { return _decoderFlavour; } 43711165SRekai.GonzalezAlberquilla@arm.com 4389553Sandreas.hansson@arm.com /// Explicitly import the otherwise hidden startup 4399553Sandreas.hansson@arm.com using SimObject::startup; 4409553Sandreas.hansson@arm.com 4419384SAndreas.Sandberg@arm.com typedef ArmISAParams Params; 4427400SAli.Saidi@ARM.com 4439384SAndreas.Sandberg@arm.com const Params *params() const; 4449384SAndreas.Sandberg@arm.com 4459384SAndreas.Sandberg@arm.com ISA(Params *p); 4466313Sgblack@eecs.umich.edu }; 4476313Sgblack@eecs.umich.edu} 4486313Sgblack@eecs.umich.edu 4496313Sgblack@eecs.umich.edu#endif 450