isa.cc revision 9431:8bb372a49e1b
18981Sandreas.hansson@arm.com/* 213573Ssascha.bischoff@arm.com * Copyright (c) 2010-2012 ARM Limited 311804Srjthakur@google.com * All rights reserved 411904Spierre-yves.peneau@lirmm.fr * 511804Srjthakur@google.com * The license below extends only to copyright in the software and shall 68981Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78981Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88981Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98981Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108981Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118981Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128981Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138981Sandreas.hansson@arm.com * 148981Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 158981Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 168981Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 178981Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 188981Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 198981Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 208981Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 218981Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 228981Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 238981Sandreas.hansson@arm.com * this software without specific prior written permission. 248981Sandreas.hansson@arm.com * 258981Sandreas.hansson@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 268981Sandreas.hansson@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 278981Sandreas.hansson@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 288981Sandreas.hansson@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 298981Sandreas.hansson@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 308981Sandreas.hansson@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 318981Sandreas.hansson@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 328981Sandreas.hansson@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 338981Sandreas.hansson@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 348981Sandreas.hansson@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 358981Sandreas.hansson@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 368981Sandreas.hansson@arm.com * 378981Sandreas.hansson@arm.com * Authors: Gabe Black 388981Sandreas.hansson@arm.com * Ali Saidi 398981Sandreas.hansson@arm.com */ 408981Sandreas.hansson@arm.com 4111804Srjthakur@google.com#include "arch/arm/isa.hh" 4211904Spierre-yves.peneau@lirmm.fr#include "arch/arm/system.hh" 438981Sandreas.hansson@arm.com#include "cpu/checker/cpu.hh" 448981Sandreas.hansson@arm.com#include "debug/Arm.hh" 458981Sandreas.hansson@arm.com#include "debug/MiscRegs.hh" 468981Sandreas.hansson@arm.com#include "params/ArmISA.hh" 478981Sandreas.hansson@arm.com#include "sim/faults.hh" 488981Sandreas.hansson@arm.com#include "sim/stat_control.hh" 4913892Sgabeblack@google.com#include "sim/system.hh" 508981Sandreas.hansson@arm.com 5110994Sandreas.sandberg@arm.comnamespace ArmISA 5213892Sgabeblack@google.com{ 538981Sandreas.hansson@arm.com 548981Sandreas.hansson@arm.comISA::ISA(Params *p) 5513892Sgabeblack@google.com : SimObject(p) 568981Sandreas.hansson@arm.com{ 578981Sandreas.hansson@arm.com SCTLR sctlr; 588981Sandreas.hansson@arm.com sctlr = 0; 598981Sandreas.hansson@arm.com miscRegs[MISCREG_SCTLR_RST] = sctlr; 608981Sandreas.hansson@arm.com clear(); 618981Sandreas.hansson@arm.com} 628981Sandreas.hansson@arm.com 638981Sandreas.hansson@arm.comconst ArmISAParams * 648981Sandreas.hansson@arm.comISA::params() const 6513892Sgabeblack@google.com{ 668981Sandreas.hansson@arm.com return dynamic_cast<const Params *>(_params); 678981Sandreas.hansson@arm.com} 6810902Sandreas.sandberg@arm.com 698981Sandreas.hansson@arm.comvoid 708981Sandreas.hansson@arm.comISA::clear() 718981Sandreas.hansson@arm.com{ 728981Sandreas.hansson@arm.com const Params *p(params()); 738981Sandreas.hansson@arm.com 748981Sandreas.hansson@arm.com SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 758981Sandreas.hansson@arm.com memset(miscRegs, 0, sizeof(miscRegs)); 768981Sandreas.hansson@arm.com CPSR cpsr = 0; 778981Sandreas.hansson@arm.com cpsr.mode = MODE_USER; 788981Sandreas.hansson@arm.com miscRegs[MISCREG_CPSR] = cpsr; 798981Sandreas.hansson@arm.com updateRegMap(cpsr); 808981Sandreas.hansson@arm.com 818981Sandreas.hansson@arm.com SCTLR sctlr = 0; 8211168Sandreas.hansson@arm.com sctlr.te = (bool)sctlr_rst.te; 8311168Sandreas.hansson@arm.com sctlr.nmfi = (bool)sctlr_rst.nmfi; 8411168Sandreas.hansson@arm.com sctlr.v = (bool)sctlr_rst.v; 8511168Sandreas.hansson@arm.com sctlr.u = 1; 868981Sandreas.hansson@arm.com sctlr.xp = 1; 8713892Sgabeblack@google.com sctlr.rao2 = 1; 8813784Sgabeblack@google.com sctlr.rao3 = 1; 8913784Sgabeblack@google.com sctlr.rao4 = 1; 908981Sandreas.hansson@arm.com miscRegs[MISCREG_SCTLR] = sctlr; 918981Sandreas.hansson@arm.com miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 928981Sandreas.hansson@arm.com 938981Sandreas.hansson@arm.com /* Start with an event in the mailbox */ 948981Sandreas.hansson@arm.com miscRegs[MISCREG_SEV_MAILBOX] = 1; 958981Sandreas.hansson@arm.com 968981Sandreas.hansson@arm.com // Separate Instruction and Data TLBs. 978981Sandreas.hansson@arm.com miscRegs[MISCREG_TLBTR] = 1; 988981Sandreas.hansson@arm.com 998981Sandreas.hansson@arm.com MVFR0 mvfr0 = 0; 1008981Sandreas.hansson@arm.com mvfr0.advSimdRegisters = 2; 1018981Sandreas.hansson@arm.com mvfr0.singlePrecision = 2; 1028981Sandreas.hansson@arm.com mvfr0.doublePrecision = 2; 1039542Sandreas.hansson@arm.com mvfr0.vfpExceptionTrapping = 0; 1049542Sandreas.hansson@arm.com mvfr0.divide = 1; 1058981Sandreas.hansson@arm.com mvfr0.squareRoot = 1; 1068981Sandreas.hansson@arm.com mvfr0.shortVectors = 1; 1078981Sandreas.hansson@arm.com mvfr0.roundingModes = 1; 1089542Sandreas.hansson@arm.com miscRegs[MISCREG_MVFR0] = mvfr0; 1099542Sandreas.hansson@arm.com 1108981Sandreas.hansson@arm.com MVFR1 mvfr1 = 0; 1118981Sandreas.hansson@arm.com mvfr1.flushToZero = 1; 1128981Sandreas.hansson@arm.com mvfr1.defaultNaN = 1; 1138981Sandreas.hansson@arm.com mvfr1.advSimdLoadStore = 1; 1148981Sandreas.hansson@arm.com mvfr1.advSimdInteger = 1; 1158981Sandreas.hansson@arm.com mvfr1.advSimdSinglePrecision = 1; 1168981Sandreas.hansson@arm.com mvfr1.advSimdHalfPrecision = 1; 1178981Sandreas.hansson@arm.com mvfr1.vfpHalfPrecision = 1; 1188981Sandreas.hansson@arm.com miscRegs[MISCREG_MVFR1] = mvfr1; 1198981Sandreas.hansson@arm.com 1208981Sandreas.hansson@arm.com // Reset values of PRRR and NMRR are implementation dependent 1218981Sandreas.hansson@arm.com 1228981Sandreas.hansson@arm.com miscRegs[MISCREG_PRRR] = 1238981Sandreas.hansson@arm.com (1 << 19) | // 19 1248981Sandreas.hansson@arm.com (0 << 18) | // 18 1258981Sandreas.hansson@arm.com (0 << 17) | // 17 1268981Sandreas.hansson@arm.com (1 << 16) | // 16 1278981Sandreas.hansson@arm.com (2 << 14) | // 15:14 1288981Sandreas.hansson@arm.com (0 << 12) | // 13:12 1298981Sandreas.hansson@arm.com (2 << 10) | // 11:10 1308981Sandreas.hansson@arm.com (2 << 8) | // 9:8 1318981Sandreas.hansson@arm.com (2 << 6) | // 7:6 1328981Sandreas.hansson@arm.com (2 << 4) | // 5:4 1338981Sandreas.hansson@arm.com (1 << 2) | // 3:2 1348981Sandreas.hansson@arm.com 0; // 1:0 1358981Sandreas.hansson@arm.com miscRegs[MISCREG_NMRR] = 1368981Sandreas.hansson@arm.com (1 << 30) | // 31:30 1378981Sandreas.hansson@arm.com (0 << 26) | // 27:26 1388981Sandreas.hansson@arm.com (0 << 24) | // 25:24 1398981Sandreas.hansson@arm.com (3 << 22) | // 23:22 1408981Sandreas.hansson@arm.com (2 << 20) | // 21:20 1418981Sandreas.hansson@arm.com (0 << 18) | // 19:18 1428981Sandreas.hansson@arm.com (0 << 16) | // 17:16 1438981Sandreas.hansson@arm.com (1 << 14) | // 15:14 1448981Sandreas.hansson@arm.com (0 << 12) | // 13:12 1458981Sandreas.hansson@arm.com (2 << 10) | // 11:10 1468981Sandreas.hansson@arm.com (0 << 8) | // 9:8 1478981Sandreas.hansson@arm.com (3 << 6) | // 7:6 1488981Sandreas.hansson@arm.com (2 << 4) | // 5:4 1498981Sandreas.hansson@arm.com (0 << 2) | // 3:2 1508981Sandreas.hansson@arm.com 0; // 1:0 1518981Sandreas.hansson@arm.com 1528981Sandreas.hansson@arm.com miscRegs[MISCREG_CPACR] = 0; 1538981Sandreas.hansson@arm.com 1548981Sandreas.hansson@arm.com // Initialize configurable default values 1558981Sandreas.hansson@arm.com miscRegs[MISCREG_MIDR] = p->midr; 1568981Sandreas.hansson@arm.com 1578981Sandreas.hansson@arm.com miscRegs[MISCREG_ID_PFR0] = p->id_pfr0; 1588981Sandreas.hansson@arm.com miscRegs[MISCREG_ID_PFR1] = p->id_pfr1; 1598981Sandreas.hansson@arm.com 1608981Sandreas.hansson@arm.com miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 1618981Sandreas.hansson@arm.com miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 1628981Sandreas.hansson@arm.com miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 1638981Sandreas.hansson@arm.com miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 1648981Sandreas.hansson@arm.com 1658981Sandreas.hansson@arm.com miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 1668981Sandreas.hansson@arm.com miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 16710713Sandreas.hansson@arm.com miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 1688981Sandreas.hansson@arm.com miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 16910713Sandreas.hansson@arm.com miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 1708981Sandreas.hansson@arm.com miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 1718981Sandreas.hansson@arm.com 17211173Sandreas.hansson@arm.com 17311173Sandreas.hansson@arm.com miscRegs[MISCREG_FPSID] = p->fpsid; 17411173Sandreas.hansson@arm.com 17511173Sandreas.hansson@arm.com 17611173Sandreas.hansson@arm.com //XXX We need to initialize the rest of the state. 1778981Sandreas.hansson@arm.com} 1788981Sandreas.hansson@arm.com 1798981Sandreas.hansson@arm.comMiscReg 1808981Sandreas.hansson@arm.comISA::readMiscRegNoEffect(int misc_reg) 1818981Sandreas.hansson@arm.com{ 1828981Sandreas.hansson@arm.com assert(misc_reg < NumMiscRegs); 1838981Sandreas.hansson@arm.com 1848981Sandreas.hansson@arm.com int flat_idx; 1858981Sandreas.hansson@arm.com if (misc_reg == MISCREG_SPSR) 1868981Sandreas.hansson@arm.com flat_idx = flattenMiscIndex(misc_reg); 1878981Sandreas.hansson@arm.com else 1888981Sandreas.hansson@arm.com flat_idx = misc_reg; 1898981Sandreas.hansson@arm.com MiscReg val = miscRegs[flat_idx]; 1908981Sandreas.hansson@arm.com 1918981Sandreas.hansson@arm.com DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n", 1928981Sandreas.hansson@arm.com misc_reg, flat_idx, val); 1938981Sandreas.hansson@arm.com return val; 1948981Sandreas.hansson@arm.com} 1958981Sandreas.hansson@arm.com 1968981Sandreas.hansson@arm.com 1978981Sandreas.hansson@arm.comMiscReg 1988981Sandreas.hansson@arm.comISA::readMiscReg(int misc_reg, ThreadContext *tc) 1998981Sandreas.hansson@arm.com{ 2008981Sandreas.hansson@arm.com ArmSystem *arm_sys; 2018981Sandreas.hansson@arm.com 2028981Sandreas.hansson@arm.com if (misc_reg == MISCREG_CPSR) { 2038981Sandreas.hansson@arm.com CPSR cpsr = miscRegs[misc_reg]; 2048981Sandreas.hansson@arm.com PCState pc = tc->pcState(); 2058981Sandreas.hansson@arm.com cpsr.j = pc.jazelle() ? 1 : 0; 2068981Sandreas.hansson@arm.com cpsr.t = pc.thumb() ? 1 : 0; 2078981Sandreas.hansson@arm.com return cpsr; 2088981Sandreas.hansson@arm.com } 2098981Sandreas.hansson@arm.com if (misc_reg >= MISCREG_CP15_UNIMP_START) 2108981Sandreas.hansson@arm.com panic("Unimplemented CP15 register %s read.\n", 2118981Sandreas.hansson@arm.com miscRegName[misc_reg]); 2128981Sandreas.hansson@arm.com 2138981Sandreas.hansson@arm.com switch (misc_reg) { 2148981Sandreas.hansson@arm.com case MISCREG_MPIDR: 2158981Sandreas.hansson@arm.com arm_sys = dynamic_cast<ArmSystem*>(tc->getSystemPtr()); 2168981Sandreas.hansson@arm.com assert(arm_sys); 2178981Sandreas.hansson@arm.com 2188981Sandreas.hansson@arm.com if (arm_sys->multiProc) { 2198981Sandreas.hansson@arm.com return 0x80000000 | // multiprocessor extensions available 2208981Sandreas.hansson@arm.com tc->cpuId(); 2218981Sandreas.hansson@arm.com } else { 2228981Sandreas.hansson@arm.com return 0x80000000 | // multiprocessor extensions available 2239090Sandreas.hansson@arm.com 0x40000000 | // in up system 2248981Sandreas.hansson@arm.com tc->cpuId(); 2258981Sandreas.hansson@arm.com } 2268981Sandreas.hansson@arm.com break; 2278981Sandreas.hansson@arm.com case MISCREG_CLIDR: 22810713Sandreas.hansson@arm.com warn_once("The clidr register always reports 0 caches.\n"); 2298981Sandreas.hansson@arm.com warn_once("clidr LoUIS field of 0b001 to match current " 23010713Sandreas.hansson@arm.com "ARM implementations.\n"); 2318981Sandreas.hansson@arm.com return 0x00200000; 2328981Sandreas.hansson@arm.com case MISCREG_CCSIDR: 23313573Ssascha.bischoff@arm.com warn_once("The ccsidr register isn't implemented and " 23413573Ssascha.bischoff@arm.com "always reads as 0.\n"); 23513573Ssascha.bischoff@arm.com break; 23613573Ssascha.bischoff@arm.com case MISCREG_CTR: 23713573Ssascha.bischoff@arm.com { 2388981Sandreas.hansson@arm.com //all caches have the same line size in gem5 2398981Sandreas.hansson@arm.com //4 byte words in ARM 2408981Sandreas.hansson@arm.com unsigned lineSizeWords = 2418981Sandreas.hansson@arm.com tc->getCpuPtr()->getInstPort().peerBlockSize() / 4; 2428981Sandreas.hansson@arm.com unsigned log2LineSizeWords = 0; 2438981Sandreas.hansson@arm.com 2448981Sandreas.hansson@arm.com while (lineSizeWords >>= 1) { 2458981Sandreas.hansson@arm.com ++log2LineSizeWords; 2468981Sandreas.hansson@arm.com } 2478981Sandreas.hansson@arm.com 2488981Sandreas.hansson@arm.com CTR ctr = 0; 2498981Sandreas.hansson@arm.com //log2 of minimun i-cache line size (words) 2508981Sandreas.hansson@arm.com ctr.iCacheLineSize = log2LineSizeWords; 2518981Sandreas.hansson@arm.com //b11 - gem5 uses pipt 2528981Sandreas.hansson@arm.com ctr.l1IndexPolicy = 0x3; 2538981Sandreas.hansson@arm.com //log2 of minimum d-cache line size (words) 2548981Sandreas.hansson@arm.com ctr.dCacheLineSize = log2LineSizeWords; 2558981Sandreas.hansson@arm.com //log2 of max reservation size (words) 2568981Sandreas.hansson@arm.com ctr.erg = log2LineSizeWords; 2578981Sandreas.hansson@arm.com //log2 of max writeback size (words) 2588981Sandreas.hansson@arm.com ctr.cwg = log2LineSizeWords; 2598981Sandreas.hansson@arm.com //b100 - gem5 format is ARMv7 2608981Sandreas.hansson@arm.com ctr.format = 0x4; 2618981Sandreas.hansson@arm.com 2628981Sandreas.hansson@arm.com return ctr; 26311173Sandreas.hansson@arm.com } 26411173Sandreas.hansson@arm.com case MISCREG_ACTLR: 2659090Sandreas.hansson@arm.com warn("Not doing anything for miscreg ACTLR\n"); 2668981Sandreas.hansson@arm.com break; 2678981Sandreas.hansson@arm.com case MISCREG_PMCR: 2688981Sandreas.hansson@arm.com case MISCREG_PMCCNTR: 26910713Sandreas.hansson@arm.com case MISCREG_PMSELR: 2708981Sandreas.hansson@arm.com warn("Not doing anything for read to miscreg %s\n", 27110713Sandreas.hansson@arm.com miscRegName[misc_reg]); 2728981Sandreas.hansson@arm.com break; 2738981Sandreas.hansson@arm.com case MISCREG_CPSR_Q: 2748981Sandreas.hansson@arm.com panic("shouldn't be reading this register seperately\n"); 27513573Ssascha.bischoff@arm.com case MISCREG_FPSCR_QC: 27613573Ssascha.bischoff@arm.com return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 2778981Sandreas.hansson@arm.com case MISCREG_FPSCR_EXC: 2788981Sandreas.hansson@arm.com return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 2798981Sandreas.hansson@arm.com case MISCREG_L2CTLR: 2808981Sandreas.hansson@arm.com { 28111848Spierre-yves.peneau@lirmm.fr // mostly unimplemented, just set NumCPUs field from sim and return 2828981Sandreas.hansson@arm.com L2CTLR l2ctlr = 0; 2838981Sandreas.hansson@arm.com // b00:1CPU to b11:4CPUs 2848981Sandreas.hansson@arm.com l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 2858981Sandreas.hansson@arm.com return l2ctlr; 2868981Sandreas.hansson@arm.com } 2878981Sandreas.hansson@arm.com case MISCREG_DBGDIDR: 2888981Sandreas.hansson@arm.com /* For now just implement the version number. 2898981Sandreas.hansson@arm.com * Return 0 as we don't support debug architecture yet. 2908981Sandreas.hansson@arm.com */ 2918981Sandreas.hansson@arm.com return 0; 2928981Sandreas.hansson@arm.com case MISCREG_DBGDSCR_INT: 2938981Sandreas.hansson@arm.com return 0; 2948981Sandreas.hansson@arm.com } 2958981Sandreas.hansson@arm.com return readMiscRegNoEffect(misc_reg); 2968981Sandreas.hansson@arm.com} 2978981Sandreas.hansson@arm.com 2988981Sandreas.hansson@arm.comvoid 2998981Sandreas.hansson@arm.comISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 3008981Sandreas.hansson@arm.com{ 3018981Sandreas.hansson@arm.com assert(misc_reg < NumMiscRegs); 3028981Sandreas.hansson@arm.com 3038981Sandreas.hansson@arm.com int flat_idx; 3048981Sandreas.hansson@arm.com if (misc_reg == MISCREG_SPSR) 3058981Sandreas.hansson@arm.com flat_idx = flattenMiscIndex(misc_reg); 3068981Sandreas.hansson@arm.com else 3078981Sandreas.hansson@arm.com flat_idx = misc_reg; 3088981Sandreas.hansson@arm.com miscRegs[flat_idx] = val; 3098981Sandreas.hansson@arm.com 3108981Sandreas.hansson@arm.com DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg, 3118981Sandreas.hansson@arm.com flat_idx, val); 3128981Sandreas.hansson@arm.com} 3138981Sandreas.hansson@arm.com 3148981Sandreas.hansson@arm.comvoid 3158981Sandreas.hansson@arm.comISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 3168981Sandreas.hansson@arm.com{ 3178981Sandreas.hansson@arm.com 3188981Sandreas.hansson@arm.com MiscReg newVal = val; 3198981Sandreas.hansson@arm.com int x; 3208981Sandreas.hansson@arm.com System *sys; 3218981Sandreas.hansson@arm.com ThreadContext *oc; 3228981Sandreas.hansson@arm.com 3238981Sandreas.hansson@arm.com if (misc_reg == MISCREG_CPSR) { 3248981Sandreas.hansson@arm.com updateRegMap(val); 3258981Sandreas.hansson@arm.com 3268981Sandreas.hansson@arm.com 3278981Sandreas.hansson@arm.com CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 3288981Sandreas.hansson@arm.com int old_mode = old_cpsr.mode; 3298981Sandreas.hansson@arm.com CPSR cpsr = val; 3308981Sandreas.hansson@arm.com if (old_mode != cpsr.mode) { 3318981Sandreas.hansson@arm.com tc->getITBPtr()->invalidateMiscReg(); 3328981Sandreas.hansson@arm.com tc->getDTBPtr()->invalidateMiscReg(); 3338981Sandreas.hansson@arm.com } 3348981Sandreas.hansson@arm.com 3358981Sandreas.hansson@arm.com DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 3368981Sandreas.hansson@arm.com miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 3378981Sandreas.hansson@arm.com PCState pc = tc->pcState(); 3388981Sandreas.hansson@arm.com pc.nextThumb(cpsr.t); 3398981Sandreas.hansson@arm.com pc.nextJazelle(cpsr.j); 3408981Sandreas.hansson@arm.com 3418981Sandreas.hansson@arm.com // Follow slightly different semantics if a CheckerCPU object 3428981Sandreas.hansson@arm.com // is connected 3438981Sandreas.hansson@arm.com CheckerCPU *checker = tc->getCheckerCpuPtr(); 3448981Sandreas.hansson@arm.com if (checker) { 3458981Sandreas.hansson@arm.com tc->pcStateNoRecord(pc); 3468981Sandreas.hansson@arm.com } else { 3478981Sandreas.hansson@arm.com tc->pcState(pc); 3488981Sandreas.hansson@arm.com } 3498981Sandreas.hansson@arm.com } else if (misc_reg >= MISCREG_CP15_UNIMP_START && 3508981Sandreas.hansson@arm.com misc_reg < MISCREG_CP15_END) { 3518981Sandreas.hansson@arm.com panic("Unimplemented CP15 register %s wrote with %#x.\n", 3528981Sandreas.hansson@arm.com miscRegName[misc_reg], val); 3538981Sandreas.hansson@arm.com } else { 3548981Sandreas.hansson@arm.com switch (misc_reg) { 3558981Sandreas.hansson@arm.com case MISCREG_CPACR: 3568981Sandreas.hansson@arm.com { 3578981Sandreas.hansson@arm.com 3588981Sandreas.hansson@arm.com const uint32_t ones = (uint32_t)(-1); 3598981Sandreas.hansson@arm.com CPACR cpacrMask = 0; 3608981Sandreas.hansson@arm.com // Only cp10, cp11, and ase are implemented, nothing else should 3618981Sandreas.hansson@arm.com // be writable 3628981Sandreas.hansson@arm.com cpacrMask.cp10 = ones; 3638981Sandreas.hansson@arm.com cpacrMask.cp11 = ones; 3648981Sandreas.hansson@arm.com cpacrMask.asedis = ones; 3658981Sandreas.hansson@arm.com newVal &= cpacrMask; 3668981Sandreas.hansson@arm.com DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 3678981Sandreas.hansson@arm.com miscRegName[misc_reg], newVal); 3688981Sandreas.hansson@arm.com } 36911804Srjthakur@google.com break; 37011804Srjthakur@google.com case MISCREG_CSSELR: 37111804Srjthakur@google.com warn_once("The csselr register isn't implemented.\n"); 37211804Srjthakur@google.com return; 37311804Srjthakur@google.com case MISCREG_FPSCR: 37411804Srjthakur@google.com { 3758981Sandreas.hansson@arm.com const uint32_t ones = (uint32_t)(-1); 3768981Sandreas.hansson@arm.com FPSCR fpscrMask = 0; 3778981Sandreas.hansson@arm.com fpscrMask.ioc = ones; 3788981Sandreas.hansson@arm.com fpscrMask.dzc = ones; 3798981Sandreas.hansson@arm.com fpscrMask.ofc = ones; 3808981Sandreas.hansson@arm.com fpscrMask.ufc = ones; 3818981Sandreas.hansson@arm.com fpscrMask.ixc = ones; 3828981Sandreas.hansson@arm.com fpscrMask.idc = ones; 3838981Sandreas.hansson@arm.com fpscrMask.len = ones; 3848981Sandreas.hansson@arm.com fpscrMask.stride = ones; 3858981Sandreas.hansson@arm.com fpscrMask.rMode = ones; 3868981Sandreas.hansson@arm.com fpscrMask.fz = ones; 3878981Sandreas.hansson@arm.com fpscrMask.dn = ones; 3888981Sandreas.hansson@arm.com fpscrMask.ahp = ones; 3898981Sandreas.hansson@arm.com fpscrMask.qc = ones; 3908981Sandreas.hansson@arm.com fpscrMask.v = ones; 3918981Sandreas.hansson@arm.com fpscrMask.c = ones; 3928981Sandreas.hansson@arm.com fpscrMask.z = ones; 3938981Sandreas.hansson@arm.com fpscrMask.n = ones; 3948981Sandreas.hansson@arm.com newVal = (newVal & (uint32_t)fpscrMask) | 3958981Sandreas.hansson@arm.com (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask); 3968981Sandreas.hansson@arm.com tc->getDecoderPtr()->setContext(newVal); 3978981Sandreas.hansson@arm.com } 3988981Sandreas.hansson@arm.com break; 3998981Sandreas.hansson@arm.com case MISCREG_CPSR_Q: 4008981Sandreas.hansson@arm.com { 4018981Sandreas.hansson@arm.com assert(!(newVal & ~CpsrMaskQ)); 4028981Sandreas.hansson@arm.com newVal = miscRegs[MISCREG_CPSR] | newVal; 40311804Srjthakur@google.com misc_reg = MISCREG_CPSR; 40411804Srjthakur@google.com } 40511804Srjthakur@google.com break; 4068981Sandreas.hansson@arm.com case MISCREG_FPSCR_QC: 4078981Sandreas.hansson@arm.com { 40811804Srjthakur@google.com newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrQcMask); 40911804Srjthakur@google.com misc_reg = MISCREG_FPSCR; 41011804Srjthakur@google.com } 41111804Srjthakur@google.com break; 4128981Sandreas.hansson@arm.com case MISCREG_FPSCR_EXC: 4138981Sandreas.hansson@arm.com { 4148981Sandreas.hansson@arm.com newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrExcMask); 4158981Sandreas.hansson@arm.com misc_reg = MISCREG_FPSCR; 4168981Sandreas.hansson@arm.com } 4178981Sandreas.hansson@arm.com break; 41812084Sspwilson2@wisc.edu case MISCREG_FPEXC: 4198981Sandreas.hansson@arm.com { 42010902Sandreas.sandberg@arm.com // vfpv3 architecture, section B.6.1 of DDI04068 42110902Sandreas.sandberg@arm.com // bit 29 - valid only if fpexc[31] is 0 42210902Sandreas.sandberg@arm.com const uint32_t fpexcMask = 0x60000000; 42310902Sandreas.sandberg@arm.com newVal = (newVal & fpexcMask) | 42410902Sandreas.sandberg@arm.com (miscRegs[MISCREG_FPEXC] & ~fpexcMask); 4258981Sandreas.hansson@arm.com } 42610902Sandreas.sandberg@arm.com break; 42710902Sandreas.sandberg@arm.com case MISCREG_SCTLR: 42810902Sandreas.sandberg@arm.com { 4298981Sandreas.hansson@arm.com DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 43010902Sandreas.sandberg@arm.com SCTLR sctlr = miscRegs[MISCREG_SCTLR]; 43110902Sandreas.sandberg@arm.com SCTLR new_sctlr = newVal; 4328981Sandreas.hansson@arm.com new_sctlr.nmfi = (bool)sctlr.nmfi; 4338981Sandreas.hansson@arm.com miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr; 43410994Sandreas.sandberg@arm.com tc->getITBPtr()->invalidateMiscReg(); 43510994Sandreas.sandberg@arm.com tc->getDTBPtr()->invalidateMiscReg(); 43610994Sandreas.sandberg@arm.com 43710994Sandreas.sandberg@arm.com // Check if all CPUs are booted with caches enabled 43810994Sandreas.sandberg@arm.com // so we can stop enforcing coherency of some kernel 43910994Sandreas.sandberg@arm.com // structures manually. 44010994Sandreas.sandberg@arm.com sys = tc->getSystemPtr(); 44110994Sandreas.sandberg@arm.com for (x = 0; x < sys->numContexts(); x++) { 44210994Sandreas.sandberg@arm.com oc = sys->getThreadContext(x); 44310994Sandreas.sandberg@arm.com SCTLR other_sctlr = oc->readMiscRegNoEffect(MISCREG_SCTLR); 44410994Sandreas.sandberg@arm.com if (!other_sctlr.c && oc->status() != ThreadContext::Halted) 44510994Sandreas.sandberg@arm.com return; 44610994Sandreas.sandberg@arm.com } 44710994Sandreas.sandberg@arm.com 4488981Sandreas.hansson@arm.com for (x = 0; x < sys->numContexts(); x++) { 4498981Sandreas.hansson@arm.com oc = sys->getThreadContext(x); 4508981Sandreas.hansson@arm.com oc->getDTBPtr()->allCpusCaching(); 451 oc->getITBPtr()->allCpusCaching(); 452 453 // If CheckerCPU is connected, need to notify it. 454 CheckerCPU *checker = oc->getCheckerCpuPtr(); 455 if (checker) { 456 checker->getDTBPtr()->allCpusCaching(); 457 checker->getITBPtr()->allCpusCaching(); 458 } 459 } 460 return; 461 } 462 463 case MISCREG_MIDR: 464 case MISCREG_ID_PFR0: 465 case MISCREG_ID_PFR1: 466 case MISCREG_ID_MMFR0: 467 case MISCREG_ID_MMFR1: 468 case MISCREG_ID_MMFR2: 469 case MISCREG_ID_MMFR3: 470 case MISCREG_ID_ISAR0: 471 case MISCREG_ID_ISAR1: 472 case MISCREG_ID_ISAR2: 473 case MISCREG_ID_ISAR3: 474 case MISCREG_ID_ISAR4: 475 case MISCREG_ID_ISAR5: 476 477 case MISCREG_MPIDR: 478 case MISCREG_FPSID: 479 case MISCREG_TLBTR: 480 case MISCREG_MVFR0: 481 case MISCREG_MVFR1: 482 // ID registers are constants. 483 return; 484 485 case MISCREG_TLBIALLIS: 486 case MISCREG_TLBIALL: 487 sys = tc->getSystemPtr(); 488 for (x = 0; x < sys->numContexts(); x++) { 489 oc = sys->getThreadContext(x); 490 assert(oc->getITBPtr() && oc->getDTBPtr()); 491 oc->getITBPtr()->flushAll(); 492 oc->getDTBPtr()->flushAll(); 493 494 // If CheckerCPU is connected, need to notify it of a flush 495 CheckerCPU *checker = oc->getCheckerCpuPtr(); 496 if (checker) { 497 checker->getITBPtr()->flushAll(); 498 checker->getDTBPtr()->flushAll(); 499 } 500 } 501 return; 502 case MISCREG_ITLBIALL: 503 tc->getITBPtr()->flushAll(); 504 return; 505 case MISCREG_DTLBIALL: 506 tc->getDTBPtr()->flushAll(); 507 return; 508 case MISCREG_TLBIMVAIS: 509 case MISCREG_TLBIMVA: 510 sys = tc->getSystemPtr(); 511 for (x = 0; x < sys->numContexts(); x++) { 512 oc = sys->getThreadContext(x); 513 assert(oc->getITBPtr() && oc->getDTBPtr()); 514 oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 515 bits(newVal, 7,0)); 516 oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 517 bits(newVal, 7,0)); 518 519 CheckerCPU *checker = oc->getCheckerCpuPtr(); 520 if (checker) { 521 checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 522 bits(newVal, 7,0)); 523 checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 524 bits(newVal, 7,0)); 525 } 526 } 527 return; 528 case MISCREG_TLBIASIDIS: 529 case MISCREG_TLBIASID: 530 sys = tc->getSystemPtr(); 531 for (x = 0; x < sys->numContexts(); x++) { 532 oc = sys->getThreadContext(x); 533 assert(oc->getITBPtr() && oc->getDTBPtr()); 534 oc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 535 oc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 536 CheckerCPU *checker = oc->getCheckerCpuPtr(); 537 if (checker) { 538 checker->getITBPtr()->flushAsid(bits(newVal, 7,0)); 539 checker->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 540 } 541 } 542 return; 543 case MISCREG_TLBIMVAAIS: 544 case MISCREG_TLBIMVAA: 545 sys = tc->getSystemPtr(); 546 for (x = 0; x < sys->numContexts(); x++) { 547 oc = sys->getThreadContext(x); 548 assert(oc->getITBPtr() && oc->getDTBPtr()); 549 oc->getITBPtr()->flushMva(mbits(newVal, 31,12)); 550 oc->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 551 552 CheckerCPU *checker = oc->getCheckerCpuPtr(); 553 if (checker) { 554 checker->getITBPtr()->flushMva(mbits(newVal, 31,12)); 555 checker->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 556 } 557 } 558 return; 559 case MISCREG_ITLBIMVA: 560 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 561 bits(newVal, 7,0)); 562 return; 563 case MISCREG_DTLBIMVA: 564 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 565 bits(newVal, 7,0)); 566 return; 567 case MISCREG_ITLBIASID: 568 tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 569 return; 570 case MISCREG_DTLBIASID: 571 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 572 return; 573 case MISCREG_ACTLR: 574 warn("Not doing anything for write of miscreg ACTLR\n"); 575 break; 576 case MISCREG_PMCR: 577 { 578 // Performance counters not implemented. Instead, interpret 579 // a reset command to this register to reset the simulator 580 // statistics. 581 // PMCR_E | PMCR_P | PMCR_C 582 const int ResetAndEnableCounters = 0x7; 583 if (newVal == ResetAndEnableCounters) { 584 inform("Resetting all simobject stats\n"); 585 Stats::schedStatEvent(false, true); 586 break; 587 } 588 } 589 case MISCREG_PMCCNTR: 590 case MISCREG_PMSELR: 591 warn("Not doing anything for write to miscreg %s\n", 592 miscRegName[misc_reg]); 593 break; 594 case MISCREG_V2PCWPR: 595 case MISCREG_V2PCWPW: 596 case MISCREG_V2PCWUR: 597 case MISCREG_V2PCWUW: 598 case MISCREG_V2POWPR: 599 case MISCREG_V2POWPW: 600 case MISCREG_V2POWUR: 601 case MISCREG_V2POWUW: 602 { 603 RequestPtr req = new Request; 604 unsigned flags; 605 BaseTLB::Mode mode; 606 Fault fault; 607 switch(misc_reg) { 608 case MISCREG_V2PCWPR: 609 flags = TLB::MustBeOne; 610 mode = BaseTLB::Read; 611 break; 612 case MISCREG_V2PCWPW: 613 flags = TLB::MustBeOne; 614 mode = BaseTLB::Write; 615 break; 616 case MISCREG_V2PCWUR: 617 flags = TLB::MustBeOne | TLB::UserMode; 618 mode = BaseTLB::Read; 619 break; 620 case MISCREG_V2PCWUW: 621 flags = TLB::MustBeOne | TLB::UserMode; 622 mode = BaseTLB::Write; 623 break; 624 default: 625 panic("Security Extensions not implemented!"); 626 } 627 warn("Translating via MISCREG in atomic mode! Fix Me!\n"); 628 req->setVirt(0, val, 1, flags, tc->pcState().pc(), 629 Request::funcMasterId); 630 fault = tc->getDTBPtr()->translateAtomic(req, tc, mode); 631 if (fault == NoFault) { 632 miscRegs[MISCREG_PAR] = 633 (req->getPaddr() & 0xfffff000) | 634 (tc->getDTBPtr()->getAttr() ); 635 DPRINTF(MiscRegs, 636 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 637 val, miscRegs[MISCREG_PAR]); 638 } 639 else { 640 // Set fault bit and FSR 641 FSR fsr = miscRegs[MISCREG_DFSR]; 642 miscRegs[MISCREG_PAR] = 643 (fsr.ext << 6) | 644 (fsr.fsHigh << 5) | 645 (fsr.fsLow << 1) | 646 0x1; // F bit 647 } 648 return; 649 } 650 case MISCREG_CONTEXTIDR: 651 case MISCREG_PRRR: 652 case MISCREG_NMRR: 653 case MISCREG_DACR: 654 tc->getITBPtr()->invalidateMiscReg(); 655 tc->getDTBPtr()->invalidateMiscReg(); 656 break; 657 case MISCREG_L2CTLR: 658 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 659 miscRegName[misc_reg], uint32_t(val)); 660 } 661 } 662 setMiscRegNoEffect(misc_reg, newVal); 663} 664 665} 666 667ArmISA::ISA * 668ArmISAParams::create() 669{ 670 return new ArmISA::ISA(this); 671} 672