isa.cc revision 9130:8423aa8c2216
110037SARM gem5 Developers/* 210037SARM gem5 Developers * Copyright (c) 2010-2012 ARM Limited 310037SARM gem5 Developers * All rights reserved 410037SARM gem5 Developers * 510037SARM gem5 Developers * The license below extends only to copyright in the software and shall 610037SARM gem5 Developers * not be construed as granting a license to any other intellectual 710037SARM gem5 Developers * property including but not limited to intellectual property relating 810037SARM gem5 Developers * to a hardware implementation of the functionality of the software 910037SARM gem5 Developers * licensed hereunder. You may use the software subject to the license 1010037SARM gem5 Developers * terms below provided that you ensure that this notice is replicated 1110037SARM gem5 Developers * unmodified and in its entirety in all distributions of the software, 1210037SARM gem5 Developers * modified or unmodified, in source code or in binary form. 1310037SARM gem5 Developers * 1410037SARM gem5 Developers * Redistribution and use in source and binary forms, with or without 1510037SARM gem5 Developers * modification, are permitted provided that the following conditions are 1610037SARM gem5 Developers * met: redistributions of source code must retain the above copyright 1710037SARM gem5 Developers * notice, this list of conditions and the following disclaimer; 1810037SARM gem5 Developers * redistributions in binary form must reproduce the above copyright 1910037SARM gem5 Developers * notice, this list of conditions and the following disclaimer in the 2010037SARM gem5 Developers * documentation and/or other materials provided with the distribution; 2110037SARM gem5 Developers * neither the name of the copyright holders nor the names of its 2210037SARM gem5 Developers * contributors may be used to endorse or promote products derived from 2310037SARM gem5 Developers * this software without specific prior written permission. 2410037SARM gem5 Developers * 2510037SARM gem5 Developers * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2610037SARM gem5 Developers * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2710037SARM gem5 Developers * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2810037SARM gem5 Developers * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2910037SARM gem5 Developers * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3010037SARM gem5 Developers * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3110037SARM gem5 Developers * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3210037SARM gem5 Developers * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3310037SARM gem5 Developers * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3410037SARM gem5 Developers * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3510037SARM gem5 Developers * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3610037SARM gem5 Developers * 3710037SARM gem5 Developers * Authors: Gabe Black 3810037SARM gem5 Developers * Ali Saidi 3910037SARM gem5 Developers */ 4010037SARM gem5 Developers 4110037SARM gem5 Developers#include "arch/arm/isa.hh" 4210037SARM gem5 Developers#include "arch/arm/system.hh" 4310037SARM gem5 Developers#include "cpu/checker/cpu.hh" 4410037SARM gem5 Developers#include "debug/Arm.hh" 4510037SARM gem5 Developers#include "debug/MiscRegs.hh" 4610037SARM gem5 Developers#include "sim/faults.hh" 4710037SARM gem5 Developers#include "sim/stat_control.hh" 4810037SARM gem5 Developers#include "sim/system.hh" 4910037SARM gem5 Developers 5010196SCurtis.Dunham@arm.comnamespace ArmISA 5110037SARM gem5 Developers{ 5210037SARM gem5 Developers 5310037SARM gem5 Developersvoid 5410037SARM gem5 DevelopersISA::clear() 5510037SARM gem5 Developers{ 5610037SARM gem5 Developers SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 5710037SARM gem5 Developers uint32_t midr = miscRegs[MISCREG_MIDR]; 5810037SARM gem5 Developers memset(miscRegs, 0, sizeof(miscRegs)); 5910037SARM gem5 Developers CPSR cpsr = 0; 6010037SARM gem5 Developers cpsr.mode = MODE_USER; 6110037SARM gem5 Developers miscRegs[MISCREG_CPSR] = cpsr; 6210037SARM gem5 Developers updateRegMap(cpsr); 6310037SARM gem5 Developers 6410037SARM gem5 Developers SCTLR sctlr = 0; 6510037SARM gem5 Developers sctlr.te = (bool)sctlr_rst.te; 6610037SARM gem5 Developers sctlr.nmfi = (bool)sctlr_rst.nmfi; 6710037SARM gem5 Developers sctlr.v = (bool)sctlr_rst.v; 6810037SARM gem5 Developers sctlr.u = 1; 6910037SARM gem5 Developers sctlr.xp = 1; 7010037SARM gem5 Developers sctlr.rao2 = 1; 7110037SARM gem5 Developers sctlr.rao3 = 1; 7210037SARM gem5 Developers sctlr.rao4 = 1; 7310037SARM gem5 Developers miscRegs[MISCREG_SCTLR] = sctlr; 7410196SCurtis.Dunham@arm.com miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 7510037SARM gem5 Developers 7610037SARM gem5 Developers // Preserve MIDR across reset 7710037SARM gem5 Developers miscRegs[MISCREG_MIDR] = midr; 7810037SARM gem5 Developers 7910037SARM gem5 Developers /* Start with an event in the mailbox */ 8010037SARM gem5 Developers miscRegs[MISCREG_SEV_MAILBOX] = 1; 8110037SARM gem5 Developers 8210037SARM gem5 Developers // Separate Instruction and Data TLBs. 8310037SARM gem5 Developers miscRegs[MISCREG_TLBTR] = 1; 8410037SARM gem5 Developers 8510037SARM gem5 Developers MVFR0 mvfr0 = 0; 8610037SARM gem5 Developers mvfr0.advSimdRegisters = 2; 8710037SARM gem5 Developers mvfr0.singlePrecision = 2; 8810037SARM gem5 Developers mvfr0.doublePrecision = 2; 8910037SARM gem5 Developers mvfr0.vfpExceptionTrapping = 0; 9010037SARM gem5 Developers mvfr0.divide = 1; 9110037SARM gem5 Developers mvfr0.squareRoot = 1; 9210037SARM gem5 Developers mvfr0.shortVectors = 1; 9310037SARM gem5 Developers mvfr0.roundingModes = 1; 9410037SARM gem5 Developers miscRegs[MISCREG_MVFR0] = mvfr0; 9510037SARM gem5 Developers 9610037SARM gem5 Developers MVFR1 mvfr1 = 0; 9710037SARM gem5 Developers mvfr1.flushToZero = 1; 9810037SARM gem5 Developers mvfr1.defaultNaN = 1; 9910037SARM gem5 Developers mvfr1.advSimdLoadStore = 1; 10010037SARM gem5 Developers mvfr1.advSimdInteger = 1; 10110037SARM gem5 Developers mvfr1.advSimdSinglePrecision = 1; 10210196SCurtis.Dunham@arm.com mvfr1.advSimdHalfPrecision = 1; 10310037SARM gem5 Developers mvfr1.vfpHalfPrecision = 1; 10410037SARM gem5 Developers miscRegs[MISCREG_MVFR1] = mvfr1; 10510037SARM gem5 Developers 10610037SARM gem5 Developers // Reset values of PRRR and NMRR are implementation dependent 10710037SARM gem5 Developers 10810037SARM gem5 Developers miscRegs[MISCREG_PRRR] = 10910037SARM gem5 Developers (1 << 19) | // 19 11010037SARM gem5 Developers (0 << 18) | // 18 11110037SARM gem5 Developers (0 << 17) | // 17 11210037SARM gem5 Developers (1 << 16) | // 16 11310037SARM gem5 Developers (2 << 14) | // 15:14 11410037SARM gem5 Developers (0 << 12) | // 13:12 11510037SARM gem5 Developers (2 << 10) | // 11:10 11610037SARM gem5 Developers (2 << 8) | // 9:8 11710037SARM gem5 Developers (2 << 6) | // 7:6 11810037SARM gem5 Developers (2 << 4) | // 5:4 11910037SARM gem5 Developers (1 << 2) | // 3:2 12010037SARM gem5 Developers 0; // 1:0 12110037SARM gem5 Developers miscRegs[MISCREG_NMRR] = 12210037SARM gem5 Developers (1 << 30) | // 31:30 12310037SARM gem5 Developers (0 << 26) | // 27:26 12410037SARM gem5 Developers (0 << 24) | // 25:24 12510037SARM gem5 Developers (3 << 22) | // 23:22 12610196SCurtis.Dunham@arm.com (2 << 20) | // 21:20 12710037SARM gem5 Developers (0 << 18) | // 19:18 12810037SARM gem5 Developers (0 << 16) | // 17:16 12910037SARM gem5 Developers (1 << 14) | // 15:14 13010037SARM gem5 Developers (0 << 12) | // 13:12 13110037SARM gem5 Developers (2 << 10) | // 11:10 13210037SARM gem5 Developers (0 << 8) | // 9:8 13310037SARM gem5 Developers (3 << 6) | // 7:6 13410037SARM gem5 Developers (2 << 4) | // 5:4 13510037SARM gem5 Developers (0 << 2) | // 3:2 13610037SARM gem5 Developers 0; // 1:0 13710037SARM gem5 Developers 13810037SARM gem5 Developers miscRegs[MISCREG_CPACR] = 0; 13910037SARM gem5 Developers miscRegs[MISCREG_FPSID] = 0x410430A0; 14010037SARM gem5 Developers 14110037SARM gem5 Developers // See section B4.1.84 of ARM ARM 14210037SARM gem5 Developers // All values are latest for ARMv7-A profile 14310037SARM gem5 Developers miscRegs[MISCREG_ID_ISAR0] = 0x02101111; 14410037SARM gem5 Developers miscRegs[MISCREG_ID_ISAR1] = 0x02112111; 14510037SARM gem5 Developers miscRegs[MISCREG_ID_ISAR2] = 0x21232141; 14610037SARM gem5 Developers miscRegs[MISCREG_ID_ISAR3] = 0x01112131; 14710037SARM gem5 Developers miscRegs[MISCREG_ID_ISAR4] = 0x10010142; 14810037SARM gem5 Developers miscRegs[MISCREG_ID_ISAR5] = 0x00000000; 14910037SARM gem5 Developers 15010037SARM gem5 Developers //XXX We need to initialize the rest of the state. 15110037SARM gem5 Developers} 15210037SARM gem5 Developers 15310037SARM gem5 DevelopersMiscReg 15410037SARM gem5 DevelopersISA::readMiscRegNoEffect(int misc_reg) 15510037SARM gem5 Developers{ 15610037SARM gem5 Developers assert(misc_reg < NumMiscRegs); 15710037SARM gem5 Developers 15810037SARM gem5 Developers int flat_idx; 15910196SCurtis.Dunham@arm.com if (misc_reg == MISCREG_SPSR) 16010037SARM gem5 Developers flat_idx = flattenMiscIndex(misc_reg); 16110037SARM gem5 Developers else 16210037SARM gem5 Developers flat_idx = misc_reg; 16310037SARM gem5 Developers MiscReg val = miscRegs[flat_idx]; 16410037SARM gem5 Developers 16510037SARM gem5 Developers DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n", 16610037SARM gem5 Developers misc_reg, flat_idx, val); 16710037SARM gem5 Developers return val; 16810037SARM gem5 Developers} 16910037SARM gem5 Developers 17010037SARM gem5 Developers 17110037SARM gem5 DevelopersMiscReg 17210037SARM gem5 DevelopersISA::readMiscReg(int misc_reg, ThreadContext *tc) 17310037SARM gem5 Developers{ 17410037SARM gem5 Developers ArmSystem *arm_sys; 17510037SARM gem5 Developers 17610037SARM gem5 Developers if (misc_reg == MISCREG_CPSR) { 17710037SARM gem5 Developers CPSR cpsr = miscRegs[misc_reg]; 17810037SARM gem5 Developers PCState pc = tc->pcState(); 17910037SARM gem5 Developers cpsr.j = pc.jazelle() ? 1 : 0; 18010037SARM gem5 Developers cpsr.t = pc.thumb() ? 1 : 0; 18110037SARM gem5 Developers return cpsr; 18210037SARM gem5 Developers } 18310196SCurtis.Dunham@arm.com if (misc_reg >= MISCREG_CP15_UNIMP_START) 18410037SARM gem5 Developers panic("Unimplemented CP15 register %s read.\n", 18510037SARM gem5 Developers miscRegName[misc_reg]); 18610037SARM gem5 Developers 18710037SARM gem5 Developers switch (misc_reg) { 18810037SARM gem5 Developers case MISCREG_MPIDR: 18910037SARM gem5 Developers arm_sys = dynamic_cast<ArmSystem*>(tc->getSystemPtr()); 19010037SARM gem5 Developers assert(arm_sys); 19110037SARM gem5 Developers 19210037SARM gem5 Developers if (arm_sys->multiProc) { 19310037SARM gem5 Developers return 0x80000000 | // multiprocessor extensions available 19410037SARM gem5 Developers tc->cpuId(); 19510037SARM gem5 Developers } else { 19610037SARM gem5 Developers return 0x80000000 | // multiprocessor extensions available 19710037SARM gem5 Developers 0x40000000 | // in up system 19810037SARM gem5 Developers tc->cpuId(); 19910037SARM gem5 Developers } 20010037SARM gem5 Developers break; 20110037SARM gem5 Developers case MISCREG_ID_MMFR0: 20210037SARM gem5 Developers return 0x03; // VMSAv7 support 20310196SCurtis.Dunham@arm.com case MISCREG_ID_MMFR2: 20410037SARM gem5 Developers return 0x01230000; // no HW access | WFI stalling | ISB and DSB 20510037SARM gem5 Developers // | all TLB maintenance | no Harvard 20610037SARM gem5 Developers case MISCREG_ID_MMFR3: 20710037SARM gem5 Developers return 0xF0102211; // SuperSec | Coherent TLB | Bcast Maint | 20810037SARM gem5 Developers // BP Maint | Cache Maint Set/way | Cache Maint MVA 20910037SARM gem5 Developers case MISCREG_CLIDR: 21010037SARM gem5 Developers warn_once("The clidr register always reports 0 caches.\n"); 21110037SARM gem5 Developers warn_once("clidr LoUIS field of 0b001 to match current " 21210037SARM gem5 Developers "ARM implementations.\n"); 21310037SARM gem5 Developers return 0x00200000; 21410037SARM gem5 Developers case MISCREG_CCSIDR: 21510037SARM gem5 Developers warn_once("The ccsidr register isn't implemented and " 21610037SARM gem5 Developers "always reads as 0.\n"); 21710037SARM gem5 Developers break; 21810037SARM gem5 Developers case MISCREG_ID_PFR0: 21910037SARM gem5 Developers warn("Returning thumbEE disabled for now since we don't support CP14" 22010037SARM gem5 Developers "config registers and jumping to ThumbEE vectors\n"); 22110037SARM gem5 Developers return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM 22210037SARM gem5 Developers case MISCREG_ID_PFR1: 22310037SARM gem5 Developers return 0x00001; // !Timer | !Virti | !M Profile | !TrustZone | ARMv4 22410037SARM gem5 Developers case MISCREG_CTR: 22510037SARM gem5 Developers { 22610037SARM gem5 Developers //all caches have the same line size in gem5 22710037SARM gem5 Developers //4 byte words in ARM 22810196SCurtis.Dunham@arm.com unsigned lineSizeWords = 22910037SARM gem5 Developers tc->getCpuPtr()->getInstPort().peerBlockSize() / 4; 23010037SARM gem5 Developers unsigned log2LineSizeWords = 0; 23110037SARM gem5 Developers 23210037SARM gem5 Developers while (lineSizeWords >>= 1) { 23310037SARM gem5 Developers ++log2LineSizeWords; 23410037SARM gem5 Developers } 23510037SARM gem5 Developers 23610037SARM gem5 Developers CTR ctr = 0; 23710196SCurtis.Dunham@arm.com //log2 of minimun i-cache line size (words) 23810037SARM gem5 Developers ctr.iCacheLineSize = log2LineSizeWords; 23910037SARM gem5 Developers //b11 - gem5 uses pipt 24010037SARM gem5 Developers ctr.l1IndexPolicy = 0x3; 24110037SARM gem5 Developers //log2 of minimum d-cache line size (words) 24210037SARM gem5 Developers ctr.dCacheLineSize = log2LineSizeWords; 24310037SARM gem5 Developers //log2 of max reservation size (words) 24410037SARM gem5 Developers ctr.erg = log2LineSizeWords; 24510037SARM gem5 Developers //log2 of max writeback size (words) 24610037SARM gem5 Developers ctr.cwg = log2LineSizeWords; 24710037SARM gem5 Developers //b100 - gem5 format is ARMv7 24810037SARM gem5 Developers ctr.format = 0x4; 24910037SARM gem5 Developers 25010037SARM gem5 Developers return ctr; 25110037SARM gem5 Developers } 25210037SARM gem5 Developers case MISCREG_ACTLR: 25310037SARM gem5 Developers warn("Not doing anything for miscreg ACTLR\n"); 25410037SARM gem5 Developers break; 25510037SARM gem5 Developers case MISCREG_PMCR: 25610037SARM gem5 Developers case MISCREG_PMCCNTR: 25710037SARM gem5 Developers case MISCREG_PMSELR: 25810037SARM gem5 Developers warn("Not doing anything for read to miscreg %s\n", 25910037SARM gem5 Developers miscRegName[misc_reg]); 26010037SARM gem5 Developers break; 26110037SARM gem5 Developers case MISCREG_CPSR_Q: 26210037SARM gem5 Developers panic("shouldn't be reading this register seperately\n"); 26310037SARM gem5 Developers case MISCREG_FPSCR_QC: 26410037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 26510037SARM gem5 Developers case MISCREG_FPSCR_EXC: 26610037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 26710037SARM gem5 Developers case MISCREG_L2CTLR: 26810037SARM gem5 Developers { 26910037SARM gem5 Developers // mostly unimplemented, just set NumCPUs field from sim and return 27010037SARM gem5 Developers L2CTLR l2ctlr = 0; 27110037SARM gem5 Developers // b00:1CPU to b11:4CPUs 27210037SARM gem5 Developers l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 27310037SARM gem5 Developers return l2ctlr; 27410037SARM gem5 Developers } 27510037SARM gem5 Developers case MISCREG_DBGDIDR: 27610037SARM gem5 Developers /* For now just implement the version number. 27710037SARM gem5 Developers * Return 0 as we don't support debug architecture yet. 27810037SARM gem5 Developers */ 27910037SARM gem5 Developers return 0; 28010037SARM gem5 Developers case MISCREG_DBGDSCR_INT: 28110037SARM gem5 Developers return 0; 28210037SARM gem5 Developers } 28310037SARM gem5 Developers return readMiscRegNoEffect(misc_reg); 28410037SARM gem5 Developers} 28510037SARM gem5 Developers 28610196SCurtis.Dunham@arm.comvoid 28710037SARM gem5 DevelopersISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 28810037SARM gem5 Developers{ 28910037SARM gem5 Developers assert(misc_reg < NumMiscRegs); 29010037SARM gem5 Developers 29110037SARM gem5 Developers int flat_idx; 29210037SARM gem5 Developers if (misc_reg == MISCREG_SPSR) 29310037SARM gem5 Developers flat_idx = flattenMiscIndex(misc_reg); 29410037SARM gem5 Developers else 29510037SARM gem5 Developers flat_idx = misc_reg; 29610037SARM gem5 Developers miscRegs[flat_idx] = val; 29710037SARM gem5 Developers 29810037SARM gem5 Developers DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg, 29910037SARM gem5 Developers flat_idx, val); 30010037SARM gem5 Developers} 30110037SARM gem5 Developers 30210037SARM gem5 Developersvoid 30310037SARM gem5 DevelopersISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 30410037SARM gem5 Developers{ 30510037SARM gem5 Developers 30610037SARM gem5 Developers MiscReg newVal = val; 30710037SARM gem5 Developers int x; 30810037SARM gem5 Developers System *sys; 30910037SARM gem5 Developers ThreadContext *oc; 31010037SARM gem5 Developers 31110037SARM gem5 Developers if (misc_reg == MISCREG_CPSR) { 31210037SARM gem5 Developers updateRegMap(val); 31310037SARM gem5 Developers 31410196SCurtis.Dunham@arm.com 31510037SARM gem5 Developers CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 31610037SARM gem5 Developers int old_mode = old_cpsr.mode; 31710037SARM gem5 Developers CPSR cpsr = val; 31810037SARM gem5 Developers if (old_mode != cpsr.mode) { 31910037SARM gem5 Developers tc->getITBPtr()->invalidateMiscReg(); 32010037SARM gem5 Developers tc->getDTBPtr()->invalidateMiscReg(); 32110037SARM gem5 Developers } 32210037SARM gem5 Developers 32310037SARM gem5 Developers DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 32410037SARM gem5 Developers miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 32510037SARM gem5 Developers PCState pc = tc->pcState(); 32610037SARM gem5 Developers pc.nextThumb(cpsr.t); 32710037SARM gem5 Developers pc.nextJazelle(cpsr.j); 32810037SARM gem5 Developers 32910037SARM gem5 Developers // Follow slightly different semantics if a CheckerCPU object 33010037SARM gem5 Developers // is connected 33110037SARM gem5 Developers CheckerCPU *checker = tc->getCheckerCpuPtr(); 33210037SARM gem5 Developers if (checker) { 33310037SARM gem5 Developers tc->pcStateNoRecord(pc); 33410037SARM gem5 Developers } else { 33510037SARM gem5 Developers tc->pcState(pc); 33610037SARM gem5 Developers } 33710037SARM gem5 Developers } else if (misc_reg >= MISCREG_CP15_UNIMP_START && 33810037SARM gem5 Developers misc_reg < MISCREG_CP15_END) { 33910037SARM gem5 Developers panic("Unimplemented CP15 register %s wrote with %#x.\n", 34010037SARM gem5 Developers miscRegName[misc_reg], val); 34110037SARM gem5 Developers } else { 34210037SARM gem5 Developers switch (misc_reg) { 34310037SARM gem5 Developers case MISCREG_CPACR: 34410037SARM gem5 Developers { 34510037SARM gem5 Developers 34610037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 34710037SARM gem5 Developers CPACR cpacrMask = 0; 34810037SARM gem5 Developers // Only cp10, cp11, and ase are implemented, nothing else should 34910037SARM gem5 Developers // be writable 35010037SARM gem5 Developers cpacrMask.cp10 = ones; 35110037SARM gem5 Developers cpacrMask.cp11 = ones; 35210037SARM gem5 Developers cpacrMask.asedis = ones; 35310037SARM gem5 Developers newVal &= cpacrMask; 35410037SARM gem5 Developers DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 35510037SARM gem5 Developers miscRegName[misc_reg], newVal); 35610037SARM gem5 Developers } 35710037SARM gem5 Developers break; 35810037SARM gem5 Developers case MISCREG_CSSELR: 35910037SARM gem5 Developers warn_once("The csselr register isn't implemented.\n"); 36010037SARM gem5 Developers return; 36110037SARM gem5 Developers case MISCREG_FPSCR: 36210037SARM gem5 Developers { 36310037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 36410037SARM gem5 Developers FPSCR fpscrMask = 0; 36510037SARM gem5 Developers fpscrMask.ioc = ones; 36610037SARM gem5 Developers fpscrMask.dzc = ones; 36710037SARM gem5 Developers fpscrMask.ofc = ones; 36810037SARM gem5 Developers fpscrMask.ufc = ones; 36910037SARM gem5 Developers fpscrMask.ixc = ones; 37010037SARM gem5 Developers fpscrMask.idc = ones; 37110037SARM gem5 Developers fpscrMask.len = ones; 37210037SARM gem5 Developers fpscrMask.stride = ones; 37310037SARM gem5 Developers fpscrMask.rMode = ones; 37410037SARM gem5 Developers fpscrMask.fz = ones; 37510037SARM gem5 Developers fpscrMask.dn = ones; 37610037SARM gem5 Developers fpscrMask.ahp = ones; 37710037SARM gem5 Developers fpscrMask.qc = ones; 37810037SARM gem5 Developers fpscrMask.v = ones; 37910037SARM gem5 Developers fpscrMask.c = ones; 38010037SARM gem5 Developers fpscrMask.z = ones; 38110037SARM gem5 Developers fpscrMask.n = ones; 38210037SARM gem5 Developers newVal = (newVal & (uint32_t)fpscrMask) | 38310037SARM gem5 Developers (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask); 38410037SARM gem5 Developers } 38510037SARM gem5 Developers break; 38610037SARM gem5 Developers case MISCREG_CPSR_Q: 38710037SARM gem5 Developers { 38810037SARM gem5 Developers assert(!(newVal & ~CpsrMaskQ)); 38910037SARM gem5 Developers newVal = miscRegs[MISCREG_CPSR] | newVal; 39010037SARM gem5 Developers misc_reg = MISCREG_CPSR; 39110037SARM gem5 Developers } 39210037SARM gem5 Developers break; 39310037SARM gem5 Developers case MISCREG_FPSCR_QC: 39410037SARM gem5 Developers { 39510037SARM gem5 Developers newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrQcMask); 39610037SARM gem5 Developers misc_reg = MISCREG_FPSCR; 39710037SARM gem5 Developers } 39810037SARM gem5 Developers break; 39910037SARM gem5 Developers case MISCREG_FPSCR_EXC: 40010037SARM gem5 Developers { 40110037SARM gem5 Developers newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrExcMask); 40210037SARM gem5 Developers misc_reg = MISCREG_FPSCR; 40310037SARM gem5 Developers } 40410037SARM gem5 Developers break; 40510037SARM gem5 Developers case MISCREG_FPEXC: 40610037SARM gem5 Developers { 40710037SARM gem5 Developers // vfpv3 architecture, section B.6.1 of DDI04068 40810037SARM gem5 Developers // bit 29 - valid only if fpexc[31] is 0 40910037SARM gem5 Developers const uint32_t fpexcMask = 0x60000000; 41010037SARM gem5 Developers newVal = (newVal & fpexcMask) | 41110037SARM gem5 Developers (miscRegs[MISCREG_FPEXC] & ~fpexcMask); 41210037SARM gem5 Developers } 41310037SARM gem5 Developers break; 41410037SARM gem5 Developers case MISCREG_SCTLR: 41510037SARM gem5 Developers { 41610037SARM gem5 Developers DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 41710037SARM gem5 Developers SCTLR sctlr = miscRegs[MISCREG_SCTLR]; 41810037SARM gem5 Developers SCTLR new_sctlr = newVal; 41910037SARM gem5 Developers new_sctlr.nmfi = (bool)sctlr.nmfi; 42010037SARM gem5 Developers miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr; 42110037SARM gem5 Developers tc->getITBPtr()->invalidateMiscReg(); 42210037SARM gem5 Developers tc->getDTBPtr()->invalidateMiscReg(); 42310037SARM gem5 Developers 42410037SARM gem5 Developers // Check if all CPUs are booted with caches enabled 42510037SARM gem5 Developers // so we can stop enforcing coherency of some kernel 42610037SARM gem5 Developers // structures manually. 42710037SARM gem5 Developers sys = tc->getSystemPtr(); 42810037SARM gem5 Developers for (x = 0; x < sys->numContexts(); x++) { 42910037SARM gem5 Developers oc = sys->getThreadContext(x); 43010037SARM gem5 Developers SCTLR other_sctlr = oc->readMiscRegNoEffect(MISCREG_SCTLR); 43110037SARM gem5 Developers if (!other_sctlr.c && oc->status() != ThreadContext::Halted) 43210037SARM gem5 Developers return; 43310037SARM gem5 Developers } 43410037SARM gem5 Developers 43510037SARM gem5 Developers for (x = 0; x < sys->numContexts(); x++) { 43610037SARM gem5 Developers oc = sys->getThreadContext(x); 43710037SARM gem5 Developers oc->getDTBPtr()->allCpusCaching(); 43810037SARM gem5 Developers oc->getITBPtr()->allCpusCaching(); 43910037SARM gem5 Developers 44010037SARM gem5 Developers // If CheckerCPU is connected, need to notify it. 44110037SARM gem5 Developers CheckerCPU *checker = oc->getCheckerCpuPtr(); 44210037SARM gem5 Developers if (checker) { 44310037SARM gem5 Developers checker->getDTBPtr()->allCpusCaching(); 44410037SARM gem5 Developers checker->getITBPtr()->allCpusCaching(); 44510037SARM gem5 Developers } 44610037SARM gem5 Developers } 44710037SARM gem5 Developers return; 44810037SARM gem5 Developers } 44910037SARM gem5 Developers case MISCREG_TLBTR: 45010037SARM gem5 Developers case MISCREG_MVFR0: 45110037SARM gem5 Developers case MISCREG_MVFR1: 45210037SARM gem5 Developers case MISCREG_MPIDR: 45310037SARM gem5 Developers case MISCREG_FPSID: 45410037SARM gem5 Developers return; 45510037SARM gem5 Developers case MISCREG_TLBIALLIS: 45610037SARM gem5 Developers case MISCREG_TLBIALL: 45710037SARM gem5 Developers sys = tc->getSystemPtr(); 45810037SARM gem5 Developers for (x = 0; x < sys->numContexts(); x++) { 45910037SARM gem5 Developers oc = sys->getThreadContext(x); 46010037SARM gem5 Developers assert(oc->getITBPtr() && oc->getDTBPtr()); 46110037SARM gem5 Developers oc->getITBPtr()->flushAll(); 46210037SARM gem5 Developers oc->getDTBPtr()->flushAll(); 46310037SARM gem5 Developers 46410037SARM gem5 Developers // If CheckerCPU is connected, need to notify it of a flush 46510037SARM gem5 Developers CheckerCPU *checker = oc->getCheckerCpuPtr(); 46610037SARM gem5 Developers if (checker) { 46710037SARM gem5 Developers checker->getITBPtr()->flushAll(); 46810037SARM gem5 Developers checker->getDTBPtr()->flushAll(); 46910037SARM gem5 Developers } 47010037SARM gem5 Developers } 47110037SARM gem5 Developers return; 47210037SARM gem5 Developers case MISCREG_ITLBIALL: 47310037SARM gem5 Developers tc->getITBPtr()->flushAll(); 47410037SARM gem5 Developers return; 47510037SARM gem5 Developers case MISCREG_DTLBIALL: 47610037SARM gem5 Developers tc->getDTBPtr()->flushAll(); 47710037SARM gem5 Developers return; 47810037SARM gem5 Developers case MISCREG_TLBIMVAIS: 47910037SARM gem5 Developers case MISCREG_TLBIMVA: 48010037SARM gem5 Developers sys = tc->getSystemPtr(); 48110037SARM gem5 Developers for (x = 0; x < sys->numContexts(); x++) { 48210037SARM gem5 Developers oc = sys->getThreadContext(x); 48310037SARM gem5 Developers assert(oc->getITBPtr() && oc->getDTBPtr()); 48410037SARM gem5 Developers oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 48510037SARM gem5 Developers bits(newVal, 7,0)); 48610037SARM gem5 Developers oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 48710037SARM gem5 Developers bits(newVal, 7,0)); 48810037SARM gem5 Developers 48910037SARM gem5 Developers CheckerCPU *checker = oc->getCheckerCpuPtr(); 49010037SARM gem5 Developers if (checker) { 49110037SARM gem5 Developers checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 49210037SARM gem5 Developers bits(newVal, 7,0)); 49310037SARM gem5 Developers checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 49410037SARM gem5 Developers bits(newVal, 7,0)); 49510037SARM gem5 Developers } 49610037SARM gem5 Developers } 49710037SARM gem5 Developers return; 49810037SARM gem5 Developers case MISCREG_TLBIASIDIS: 49910037SARM gem5 Developers case MISCREG_TLBIASID: 50010037SARM gem5 Developers sys = tc->getSystemPtr(); 50110037SARM gem5 Developers for (x = 0; x < sys->numContexts(); x++) { 50210037SARM gem5 Developers oc = sys->getThreadContext(x); 50310037SARM gem5 Developers assert(oc->getITBPtr() && oc->getDTBPtr()); 50410037SARM gem5 Developers oc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 50510037SARM gem5 Developers oc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 50610037SARM gem5 Developers CheckerCPU *checker = oc->getCheckerCpuPtr(); 50710037SARM gem5 Developers if (checker) { 50810037SARM gem5 Developers checker->getITBPtr()->flushAsid(bits(newVal, 7,0)); 50910037SARM gem5 Developers checker->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 51010037SARM gem5 Developers } 51110037SARM gem5 Developers } 51210037SARM gem5 Developers return; 51310037SARM gem5 Developers case MISCREG_TLBIMVAAIS: 51410037SARM gem5 Developers case MISCREG_TLBIMVAA: 51510037SARM gem5 Developers sys = tc->getSystemPtr(); 51610037SARM gem5 Developers for (x = 0; x < sys->numContexts(); x++) { 51710037SARM gem5 Developers oc = sys->getThreadContext(x); 51810037SARM gem5 Developers assert(oc->getITBPtr() && oc->getDTBPtr()); 51910037SARM gem5 Developers oc->getITBPtr()->flushMva(mbits(newVal, 31,12)); 52010037SARM gem5 Developers oc->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 52110037SARM gem5 Developers 52210037SARM gem5 Developers CheckerCPU *checker = oc->getCheckerCpuPtr(); 52310037SARM gem5 Developers if (checker) { 52410037SARM gem5 Developers checker->getITBPtr()->flushMva(mbits(newVal, 31,12)); 52510037SARM gem5 Developers checker->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 52610037SARM gem5 Developers } 52710037SARM gem5 Developers } 52810037SARM gem5 Developers return; 52910037SARM gem5 Developers case MISCREG_ITLBIMVA: 53010037SARM gem5 Developers tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 53110037SARM gem5 Developers bits(newVal, 7,0)); 53210037SARM gem5 Developers return; 53310037SARM gem5 Developers case MISCREG_DTLBIMVA: 53410037SARM gem5 Developers tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 53510037SARM gem5 Developers bits(newVal, 7,0)); 53610037SARM gem5 Developers return; 53710037SARM gem5 Developers case MISCREG_ITLBIASID: 53810037SARM gem5 Developers tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 53910037SARM gem5 Developers return; 54010037SARM gem5 Developers case MISCREG_DTLBIASID: 54110037SARM gem5 Developers tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 54210037SARM gem5 Developers return; 54310037SARM gem5 Developers case MISCREG_ACTLR: 54410037SARM gem5 Developers warn("Not doing anything for write of miscreg ACTLR\n"); 54510037SARM gem5 Developers break; 54610037SARM gem5 Developers case MISCREG_PMCR: 54710037SARM gem5 Developers { 54810037SARM gem5 Developers // Performance counters not implemented. Instead, interpret 54910037SARM gem5 Developers // a reset command to this register to reset the simulator 55010037SARM gem5 Developers // statistics. 55110037SARM gem5 Developers // PMCR_E | PMCR_P | PMCR_C 55210037SARM gem5 Developers const int ResetAndEnableCounters = 0x7; 55310037SARM gem5 Developers if (newVal == ResetAndEnableCounters) { 55410037SARM gem5 Developers inform("Resetting all simobject stats\n"); 55510037SARM gem5 Developers Stats::schedStatEvent(false, true); 55610037SARM gem5 Developers break; 55710037SARM gem5 Developers } 55810037SARM gem5 Developers } 55910037SARM gem5 Developers case MISCREG_PMCCNTR: 56010037SARM gem5 Developers case MISCREG_PMSELR: 56110037SARM gem5 Developers warn("Not doing anything for write to miscreg %s\n", 56210037SARM gem5 Developers miscRegName[misc_reg]); 56310037SARM gem5 Developers break; 56410037SARM gem5 Developers case MISCREG_V2PCWPR: 56510037SARM gem5 Developers case MISCREG_V2PCWPW: 56610037SARM gem5 Developers case MISCREG_V2PCWUR: 56710037SARM gem5 Developers case MISCREG_V2PCWUW: 56810037SARM gem5 Developers case MISCREG_V2POWPR: 56910037SARM gem5 Developers case MISCREG_V2POWPW: 57010037SARM gem5 Developers case MISCREG_V2POWUR: 57110037SARM gem5 Developers case MISCREG_V2POWUW: 57210037SARM gem5 Developers { 57310037SARM gem5 Developers RequestPtr req = new Request; 57410037SARM gem5 Developers unsigned flags; 57510037SARM gem5 Developers BaseTLB::Mode mode; 57610037SARM gem5 Developers Fault fault; 57710037SARM gem5 Developers switch(misc_reg) { 57810037SARM gem5 Developers case MISCREG_V2PCWPR: 57910037SARM gem5 Developers flags = TLB::MustBeOne; 58010037SARM gem5 Developers mode = BaseTLB::Read; 58110037SARM gem5 Developers break; 58210037SARM gem5 Developers case MISCREG_V2PCWPW: 58310037SARM gem5 Developers flags = TLB::MustBeOne; 58410037SARM gem5 Developers mode = BaseTLB::Write; 58510037SARM gem5 Developers break; 58610037SARM gem5 Developers case MISCREG_V2PCWUR: 58710037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 58810037SARM gem5 Developers mode = BaseTLB::Read; 58910037SARM gem5 Developers break; 59010037SARM gem5 Developers case MISCREG_V2PCWUW: 59110037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 59210184SCurtis.Dunham@arm.com mode = BaseTLB::Write; 59310037SARM gem5 Developers break; 59410037SARM gem5 Developers default: 59510037SARM gem5 Developers panic("Security Extensions not implemented!"); 59610037SARM gem5 Developers } 59710037SARM gem5 Developers warn("Translating via MISCREG in atomic mode! Fix Me!\n"); 59810037SARM gem5 Developers req->setVirt(0, val, 1, flags, tc->pcState().pc(), 59910037SARM gem5 Developers Request::funcMasterId); 60010037SARM gem5 Developers fault = tc->getDTBPtr()->translateAtomic(req, tc, mode); 60110037SARM gem5 Developers if (fault == NoFault) { 60210037SARM gem5 Developers miscRegs[MISCREG_PAR] = 60310037SARM gem5 Developers (req->getPaddr() & 0xfffff000) | 60410037SARM gem5 Developers (tc->getDTBPtr()->getAttr() ); 60510037SARM gem5 Developers DPRINTF(MiscRegs, 60610037SARM gem5 Developers "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 60710037SARM gem5 Developers val, miscRegs[MISCREG_PAR]); 60810037SARM gem5 Developers } 60910037SARM gem5 Developers else { 61010037SARM gem5 Developers // Set fault bit and FSR 61110037SARM gem5 Developers FSR fsr = miscRegs[MISCREG_DFSR]; 61210037SARM gem5 Developers miscRegs[MISCREG_PAR] = 61310037SARM gem5 Developers (fsr.ext << 6) | 61410037SARM gem5 Developers (fsr.fsHigh << 5) | 61510037SARM gem5 Developers (fsr.fsLow << 1) | 61610037SARM gem5 Developers 0x1; // F bit 61710037SARM gem5 Developers } 61810037SARM gem5 Developers return; 61910037SARM gem5 Developers } 62010037SARM gem5 Developers case MISCREG_CONTEXTIDR: 62110037SARM gem5 Developers case MISCREG_PRRR: 62210037SARM gem5 Developers case MISCREG_NMRR: 62310037SARM gem5 Developers case MISCREG_DACR: 62410037SARM gem5 Developers tc->getITBPtr()->invalidateMiscReg(); 62510037SARM gem5 Developers tc->getDTBPtr()->invalidateMiscReg(); 62610037SARM gem5 Developers break; 62710037SARM gem5 Developers case MISCREG_CPSR_MODE: 62810037SARM gem5 Developers // This miscreg is used by copy*Regs to set the CPSR mode 62910037SARM gem5 Developers // without updating other CPSR variables. It's used to 63010037SARM gem5 Developers // make sure the register map is in such a state that we can 63110037SARM gem5 Developers // see all of the registers for the copy. 63210037SARM gem5 Developers updateRegMap(val); 63310037SARM gem5 Developers return; 63410037SARM gem5 Developers case MISCREG_L2CTLR: 63510037SARM gem5 Developers warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 63610037SARM gem5 Developers miscRegName[misc_reg], uint32_t(val)); 63710037SARM gem5 Developers } 63810037SARM gem5 Developers } 63910037SARM gem5 Developers setMiscRegNoEffect(misc_reg, newVal); 64010037SARM gem5 Developers} 64110037SARM gem5 Developers 64210037SARM gem5 Developers} 64310037SARM gem5 Developers