isa.cc revision 8527:6bac5b04d588
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 */ 40 41#include "arch/arm/isa.hh" 42#include "debug/Arm.hh" 43#include "debug/MiscRegs.hh" 44#include "sim/faults.hh" 45#include "sim/stat_control.hh" 46#include "sim/system.hh" 47 48namespace ArmISA 49{ 50 51void 52ISA::clear() 53{ 54 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 55 uint32_t midr = miscRegs[MISCREG_MIDR]; 56 memset(miscRegs, 0, sizeof(miscRegs)); 57 CPSR cpsr = 0; 58 cpsr.mode = MODE_USER; 59 miscRegs[MISCREG_CPSR] = cpsr; 60 updateRegMap(cpsr); 61 62 SCTLR sctlr = 0; 63 sctlr.te = (bool)sctlr_rst.te; 64 sctlr.nmfi = (bool)sctlr_rst.nmfi; 65 sctlr.v = (bool)sctlr_rst.v; 66 sctlr.u = 1; 67 sctlr.xp = 1; 68 sctlr.rao2 = 1; 69 sctlr.rao3 = 1; 70 sctlr.rao4 = 1; 71 miscRegs[MISCREG_SCTLR] = sctlr; 72 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 73 74 // Preserve MIDR accross reset 75 miscRegs[MISCREG_MIDR] = midr; 76 77 /* Start with an event in the mailbox */ 78 miscRegs[MISCREG_SEV_MAILBOX] = 1; 79 80 // Separate Instruction and Data TLBs. 81 miscRegs[MISCREG_TLBTR] = 1; 82 83 MVFR0 mvfr0 = 0; 84 mvfr0.advSimdRegisters = 2; 85 mvfr0.singlePrecision = 2; 86 mvfr0.doublePrecision = 2; 87 mvfr0.vfpExceptionTrapping = 0; 88 mvfr0.divide = 1; 89 mvfr0.squareRoot = 1; 90 mvfr0.shortVectors = 1; 91 mvfr0.roundingModes = 1; 92 miscRegs[MISCREG_MVFR0] = mvfr0; 93 94 MVFR1 mvfr1 = 0; 95 mvfr1.flushToZero = 1; 96 mvfr1.defaultNaN = 1; 97 mvfr1.advSimdLoadStore = 1; 98 mvfr1.advSimdInteger = 1; 99 mvfr1.advSimdSinglePrecision = 1; 100 mvfr1.advSimdHalfPrecision = 1; 101 mvfr1.vfpHalfPrecision = 1; 102 miscRegs[MISCREG_MVFR1] = mvfr1; 103 104 miscRegs[MISCREG_MPIDR] = 0; 105 106 // Reset values of PRRR and NMRR are implementation dependent 107 108 miscRegs[MISCREG_PRRR] = 109 (1 << 19) | // 19 110 (0 << 18) | // 18 111 (0 << 17) | // 17 112 (1 << 16) | // 16 113 (2 << 14) | // 15:14 114 (0 << 12) | // 13:12 115 (2 << 10) | // 11:10 116 (2 << 8) | // 9:8 117 (2 << 6) | // 7:6 118 (2 << 4) | // 5:4 119 (1 << 2) | // 3:2 120 0; // 1:0 121 miscRegs[MISCREG_NMRR] = 122 (1 << 30) | // 31:30 123 (0 << 26) | // 27:26 124 (0 << 24) | // 25:24 125 (3 << 22) | // 23:22 126 (2 << 20) | // 21:20 127 (0 << 18) | // 19:18 128 (0 << 16) | // 17:16 129 (1 << 14) | // 15:14 130 (0 << 12) | // 13:12 131 (2 << 10) | // 11:10 132 (0 << 8) | // 9:8 133 (3 << 6) | // 7:6 134 (2 << 4) | // 5:4 135 (0 << 2) | // 3:2 136 0; // 1:0 137 138 miscRegs[MISCREG_CPACR] = 0; 139 miscRegs[MISCREG_FPSID] = 0x410430A0; 140 141 // See section B4.1.84 of ARM ARM 142 // All values are latest for ARMv7-A profile 143 miscRegs[MISCREG_ID_ISAR0] = 0x02101111; 144 miscRegs[MISCREG_ID_ISAR1] = 0x02112111; 145 miscRegs[MISCREG_ID_ISAR2] = 0x21232141; 146 miscRegs[MISCREG_ID_ISAR3] = 0x01112131; 147 miscRegs[MISCREG_ID_ISAR4] = 0x10010142; 148 miscRegs[MISCREG_ID_ISAR5] = 0x00000000; 149 150 //XXX We need to initialize the rest of the state. 151} 152 153MiscReg 154ISA::readMiscRegNoEffect(int misc_reg) 155{ 156 assert(misc_reg < NumMiscRegs); 157 158 int flat_idx; 159 if (misc_reg == MISCREG_SPSR) 160 flat_idx = flattenMiscIndex(misc_reg); 161 else 162 flat_idx = misc_reg; 163 MiscReg val = miscRegs[flat_idx]; 164 165 DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n", 166 misc_reg, flat_idx, val); 167 return val; 168} 169 170 171MiscReg 172ISA::readMiscReg(int misc_reg, ThreadContext *tc) 173{ 174 if (misc_reg == MISCREG_CPSR) { 175 CPSR cpsr = miscRegs[misc_reg]; 176 PCState pc = tc->pcState(); 177 cpsr.j = pc.jazelle() ? 1 : 0; 178 cpsr.t = pc.thumb() ? 1 : 0; 179 return cpsr; 180 } 181 if (misc_reg >= MISCREG_CP15_UNIMP_START) 182 panic("Unimplemented CP15 register %s read.\n", 183 miscRegName[misc_reg]); 184 185 switch (misc_reg) { 186 case MISCREG_MPIDR: 187 return tc->cpuId(); 188 break; 189 case MISCREG_ID_MMFR0: 190 return 0x03; // VMSAv7 support 191 case MISCREG_ID_MMFR2: 192 return 0x01230000; // no HW access | WFI stalling | ISB and DSB 193 // | all TLB maintenance | no Harvard 194 case MISCREG_ID_MMFR3: 195 return 0xF0102211; // SuperSec | Coherent TLB | Bcast Maint | 196 // BP Maint | Cache Maint Set/way | Cache Maint MVA 197 case MISCREG_CLIDR: 198 warn_once("The clidr register always reports 0 caches.\n"); 199 warn_once("clidr LoUIS field of 0b001 to match current " 200 "ARM implementations.\n"); 201 return 0x00200000; 202 case MISCREG_CCSIDR: 203 warn_once("The ccsidr register isn't implemented and " 204 "always reads as 0.\n"); 205 break; 206 case MISCREG_ID_PFR0: 207 warn("Returning thumbEE disabled for now since we don't support CP14" 208 "config registers and jumping to ThumbEE vectors\n"); 209 return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM 210 case MISCREG_ID_PFR1: 211 warn("reading unimplmented register ID_PFR1"); 212 return 0; 213 case MISCREG_CTR: 214 return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact 215 case MISCREG_ACTLR: 216 warn("Not doing anything for miscreg ACTLR\n"); 217 break; 218 case MISCREG_PMCR: 219 case MISCREG_PMCCNTR: 220 case MISCREG_PMSELR: 221 warn("Not doing anything for read to miscreg %s\n", 222 miscRegName[misc_reg]); 223 break; 224 case MISCREG_CPSR_Q: 225 panic("shouldn't be reading this register seperately\n"); 226 case MISCREG_FPSCR_QC: 227 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 228 case MISCREG_FPSCR_EXC: 229 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 230 } 231 return readMiscRegNoEffect(misc_reg); 232} 233 234void 235ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 236{ 237 assert(misc_reg < NumMiscRegs); 238 239 int flat_idx; 240 if (misc_reg == MISCREG_SPSR) 241 flat_idx = flattenMiscIndex(misc_reg); 242 else 243 flat_idx = misc_reg; 244 miscRegs[flat_idx] = val; 245 246 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg, 247 flat_idx, val); 248} 249 250void 251ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 252{ 253 254 MiscReg newVal = val; 255 int x; 256 System *sys; 257 ThreadContext *oc; 258 259 if (misc_reg == MISCREG_CPSR) { 260 updateRegMap(val); 261 262 263 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 264 int old_mode = old_cpsr.mode; 265 CPSR cpsr = val; 266 if (old_mode != cpsr.mode) { 267 tc->getITBPtr()->invalidateMiscReg(); 268 tc->getDTBPtr()->invalidateMiscReg(); 269 } 270 271 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 272 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 273 PCState pc = tc->pcState(); 274 pc.nextThumb(cpsr.t); 275 pc.nextJazelle(cpsr.j); 276 tc->pcState(pc); 277 } else if (misc_reg >= MISCREG_CP15_UNIMP_START && 278 misc_reg < MISCREG_CP15_END) { 279 panic("Unimplemented CP15 register %s wrote with %#x.\n", 280 miscRegName[misc_reg], val); 281 } else { 282 switch (misc_reg) { 283 case MISCREG_CPACR: 284 { 285 286 const uint32_t ones = (uint32_t)(-1); 287 CPACR cpacrMask = 0; 288 // Only cp10, cp11, and ase are implemented, nothing else should 289 // be writable 290 cpacrMask.cp10 = ones; 291 cpacrMask.cp11 = ones; 292 cpacrMask.asedis = ones; 293 newVal &= cpacrMask; 294 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 295 miscRegName[misc_reg], newVal); 296 } 297 break; 298 case MISCREG_CSSELR: 299 warn_once("The csselr register isn't implemented.\n"); 300 return; 301 case MISCREG_FPSCR: 302 { 303 const uint32_t ones = (uint32_t)(-1); 304 FPSCR fpscrMask = 0; 305 fpscrMask.ioc = ones; 306 fpscrMask.dzc = ones; 307 fpscrMask.ofc = ones; 308 fpscrMask.ufc = ones; 309 fpscrMask.ixc = ones; 310 fpscrMask.idc = ones; 311 fpscrMask.len = ones; 312 fpscrMask.stride = ones; 313 fpscrMask.rMode = ones; 314 fpscrMask.fz = ones; 315 fpscrMask.dn = ones; 316 fpscrMask.ahp = ones; 317 fpscrMask.qc = ones; 318 fpscrMask.v = ones; 319 fpscrMask.c = ones; 320 fpscrMask.z = ones; 321 fpscrMask.n = ones; 322 newVal = (newVal & (uint32_t)fpscrMask) | 323 (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask); 324 } 325 break; 326 case MISCREG_CPSR_Q: 327 { 328 assert(!(newVal & ~CpsrMaskQ)); 329 newVal = miscRegs[MISCREG_CPSR] | newVal; 330 misc_reg = MISCREG_CPSR; 331 } 332 break; 333 case MISCREG_FPSCR_QC: 334 { 335 newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrQcMask); 336 misc_reg = MISCREG_FPSCR; 337 } 338 break; 339 case MISCREG_FPSCR_EXC: 340 { 341 newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrExcMask); 342 misc_reg = MISCREG_FPSCR; 343 } 344 break; 345 case MISCREG_FPEXC: 346 { 347 // vfpv3 architecture, section B.6.1 of DDI04068 348 // bit 29 - valid only if fpexc[31] is 0 349 const uint32_t fpexcMask = 0x60000000; 350 newVal = (newVal & fpexcMask) | 351 (miscRegs[MISCREG_FPEXC] & ~fpexcMask); 352 } 353 break; 354 case MISCREG_SCTLR: 355 { 356 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 357 SCTLR sctlr = miscRegs[MISCREG_SCTLR]; 358 SCTLR new_sctlr = newVal; 359 new_sctlr.nmfi = (bool)sctlr.nmfi; 360 miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr; 361 tc->getITBPtr()->invalidateMiscReg(); 362 tc->getDTBPtr()->invalidateMiscReg(); 363 364 // Check if all CPUs are booted with caches enabled 365 // so we can stop enforcing coherency of some kernel 366 // structures manually. 367 sys = tc->getSystemPtr(); 368 for (x = 0; x < sys->numContexts(); x++) { 369 oc = sys->getThreadContext(x); 370 SCTLR other_sctlr = oc->readMiscRegNoEffect(MISCREG_SCTLR); 371 if (!other_sctlr.c && oc->status() != ThreadContext::Halted) 372 return; 373 } 374 375 for (x = 0; x < sys->numContexts(); x++) { 376 oc = sys->getThreadContext(x); 377 oc->getDTBPtr()->allCpusCaching(); 378 oc->getITBPtr()->allCpusCaching(); 379 } 380 return; 381 } 382 case MISCREG_TLBTR: 383 case MISCREG_MVFR0: 384 case MISCREG_MVFR1: 385 case MISCREG_MPIDR: 386 case MISCREG_FPSID: 387 return; 388 case MISCREG_TLBIALLIS: 389 case MISCREG_TLBIALL: 390 sys = tc->getSystemPtr(); 391 for (x = 0; x < sys->numContexts(); x++) { 392 oc = sys->getThreadContext(x); 393 assert(oc->getITBPtr() && oc->getDTBPtr()); 394 oc->getITBPtr()->flushAll(); 395 oc->getDTBPtr()->flushAll(); 396 } 397 return; 398 case MISCREG_ITLBIALL: 399 tc->getITBPtr()->flushAll(); 400 return; 401 case MISCREG_DTLBIALL: 402 tc->getDTBPtr()->flushAll(); 403 return; 404 case MISCREG_TLBIMVAIS: 405 case MISCREG_TLBIMVA: 406 sys = tc->getSystemPtr(); 407 for (x = 0; x < sys->numContexts(); x++) { 408 oc = sys->getThreadContext(x); 409 assert(oc->getITBPtr() && oc->getDTBPtr()); 410 oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 411 bits(newVal, 7,0)); 412 oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 413 bits(newVal, 7,0)); 414 } 415 return; 416 case MISCREG_TLBIASIDIS: 417 case MISCREG_TLBIASID: 418 sys = tc->getSystemPtr(); 419 for (x = 0; x < sys->numContexts(); x++) { 420 oc = sys->getThreadContext(x); 421 assert(oc->getITBPtr() && oc->getDTBPtr()); 422 oc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 423 oc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 424 } 425 return; 426 case MISCREG_TLBIMVAAIS: 427 case MISCREG_TLBIMVAA: 428 sys = tc->getSystemPtr(); 429 for (x = 0; x < sys->numContexts(); x++) { 430 oc = sys->getThreadContext(x); 431 assert(oc->getITBPtr() && oc->getDTBPtr()); 432 oc->getITBPtr()->flushMva(mbits(newVal, 31,12)); 433 oc->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 434 } 435 return; 436 case MISCREG_ITLBIMVA: 437 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 438 bits(newVal, 7,0)); 439 return; 440 case MISCREG_DTLBIMVA: 441 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 442 bits(newVal, 7,0)); 443 return; 444 case MISCREG_ITLBIASID: 445 tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 446 return; 447 case MISCREG_DTLBIASID: 448 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 449 return; 450 case MISCREG_ACTLR: 451 warn("Not doing anything for write of miscreg ACTLR\n"); 452 break; 453 case MISCREG_PMCR: 454 { 455 // Performance counters not implemented. Instead, interpret 456 // a reset command to this register to reset the simulator 457 // statistics. 458 // PMCR_E | PMCR_P | PMCR_C 459 const int ResetAndEnableCounters = 0x7; 460 if (newVal == ResetAndEnableCounters) { 461 inform("Resetting all simobject stats\n"); 462 Stats::schedStatEvent(false, true); 463 break; 464 } 465 } 466 case MISCREG_PMCCNTR: 467 case MISCREG_PMSELR: 468 warn("Not doing anything for write to miscreg %s\n", 469 miscRegName[misc_reg]); 470 break; 471 case MISCREG_V2PCWPR: 472 case MISCREG_V2PCWPW: 473 case MISCREG_V2PCWUR: 474 case MISCREG_V2PCWUW: 475 case MISCREG_V2POWPR: 476 case MISCREG_V2POWPW: 477 case MISCREG_V2POWUR: 478 case MISCREG_V2POWUW: 479 { 480 RequestPtr req = new Request; 481 unsigned flags; 482 BaseTLB::Mode mode; 483 Fault fault; 484 switch(misc_reg) { 485 case MISCREG_V2PCWPR: 486 flags = TLB::MustBeOne; 487 mode = BaseTLB::Read; 488 break; 489 case MISCREG_V2PCWPW: 490 flags = TLB::MustBeOne; 491 mode = BaseTLB::Write; 492 break; 493 case MISCREG_V2PCWUR: 494 flags = TLB::MustBeOne | TLB::UserMode; 495 mode = BaseTLB::Read; 496 break; 497 case MISCREG_V2PCWUW: 498 flags = TLB::MustBeOne | TLB::UserMode; 499 mode = BaseTLB::Write; 500 break; 501 default: 502 panic("Security Extensions not implemented!"); 503 } 504 warn("Translating via MISCREG in atomic mode! Fix Me!\n"); 505 req->setVirt(0, val, 1, flags, tc->pcState().pc()); 506 fault = tc->getDTBPtr()->translateAtomic(req, tc, mode); 507 if (fault == NoFault) { 508 miscRegs[MISCREG_PAR] = 509 (req->getPaddr() & 0xfffff000) | 510 (tc->getDTBPtr()->getAttr() ); 511 DPRINTF(MiscRegs, 512 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 513 val, miscRegs[MISCREG_PAR]); 514 } 515 else { 516 // Set fault bit and FSR 517 FSR fsr = miscRegs[MISCREG_DFSR]; 518 miscRegs[MISCREG_PAR] = 519 (fsr.ext << 6) | 520 (fsr.fsHigh << 5) | 521 (fsr.fsLow << 1) | 522 0x1; // F bit 523 } 524 return; 525 } 526 case MISCREG_CONTEXTIDR: 527 case MISCREG_PRRR: 528 case MISCREG_NMRR: 529 case MISCREG_DACR: 530 tc->getITBPtr()->invalidateMiscReg(); 531 tc->getDTBPtr()->invalidateMiscReg(); 532 break; 533 case MISCREG_CPSR_MODE: 534 // This miscreg is used by copy*Regs to set the CPSR mode 535 // without updating other CPSR variables. It's used to 536 // make sure the register map is in such a state that we can 537 // see all of the registers for the copy. 538 updateRegMap(val); 539 return; 540 } 541 } 542 setMiscRegNoEffect(misc_reg, newVal); 543} 544 545} 546