isa.cc revision 8520:f9a495adafd9
12623SN/A/* 22623SN/A * Copyright (c) 2010 ARM Limited 32623SN/A * All rights reserved 42623SN/A * 52623SN/A * The license below extends only to copyright in the software and shall 62623SN/A * not be construed as granting a license to any other intellectual 72623SN/A * property including but not limited to intellectual property relating 82623SN/A * to a hardware implementation of the functionality of the software 92623SN/A * licensed hereunder. You may use the software subject to the license 102623SN/A * terms below provided that you ensure that this notice is replicated 112623SN/A * unmodified and in its entirety in all distributions of the software, 122623SN/A * modified or unmodified, in source code or in binary form. 132623SN/A * 142623SN/A * Redistribution and use in source and binary forms, with or without 152623SN/A * modification, are permitted provided that the following conditions are 162623SN/A * met: redistributions of source code must retain the above copyright 172623SN/A * notice, this list of conditions and the following disclaimer; 182623SN/A * redistributions in binary form must reproduce the above copyright 192623SN/A * notice, this list of conditions and the following disclaimer in the 202623SN/A * documentation and/or other materials provided with the distribution; 212623SN/A * neither the name of the copyright holders nor the names of its 222623SN/A * contributors may be used to endorse or promote products derived from 232623SN/A * this software without specific prior written permission. 242623SN/A * 252623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 262623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 272665Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 282665Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 292623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 302623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 313170Sstever@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 328105Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 332623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 344040Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 356658Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 368229Snate@binkert.org * 372623SN/A * Authors: Gabe Black 388232Snate@binkert.org * Ali Saidi 398232Snate@binkert.org */ 403348Sbinkertn@umich.edu 413348Sbinkertn@umich.edu#include "arch/arm/isa.hh" 424762Snate@binkert.org#include "debug/Arm.hh" 437678Sgblack@eecs.umich.edu#include "debug/MiscRegs.hh" 442901Ssaidi@eecs.umich.edu#include "sim/faults.hh" 452623SN/A#include "sim/stat_control.hh" 462623SN/A#include "sim/system.hh" 472623SN/A 482623SN/Anamespace ArmISA 492623SN/A{ 505606Snate@binkert.org 512623SN/Avoid 522623SN/AISA::clear() 532623SN/A{ 542623SN/A SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 552623SN/A uint32_t midr = miscRegs[MISCREG_MIDR]; 562623SN/A memset(miscRegs, 0, sizeof(miscRegs)); 572623SN/A CPSR cpsr = 0; 582623SN/A cpsr.mode = MODE_USER; 592623SN/A miscRegs[MISCREG_CPSR] = cpsr; 602623SN/A updateRegMap(cpsr); 612623SN/A 625336Shines@cs.fsu.edu SCTLR sctlr = 0; 632623SN/A sctlr.te = (bool)sctlr_rst.te; 644873Sstever@eecs.umich.edu sctlr.nmfi = (bool)sctlr_rst.nmfi; 652623SN/A sctlr.v = (bool)sctlr_rst.v; 662623SN/A sctlr.u = 1; 672856Srdreslin@umich.edu sctlr.xp = 1; 686227Snate@binkert.org sctlr.rao2 = 1; 692856Srdreslin@umich.edu sctlr.rao3 = 1; 702856Srdreslin@umich.edu sctlr.rao4 = 1; 712856Srdreslin@umich.edu miscRegs[MISCREG_SCTLR] = sctlr; 722856Srdreslin@umich.edu miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 732856Srdreslin@umich.edu 744968Sacolyte@umich.edu // Preserve MIDR accross reset 754968Sacolyte@umich.edu miscRegs[MISCREG_MIDR] = midr; 764968Sacolyte@umich.edu 774968Sacolyte@umich.edu /* Start with an event in the mailbox */ 782856Srdreslin@umich.edu miscRegs[MISCREG_SEV_MAILBOX] = 1; 792856Srdreslin@umich.edu 802856Srdreslin@umich.edu // Separate Instruction and Data TLBs. 812623SN/A miscRegs[MISCREG_TLBTR] = 1; 822623SN/A 832623SN/A MVFR0 mvfr0 = 0; 842623SN/A mvfr0.advSimdRegisters = 2; 852623SN/A mvfr0.singlePrecision = 2; 862623SN/A mvfr0.doublePrecision = 2; 876221Snate@binkert.org mvfr0.vfpExceptionTrapping = 0; 886221Snate@binkert.org mvfr0.divide = 1; 892680Sktlim@umich.edu mvfr0.squareRoot = 1; 902623SN/A mvfr0.shortVectors = 1; 912623SN/A mvfr0.roundingModes = 1; 925714Shsul@eecs.umich.edu miscRegs[MISCREG_MVFR0] = mvfr0; 932623SN/A 942623SN/A MVFR1 mvfr1 = 0; 954968Sacolyte@umich.edu mvfr1.flushToZero = 1; 964968Sacolyte@umich.edu mvfr1.defaultNaN = 1; 974968Sacolyte@umich.edu mvfr1.advSimdLoadStore = 1; 984968Sacolyte@umich.edu mvfr1.advSimdInteger = 1; 994968Sacolyte@umich.edu mvfr1.advSimdSinglePrecision = 1; 1004968Sacolyte@umich.edu mvfr1.advSimdHalfPrecision = 1; 1015714Shsul@eecs.umich.edu mvfr1.vfpHalfPrecision = 1; 1025712Shsul@eecs.umich.edu miscRegs[MISCREG_MVFR1] = mvfr1; 1035712Shsul@eecs.umich.edu 1045712Shsul@eecs.umich.edu miscRegs[MISCREG_MPIDR] = 0; 1052623SN/A 1062623SN/A // Reset values of PRRR and NMRR are implementation dependent 1072623SN/A 1083349Sbinkertn@umich.edu miscRegs[MISCREG_PRRR] = 1092623SN/A (1 << 19) | // 19 1103184Srdreslin@umich.edu (0 << 18) | // 18 1112623SN/A (0 << 17) | // 17 1122623SN/A (1 << 16) | // 16 1132623SN/A (2 << 14) | // 15:14 1142623SN/A (0 << 12) | // 13:12 1153349Sbinkertn@umich.edu (2 << 10) | // 11:10 1162623SN/A (2 << 8) | // 9:8 1173310Srdreslin@umich.edu (2 << 6) | // 7:6 1183649Srdreslin@umich.edu (2 << 4) | // 5:4 1192623SN/A (1 << 2) | // 3:2 1202623SN/A 0; // 1:0 1212623SN/A miscRegs[MISCREG_NMRR] = 1223349Sbinkertn@umich.edu (1 << 30) | // 31:30 1232623SN/A (0 << 26) | // 27:26 1243184Srdreslin@umich.edu (0 << 24) | // 25:24 1253184Srdreslin@umich.edu (3 << 22) | // 23:22 1262623SN/A (2 << 20) | // 21:20 1272623SN/A (0 << 18) | // 19:18 1282623SN/A (0 << 16) | // 17:16 1292623SN/A (1 << 14) | // 15:14 1302623SN/A (0 << 12) | // 13:12 1313647Srdreslin@umich.edu (2 << 10) | // 11:10 1323647Srdreslin@umich.edu (0 << 8) | // 9:8 1333647Srdreslin@umich.edu (3 << 6) | // 7:6 1343647Srdreslin@umich.edu (2 << 4) | // 5:4 1353647Srdreslin@umich.edu (0 << 2) | // 3:2 1362626SN/A 0; // 1:0 1373647Srdreslin@umich.edu 1382626SN/A miscRegs[MISCREG_CPACR] = 0; 1392623SN/A miscRegs[MISCREG_FPSID] = 0x410430A0; 1402623SN/A 1412623SN/A // See section B4.1.84 of ARM ARM 1422657Ssaidi@eecs.umich.edu // All values are latest for ARMv7-A profile 1432623SN/A miscRegs[MISCREG_ID_ISAR0] = 0x02101111; 1442623SN/A miscRegs[MISCREG_ID_ISAR1] = 0x02112111; 1452623SN/A miscRegs[MISCREG_ID_ISAR2] = 0x21232141; 1462623SN/A miscRegs[MISCREG_ID_ISAR3] = 0x01112131; 1472623SN/A miscRegs[MISCREG_ID_ISAR4] = 0x10010142; 1484192Sktlim@umich.edu miscRegs[MISCREG_ID_ISAR5] = 0x00000000; 1494192Sktlim@umich.edu 1504192Sktlim@umich.edu //XXX We need to initialize the rest of the state. 1514192Sktlim@umich.edu} 1524192Sktlim@umich.edu 1534192Sktlim@umich.eduMiscReg 1544192Sktlim@umich.eduISA::readMiscRegNoEffect(int misc_reg) 1554192Sktlim@umich.edu{ 1565497Ssaidi@eecs.umich.edu assert(misc_reg < NumMiscRegs); 1574192Sktlim@umich.edu 1584192Sktlim@umich.edu int flat_idx; 1592623SN/A if (misc_reg == MISCREG_SPSR) 1605529Snate@binkert.org flat_idx = flattenMiscIndex(misc_reg); 1616078Sgblack@eecs.umich.edu else 1625487Snate@binkert.org flat_idx = misc_reg; 1635487Snate@binkert.org MiscReg val = miscRegs[flat_idx]; 1644968Sacolyte@umich.edu 1654968Sacolyte@umich.edu DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n", 1662623SN/A misc_reg, flat_idx, val); 1672623SN/A return val; 1682623SN/A} 1693647Srdreslin@umich.edu 1703647Srdreslin@umich.edu 1713647Srdreslin@umich.eduMiscReg 1722623SN/AISA::readMiscReg(int misc_reg, ThreadContext *tc) 1732623SN/A{ 1742623SN/A if (misc_reg == MISCREG_CPSR) { 1752623SN/A CPSR cpsr = miscRegs[misc_reg]; 1762623SN/A PCState pc = tc->pcState(); 1776775SBrad.Beckmann@amd.com cpsr.j = pc.jazelle() ? 1 : 0; 1786775SBrad.Beckmann@amd.com cpsr.t = pc.thumb() ? 1 : 0; 1796775SBrad.Beckmann@amd.com return cpsr; 1802623SN/A } 1812623SN/A if (misc_reg >= MISCREG_CP15_UNIMP_START) 1822623SN/A panic("Unimplemented CP15 register %s read.\n", 1832623SN/A miscRegName[misc_reg]); 1842623SN/A 1852915Sktlim@umich.edu switch (misc_reg) { 1862915Sktlim@umich.edu case MISCREG_MPIDR: 1876078Sgblack@eecs.umich.edu return tc->cpuId(); 1883145Shsul@eecs.umich.edu break; 1892623SN/A case MISCREG_ID_MMFR0: 1902623SN/A return 0x03; // VMSAv7 support 1912623SN/A case MISCREG_ID_MMFR2: 1922623SN/A return 0x01230000; // no HW access | WFI stalling | ISB and DSB 1932623SN/A // | all TLB maintenance | no Harvard 1942623SN/A case MISCREG_ID_MMFR3: 1952623SN/A return 0xF0102211; // SuperSec | Coherent TLB | Bcast Maint | 1962915Sktlim@umich.edu // BP Maint | Cache Maint Set/way | Cache Maint MVA 1972915Sktlim@umich.edu case MISCREG_CLIDR: 1986078Sgblack@eecs.umich.edu warn_once("The clidr register always reports 0 caches.\n"); 1993145Shsul@eecs.umich.edu warn_once("clidr LoUIS field of 0b001 to match current " 2002915Sktlim@umich.edu "ARM implementations.\n"); 2012915Sktlim@umich.edu return 0x00200000; 2022915Sktlim@umich.edu case MISCREG_CCSIDR: 2032915Sktlim@umich.edu warn_once("The ccsidr register isn't implemented and " 2042915Sktlim@umich.edu "always reads as 0.\n"); 2052915Sktlim@umich.edu break; 2065220Ssaidi@eecs.umich.edu case MISCREG_ID_PFR0: 2075220Ssaidi@eecs.umich.edu warn("Returning thumbEE disabled for now since we don't support CP14" 2085220Ssaidi@eecs.umich.edu "config registers and jumping to ThumbEE vectors\n"); 2094940Snate@binkert.org return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM 2105220Ssaidi@eecs.umich.edu case MISCREG_ID_PFR1: 2113324Shsul@eecs.umich.edu warn("reading unimplmented register ID_PFR1"); 2125220Ssaidi@eecs.umich.edu return 0; 2135220Ssaidi@eecs.umich.edu case MISCREG_CTR: 2145606Snate@binkert.org return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact 2155606Snate@binkert.org case MISCREG_ACTLR: 2162915Sktlim@umich.edu warn("Not doing anything for miscreg ACTLR\n"); 2177897Shestness@cs.utexas.edu break; 2182623SN/A case MISCREG_PMCR: 2192623SN/A case MISCREG_PMCCNTR: 2202623SN/A case MISCREG_PMSELR: 2212798Sktlim@umich.edu warn("Not doing anything for read to miscreg %s\n", 2222623SN/A miscRegName[misc_reg]); 2235496Ssaidi@eecs.umich.edu break; 2242798Sktlim@umich.edu case MISCREG_CPSR_Q: 2252623SN/A panic("shouldn't be reading this register seperately\n"); 2262798Sktlim@umich.edu case MISCREG_FPSCR_QC: 2272623SN/A return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 2282623SN/A case MISCREG_FPSCR_EXC: 2292623SN/A return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 2302623SN/A } 2312623SN/A return readMiscRegNoEffect(misc_reg); 2322623SN/A} 2334192Sktlim@umich.edu 2342623SN/Avoid 2352623SN/AISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 2362623SN/A{ 2372680Sktlim@umich.edu assert(misc_reg < NumMiscRegs); 2382623SN/A 2396221Snate@binkert.org int flat_idx; 2406221Snate@binkert.org if (misc_reg == MISCREG_SPSR) 2412680Sktlim@umich.edu flat_idx = flattenMiscIndex(misc_reg); 2422680Sktlim@umich.edu else 2432623SN/A flat_idx = misc_reg; 2445606Snate@binkert.org miscRegs[flat_idx] = val; 2452623SN/A 2462623SN/A DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg, 2472623SN/A flat_idx, val); 2483512Sktlim@umich.edu} 2493512Sktlim@umich.edu 2503512Sktlim@umich.eduvoid 2515169Ssaidi@eecs.umich.eduISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 2525712Shsul@eecs.umich.edu{ 2535712Shsul@eecs.umich.edu 2545712Shsul@eecs.umich.edu MiscReg newVal = val; 2552623SN/A int x; 2562623SN/A System *sys; 2572623SN/A ThreadContext *oc; 2582623SN/A 2592623SN/A if (misc_reg == MISCREG_CPSR) { 2602623SN/A updateRegMap(val); 2614940Snate@binkert.org 2624940Snate@binkert.org 2632623SN/A CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 2642683Sktlim@umich.edu int old_mode = old_cpsr.mode; 2652623SN/A CPSR cpsr = val; 2662623SN/A if (old_mode != cpsr.mode) { 2672623SN/A tc->getITBPtr()->invalidateMiscReg(); 2682623SN/A tc->getDTBPtr()->invalidateMiscReg(); 2692623SN/A } 2705101Ssaidi@eecs.umich.edu 2713686Sktlim@umich.edu DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 2723430Sgblack@eecs.umich.edu miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 2737823Ssteve.reinhardt@amd.com PCState pc = tc->pcState(); 2742623SN/A pc.nextThumb(cpsr.t); 2752623SN/A pc.nextJazelle(cpsr.j); 2762623SN/A tc->pcState(pc); 2772623SN/A } else if (misc_reg >= MISCREG_CP15_UNIMP_START && 2782623SN/A misc_reg < MISCREG_CP15_END) { 2792623SN/A panic("Unimplemented CP15 register %s wrote with %#x.\n", 2802623SN/A miscRegName[misc_reg], val); 2814940Snate@binkert.org } else { 2824940Snate@binkert.org switch (misc_reg) { 2832623SN/A case MISCREG_CPACR: 2842683Sktlim@umich.edu { 2852623SN/A 2866043Sgblack@eecs.umich.edu const uint32_t ones = (uint32_t)(-1); 2876043Sgblack@eecs.umich.edu CPACR cpacrMask = 0; 2886043Sgblack@eecs.umich.edu // Only cp10, cp11, and ase are implemented, nothing else should 2892623SN/A // be writable 2902626SN/A cpacrMask.cp10 = ones; 2912626SN/A cpacrMask.cp11 = ones; 2922626SN/A cpacrMask.asedis = ones; 2932626SN/A newVal &= cpacrMask; 2945606Snate@binkert.org DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 2952623SN/A miscRegName[misc_reg], newVal); 2962623SN/A } 2972623SN/A break; 2982623SN/A case MISCREG_CSSELR: 2992623SN/A warn_once("The csselr register isn't implemented.\n"); 3002623SN/A return; 3012623SN/A case MISCREG_FPSCR: 3027520Sgblack@eecs.umich.edu { 3037520Sgblack@eecs.umich.edu const uint32_t ones = (uint32_t)(-1); 3042623SN/A FPSCR fpscrMask = 0; 3053169Sstever@eecs.umich.edu fpscrMask.ioc = ones; 3064870Sstever@eecs.umich.edu fpscrMask.dzc = ones; 3072623SN/A fpscrMask.ofc = ones; 3082623SN/A fpscrMask.ufc = ones; 3092623SN/A fpscrMask.ixc = ones; 3102623SN/A fpscrMask.idc = ones; 3112623SN/A fpscrMask.len = ones; 3124999Sgblack@eecs.umich.edu fpscrMask.stride = ones; 3136227Snate@binkert.org fpscrMask.rMode = ones; 3144999Sgblack@eecs.umich.edu fpscrMask.fz = ones; 3157520Sgblack@eecs.umich.edu fpscrMask.dn = ones; 3162623SN/A fpscrMask.ahp = ones; 3174999Sgblack@eecs.umich.edu fpscrMask.qc = ones; 3184999Sgblack@eecs.umich.edu fpscrMask.v = ones; 3197520Sgblack@eecs.umich.edu fpscrMask.c = ones; 3204999Sgblack@eecs.umich.edu fpscrMask.z = ones; 3217520Sgblack@eecs.umich.edu fpscrMask.n = ones; 3227520Sgblack@eecs.umich.edu newVal = (newVal & (uint32_t)fpscrMask) | 3234999Sgblack@eecs.umich.edu (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask); 3244999Sgblack@eecs.umich.edu } 3254999Sgblack@eecs.umich.edu break; 3267520Sgblack@eecs.umich.edu case MISCREG_CPSR_Q: 3277720Sgblack@eecs.umich.edu { 3284999Sgblack@eecs.umich.edu assert(!(newVal & ~CpsrMaskQ)); 3294999Sgblack@eecs.umich.edu newVal = miscRegs[MISCREG_CPSR] | newVal; 3306023Snate@binkert.org misc_reg = MISCREG_CPSR; 3314999Sgblack@eecs.umich.edu } 3324999Sgblack@eecs.umich.edu break; 3336623Sgblack@eecs.umich.edu case MISCREG_FPSCR_QC: 3344999Sgblack@eecs.umich.edu { 3356102Sgblack@eecs.umich.edu newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrQcMask); 3364999Sgblack@eecs.umich.edu misc_reg = MISCREG_FPSCR; 3377520Sgblack@eecs.umich.edu } 3384999Sgblack@eecs.umich.edu break; 3398105Sgblack@eecs.umich.edu case MISCREG_FPSCR_EXC: 3404999Sgblack@eecs.umich.edu { 3414999Sgblack@eecs.umich.edu newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrExcMask); 3424999Sgblack@eecs.umich.edu misc_reg = MISCREG_FPSCR; 3434999Sgblack@eecs.umich.edu } 3444999Sgblack@eecs.umich.edu break; 3454999Sgblack@eecs.umich.edu case MISCREG_FPEXC: 3464999Sgblack@eecs.umich.edu { 3474999Sgblack@eecs.umich.edu // vfpv3 architecture, section B.6.1 of DDI04068 3485012Sgblack@eecs.umich.edu // bit 29 - valid only if fpexc[31] is 0 3494999Sgblack@eecs.umich.edu const uint32_t fpexcMask = 0x60000000; 3504999Sgblack@eecs.umich.edu newVal = (newVal & fpexcMask) | 3516102Sgblack@eecs.umich.edu (miscRegs[MISCREG_FPEXC] & ~fpexcMask); 3524999Sgblack@eecs.umich.edu } 3534999Sgblack@eecs.umich.edu break; 3544968Sacolyte@umich.edu case MISCREG_SCTLR: 3554986Ssaidi@eecs.umich.edu { 3564999Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 3576739Sgblack@eecs.umich.edu SCTLR sctlr = miscRegs[MISCREG_SCTLR]; 3586739Sgblack@eecs.umich.edu SCTLR new_sctlr = newVal; 3596739Sgblack@eecs.umich.edu new_sctlr.nmfi = (bool)sctlr.nmfi; 3606739Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr; 3616739Sgblack@eecs.umich.edu tc->getITBPtr()->invalidateMiscReg(); 3626739Sgblack@eecs.umich.edu tc->getDTBPtr()->invalidateMiscReg(); 3636739Sgblack@eecs.umich.edu return; 3646739Sgblack@eecs.umich.edu } 3654999Sgblack@eecs.umich.edu case MISCREG_TLBTR: 3664999Sgblack@eecs.umich.edu case MISCREG_MVFR0: 3674999Sgblack@eecs.umich.edu case MISCREG_MVFR1: 3686078Sgblack@eecs.umich.edu case MISCREG_MPIDR: 3696078Sgblack@eecs.umich.edu case MISCREG_FPSID: 3706078Sgblack@eecs.umich.edu return; 3716078Sgblack@eecs.umich.edu case MISCREG_TLBIALLIS: 3724999Sgblack@eecs.umich.edu case MISCREG_TLBIALL: 3734968Sacolyte@umich.edu sys = tc->getSystemPtr(); 3743170Sstever@eecs.umich.edu for (x = 0; x < sys->numContexts(); x++) { 3754999Sgblack@eecs.umich.edu oc = sys->getThreadContext(x); 3764999Sgblack@eecs.umich.edu assert(oc->getITBPtr() && oc->getDTBPtr()); 3774999Sgblack@eecs.umich.edu oc->getITBPtr()->flushAll(); 3784999Sgblack@eecs.umich.edu oc->getDTBPtr()->flushAll(); 3794999Sgblack@eecs.umich.edu } 3807520Sgblack@eecs.umich.edu return; 3814999Sgblack@eecs.umich.edu case MISCREG_ITLBIALL: 3827520Sgblack@eecs.umich.edu tc->getITBPtr()->flushAll(); 3834999Sgblack@eecs.umich.edu return; 3844999Sgblack@eecs.umich.edu case MISCREG_DTLBIALL: 3852623SN/A tc->getDTBPtr()->flushAll(); 3862623SN/A return; 3872623SN/A case MISCREG_TLBIMVAIS: 3887520Sgblack@eecs.umich.edu case MISCREG_TLBIMVA: 3897520Sgblack@eecs.umich.edu sys = tc->getSystemPtr(); 3907520Sgblack@eecs.umich.edu for (x = 0; x < sys->numContexts(); x++) { 3917520Sgblack@eecs.umich.edu oc = sys->getThreadContext(x); 3927520Sgblack@eecs.umich.edu assert(oc->getITBPtr() && oc->getDTBPtr()); 3937520Sgblack@eecs.umich.edu oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 3947520Sgblack@eecs.umich.edu bits(newVal, 7,0)); 3957520Sgblack@eecs.umich.edu oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 3967520Sgblack@eecs.umich.edu bits(newVal, 7,0)); 3977520Sgblack@eecs.umich.edu } 3987520Sgblack@eecs.umich.edu return; 3997520Sgblack@eecs.umich.edu case MISCREG_TLBIASIDIS: 4007520Sgblack@eecs.umich.edu case MISCREG_TLBIASID: 4017520Sgblack@eecs.umich.edu sys = tc->getSystemPtr(); 4027520Sgblack@eecs.umich.edu for (x = 0; x < sys->numContexts(); x++) { 4037520Sgblack@eecs.umich.edu oc = sys->getThreadContext(x); 4042623SN/A assert(oc->getITBPtr() && oc->getDTBPtr()); 4052623SN/A oc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 4062623SN/A oc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 4072623SN/A } 4084115Ssaidi@eecs.umich.edu return; 4094115Ssaidi@eecs.umich.edu case MISCREG_TLBIMVAAIS: 4104115Ssaidi@eecs.umich.edu case MISCREG_TLBIMVAA: 4114115Ssaidi@eecs.umich.edu sys = tc->getSystemPtr(); 4124040Ssaidi@eecs.umich.edu for (x = 0; x < sys->numContexts(); x++) { 4134040Ssaidi@eecs.umich.edu oc = sys->getThreadContext(x); 4144040Ssaidi@eecs.umich.edu assert(oc->getITBPtr() && oc->getDTBPtr()); 4154040Ssaidi@eecs.umich.edu oc->getITBPtr()->flushMva(mbits(newVal, 31,12)); 4162623SN/A oc->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 4172623SN/A } 4182623SN/A return; 4192623SN/A case MISCREG_ITLBIMVA: 4202623SN/A tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 4212623SN/A bits(newVal, 7,0)); 4222623SN/A return; 4232623SN/A case MISCREG_DTLBIMVA: 4242623SN/A tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 4252623SN/A bits(newVal, 7,0)); 4262623SN/A return; 4272623SN/A case MISCREG_ITLBIASID: 4282623SN/A tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 4292623SN/A return; 4302623SN/A case MISCREG_DTLBIASID: 4312623SN/A tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 4322623SN/A return; 4332623SN/A case MISCREG_ACTLR: 4342623SN/A warn("Not doing anything for write of miscreg ACTLR\n"); 4352623SN/A break; 4362623SN/A case MISCREG_PMCR: 4372623SN/A { 4382623SN/A // Performance counters not implemented. Instead, interpret 4392623SN/A // a reset command to this register to reset the simulator 4402623SN/A // statistics. 4412623SN/A // PMCR_E | PMCR_P | PMCR_C 4422623SN/A const int ResetAndEnableCounters = 0x7; 4432623SN/A if (newVal == ResetAndEnableCounters) { 4442623SN/A inform("Resetting all simobject stats\n"); 4452623SN/A Stats::schedStatEvent(false, true); 4462623SN/A break; 4472623SN/A } 4482623SN/A } 4492623SN/A case MISCREG_PMCCNTR: 4502623SN/A case MISCREG_PMSELR: 4512623SN/A warn("Not doing anything for write to miscreg %s\n", 4522623SN/A miscRegName[misc_reg]); 4532623SN/A break; 4542623SN/A case MISCREG_V2PCWPR: 4552623SN/A case MISCREG_V2PCWPW: 4567520Sgblack@eecs.umich.edu case MISCREG_V2PCWUR: 4577520Sgblack@eecs.umich.edu case MISCREG_V2PCWUW: 4582623SN/A case MISCREG_V2POWPR: 4593169Sstever@eecs.umich.edu case MISCREG_V2POWPW: 4604870Sstever@eecs.umich.edu case MISCREG_V2POWUR: 4612623SN/A case MISCREG_V2POWUW: 4622623SN/A { 4632623SN/A RequestPtr req = new Request; 4642623SN/A unsigned flags; 4652623SN/A BaseTLB::Mode mode; 4664999Sgblack@eecs.umich.edu Fault fault; 4676227Snate@binkert.org switch(misc_reg) { 4684999Sgblack@eecs.umich.edu case MISCREG_V2PCWPR: 4697520Sgblack@eecs.umich.edu flags = TLB::MustBeOne; 4702623SN/A mode = BaseTLB::Read; 4714999Sgblack@eecs.umich.edu break; 4724999Sgblack@eecs.umich.edu case MISCREG_V2PCWPW: 4737520Sgblack@eecs.umich.edu flags = TLB::MustBeOne; 4744999Sgblack@eecs.umich.edu mode = BaseTLB::Write; 4754999Sgblack@eecs.umich.edu break; 4767520Sgblack@eecs.umich.edu case MISCREG_V2PCWUR: 4774999Sgblack@eecs.umich.edu flags = TLB::MustBeOne | TLB::UserMode; 4784999Sgblack@eecs.umich.edu mode = BaseTLB::Read; 4794999Sgblack@eecs.umich.edu break; 4804999Sgblack@eecs.umich.edu case MISCREG_V2PCWUW: 4817720Sgblack@eecs.umich.edu flags = TLB::MustBeOne | TLB::UserMode; 4824999Sgblack@eecs.umich.edu mode = BaseTLB::Write; 4834999Sgblack@eecs.umich.edu break; 4846023Snate@binkert.org default: 4854999Sgblack@eecs.umich.edu panic("Security Extensions not implemented!"); 4864999Sgblack@eecs.umich.edu } 4874999Sgblack@eecs.umich.edu warn("Translating via MISCREG in atomic mode! Fix Me!\n"); 4884999Sgblack@eecs.umich.edu req->setVirt(0, val, 1, flags, tc->pcState().pc()); 4894999Sgblack@eecs.umich.edu fault = tc->getDTBPtr()->translateAtomic(req, tc, mode); 4904999Sgblack@eecs.umich.edu if (fault == NoFault) { 4916102Sgblack@eecs.umich.edu miscRegs[MISCREG_PAR] = 4924999Sgblack@eecs.umich.edu (req->getPaddr() & 0xfffff000) | 4934999Sgblack@eecs.umich.edu (tc->getDTBPtr()->getAttr() ); 4944999Sgblack@eecs.umich.edu DPRINTF(MiscRegs, 4954999Sgblack@eecs.umich.edu "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 4964999Sgblack@eecs.umich.edu val, miscRegs[MISCREG_PAR]); 4974999Sgblack@eecs.umich.edu } 4984999Sgblack@eecs.umich.edu else { 4994999Sgblack@eecs.umich.edu // Set fault bit and FSR 5004999Sgblack@eecs.umich.edu FSR fsr = miscRegs[MISCREG_DFSR]; 5014999Sgblack@eecs.umich.edu miscRegs[MISCREG_PAR] = 5026623Sgblack@eecs.umich.edu (fsr.ext << 6) | 5034999Sgblack@eecs.umich.edu (fsr.fsHigh << 5) | 5047520Sgblack@eecs.umich.edu (fsr.fsLow << 1) | 5054999Sgblack@eecs.umich.edu 0x1; // F bit 5068105Sgblack@eecs.umich.edu } 5074999Sgblack@eecs.umich.edu return; 5084999Sgblack@eecs.umich.edu } 5094999Sgblack@eecs.umich.edu case MISCREG_CONTEXTIDR: 5104999Sgblack@eecs.umich.edu case MISCREG_PRRR: 5114999Sgblack@eecs.umich.edu case MISCREG_NMRR: 5124999Sgblack@eecs.umich.edu case MISCREG_DACR: 5134999Sgblack@eecs.umich.edu tc->getITBPtr()->invalidateMiscReg(); 5144999Sgblack@eecs.umich.edu tc->getDTBPtr()->invalidateMiscReg(); 5154999Sgblack@eecs.umich.edu break; 5164999Sgblack@eecs.umich.edu case MISCREG_CPSR_MODE: 5174999Sgblack@eecs.umich.edu // This miscreg is used by copy*Regs to set the CPSR mode 5184999Sgblack@eecs.umich.edu // without updating other CPSR variables. It's used to 5194999Sgblack@eecs.umich.edu // make sure the register map is in such a state that we can 5207520Sgblack@eecs.umich.edu // see all of the registers for the copy. 5214999Sgblack@eecs.umich.edu updateRegMap(val); 5224999Sgblack@eecs.umich.edu return; 5234999Sgblack@eecs.umich.edu } 5244999Sgblack@eecs.umich.edu } 5254999Sgblack@eecs.umich.edu setMiscRegNoEffect(misc_reg, newVal); 5264878Sstever@eecs.umich.edu} 5274040Ssaidi@eecs.umich.edu 5284040Ssaidi@eecs.umich.edu} 5294999Sgblack@eecs.umich.edu