isa.cc revision 8299:64a938a8b7fc
16145Snate@binkert.org/* 26145Snate@binkert.org * Copyright (c) 2010 ARM Limited 36145Snate@binkert.org * All rights reserved 46145Snate@binkert.org * 56145Snate@binkert.org * The license below extends only to copyright in the software and shall 66145Snate@binkert.org * not be construed as granting a license to any other intellectual 76145Snate@binkert.org * property including but not limited to intellectual property relating 86145Snate@binkert.org * to a hardware implementation of the functionality of the software 96145Snate@binkert.org * licensed hereunder. You may use the software subject to the license 106145Snate@binkert.org * terms below provided that you ensure that this notice is replicated 116145Snate@binkert.org * unmodified and in its entirety in all distributions of the software, 126145Snate@binkert.org * modified or unmodified, in source code or in binary form. 136145Snate@binkert.org * 146145Snate@binkert.org * Redistribution and use in source and binary forms, with or without 156145Snate@binkert.org * modification, are permitted provided that the following conditions are 166145Snate@binkert.org * met: redistributions of source code must retain the above copyright 176145Snate@binkert.org * notice, this list of conditions and the following disclaimer; 186145Snate@binkert.org * redistributions in binary form must reproduce the above copyright 196145Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 206145Snate@binkert.org * documentation and/or other materials provided with the distribution; 216145Snate@binkert.org * neither the name of the copyright holders nor the names of its 226145Snate@binkert.org * contributors may be used to endorse or promote products derived from 236145Snate@binkert.org * this software without specific prior written permission. 246145Snate@binkert.org * 256145Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 266145Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 276145Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 286145Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297054Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307054Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317054Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327054Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337054Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 346154Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 356154Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 366145Snate@binkert.org * 377055Snate@binkert.org * Authors: Gabe Black 387055Snate@binkert.org * Ali Saidi 396145Snate@binkert.org */ 406145Snate@binkert.org 417054Snate@binkert.org#include "arch/arm/isa.hh" 427054Snate@binkert.org#include "debug/Arm.hh" 437054Snate@binkert.org#include "debug/MiscRegs.hh" 446145Snate@binkert.org#include "sim/faults.hh" 456145Snate@binkert.org#include "sim/stat_control.hh" 466145Snate@binkert.org#include "sim/system.hh" 476145Snate@binkert.org 487054Snate@binkert.orgnamespace ArmISA 496145Snate@binkert.org{ 507054Snate@binkert.org 517054Snate@binkert.orgvoid 526145Snate@binkert.orgISA::clear() 537054Snate@binkert.org{ 547054Snate@binkert.org SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 556145Snate@binkert.org uint32_t midr = miscRegs[MISCREG_MIDR]; 566145Snate@binkert.org memset(miscRegs, 0, sizeof(miscRegs)); 577054Snate@binkert.org CPSR cpsr = 0; 587054Snate@binkert.org cpsr.mode = MODE_USER; 596145Snate@binkert.org miscRegs[MISCREG_CPSR] = cpsr; 607054Snate@binkert.org updateRegMap(cpsr); 616145Snate@binkert.org 626145Snate@binkert.org SCTLR sctlr = 0; 637054Snate@binkert.org sctlr.te = (bool)sctlr_rst.te; 647054Snate@binkert.org sctlr.nmfi = (bool)sctlr_rst.nmfi; 657054Snate@binkert.org sctlr.v = (bool)sctlr_rst.v; 666145Snate@binkert.org sctlr.u = 1; 677054Snate@binkert.org sctlr.xp = 1; 686145Snate@binkert.org sctlr.rao2 = 1; 697054Snate@binkert.org sctlr.rao3 = 1; 707054Snate@binkert.org sctlr.rao4 = 1; 717054Snate@binkert.org miscRegs[MISCREG_SCTLR] = sctlr; 727054Snate@binkert.org miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 736145Snate@binkert.org 747054Snate@binkert.org // Preserve MIDR accross reset 757054Snate@binkert.org miscRegs[MISCREG_MIDR] = midr; 767054Snate@binkert.org 777054Snate@binkert.org /* Start with an event in the mailbox */ 787054Snate@binkert.org miscRegs[MISCREG_SEV_MAILBOX] = 1; 797054Snate@binkert.org 807054Snate@binkert.org // Separate Instruction and Data TLBs. 817054Snate@binkert.org miscRegs[MISCREG_TLBTR] = 1; 827054Snate@binkert.org 837054Snate@binkert.org MVFR0 mvfr0 = 0; 847054Snate@binkert.org mvfr0.advSimdRegisters = 2; 857054Snate@binkert.org mvfr0.singlePrecision = 2; 866145Snate@binkert.org mvfr0.doublePrecision = 2; 876145Snate@binkert.org mvfr0.vfpExceptionTrapping = 0; 887054Snate@binkert.org mvfr0.divide = 1; 897054Snate@binkert.org mvfr0.squareRoot = 1; 906145Snate@binkert.org mvfr0.shortVectors = 1; 917054Snate@binkert.org mvfr0.roundingModes = 1; 927054Snate@binkert.org miscRegs[MISCREG_MVFR0] = mvfr0; 936145Snate@binkert.org 946145Snate@binkert.org MVFR1 mvfr1 = 0; 957054Snate@binkert.org mvfr1.flushToZero = 1; 967054Snate@binkert.org mvfr1.defaultNaN = 1; 976145Snate@binkert.org mvfr1.advSimdLoadStore = 1; 987054Snate@binkert.org mvfr1.advSimdInteger = 1; 996145Snate@binkert.org mvfr1.advSimdSinglePrecision = 1; 1006145Snate@binkert.org mvfr1.advSimdHalfPrecision = 1; 1017054Snate@binkert.org mvfr1.vfpHalfPrecision = 1; 1027054Snate@binkert.org miscRegs[MISCREG_MVFR1] = mvfr1; 1036145Snate@binkert.org 1047054Snate@binkert.org miscRegs[MISCREG_MPIDR] = 0; 1057054Snate@binkert.org 1067054Snate@binkert.org // Reset values of PRRR and NMRR are implementation dependent 1077054Snate@binkert.org 1087054Snate@binkert.org miscRegs[MISCREG_PRRR] = 1096145Snate@binkert.org (1 << 19) | // 19 1106145Snate@binkert.org (0 << 18) | // 18 1116145Snate@binkert.org (0 << 17) | // 17 1127054Snate@binkert.org (1 << 16) | // 16 1137054Snate@binkert.org (2 << 14) | // 15:14 1146145Snate@binkert.org (0 << 12) | // 13:12 1157054Snate@binkert.org (2 << 10) | // 11:10 1166145Snate@binkert.org (2 << 8) | // 9:8 1176145Snate@binkert.org (2 << 6) | // 7:6 1187054Snate@binkert.org (2 << 4) | // 5:4 1197054Snate@binkert.org (1 << 2) | // 3:2 1206145Snate@binkert.org 0; // 1:0 1217054Snate@binkert.org miscRegs[MISCREG_NMRR] = 1227054Snate@binkert.org (1 << 30) | // 31:30 1236145Snate@binkert.org (0 << 26) | // 27:26 1246145Snate@binkert.org (0 << 24) | // 25:24 1257054Snate@binkert.org (3 << 22) | // 23:22 1267054Snate@binkert.org (2 << 20) | // 21:20 1276145Snate@binkert.org (0 << 18) | // 19:18 1287054Snate@binkert.org (0 << 16) | // 17:16 1296145Snate@binkert.org (1 << 14) | // 15:14 1306145Snate@binkert.org (0 << 12) | // 13:12 1317054Snate@binkert.org (2 << 10) | // 11:10 1327054Snate@binkert.org (0 << 8) | // 9:8 1336145Snate@binkert.org (3 << 6) | // 7:6 1347054Snate@binkert.org (2 << 4) | // 5:4 1357054Snate@binkert.org (0 << 2) | // 3:2 1367054Snate@binkert.org 0; // 1:0 1377054Snate@binkert.org 1386145Snate@binkert.org miscRegs[MISCREG_CPACR] = 0; 1397054Snate@binkert.org miscRegs[MISCREG_FPSID] = 0x410430A0; 1407054Snate@binkert.org 1417054Snate@binkert.org // See section B4.1.84 of ARM ARM 1426145Snate@binkert.org // All values are latest for ARMv7-A profile 1437054Snate@binkert.org miscRegs[MISCREG_ID_ISAR0] = 0x01101111; 1447054Snate@binkert.org miscRegs[MISCREG_ID_ISAR1] = 0x02112111; 1457054Snate@binkert.org miscRegs[MISCREG_ID_ISAR2] = 0x21232141; 1467054Snate@binkert.org miscRegs[MISCREG_ID_ISAR3] = 0x01112131; 1477054Snate@binkert.org miscRegs[MISCREG_ID_ISAR4] = 0x10010142; 1487054Snate@binkert.org miscRegs[MISCREG_ID_ISAR5] = 0x00000000; 1496145Snate@binkert.org 1507054Snate@binkert.org //XXX We need to initialize the rest of the state. 1517054Snate@binkert.org} 1526145Snate@binkert.org 1537054Snate@binkert.orgMiscReg 1547054Snate@binkert.orgISA::readMiscRegNoEffect(int misc_reg) 1557054Snate@binkert.org{ 1567054Snate@binkert.org assert(misc_reg < NumMiscRegs); 1577054Snate@binkert.org 1587054Snate@binkert.org int flat_idx; 1597054Snate@binkert.org if (misc_reg == MISCREG_SPSR) 1607054Snate@binkert.org flat_idx = flattenMiscIndex(misc_reg); 1617054Snate@binkert.org else 1627054Snate@binkert.org flat_idx = misc_reg; 1637054Snate@binkert.org MiscReg val = miscRegs[flat_idx]; 1647054Snate@binkert.org 1657054Snate@binkert.org DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n", 1666145Snate@binkert.org misc_reg, flat_idx, val); 1677054Snate@binkert.org return val; 1686145Snate@binkert.org} 1697054Snate@binkert.org 1707054Snate@binkert.org 1717054Snate@binkert.orgMiscReg 1727054Snate@binkert.orgISA::readMiscReg(int misc_reg, ThreadContext *tc) 1737054Snate@binkert.org{ 1747054Snate@binkert.org if (misc_reg == MISCREG_CPSR) { 1757054Snate@binkert.org CPSR cpsr = miscRegs[misc_reg]; 1767054Snate@binkert.org PCState pc = tc->pcState(); 1777054Snate@binkert.org cpsr.j = pc.jazelle() ? 1 : 0; 1787054Snate@binkert.org cpsr.t = pc.thumb() ? 1 : 0; 1797054Snate@binkert.org return cpsr; 1807054Snate@binkert.org } 1817054Snate@binkert.org if (misc_reg >= MISCREG_CP15_UNIMP_START) 1827054Snate@binkert.org panic("Unimplemented CP15 register %s read.\n", 1837054Snate@binkert.org miscRegName[misc_reg]); 1847054Snate@binkert.org 1857054Snate@binkert.org switch (misc_reg) { 1867054Snate@binkert.org case MISCREG_MPIDR: 1877054Snate@binkert.org return tc->cpuId(); 1886145Snate@binkert.org break; 1896145Snate@binkert.org case MISCREG_ID_MMFR3: 1907054Snate@binkert.org return 0xF0102211; // SuperSec | Coherent TLB | Bcast Maint | 1916145Snate@binkert.org // BP Maint | Cache Maint Set/way | Cache Maint MVA 1926145Snate@binkert.org case MISCREG_CLIDR: 1937054Snate@binkert.org warn_once("The clidr register always reports 0 caches.\n"); 1947054Snate@binkert.org break; 1956145Snate@binkert.org case MISCREG_CCSIDR: 1967054Snate@binkert.org warn_once("The ccsidr register isn't implemented and " 1977054Snate@binkert.org "always reads as 0.\n"); 1987054Snate@binkert.org break; 1997054Snate@binkert.org case MISCREG_ID_PFR0: 2006145Snate@binkert.org warn("Returning thumbEE disabled for now since we don't support CP14" 2016145Snate@binkert.org "config registers and jumping to ThumbEE vectors\n"); 2026145Snate@binkert.org return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM 2037054Snate@binkert.org case MISCREG_ID_PFR1: 2047054Snate@binkert.org warn("reading unimplmented register ID_PFR1"); 2056145Snate@binkert.org return 0; 2067054Snate@binkert.org case MISCREG_ID_MMFR0: 2077054Snate@binkert.org return 0x03; //VMSAz7 2087054Snate@binkert.org case MISCREG_CTR: 2097054Snate@binkert.org return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact 2106145Snate@binkert.org case MISCREG_ACTLR: 2116145Snate@binkert.org warn("Not doing anything for miscreg ACTLR\n"); 2126145Snate@binkert.org break; 2137054Snate@binkert.org case MISCREG_PMCR: 2147054Snate@binkert.org case MISCREG_PMCCNTR: 2156145Snate@binkert.org case MISCREG_PMSELR: 2167054Snate@binkert.org warn("Not doing anything for read to miscreg %s\n", 2177054Snate@binkert.org miscRegName[misc_reg]); 2186145Snate@binkert.org break; 2196145Snate@binkert.org case MISCREG_FPSCR_QC: 220 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 221 case MISCREG_FPSCR_EXC: 222 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 223 } 224 return readMiscRegNoEffect(misc_reg); 225} 226 227void 228ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 229{ 230 assert(misc_reg < NumMiscRegs); 231 232 int flat_idx; 233 if (misc_reg == MISCREG_SPSR) 234 flat_idx = flattenMiscIndex(misc_reg); 235 else 236 flat_idx = misc_reg; 237 miscRegs[flat_idx] = val; 238 239 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg, 240 flat_idx, val); 241} 242 243void 244ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 245{ 246 247 MiscReg newVal = val; 248 int x; 249 System *sys; 250 ThreadContext *oc; 251 252 if (misc_reg == MISCREG_CPSR) { 253 updateRegMap(val); 254 255 256 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 257 int old_mode = old_cpsr.mode; 258 CPSR cpsr = val; 259 if (old_mode != cpsr.mode) { 260 tc->getITBPtr()->invalidateMiscReg(); 261 tc->getDTBPtr()->invalidateMiscReg(); 262 } 263 264 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 265 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 266 PCState pc = tc->pcState(); 267 pc.nextThumb(cpsr.t); 268 pc.nextJazelle(cpsr.j); 269 tc->pcState(pc); 270 } else if (misc_reg >= MISCREG_CP15_UNIMP_START && 271 misc_reg < MISCREG_CP15_END) { 272 panic("Unimplemented CP15 register %s wrote with %#x.\n", 273 miscRegName[misc_reg], val); 274 } else { 275 switch (misc_reg) { 276 case MISCREG_CPACR: 277 { 278 279 const uint32_t ones = (uint32_t)(-1); 280 CPACR cpacrMask = 0; 281 // Only cp10, cp11, and ase are implemented, nothing else should 282 // be writable 283 cpacrMask.cp10 = ones; 284 cpacrMask.cp11 = ones; 285 cpacrMask.asedis = ones; 286 newVal &= cpacrMask; 287 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 288 miscRegName[misc_reg], newVal); 289 } 290 break; 291 case MISCREG_CSSELR: 292 warn_once("The csselr register isn't implemented.\n"); 293 return; 294 case MISCREG_FPSCR: 295 { 296 const uint32_t ones = (uint32_t)(-1); 297 FPSCR fpscrMask = 0; 298 fpscrMask.ioc = ones; 299 fpscrMask.dzc = ones; 300 fpscrMask.ofc = ones; 301 fpscrMask.ufc = ones; 302 fpscrMask.ixc = ones; 303 fpscrMask.idc = ones; 304 fpscrMask.len = ones; 305 fpscrMask.stride = ones; 306 fpscrMask.rMode = ones; 307 fpscrMask.fz = ones; 308 fpscrMask.dn = ones; 309 fpscrMask.ahp = ones; 310 fpscrMask.qc = ones; 311 fpscrMask.v = ones; 312 fpscrMask.c = ones; 313 fpscrMask.z = ones; 314 fpscrMask.n = ones; 315 newVal = (newVal & (uint32_t)fpscrMask) | 316 (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask); 317 } 318 break; 319 case MISCREG_FPSCR_QC: 320 { 321 newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrQcMask); 322 misc_reg = MISCREG_FPSCR; 323 } 324 break; 325 case MISCREG_FPSCR_EXC: 326 { 327 newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrExcMask); 328 misc_reg = MISCREG_FPSCR; 329 } 330 break; 331 case MISCREG_FPEXC: 332 { 333 // vfpv3 architecture, section B.6.1 of DDI04068 334 // bit 29 - valid only if fpexc[31] is 0 335 const uint32_t fpexcMask = 0x60000000; 336 newVal = (newVal & fpexcMask) | 337 (miscRegs[MISCREG_FPEXC] & ~fpexcMask); 338 } 339 break; 340 case MISCREG_SCTLR: 341 { 342 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 343 SCTLR sctlr = miscRegs[MISCREG_SCTLR]; 344 SCTLR new_sctlr = newVal; 345 new_sctlr.nmfi = (bool)sctlr.nmfi; 346 miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr; 347 tc->getITBPtr()->invalidateMiscReg(); 348 tc->getDTBPtr()->invalidateMiscReg(); 349 return; 350 } 351 case MISCREG_TLBTR: 352 case MISCREG_MVFR0: 353 case MISCREG_MVFR1: 354 case MISCREG_MPIDR: 355 case MISCREG_FPSID: 356 return; 357 case MISCREG_TLBIALLIS: 358 case MISCREG_TLBIALL: 359 sys = tc->getSystemPtr(); 360 for (x = 0; x < sys->numContexts(); x++) { 361 oc = sys->getThreadContext(x); 362 assert(oc->getITBPtr() && oc->getDTBPtr()); 363 oc->getITBPtr()->flushAll(); 364 oc->getDTBPtr()->flushAll(); 365 } 366 return; 367 case MISCREG_ITLBIALL: 368 tc->getITBPtr()->flushAll(); 369 return; 370 case MISCREG_DTLBIALL: 371 tc->getDTBPtr()->flushAll(); 372 return; 373 case MISCREG_TLBIMVAIS: 374 case MISCREG_TLBIMVA: 375 sys = tc->getSystemPtr(); 376 for (x = 0; x < sys->numContexts(); x++) { 377 oc = sys->getThreadContext(x); 378 assert(oc->getITBPtr() && oc->getDTBPtr()); 379 oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 380 bits(newVal, 7,0)); 381 oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 382 bits(newVal, 7,0)); 383 } 384 return; 385 case MISCREG_TLBIASIDIS: 386 case MISCREG_TLBIASID: 387 sys = tc->getSystemPtr(); 388 for (x = 0; x < sys->numContexts(); x++) { 389 oc = sys->getThreadContext(x); 390 assert(oc->getITBPtr() && oc->getDTBPtr()); 391 oc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 392 oc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 393 } 394 return; 395 case MISCREG_TLBIMVAAIS: 396 case MISCREG_TLBIMVAA: 397 sys = tc->getSystemPtr(); 398 for (x = 0; x < sys->numContexts(); x++) { 399 oc = sys->getThreadContext(x); 400 assert(oc->getITBPtr() && oc->getDTBPtr()); 401 oc->getITBPtr()->flushMva(mbits(newVal, 31,12)); 402 oc->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 403 } 404 return; 405 case MISCREG_ITLBIMVA: 406 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 407 bits(newVal, 7,0)); 408 return; 409 case MISCREG_DTLBIMVA: 410 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 411 bits(newVal, 7,0)); 412 return; 413 case MISCREG_ITLBIASID: 414 tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 415 return; 416 case MISCREG_DTLBIASID: 417 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 418 return; 419 case MISCREG_ACTLR: 420 warn("Not doing anything for write of miscreg ACTLR\n"); 421 break; 422 case MISCREG_PMCR: 423 { 424 // Performance counters not implemented. Instead, interpret 425 // a reset command to this register to reset the simulator 426 // statistics. 427 // PMCR_E | PMCR_P | PMCR_C 428 const int ResetAndEnableCounters = 0x7; 429 if (newVal == ResetAndEnableCounters) { 430 inform("Resetting all simobject stats\n"); 431 Stats::schedStatEvent(false, true); 432 break; 433 } 434 } 435 case MISCREG_PMCCNTR: 436 case MISCREG_PMSELR: 437 warn("Not doing anything for write to miscreg %s\n", 438 miscRegName[misc_reg]); 439 break; 440 case MISCREG_V2PCWPR: 441 case MISCREG_V2PCWPW: 442 case MISCREG_V2PCWUR: 443 case MISCREG_V2PCWUW: 444 case MISCREG_V2POWPR: 445 case MISCREG_V2POWPW: 446 case MISCREG_V2POWUR: 447 case MISCREG_V2POWUW: 448 { 449 RequestPtr req = new Request; 450 unsigned flags; 451 BaseTLB::Mode mode; 452 Fault fault; 453 switch(misc_reg) { 454 case MISCREG_V2PCWPR: 455 flags = TLB::MustBeOne; 456 mode = BaseTLB::Read; 457 break; 458 case MISCREG_V2PCWPW: 459 flags = TLB::MustBeOne; 460 mode = BaseTLB::Write; 461 break; 462 case MISCREG_V2PCWUR: 463 flags = TLB::MustBeOne | TLB::UserMode; 464 mode = BaseTLB::Read; 465 break; 466 case MISCREG_V2PCWUW: 467 flags = TLB::MustBeOne | TLB::UserMode; 468 mode = BaseTLB::Write; 469 break; 470 default: 471 panic("Security Extensions not implemented!"); 472 } 473 warn("Translating via MISCREG in atomic mode! Fix Me!\n"); 474 req->setVirt(0, val, 1, flags, tc->pcState().pc()); 475 fault = tc->getDTBPtr()->translateAtomic(req, tc, mode); 476 if (fault == NoFault) { 477 miscRegs[MISCREG_PAR] = 478 (req->getPaddr() & 0xfffff000) | 479 (tc->getDTBPtr()->getAttr() ); 480 DPRINTF(MiscRegs, 481 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 482 val, miscRegs[MISCREG_PAR]); 483 } 484 else { 485 // Set fault bit and FSR 486 FSR fsr = miscRegs[MISCREG_DFSR]; 487 miscRegs[MISCREG_PAR] = 488 (fsr.ext << 6) | 489 (fsr.fsHigh << 5) | 490 (fsr.fsLow << 1) | 491 0x1; // F bit 492 } 493 return; 494 } 495 case MISCREG_CONTEXTIDR: 496 case MISCREG_PRRR: 497 case MISCREG_NMRR: 498 case MISCREG_DACR: 499 tc->getITBPtr()->invalidateMiscReg(); 500 tc->getDTBPtr()->invalidateMiscReg(); 501 break; 502 case MISCREG_CPSR_MODE: 503 // This miscreg is used by copy*Regs to set the CPSR mode 504 // without updating other CPSR variables. It's used to 505 // make sure the register map is in such a state that we can 506 // see all of the registers for the copy. 507 updateRegMap(val); 508 return; 509 } 510 } 511 setMiscRegNoEffect(misc_reg, newVal); 512} 513 514} 515