isa.cc revision 8206:c3090dc00ddf
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 */ 40 41#include "arch/arm/isa.hh" 42#include "sim/faults.hh" 43#include "sim/stat_control.hh" 44 45namespace ArmISA 46{ 47 48void 49ISA::clear() 50{ 51 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 52 53 memset(miscRegs, 0, sizeof(miscRegs)); 54 CPSR cpsr = 0; 55 cpsr.mode = MODE_USER; 56 miscRegs[MISCREG_CPSR] = cpsr; 57 updateRegMap(cpsr); 58 59 SCTLR sctlr = 0; 60 sctlr.te = (bool)sctlr_rst.te; 61 sctlr.nmfi = (bool)sctlr_rst.nmfi; 62 sctlr.v = (bool)sctlr_rst.v; 63 sctlr.u = 1; 64 sctlr.xp = 1; 65 sctlr.rao2 = 1; 66 sctlr.rao3 = 1; 67 sctlr.rao4 = 1; 68 miscRegs[MISCREG_SCTLR] = sctlr; 69 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 70 71 /* Start with an event in the mailbox */ 72 miscRegs[MISCREG_SEV_MAILBOX] = 1; 73 74 /* 75 * Implemented = '5' from "M5", 76 * Variant = 0, 77 */ 78 miscRegs[MISCREG_MIDR] = 79 (0x35 << 24) | // Implementor is '5' from "M5" 80 (0 << 20) | // Variant 81 (0xf << 16) | // Architecture from CPUID scheme 82 (0xf00 << 4) | // Primary part number 83 (0 << 0) | // Revision 84 0; 85 86 // Separate Instruction and Data TLBs. 87 miscRegs[MISCREG_TLBTR] = 1; 88 89 MVFR0 mvfr0 = 0; 90 mvfr0.advSimdRegisters = 2; 91 mvfr0.singlePrecision = 2; 92 mvfr0.doublePrecision = 2; 93 mvfr0.vfpExceptionTrapping = 0; 94 mvfr0.divide = 1; 95 mvfr0.squareRoot = 1; 96 mvfr0.shortVectors = 1; 97 mvfr0.roundingModes = 1; 98 miscRegs[MISCREG_MVFR0] = mvfr0; 99 100 MVFR1 mvfr1 = 0; 101 mvfr1.flushToZero = 1; 102 mvfr1.defaultNaN = 1; 103 mvfr1.advSimdLoadStore = 1; 104 mvfr1.advSimdInteger = 1; 105 mvfr1.advSimdSinglePrecision = 1; 106 mvfr1.advSimdHalfPrecision = 1; 107 mvfr1.vfpHalfPrecision = 1; 108 miscRegs[MISCREG_MVFR1] = mvfr1; 109 110 miscRegs[MISCREG_MPIDR] = 0; 111 112 // Reset values of PRRR and NMRR are implementation dependent 113 114 miscRegs[MISCREG_PRRR] = 115 (1 << 19) | // 19 116 (0 << 18) | // 18 117 (0 << 17) | // 17 118 (1 << 16) | // 16 119 (2 << 14) | // 15:14 120 (0 << 12) | // 13:12 121 (2 << 10) | // 11:10 122 (2 << 8) | // 9:8 123 (2 << 6) | // 7:6 124 (2 << 4) | // 5:4 125 (1 << 2) | // 3:2 126 0; // 1:0 127 miscRegs[MISCREG_NMRR] = 128 (1 << 30) | // 31:30 129 (0 << 26) | // 27:26 130 (0 << 24) | // 25:24 131 (3 << 22) | // 23:22 132 (2 << 20) | // 21:20 133 (0 << 18) | // 19:18 134 (0 << 16) | // 17:16 135 (1 << 14) | // 15:14 136 (0 << 12) | // 13:12 137 (2 << 10) | // 11:10 138 (0 << 8) | // 9:8 139 (3 << 6) | // 7:6 140 (2 << 4) | // 5:4 141 (0 << 2) | // 3:2 142 0; // 1:0 143 144 miscRegs[MISCREG_CPACR] = 0; 145 miscRegs[MISCREG_FPSID] = 0x410430A0; 146 147 // See section B4.1.84 of ARM ARM 148 // All values are latest for ARMv7-A profile 149 miscRegs[MISCREG_ID_ISAR0] = 0x01101111; 150 miscRegs[MISCREG_ID_ISAR1] = 0x02112111; 151 miscRegs[MISCREG_ID_ISAR2] = 0x21232141; 152 miscRegs[MISCREG_ID_ISAR3] = 0x01112131; 153 miscRegs[MISCREG_ID_ISAR4] = 0x10010142; 154 miscRegs[MISCREG_ID_ISAR5] = 0x00000000; 155 156 //XXX We need to initialize the rest of the state. 157} 158 159MiscReg 160ISA::readMiscRegNoEffect(int misc_reg) 161{ 162 assert(misc_reg < NumMiscRegs); 163 164 int flat_idx; 165 if (misc_reg == MISCREG_SPSR) 166 flat_idx = flattenMiscIndex(misc_reg); 167 else 168 flat_idx = misc_reg; 169 MiscReg val = miscRegs[flat_idx]; 170 171 DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n", 172 misc_reg, flat_idx, val); 173 return val; 174} 175 176 177MiscReg 178ISA::readMiscReg(int misc_reg, ThreadContext *tc) 179{ 180 if (misc_reg == MISCREG_CPSR) { 181 CPSR cpsr = miscRegs[misc_reg]; 182 PCState pc = tc->pcState(); 183 cpsr.j = pc.jazelle() ? 1 : 0; 184 cpsr.t = pc.thumb() ? 1 : 0; 185 return cpsr; 186 } 187 if (misc_reg >= MISCREG_CP15_UNIMP_START) 188 panic("Unimplemented CP15 register %s read.\n", 189 miscRegName[misc_reg]); 190 191 switch (misc_reg) { 192 case MISCREG_CLIDR: 193 warn_once("The clidr register always reports 0 caches.\n"); 194 break; 195 case MISCREG_CCSIDR: 196 warn_once("The ccsidr register isn't implemented and " 197 "always reads as 0.\n"); 198 break; 199 case MISCREG_ID_PFR0: 200 warn("Returning thumbEE disabled for now since we don't support CP14" 201 "config registers and jumping to ThumbEE vectors\n"); 202 return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM 203 case MISCREG_ID_MMFR0: 204 return 0x03; //VMSAz7 205 case MISCREG_CTR: 206 return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact 207 case MISCREG_ACTLR: 208 warn("Not doing anything for miscreg ACTLR\n"); 209 break; 210 case MISCREG_PMCR: 211 case MISCREG_PMCCNTR: 212 case MISCREG_PMSELR: 213 warn("Not doing anyhting for read to miscreg %s\n", 214 miscRegName[misc_reg]); 215 break; 216 case MISCREG_FPSCR_QC: 217 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 218 case MISCREG_FPSCR_EXC: 219 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 220 } 221 return readMiscRegNoEffect(misc_reg); 222} 223 224void 225ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 226{ 227 assert(misc_reg < NumMiscRegs); 228 229 int flat_idx; 230 if (misc_reg == MISCREG_SPSR) 231 flat_idx = flattenMiscIndex(misc_reg); 232 else 233 flat_idx = misc_reg; 234 miscRegs[flat_idx] = val; 235 236 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg, 237 flat_idx, val); 238} 239 240void 241ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 242{ 243 244 MiscReg newVal = val; 245 if (misc_reg == MISCREG_CPSR) { 246 updateRegMap(val); 247 248 249 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 250 int old_mode = old_cpsr.mode; 251 CPSR cpsr = val; 252 if (old_mode != cpsr.mode) { 253 tc->getITBPtr()->invalidateMiscReg(); 254 tc->getDTBPtr()->invalidateMiscReg(); 255 } 256 257 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 258 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 259 PCState pc = tc->pcState(); 260 pc.nextThumb(cpsr.t); 261 pc.nextJazelle(cpsr.j); 262 tc->pcState(pc); 263 } else if (misc_reg >= MISCREG_CP15_UNIMP_START && 264 misc_reg < MISCREG_CP15_END) { 265 panic("Unimplemented CP15 register %s wrote with %#x.\n", 266 miscRegName[misc_reg], val); 267 } else { 268 switch (misc_reg) { 269 case MISCREG_CPACR: 270 { 271 272 const uint32_t ones = (uint32_t)(-1); 273 CPACR cpacrMask = 0; 274 // Only cp10, cp11, and ase are implemented, nothing else should 275 // be writable 276 cpacrMask.cp10 = ones; 277 cpacrMask.cp11 = ones; 278 cpacrMask.asedis = ones; 279 newVal &= cpacrMask; 280 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 281 miscRegName[misc_reg], newVal); 282 } 283 break; 284 case MISCREG_CSSELR: 285 warn_once("The csselr register isn't implemented.\n"); 286 return; 287 case MISCREG_FPSCR: 288 { 289 const uint32_t ones = (uint32_t)(-1); 290 FPSCR fpscrMask = 0; 291 fpscrMask.ioc = ones; 292 fpscrMask.dzc = ones; 293 fpscrMask.ofc = ones; 294 fpscrMask.ufc = ones; 295 fpscrMask.ixc = ones; 296 fpscrMask.idc = ones; 297 fpscrMask.len = ones; 298 fpscrMask.stride = ones; 299 fpscrMask.rMode = ones; 300 fpscrMask.fz = ones; 301 fpscrMask.dn = ones; 302 fpscrMask.ahp = ones; 303 fpscrMask.qc = ones; 304 fpscrMask.v = ones; 305 fpscrMask.c = ones; 306 fpscrMask.z = ones; 307 fpscrMask.n = ones; 308 newVal = (newVal & (uint32_t)fpscrMask) | 309 (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask); 310 } 311 break; 312 case MISCREG_FPSCR_QC: 313 { 314 newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrQcMask); 315 misc_reg = MISCREG_FPSCR; 316 } 317 break; 318 case MISCREG_FPSCR_EXC: 319 { 320 newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrExcMask); 321 misc_reg = MISCREG_FPSCR; 322 } 323 break; 324 case MISCREG_FPEXC: 325 { 326 // vfpv3 architecture, section B.6.1 of DDI04068 327 // bit 29 - valid only if fpexc[31] is 0 328 const uint32_t fpexcMask = 0x60000000; 329 newVal = (newVal & fpexcMask) | 330 (miscRegs[MISCREG_FPEXC] & ~fpexcMask); 331 } 332 break; 333 case MISCREG_SCTLR: 334 { 335 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 336 SCTLR sctlr = miscRegs[MISCREG_SCTLR]; 337 SCTLR new_sctlr = newVal; 338 new_sctlr.nmfi = (bool)sctlr.nmfi; 339 miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr; 340 tc->getITBPtr()->invalidateMiscReg(); 341 tc->getDTBPtr()->invalidateMiscReg(); 342 return; 343 } 344 case MISCREG_TLBTR: 345 case MISCREG_MVFR0: 346 case MISCREG_MVFR1: 347 case MISCREG_MPIDR: 348 case MISCREG_FPSID: 349 return; 350 case MISCREG_TLBIALLIS: 351 case MISCREG_TLBIALL: 352 warn_once("Need to flush all TLBs in MP\n"); 353 tc->getITBPtr()->flushAll(); 354 tc->getDTBPtr()->flushAll(); 355 return; 356 case MISCREG_ITLBIALL: 357 tc->getITBPtr()->flushAll(); 358 return; 359 case MISCREG_DTLBIALL: 360 tc->getDTBPtr()->flushAll(); 361 return; 362 case MISCREG_TLBIMVAIS: 363 case MISCREG_TLBIMVA: 364 warn_once("Need to flush all TLBs in MP\n"); 365 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 366 bits(newVal, 7,0)); 367 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 368 bits(newVal, 7,0)); 369 return; 370 case MISCREG_TLBIASIDIS: 371 case MISCREG_TLBIASID: 372 warn_once("Need to flush all TLBs in MP\n"); 373 tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 374 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 375 return; 376 case MISCREG_TLBIMVAAIS: 377 case MISCREG_TLBIMVAA: 378 warn_once("Need to flush all TLBs in MP\n"); 379 tc->getITBPtr()->flushMva(mbits(newVal, 31,12)); 380 tc->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 381 return; 382 case MISCREG_ITLBIMVA: 383 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 384 bits(newVal, 7,0)); 385 return; 386 case MISCREG_DTLBIMVA: 387 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 388 bits(newVal, 7,0)); 389 return; 390 case MISCREG_ITLBIASID: 391 tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 392 return; 393 case MISCREG_DTLBIASID: 394 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 395 return; 396 case MISCREG_ACTLR: 397 warn("Not doing anything for write of miscreg ACTLR\n"); 398 break; 399 case MISCREG_PMCR: 400 { 401 // Performance counters not implemented. Instead, interpret 402 // a reset command to this register to reset the simulator 403 // statistics. 404 // PMCR_E | PMCR_P | PMCR_C 405 const int ResetAndEnableCounters = 0x7; 406 if (newVal == ResetAndEnableCounters) { 407 inform("Resetting all simobject stats\n"); 408 Stats::schedStatEvent(false, true); 409 break; 410 } 411 } 412 case MISCREG_PMCCNTR: 413 case MISCREG_PMSELR: 414 warn("Not doing anything for write to miscreg %s\n", 415 miscRegName[misc_reg]); 416 break; 417 case MISCREG_V2PCWPR: 418 case MISCREG_V2PCWPW: 419 case MISCREG_V2PCWUR: 420 case MISCREG_V2PCWUW: 421 case MISCREG_V2POWPR: 422 case MISCREG_V2POWPW: 423 case MISCREG_V2POWUR: 424 case MISCREG_V2POWUW: 425 { 426 RequestPtr req = new Request; 427 unsigned flags; 428 BaseTLB::Mode mode; 429 Fault fault; 430 switch(misc_reg) { 431 case MISCREG_V2PCWPR: 432 flags = TLB::MustBeOne; 433 mode = BaseTLB::Read; 434 break; 435 case MISCREG_V2PCWPW: 436 flags = TLB::MustBeOne; 437 mode = BaseTLB::Write; 438 break; 439 case MISCREG_V2PCWUR: 440 flags = TLB::MustBeOne | TLB::UserMode; 441 mode = BaseTLB::Read; 442 break; 443 case MISCREG_V2PCWUW: 444 flags = TLB::MustBeOne | TLB::UserMode; 445 mode = BaseTLB::Write; 446 break; 447 default: 448 panic("Security Extensions not implemented!"); 449 } 450 req->setVirt(0, val, 1, flags, tc->pcState().pc()); 451 fault = tc->getDTBPtr()->translateAtomic(req, tc, mode); 452 if (fault == NoFault) { 453 miscRegs[MISCREG_PAR] = 454 (req->getPaddr() & 0xfffff000) | 455 (tc->getDTBPtr()->getAttr() ); 456 DPRINTF(MiscRegs, 457 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 458 val, miscRegs[MISCREG_PAR]); 459 } 460 else { 461 // Set fault bit and FSR 462 FSR fsr = miscRegs[MISCREG_DFSR]; 463 miscRegs[MISCREG_PAR] = 464 (fsr.ext << 6) | 465 (fsr.fsHigh << 5) | 466 (fsr.fsLow << 1) | 467 0x1; // F bit 468 } 469 return; 470 } 471 case MISCREG_CONTEXTIDR: 472 case MISCREG_PRRR: 473 case MISCREG_NMRR: 474 case MISCREG_DACR: 475 tc->getITBPtr()->invalidateMiscReg(); 476 tc->getDTBPtr()->invalidateMiscReg(); 477 break; 478 479 } 480 } 481 setMiscRegNoEffect(misc_reg, newVal); 482} 483 484} 485