isa.cc revision 7731:e1eace3a118a
111106Spower.jg@gmail.com/* 211106Spower.jg@gmail.com * Copyright (c) 2010 ARM Limited 311106Spower.jg@gmail.com * All rights reserved 411106Spower.jg@gmail.com * 511106Spower.jg@gmail.com * The license below extends only to copyright in the software and shall 611106Spower.jg@gmail.com * not be construed as granting a license to any other intellectual 711106Spower.jg@gmail.com * property including but not limited to intellectual property relating 811106Spower.jg@gmail.com * to a hardware implementation of the functionality of the software 911106Spower.jg@gmail.com * licensed hereunder. You may use the software subject to the license 1011106Spower.jg@gmail.com * terms below provided that you ensure that this notice is replicated 1111106Spower.jg@gmail.com * unmodified and in its entirety in all distributions of the software, 1211106Spower.jg@gmail.com * modified or unmodified, in source code or in binary form. 1311106Spower.jg@gmail.com * 1411106Spower.jg@gmail.com * Redistribution and use in source and binary forms, with or without 1511106Spower.jg@gmail.com * modification, are permitted provided that the following conditions are 1611106Spower.jg@gmail.com * met: redistributions of source code must retain the above copyright 1711570SCurtis.Dunham@arm.com * notice, this list of conditions and the following disclaimer; 1811106Spower.jg@gmail.com * redistributions in binary form must reproduce the above copyright 1911312Santhony.gutierrez@amd.com * notice, this list of conditions and the following disclaimer in the 2011106Spower.jg@gmail.com * documentation and/or other materials provided with the distribution; 2111106Spower.jg@gmail.com * neither the name of the copyright holders nor the names of its 2211106Spower.jg@gmail.com * contributors may be used to endorse or promote products derived from 2311960Sgabeblack@google.com * this software without specific prior written permission. 2411106Spower.jg@gmail.com * 2511106Spower.jg@gmail.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2611106Spower.jg@gmail.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2711680SCurtis.Dunham@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2811106Spower.jg@gmail.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2911106Spower.jg@gmail.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3011219Snilay@cs.wisc.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3111106Spower.jg@gmail.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3211570SCurtis.Dunham@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3311570SCurtis.Dunham@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3411570SCurtis.Dunham@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3511570SCurtis.Dunham@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3611106Spower.jg@gmail.com * 3711106Spower.jg@gmail.com * Authors: Gabe Black 3811440SCurtis.Dunham@arm.com * Ali Saidi 3911440SCurtis.Dunham@arm.com */ 4011106Spower.jg@gmail.com 4111106Spower.jg@gmail.com#include "arch/arm/isa.hh" 4211106Spower.jg@gmail.com#include "sim/faults.hh" 4311106Spower.jg@gmail.com 4411106Spower.jg@gmail.comnamespace ArmISA 4511106Spower.jg@gmail.com{ 4611106Spower.jg@gmail.com 4711106Spower.jg@gmail.comvoid 4811106Spower.jg@gmail.comISA::clear() 4911106Spower.jg@gmail.com{ 5011106Spower.jg@gmail.com SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 5111106Spower.jg@gmail.com 5211106Spower.jg@gmail.com memset(miscRegs, 0, sizeof(miscRegs)); 5311106Spower.jg@gmail.com CPSR cpsr = 0; 5411106Spower.jg@gmail.com cpsr.mode = MODE_USER; 5511106Spower.jg@gmail.com miscRegs[MISCREG_CPSR] = cpsr; 5611106Spower.jg@gmail.com updateRegMap(cpsr); 5711106Spower.jg@gmail.com 5811106Spower.jg@gmail.com SCTLR sctlr = 0; 5911106Spower.jg@gmail.com sctlr.te = (bool)sctlr_rst.te; 6011106Spower.jg@gmail.com sctlr.nmfi = (bool)sctlr_rst.nmfi; 6111106Spower.jg@gmail.com sctlr.v = (bool)sctlr_rst.v; 6211106Spower.jg@gmail.com sctlr.u = 1; 6311106Spower.jg@gmail.com sctlr.xp = 1; 6411106Spower.jg@gmail.com sctlr.rao2 = 1; 6511106Spower.jg@gmail.com sctlr.rao3 = 1; 6611106Spower.jg@gmail.com sctlr.rao4 = 1; 6711106Spower.jg@gmail.com miscRegs[MISCREG_SCTLR] = sctlr; 6811106Spower.jg@gmail.com miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 6911106Spower.jg@gmail.com 7011570SCurtis.Dunham@arm.com /* Start with an event in the mailbox */ 7111106Spower.jg@gmail.com miscRegs[MISCREG_SEV_MAILBOX] = 1; 7211106Spower.jg@gmail.com 7311106Spower.jg@gmail.com /* 7411106Spower.jg@gmail.com * Implemented = '5' from "M5", 7511106Spower.jg@gmail.com * Variant = 0, 7611106Spower.jg@gmail.com */ 7711106Spower.jg@gmail.com miscRegs[MISCREG_MIDR] = 7811106Spower.jg@gmail.com (0x35 << 24) | // Implementor is '5' from "M5" 7911106Spower.jg@gmail.com (0 << 20) | // Variant 8011106Spower.jg@gmail.com (0xf << 16) | // Architecture from CPUID scheme 8111106Spower.jg@gmail.com (0xf00 << 4) | // Primary part number 8211106Spower.jg@gmail.com (0 << 0) | // Revision 8311106Spower.jg@gmail.com 0; 8411106Spower.jg@gmail.com 8511106Spower.jg@gmail.com // Separate Instruction and Data TLBs. 8611570SCurtis.Dunham@arm.com miscRegs[MISCREG_TLBTR] = 1; 8711570SCurtis.Dunham@arm.com 8811570SCurtis.Dunham@arm.com MVFR0 mvfr0 = 0; 8911570SCurtis.Dunham@arm.com mvfr0.advSimdRegisters = 2; 9011106Spower.jg@gmail.com mvfr0.singlePrecision = 2; 9111106Spower.jg@gmail.com mvfr0.doublePrecision = 2; 9211106Spower.jg@gmail.com mvfr0.vfpExceptionTrapping = 0; 9311106Spower.jg@gmail.com mvfr0.divide = 1; 9411106Spower.jg@gmail.com mvfr0.squareRoot = 1; 9511960Sgabeblack@google.com mvfr0.shortVectors = 1; 9611106Spower.jg@gmail.com mvfr0.roundingModes = 1; 9711106Spower.jg@gmail.com miscRegs[MISCREG_MVFR0] = mvfr0; 9811106Spower.jg@gmail.com 9911106Spower.jg@gmail.com MVFR1 mvfr1 = 0; 10011106Spower.jg@gmail.com mvfr1.flushToZero = 1; 10111106Spower.jg@gmail.com mvfr1.defaultNaN = 1; 10211106Spower.jg@gmail.com mvfr1.advSimdLoadStore = 1; 10311106Spower.jg@gmail.com mvfr1.advSimdInteger = 1; 10411106Spower.jg@gmail.com mvfr1.advSimdSinglePrecision = 1; 10511106Spower.jg@gmail.com mvfr1.advSimdHalfPrecision = 1; 10611106Spower.jg@gmail.com mvfr1.vfpHalfPrecision = 1; 10711106Spower.jg@gmail.com miscRegs[MISCREG_MVFR1] = mvfr1; 10811106Spower.jg@gmail.com 10911106Spower.jg@gmail.com miscRegs[MISCREG_MPIDR] = 0; 11011106Spower.jg@gmail.com 11111106Spower.jg@gmail.com // Reset values of PRRR and NMRR are implementation dependent 11211106Spower.jg@gmail.com 11311106Spower.jg@gmail.com miscRegs[MISCREG_PRRR] = 11411106Spower.jg@gmail.com (1 << 19) | // 19 11511106Spower.jg@gmail.com (0 << 18) | // 18 11611106Spower.jg@gmail.com (0 << 17) | // 17 11711106Spower.jg@gmail.com (1 << 16) | // 16 11811570SCurtis.Dunham@arm.com (2 << 14) | // 15:14 11911106Spower.jg@gmail.com (0 << 12) | // 13:12 12011106Spower.jg@gmail.com (2 << 10) | // 11:10 12111570SCurtis.Dunham@arm.com (2 << 8) | // 9:8 12211570SCurtis.Dunham@arm.com (2 << 6) | // 7:6 12311570SCurtis.Dunham@arm.com (2 << 4) | // 5:4 12411570SCurtis.Dunham@arm.com (1 << 2) | // 3:2 12511106Spower.jg@gmail.com 0; // 1:0 12611106Spower.jg@gmail.com miscRegs[MISCREG_NMRR] = 12711106Spower.jg@gmail.com (1 << 30) | // 31:30 12811106Spower.jg@gmail.com (0 << 26) | // 27:26 12911106Spower.jg@gmail.com (0 << 24) | // 25:24 13011570SCurtis.Dunham@arm.com (3 << 22) | // 23:22 13111106Spower.jg@gmail.com (2 << 20) | // 21:20 13211106Spower.jg@gmail.com (0 << 18) | // 19:18 13311570SCurtis.Dunham@arm.com (0 << 16) | // 17:16 13411570SCurtis.Dunham@arm.com (1 << 14) | // 15:14 13511570SCurtis.Dunham@arm.com (0 << 12) | // 13:12 13611106Spower.jg@gmail.com (2 << 10) | // 11:10 13711106Spower.jg@gmail.com (0 << 8) | // 9:8 13811570SCurtis.Dunham@arm.com (3 << 6) | // 7:6 13911106Spower.jg@gmail.com (2 << 4) | // 5:4 14011106Spower.jg@gmail.com (0 << 2) | // 3:2 14111106Spower.jg@gmail.com 0; // 1:0 14211106Spower.jg@gmail.com 14311106Spower.jg@gmail.com miscRegs[MISCREG_CPACR] = 0; 14411106Spower.jg@gmail.com miscRegs[MISCREG_FPSID] = 0x410430A0; 14511106Spower.jg@gmail.com //XXX We need to initialize the rest of the state. 14611106Spower.jg@gmail.com} 14711106Spower.jg@gmail.com 14811106Spower.jg@gmail.comMiscReg 14911106Spower.jg@gmail.comISA::readMiscRegNoEffect(int misc_reg) 15011106Spower.jg@gmail.com{ 15111106Spower.jg@gmail.com assert(misc_reg < NumMiscRegs); 15211106Spower.jg@gmail.com 15311106Spower.jg@gmail.com int flat_idx; 15411106Spower.jg@gmail.com if (misc_reg == MISCREG_SPSR) 15511106Spower.jg@gmail.com flat_idx = flattenMiscIndex(misc_reg); 15611106Spower.jg@gmail.com else 15711106Spower.jg@gmail.com flat_idx = misc_reg; 15811570SCurtis.Dunham@arm.com MiscReg val = miscRegs[flat_idx]; 15911106Spower.jg@gmail.com 16011106Spower.jg@gmail.com DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n", 16111570SCurtis.Dunham@arm.com misc_reg, flat_idx, val); 16211570SCurtis.Dunham@arm.com return val; 16311570SCurtis.Dunham@arm.com} 16411570SCurtis.Dunham@arm.com 16511106Spower.jg@gmail.com 16611106Spower.jg@gmail.comMiscReg 16711106Spower.jg@gmail.comISA::readMiscReg(int misc_reg, ThreadContext *tc) 16811106Spower.jg@gmail.com{ 16911106Spower.jg@gmail.com if (misc_reg == MISCREG_CPSR) { 17011106Spower.jg@gmail.com CPSR cpsr = miscRegs[misc_reg]; 17111106Spower.jg@gmail.com PCState pc = tc->pcState(); 17211960Sgabeblack@google.com cpsr.j = pc.jazelle() ? 1 : 0; 17311106Spower.jg@gmail.com cpsr.t = pc.thumb() ? 1 : 0; 17411106Spower.jg@gmail.com return cpsr; 17511106Spower.jg@gmail.com } 17611106Spower.jg@gmail.com if (misc_reg >= MISCREG_CP15_UNIMP_START && 17711106Spower.jg@gmail.com misc_reg < MISCREG_CP15_END) { 17811106Spower.jg@gmail.com panic("Unimplemented CP15 register %s read.\n", 17911106Spower.jg@gmail.com miscRegName[misc_reg]); 18011106Spower.jg@gmail.com } 18111106Spower.jg@gmail.com switch (misc_reg) { 18211106Spower.jg@gmail.com case MISCREG_CLIDR: 18311106Spower.jg@gmail.com warn_once("The clidr register always reports 0 caches.\n"); 18411106Spower.jg@gmail.com break; 18511960Sgabeblack@google.com case MISCREG_CCSIDR: 18611106Spower.jg@gmail.com warn_once("The ccsidr register isn't implemented and " 18711960Sgabeblack@google.com "always reads as 0.\n"); 18811106Spower.jg@gmail.com break; 18911960Sgabeblack@google.com case MISCREG_ID_PFR0: 19011106Spower.jg@gmail.com warn("Returning thumbEE disabled for now since we don't support CP14" 19111106Spower.jg@gmail.com "config registers and jumping to ThumbEE vectors\n"); 19211106Spower.jg@gmail.com return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM 19311106Spower.jg@gmail.com case MISCREG_ID_MMFR0: 19411106Spower.jg@gmail.com return 0x03; //VMSAz7 19511106Spower.jg@gmail.com case MISCREG_CTR: 19611106Spower.jg@gmail.com return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact 19711106Spower.jg@gmail.com case MISCREG_ACTLR: 19811106Spower.jg@gmail.com warn("Not doing anything for miscreg ACTLR\n"); 19911106Spower.jg@gmail.com break; 20011106Spower.jg@gmail.com case MISCREG_PMCR: 20111106Spower.jg@gmail.com case MISCREG_PMCCNTR: 20211106Spower.jg@gmail.com case MISCREG_PMSELR: 20311106Spower.jg@gmail.com warn("Not doing anyhting for read to miscreg %s\n", 20411106Spower.jg@gmail.com miscRegName[misc_reg]); 20511680SCurtis.Dunham@arm.com break; 20611106Spower.jg@gmail.com 20711680SCurtis.Dunham@arm.com } 20811106Spower.jg@gmail.com return readMiscRegNoEffect(misc_reg); 20911106Spower.jg@gmail.com} 21011106Spower.jg@gmail.com 21111680SCurtis.Dunham@arm.comvoid 21211106Spower.jg@gmail.comISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 21311680SCurtis.Dunham@arm.com{ 21411106Spower.jg@gmail.com assert(misc_reg < NumMiscRegs); 21511106Spower.jg@gmail.com 21611106Spower.jg@gmail.com int flat_idx; 21711680SCurtis.Dunham@arm.com if (misc_reg == MISCREG_SPSR) 21811106Spower.jg@gmail.com flat_idx = flattenMiscIndex(misc_reg); 21911680SCurtis.Dunham@arm.com else 22011106Spower.jg@gmail.com flat_idx = misc_reg; 22111680SCurtis.Dunham@arm.com miscRegs[flat_idx] = val; 22211106Spower.jg@gmail.com 22311680SCurtis.Dunham@arm.com DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg, 22411106Spower.jg@gmail.com flat_idx, val); 22511680SCurtis.Dunham@arm.com} 22611106Spower.jg@gmail.com 22711106Spower.jg@gmail.comvoid 22811106Spower.jg@gmail.comISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 22911106Spower.jg@gmail.com{ 23011106Spower.jg@gmail.com MiscReg newVal = val; 23111106Spower.jg@gmail.com if (misc_reg == MISCREG_CPSR) { 23211106Spower.jg@gmail.com updateRegMap(val); 23311106Spower.jg@gmail.com CPSR cpsr = val; 23411106Spower.jg@gmail.com DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 23511106Spower.jg@gmail.com miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 23611106Spower.jg@gmail.com PCState pc = tc->pcState(); 23711570SCurtis.Dunham@arm.com pc.nextThumb(cpsr.t); 23811106Spower.jg@gmail.com pc.nextJazelle(cpsr.j); 23911106Spower.jg@gmail.com tc->pcState(pc); 24011106Spower.jg@gmail.com } else if (misc_reg >= MISCREG_CP15_UNIMP_START && 24111106Spower.jg@gmail.com misc_reg < MISCREG_CP15_END) { 24211106Spower.jg@gmail.com panic("Unimplemented CP15 register %s wrote with %#x.\n", 24311106Spower.jg@gmail.com miscRegName[misc_reg], val); 24411106Spower.jg@gmail.com } else { 24511680SCurtis.Dunham@arm.com switch (misc_reg) { 24611106Spower.jg@gmail.com case MISCREG_ITSTATE: 24711106Spower.jg@gmail.com { 24811106Spower.jg@gmail.com ITSTATE itstate = newVal; 24911106Spower.jg@gmail.com CPSR cpsr = miscRegs[MISCREG_CPSR]; 25011570SCurtis.Dunham@arm.com cpsr.it1 = itstate.bottom2; 25111570SCurtis.Dunham@arm.com cpsr.it2 = itstate.top6; 25211570SCurtis.Dunham@arm.com miscRegs[MISCREG_CPSR] = cpsr; 25311106Spower.jg@gmail.com DPRINTF(MiscRegs, 25411570SCurtis.Dunham@arm.com "Updating ITSTATE -> %#x in CPSR -> %#x.\n", 25511680SCurtis.Dunham@arm.com (uint8_t)itstate, (uint32_t)cpsr); 25611106Spower.jg@gmail.com } 25711106Spower.jg@gmail.com break; 25811106Spower.jg@gmail.com case MISCREG_CPACR: 25911106Spower.jg@gmail.com { 26011106Spower.jg@gmail.com CPACR newCpacr = 0; 26111106Spower.jg@gmail.com CPACR valCpacr = val; 26211106Spower.jg@gmail.com newCpacr.cp10 = valCpacr.cp10; 26311106Spower.jg@gmail.com newCpacr.cp11 = valCpacr.cp11; 26411106Spower.jg@gmail.com //XXX d32dis isn't implemented. The manual says whether or not 26511106Spower.jg@gmail.com //it works is implementation defined. 26611106Spower.jg@gmail.com newCpacr.asedis = valCpacr.asedis; 26711106Spower.jg@gmail.com newVal = newCpacr; 26811106Spower.jg@gmail.com } 26911106Spower.jg@gmail.com break; 27011106Spower.jg@gmail.com case MISCREG_CSSELR: 27111106Spower.jg@gmail.com warn_once("The csselr register isn't implemented.\n"); 27211106Spower.jg@gmail.com break; 27311106Spower.jg@gmail.com case MISCREG_FPSCR: 27411106Spower.jg@gmail.com { 27511106Spower.jg@gmail.com const uint32_t ones = (uint32_t)(-1); 27611106Spower.jg@gmail.com FPSCR fpscrMask = 0; 27711680SCurtis.Dunham@arm.com fpscrMask.ioc = ones; 27811106Spower.jg@gmail.com fpscrMask.dzc = ones; 27911680SCurtis.Dunham@arm.com fpscrMask.ofc = ones; 28011106Spower.jg@gmail.com fpscrMask.ufc = ones; 28111106Spower.jg@gmail.com fpscrMask.ixc = ones; 28211106Spower.jg@gmail.com fpscrMask.idc = ones; 28311106Spower.jg@gmail.com fpscrMask.len = ones; 28411106Spower.jg@gmail.com fpscrMask.stride = ones; 28511106Spower.jg@gmail.com fpscrMask.rMode = ones; 28611106Spower.jg@gmail.com fpscrMask.fz = ones; 28711106Spower.jg@gmail.com fpscrMask.dn = ones; 28811680SCurtis.Dunham@arm.com fpscrMask.ahp = ones; 28911106Spower.jg@gmail.com fpscrMask.qc = ones; 29011570SCurtis.Dunham@arm.com fpscrMask.v = ones; 29111106Spower.jg@gmail.com fpscrMask.c = ones; 29211106Spower.jg@gmail.com fpscrMask.z = ones; 29311106Spower.jg@gmail.com fpscrMask.n = ones; 29411570SCurtis.Dunham@arm.com newVal = (newVal & (uint32_t)fpscrMask) | 29511570SCurtis.Dunham@arm.com (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask); 29611570SCurtis.Dunham@arm.com } 29711440SCurtis.Dunham@arm.com break; 29811570SCurtis.Dunham@arm.com case MISCREG_FPEXC: 29911106Spower.jg@gmail.com { 30011680SCurtis.Dunham@arm.com const uint32_t fpexcMask = 0x60000000; 30111106Spower.jg@gmail.com newVal = (newVal & fpexcMask) | 30211106Spower.jg@gmail.com (miscRegs[MISCREG_FPEXC] & ~fpexcMask); 30311106Spower.jg@gmail.com } 30411106Spower.jg@gmail.com break; 30511106Spower.jg@gmail.com case MISCREG_SCTLR: 30611106Spower.jg@gmail.com { 30711106Spower.jg@gmail.com DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 30811680SCurtis.Dunham@arm.com SCTLR sctlr = miscRegs[MISCREG_SCTLR]; 30911680SCurtis.Dunham@arm.com SCTLR new_sctlr = newVal; 31011680SCurtis.Dunham@arm.com new_sctlr.nmfi = (bool)sctlr.nmfi; 31111680SCurtis.Dunham@arm.com miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr; 31211680SCurtis.Dunham@arm.com return; 31311680SCurtis.Dunham@arm.com } 31411680SCurtis.Dunham@arm.com case MISCREG_TLBTR: 315 case MISCREG_MVFR0: 316 case MISCREG_MVFR1: 317 case MISCREG_MPIDR: 318 case MISCREG_FPSID: 319 return; 320 case MISCREG_TLBIALLIS: 321 case MISCREG_TLBIALL: 322 warn_once("Need to flush all TLBs in MP\n"); 323 tc->getITBPtr()->flushAll(); 324 tc->getDTBPtr()->flushAll(); 325 return; 326 case MISCREG_ITLBIALL: 327 tc->getITBPtr()->flushAll(); 328 return; 329 case MISCREG_DTLBIALL: 330 tc->getDTBPtr()->flushAll(); 331 return; 332 case MISCREG_TLBIMVAIS: 333 case MISCREG_TLBIMVA: 334 warn_once("Need to flush all TLBs in MP\n"); 335 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 336 bits(newVal, 7,0)); 337 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 338 bits(newVal, 7,0)); 339 return; 340 case MISCREG_TLBIASIDIS: 341 case MISCREG_TLBIASID: 342 warn_once("Need to flush all TLBs in MP\n"); 343 tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 344 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 345 return; 346 case MISCREG_TLBIMVAAIS: 347 case MISCREG_TLBIMVAA: 348 warn_once("Need to flush all TLBs in MP\n"); 349 tc->getITBPtr()->flushMva(mbits(newVal, 31,12)); 350 tc->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 351 return; 352 case MISCREG_ITLBIMVA: 353 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 354 bits(newVal, 7,0)); 355 return; 356 case MISCREG_DTLBIMVA: 357 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 358 bits(newVal, 7,0)); 359 return; 360 case MISCREG_ITLBIASID: 361 tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 362 return; 363 case MISCREG_DTLBIASID: 364 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 365 return; 366 case MISCREG_ACTLR: 367 warn("Not doing anything for write of miscreg ACTLR\n"); 368 break; 369 case MISCREG_PMCR: 370 case MISCREG_PMCCNTR: 371 case MISCREG_PMSELR: 372 warn("Not doing anything for write to miscreg %s\n", 373 miscRegName[misc_reg]); 374 break; 375 case MISCREG_V2PCWPR: 376 case MISCREG_V2PCWPW: 377 case MISCREG_V2PCWUR: 378 case MISCREG_V2PCWUW: 379 case MISCREG_V2POWPR: 380 case MISCREG_V2POWPW: 381 case MISCREG_V2POWUR: 382 case MISCREG_V2POWUW: 383 { 384 RequestPtr req = new Request; 385 unsigned flags; 386 BaseTLB::Mode mode; 387 Fault fault; 388 switch(misc_reg) { 389 case MISCREG_V2PCWPR: 390 flags = TLB::MustBeOne; 391 mode = BaseTLB::Read; 392 break; 393 case MISCREG_V2PCWPW: 394 flags = TLB::MustBeOne; 395 mode = BaseTLB::Write; 396 break; 397 case MISCREG_V2PCWUR: 398 flags = TLB::MustBeOne | TLB::UserMode; 399 mode = BaseTLB::Read; 400 break; 401 case MISCREG_V2PCWUW: 402 flags = TLB::MustBeOne | TLB::UserMode; 403 mode = BaseTLB::Write; 404 break; 405 default: 406 panic("Security Extensions not implemented!"); 407 } 408 req->setVirt(0, val, 1, flags, tc->pcState().pc()); 409 fault = tc->getDTBPtr()->translateAtomic(req, tc, mode); 410 if (fault == NoFault) { 411 miscRegs[MISCREG_PAR] = 412 (req->getPaddr() & 0xfffff000) | 413 (tc->getDTBPtr()->getAttr() ); 414 DPRINTF(MiscRegs, 415 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 416 val, miscRegs[MISCREG_PAR]); 417 } 418 else { 419 // Set fault bit and FSR 420 FSR fsr = miscRegs[MISCREG_DFSR]; 421 miscRegs[MISCREG_PAR] = 422 (fsr.ext << 6) | 423 (fsr.fsHigh << 5) | 424 (fsr.fsLow << 1) | 425 0x1; // F bit 426 } 427 return; 428 } 429 } 430 } 431 setMiscRegNoEffect(misc_reg, newVal); 432} 433 434} 435