isa.cc revision 7604:9ac39aa78c33
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 */ 40 41#include "arch/arm/isa.hh" 42 43namespace ArmISA 44{ 45 46void 47ISA::clear() 48{ 49 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 50 51 memset(miscRegs, 0, sizeof(miscRegs)); 52 CPSR cpsr = 0; 53 cpsr.mode = MODE_USER; 54 miscRegs[MISCREG_CPSR] = cpsr; 55 updateRegMap(cpsr); 56 57 SCTLR sctlr = 0; 58 sctlr.te = (bool)sctlr_rst.te; 59 sctlr.nmfi = (bool)sctlr_rst.nmfi; 60 sctlr.v = (bool)sctlr_rst.v; 61 sctlr.u = 1; 62 sctlr.xp = 1; 63 sctlr.rao2 = 1; 64 sctlr.rao3 = 1; 65 sctlr.rao4 = 1; 66 miscRegs[MISCREG_SCTLR] = sctlr; 67 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 68 69 70 /* 71 * Technically this should be 0, but we don't support those 72 * settings. 73 */ 74 CPACR cpacr = 0; 75 // Enable CP 10, 11 76 cpacr.cp10 = 0x3; 77 cpacr.cp11 = 0x3; 78 miscRegs[MISCREG_CPACR] = cpacr; 79 80 /* Start with an event in the mailbox */ 81 miscRegs[MISCREG_SEV_MAILBOX] = 1; 82 83 /* 84 * Implemented = '5' from "M5", 85 * Variant = 0, 86 */ 87 miscRegs[MISCREG_MIDR] = 88 (0x35 << 24) | //Implementor is '5' from "M5" 89 (0 << 20) | //Variant 90 (0xf << 16) | //Architecture from CPUID scheme 91 (0 << 4) | //Primary part number 92 (0 << 0) | //Revision 93 0; 94 95 // Separate Instruction and Data TLBs. 96 miscRegs[MISCREG_TLBTR] = 1; 97 98 MVFR0 mvfr0 = 0; 99 mvfr0.advSimdRegisters = 2; 100 mvfr0.singlePrecision = 2; 101 mvfr0.doublePrecision = 2; 102 mvfr0.vfpExceptionTrapping = 0; 103 mvfr0.divide = 1; 104 mvfr0.squareRoot = 1; 105 mvfr0.shortVectors = 1; 106 mvfr0.roundingModes = 1; 107 miscRegs[MISCREG_MVFR0] = mvfr0; 108 109 MVFR1 mvfr1 = 0; 110 mvfr1.flushToZero = 1; 111 mvfr1.defaultNaN = 1; 112 mvfr1.advSimdLoadStore = 1; 113 mvfr1.advSimdInteger = 1; 114 mvfr1.advSimdSinglePrecision = 1; 115 mvfr1.advSimdHalfPrecision = 1; 116 mvfr1.vfpHalfPrecision = 1; 117 miscRegs[MISCREG_MVFR1] = mvfr1; 118 119 miscRegs[MISCREG_MPIDR] = 0; 120 121 // Reset values of PRRR and NMRR are implementation dependent 122 123 miscRegs[MISCREG_PRRR] = 124 (1 << 19) | // 19 125 (0 << 18) | // 18 126 (0 << 17) | // 17 127 (1 << 16) | // 16 128 (2 << 14) | // 15:14 129 (0 << 12) | // 13:12 130 (2 << 10) | // 11:10 131 (2 << 8) | // 9:8 132 (2 << 6) | // 7:6 133 (2 << 4) | // 5:4 134 (1 << 2) | // 3:2 135 0; // 1:0 136 miscRegs[MISCREG_NMRR] = 137 (1 << 30) | // 31:30 138 (0 << 26) | // 27:26 139 (0 << 24) | // 25:24 140 (3 << 22) | // 23:22 141 (2 << 20) | // 21:20 142 (0 << 18) | // 19:18 143 (0 << 16) | // 17:16 144 (1 << 14) | // 15:14 145 (0 << 12) | // 13:12 146 (2 << 10) | // 11:10 147 (0 << 8) | // 9:8 148 (3 << 6) | // 7:6 149 (2 << 4) | // 5:4 150 (0 << 2) | // 3:2 151 0; // 1:0 152 153 //XXX We need to initialize the rest of the state. 154} 155 156MiscReg 157ISA::readMiscRegNoEffect(int misc_reg) 158{ 159 assert(misc_reg < NumMiscRegs); 160 if (misc_reg == MISCREG_SPSR) { 161 CPSR cpsr = miscRegs[MISCREG_CPSR]; 162 switch (cpsr.mode) { 163 case MODE_USER: 164 return miscRegs[MISCREG_SPSR]; 165 case MODE_FIQ: 166 return miscRegs[MISCREG_SPSR_FIQ]; 167 case MODE_IRQ: 168 return miscRegs[MISCREG_SPSR_IRQ]; 169 case MODE_SVC: 170 return miscRegs[MISCREG_SPSR_SVC]; 171 case MODE_MON: 172 return miscRegs[MISCREG_SPSR_MON]; 173 case MODE_ABORT: 174 return miscRegs[MISCREG_SPSR_ABT]; 175 case MODE_UNDEFINED: 176 return miscRegs[MISCREG_SPSR_UND]; 177 default: 178 return miscRegs[MISCREG_SPSR]; 179 } 180 } 181 return miscRegs[misc_reg]; 182} 183 184 185MiscReg 186ISA::readMiscReg(int misc_reg, ThreadContext *tc) 187{ 188 if (misc_reg == MISCREG_CPSR) { 189 CPSR cpsr = miscRegs[misc_reg]; 190 Addr pc = tc->readPC(); 191 if (pc & (ULL(1) << PcJBitShift)) 192 cpsr.j = 1; 193 else 194 cpsr.j = 0; 195 if (pc & (ULL(1) << PcTBitShift)) 196 cpsr.t = 1; 197 else 198 cpsr.t = 0; 199 return cpsr; 200 } 201 if (misc_reg >= MISCREG_CP15_UNIMP_START && 202 misc_reg < MISCREG_CP15_END) { 203 panic("Unimplemented CP15 register %s read.\n", 204 miscRegName[misc_reg]); 205 } 206 switch (misc_reg) { 207 case MISCREG_CLIDR: 208 warn("The clidr register always reports 0 caches.\n"); 209 break; 210 case MISCREG_CCSIDR: 211 warn("The ccsidr register isn't implemented and " 212 "always reads as 0.\n"); 213 break; 214 case MISCREG_ID_PFR0: 215 warn("Returning thumbEE disabled for now since we don't support CP14" 216 "config registers and jumping to ThumbEE vectors\n"); 217 return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM 218 case MISCREG_ID_MMFR0: 219 return 0x03; //VMSAz7 220 case MISCREG_CTR: 221 return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact 222 case MISCREG_ACTLR: 223 warn("Not doing anything for miscreg ACTLR\n"); 224 break; 225 case MISCREG_PMCR: 226 case MISCREG_PMCCNTR: 227 case MISCREG_PMSELR: 228 warn("Not doing anyhting for read to miscreg %s\n", 229 miscRegName[misc_reg]); 230 break; 231 232 } 233 return readMiscRegNoEffect(misc_reg); 234} 235 236void 237ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 238{ 239 assert(misc_reg < NumMiscRegs); 240 if (misc_reg == MISCREG_SPSR) { 241 CPSR cpsr = miscRegs[MISCREG_CPSR]; 242 switch (cpsr.mode) { 243 case MODE_USER: 244 miscRegs[MISCREG_SPSR] = val; 245 return; 246 case MODE_FIQ: 247 miscRegs[MISCREG_SPSR_FIQ] = val; 248 return; 249 case MODE_IRQ: 250 miscRegs[MISCREG_SPSR_IRQ] = val; 251 return; 252 case MODE_SVC: 253 miscRegs[MISCREG_SPSR_SVC] = val; 254 return; 255 case MODE_MON: 256 miscRegs[MISCREG_SPSR_MON] = val; 257 return; 258 case MODE_ABORT: 259 miscRegs[MISCREG_SPSR_ABT] = val; 260 return; 261 case MODE_UNDEFINED: 262 miscRegs[MISCREG_SPSR_UND] = val; 263 return; 264 default: 265 miscRegs[MISCREG_SPSR] = val; 266 return; 267 } 268 } 269 miscRegs[misc_reg] = val; 270} 271 272void 273ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 274{ 275 MiscReg newVal = val; 276 if (misc_reg == MISCREG_CPSR) { 277 updateRegMap(val); 278 CPSR cpsr = val; 279 DPRINTF(Arm, "Updating CPSR to %#x f:%d i:%d a:%d mode:%#x\n", 280 cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 281 Addr npc = tc->readNextPC() & ~PcModeMask; 282 if (cpsr.j) 283 npc = npc | (ULL(1) << PcJBitShift); 284 if (cpsr.t) 285 npc = npc | (ULL(1) << PcTBitShift); 286 287 tc->setNextPC(npc); 288 } else if (misc_reg >= MISCREG_CP15_UNIMP_START && 289 misc_reg < MISCREG_CP15_END) { 290 panic("Unimplemented CP15 register %s wrote with %#x.\n", 291 miscRegName[misc_reg], val); 292 } else { 293 switch (misc_reg) { 294 case MISCREG_ITSTATE: 295 { 296 ITSTATE itstate = newVal; 297 CPSR cpsr = miscRegs[MISCREG_CPSR]; 298 cpsr.it1 = itstate.bottom2; 299 cpsr.it2 = itstate.top6; 300 miscRegs[MISCREG_CPSR] = cpsr; 301 DPRINTF(MiscRegs, 302 "Updating ITSTATE -> %#x in CPSR -> %#x.\n", 303 (uint8_t)itstate, (uint32_t)cpsr); 304 } 305 break; 306 case MISCREG_CPACR: 307 { 308 CPACR newCpacr = 0; 309 CPACR valCpacr = val; 310 newCpacr.cp10 = valCpacr.cp10; 311 newCpacr.cp11 = valCpacr.cp11; 312 if (newCpacr.cp10 != 0x3 || newCpacr.cp11 != 3) { 313 panic("Disabling coprocessors isn't implemented.\n"); 314 } 315 newVal = newCpacr; 316 } 317 break; 318 case MISCREG_CSSELR: 319 warn("The csselr register isn't implemented.\n"); 320 break; 321 case MISCREG_FPSCR: 322 { 323 const uint32_t ones = (uint32_t)(-1); 324 FPSCR fpscrMask = 0; 325 fpscrMask.ioc = ones; 326 fpscrMask.dzc = ones; 327 fpscrMask.ofc = ones; 328 fpscrMask.ufc = ones; 329 fpscrMask.ixc = ones; 330 fpscrMask.idc = ones; 331 fpscrMask.len = ones; 332 fpscrMask.stride = ones; 333 fpscrMask.rMode = ones; 334 fpscrMask.fz = ones; 335 fpscrMask.dn = ones; 336 fpscrMask.ahp = ones; 337 fpscrMask.qc = ones; 338 fpscrMask.v = ones; 339 fpscrMask.c = ones; 340 fpscrMask.z = ones; 341 fpscrMask.n = ones; 342 newVal = (newVal & (uint32_t)fpscrMask) | 343 (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask); 344 } 345 break; 346 case MISCREG_FPEXC: 347 { 348 const uint32_t fpexcMask = 0x60000000; 349 newVal = (newVal & fpexcMask) | 350 (miscRegs[MISCREG_FPEXC] & ~fpexcMask); 351 } 352 break; 353 case MISCREG_SCTLR: 354 { 355 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 356 SCTLR sctlr = miscRegs[MISCREG_SCTLR]; 357 SCTLR new_sctlr = newVal; 358 new_sctlr.nmfi = (bool)sctlr.nmfi; 359 miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr; 360 return; 361 } 362 case MISCREG_TLBTR: 363 case MISCREG_MVFR0: 364 case MISCREG_MVFR1: 365 case MISCREG_MPIDR: 366 case MISCREG_FPSID: 367 return; 368 case MISCREG_TLBIALLIS: 369 case MISCREG_TLBIALL: 370 warn("Need to flush all TLBs in MP\n"); 371 tc->getITBPtr()->flushAll(); 372 tc->getDTBPtr()->flushAll(); 373 return; 374 case MISCREG_ITLBIALL: 375 tc->getITBPtr()->flushAll(); 376 return; 377 case MISCREG_DTLBIALL: 378 tc->getDTBPtr()->flushAll(); 379 return; 380 case MISCREG_TLBIMVAIS: 381 case MISCREG_TLBIMVA: 382 warn("Need to flush all TLBs in MP\n"); 383 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 384 bits(newVal, 7,0)); 385 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 386 bits(newVal, 7,0)); 387 return; 388 case MISCREG_TLBIASIDIS: 389 case MISCREG_TLBIASID: 390 warn("Need to flush all TLBs in MP\n"); 391 tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 392 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 393 return; 394 case MISCREG_TLBIMVAAIS: 395 case MISCREG_TLBIMVAA: 396 warn("Need to flush all TLBs in MP\n"); 397 tc->getITBPtr()->flushMva(mbits(newVal, 31,12)); 398 tc->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 399 return; 400 case MISCREG_ITLBIMVA: 401 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 402 bits(newVal, 7,0)); 403 return; 404 case MISCREG_DTLBIMVA: 405 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 406 bits(newVal, 7,0)); 407 return; 408 case MISCREG_ITLBIASID: 409 tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 410 return; 411 case MISCREG_DTLBIASID: 412 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 413 return; 414 case MISCREG_ACTLR: 415 warn("Not doing anything for write of miscreg ACTLR\n"); 416 break; 417 case MISCREG_PMCR: 418 case MISCREG_PMCCNTR: 419 case MISCREG_PMSELR: 420 warn("Not doing anything for write to miscreg %s\n", 421 miscRegName[misc_reg]); 422 break; 423 case MISCREG_V2PCWPR: 424 case MISCREG_V2PCWPW: 425 case MISCREG_V2PCWUR: 426 case MISCREG_V2PCWUW: 427 case MISCREG_V2POWPR: 428 case MISCREG_V2POWPW: 429 case MISCREG_V2POWUR: 430 case MISCREG_V2POWUW: 431 { 432 RequestPtr req = new Request; 433 unsigned flags; 434 BaseTLB::Mode mode; 435 Fault fault; 436 switch(misc_reg) { 437 case MISCREG_V2PCWPR: 438 flags = TLB::MustBeOne; 439 mode = BaseTLB::Read; 440 break; 441 case MISCREG_V2PCWPW: 442 flags = TLB::MustBeOne; 443 mode = BaseTLB::Write; 444 break; 445 case MISCREG_V2PCWUR: 446 flags = TLB::MustBeOne | TLB::UserMode; 447 mode = BaseTLB::Read; 448 break; 449 case MISCREG_V2PCWUW: 450 flags = TLB::MustBeOne | TLB::UserMode; 451 mode = BaseTLB::Write; 452 break; 453 default: 454 panic("Security Extensions not implemented!"); 455 } 456 req->setVirt(0, val, 1, flags, tc->readPC()); 457 fault = tc->getDTBPtr()->translateAtomic(req, tc, mode); 458 if (fault == NoFault) { 459 miscRegs[MISCREG_PAR] = 460 (req->getPaddr() & 0xfffff000) | 461 (tc->getDTBPtr()->getAttr() ); 462 DPRINTF(MiscRegs, 463 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 464 val, miscRegs[MISCREG_PAR]); 465 } 466 else { 467 // Set fault bit and FSR 468 FSR fsr = miscRegs[MISCREG_DFSR]; 469 miscRegs[MISCREG_PAR] = 470 (fsr.ext << 6) | 471 (fsr.fsHigh << 5) | 472 (fsr.fsLow << 1) | 473 0x1; // F bit 474 } 475 return; 476 } 477 } 478 } 479 setMiscRegNoEffect(misc_reg, newVal); 480} 481 482} 483