isa.cc revision 7442:2dc67291f730
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 */ 40 41#include "arch/arm/isa.hh" 42 43namespace ArmISA 44{ 45 46void 47ISA::clear() 48{ 49 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 50 51 memset(miscRegs, 0, sizeof(miscRegs)); 52 CPSR cpsr = 0; 53 cpsr.mode = MODE_USER; 54 miscRegs[MISCREG_CPSR] = cpsr; 55 updateRegMap(cpsr); 56 57 SCTLR sctlr = 0; 58 sctlr.nmfi = (bool)sctlr_rst.nmfi; 59 sctlr.v = (bool)sctlr_rst.v; 60 sctlr.u = 1; 61 sctlr.xp = 1; 62 sctlr.rao2 = 1; 63 sctlr.rao3 = 1; 64 sctlr.rao4 = 1; 65 miscRegs[MISCREG_SCTLR] = sctlr; 66 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 67 68 69 /* 70 * Technically this should be 0, but we don't support those 71 * settings. 72 */ 73 CPACR cpacr = 0; 74 // Enable CP 10, 11 75 cpacr.cp10 = 0x3; 76 cpacr.cp11 = 0x3; 77 miscRegs[MISCREG_CPACR] = cpacr; 78 79 /* Start with an event in the mailbox */ 80 miscRegs[MISCREG_SEV_MAILBOX] = 1; 81 82 /* 83 * Implemented = '5' from "M5", 84 * Variant = 0, 85 */ 86 miscRegs[MISCREG_MIDR] = 87 (0x35 << 24) | //Implementor is '5' from "M5" 88 (0 << 20) | //Variant 89 (0xf << 16) | //Architecture from CPUID scheme 90 (0 << 4) | //Primary part number 91 (0 << 0) | //Revision 92 0; 93 94 // Separate Instruction and Data TLBs. 95 miscRegs[MISCREG_TLBTR] = 1; 96 97 MVFR0 mvfr0 = 0; 98 mvfr0.advSimdRegisters = 2; 99 mvfr0.singlePrecision = 2; 100 mvfr0.doublePrecision = 2; 101 mvfr0.vfpExceptionTrapping = 0; 102 mvfr0.divide = 1; 103 mvfr0.squareRoot = 1; 104 mvfr0.shortVectors = 1; 105 mvfr0.roundingModes = 1; 106 miscRegs[MISCREG_MVFR0] = mvfr0; 107 108 MVFR1 mvfr1 = 0; 109 mvfr1.flushToZero = 1; 110 mvfr1.defaultNaN = 1; 111 mvfr1.advSimdLoadStore = 1; 112 mvfr1.advSimdInteger = 1; 113 mvfr1.advSimdSinglePrecision = 1; 114 mvfr1.advSimdHalfPrecision = 1; 115 mvfr1.vfpHalfPrecision = 1; 116 miscRegs[MISCREG_MVFR1] = mvfr1; 117 118 miscRegs[MISCREG_MPIDR] = 0; 119 120 // Reset values of PRRR and NMRR are implementation dependent 121 122 miscRegs[MISCREG_PRRR] = 123 (1 << 19) | // 19 124 (0 << 18) | // 18 125 (0 << 17) | // 17 126 (1 << 16) | // 16 127 (2 << 14) | // 15:14 128 (0 << 12) | // 13:12 129 (2 << 10) | // 11:10 130 (2 << 8) | // 9:8 131 (2 << 6) | // 7:6 132 (2 << 4) | // 5:4 133 (1 << 2) | // 3:2 134 0; // 1:0 135 miscRegs[MISCREG_NMRR] = 136 (1 << 30) | // 31:30 137 (0 << 26) | // 27:26 138 (0 << 24) | // 25:24 139 (3 << 22) | // 23:22 140 (2 << 20) | // 21:20 141 (0 << 18) | // 19:18 142 (0 << 16) | // 17:16 143 (1 << 14) | // 15:14 144 (0 << 12) | // 13:12 145 (2 << 10) | // 11:10 146 (0 << 8) | // 9:8 147 (3 << 6) | // 7:6 148 (2 << 4) | // 5:4 149 (0 << 2) | // 3:2 150 0; // 1:0 151 152 //XXX We need to initialize the rest of the state. 153} 154 155MiscReg 156ISA::readMiscRegNoEffect(int misc_reg) 157{ 158 assert(misc_reg < NumMiscRegs); 159 if (misc_reg == MISCREG_SPSR) { 160 CPSR cpsr = miscRegs[MISCREG_CPSR]; 161 switch (cpsr.mode) { 162 case MODE_USER: 163 return miscRegs[MISCREG_SPSR]; 164 case MODE_FIQ: 165 return miscRegs[MISCREG_SPSR_FIQ]; 166 case MODE_IRQ: 167 return miscRegs[MISCREG_SPSR_IRQ]; 168 case MODE_SVC: 169 return miscRegs[MISCREG_SPSR_SVC]; 170 case MODE_MON: 171 return miscRegs[MISCREG_SPSR_MON]; 172 case MODE_ABORT: 173 return miscRegs[MISCREG_SPSR_ABT]; 174 case MODE_UNDEFINED: 175 return miscRegs[MISCREG_SPSR_UND]; 176 default: 177 return miscRegs[MISCREG_SPSR]; 178 } 179 } 180 return miscRegs[misc_reg]; 181} 182 183 184MiscReg 185ISA::readMiscReg(int misc_reg, ThreadContext *tc) 186{ 187 if (misc_reg == MISCREG_CPSR) { 188 CPSR cpsr = miscRegs[misc_reg]; 189 Addr pc = tc->readPC(); 190 if (pc & (ULL(1) << PcJBitShift)) 191 cpsr.j = 1; 192 else 193 cpsr.j = 0; 194 if (pc & (ULL(1) << PcTBitShift)) 195 cpsr.t = 1; 196 else 197 cpsr.t = 0; 198 return cpsr; 199 } 200 if (misc_reg >= MISCREG_CP15_UNIMP_START && 201 misc_reg < MISCREG_CP15_END) { 202 panic("Unimplemented CP15 register %s read.\n", 203 miscRegName[misc_reg]); 204 } 205 switch (misc_reg) { 206 case MISCREG_CLIDR: 207 warn("The clidr register always reports 0 caches.\n"); 208 break; 209 case MISCREG_CCSIDR: 210 warn("The ccsidr register isn't implemented and " 211 "always reads as 0.\n"); 212 break; 213 case MISCREG_ID_PFR0: 214 return 0x1031; // ThumbEE | !Jazelle | Thumb | ARM 215 } 216 return readMiscRegNoEffect(misc_reg); 217} 218 219void 220ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 221{ 222 assert(misc_reg < NumMiscRegs); 223 if (misc_reg == MISCREG_SPSR) { 224 CPSR cpsr = miscRegs[MISCREG_CPSR]; 225 switch (cpsr.mode) { 226 case MODE_USER: 227 miscRegs[MISCREG_SPSR] = val; 228 return; 229 case MODE_FIQ: 230 miscRegs[MISCREG_SPSR_FIQ] = val; 231 return; 232 case MODE_IRQ: 233 miscRegs[MISCREG_SPSR_IRQ] = val; 234 return; 235 case MODE_SVC: 236 miscRegs[MISCREG_SPSR_SVC] = val; 237 return; 238 case MODE_MON: 239 miscRegs[MISCREG_SPSR_MON] = val; 240 return; 241 case MODE_ABORT: 242 miscRegs[MISCREG_SPSR_ABT] = val; 243 return; 244 case MODE_UNDEFINED: 245 miscRegs[MISCREG_SPSR_UND] = val; 246 return; 247 default: 248 miscRegs[MISCREG_SPSR] = val; 249 return; 250 } 251 } 252 miscRegs[misc_reg] = val; 253} 254 255void 256ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 257{ 258 MiscReg newVal = val; 259 if (misc_reg == MISCREG_CPSR) { 260 updateRegMap(val); 261 CPSR cpsr = val; 262 DPRINTF(Arm, "Updating CPSR to %#x f:%d i:%d a:%d mode:%#x\n", 263 cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 264 Addr npc = tc->readNextPC() & ~PcModeMask; 265 if (cpsr.j) 266 npc = npc | (ULL(1) << PcJBitShift); 267 if (cpsr.t) 268 npc = npc | (ULL(1) << PcTBitShift); 269 270 tc->setNextPC(npc); 271 } else if (misc_reg >= MISCREG_CP15_UNIMP_START && 272 misc_reg < MISCREG_CP15_END) { 273 panic("Unimplemented CP15 register %s wrote with %#x.\n", 274 miscRegName[misc_reg], val); 275 } else { 276 switch (misc_reg) { 277 case MISCREG_ITSTATE: 278 { 279 ITSTATE itstate = newVal; 280 CPSR cpsr = miscRegs[MISCREG_CPSR]; 281 cpsr.it1 = itstate.bottom2; 282 cpsr.it2 = itstate.top6; 283 miscRegs[MISCREG_CPSR] = cpsr; 284 DPRINTF(MiscRegs, 285 "Updating ITSTATE -> %#x in CPSR -> %#x.\n", 286 (uint8_t)itstate, (uint32_t)cpsr); 287 } 288 break; 289 case MISCREG_CPACR: 290 { 291 CPACR newCpacr = 0; 292 CPACR valCpacr = val; 293 newCpacr.cp10 = valCpacr.cp10; 294 newCpacr.cp11 = valCpacr.cp11; 295 if (newCpacr.cp10 != 0x3 || newCpacr.cp11 != 3) { 296 panic("Disabling coprocessors isn't implemented.\n"); 297 } 298 newVal = newCpacr; 299 } 300 break; 301 case MISCREG_CSSELR: 302 warn("The csselr register isn't implemented.\n"); 303 break; 304 case MISCREG_FPSCR: 305 { 306 const uint32_t ones = (uint32_t)(-1); 307 FPSCR fpscrMask = 0; 308 fpscrMask.ioc = ones; 309 fpscrMask.dzc = ones; 310 fpscrMask.ofc = ones; 311 fpscrMask.ufc = ones; 312 fpscrMask.ixc = ones; 313 fpscrMask.idc = ones; 314 fpscrMask.len = ones; 315 fpscrMask.stride = ones; 316 fpscrMask.rMode = ones; 317 fpscrMask.fz = ones; 318 fpscrMask.dn = ones; 319 fpscrMask.ahp = ones; 320 fpscrMask.qc = ones; 321 fpscrMask.v = ones; 322 fpscrMask.c = ones; 323 fpscrMask.z = ones; 324 fpscrMask.n = ones; 325 newVal = (newVal & (uint32_t)fpscrMask) | 326 (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask); 327 } 328 break; 329 case MISCREG_FPEXC: 330 { 331 const uint32_t fpexcMask = 0x60000000; 332 newVal = (newVal & fpexcMask) | 333 (miscRegs[MISCREG_FPEXC] & ~fpexcMask); 334 } 335 break; 336 case MISCREG_SCTLR: 337 { 338 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 339 SCTLR sctlr = miscRegs[MISCREG_SCTLR]; 340 SCTLR new_sctlr = newVal; 341 new_sctlr.nmfi = (bool)sctlr.nmfi; 342 miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr; 343 return; 344 } 345 case MISCREG_TLBTR: 346 case MISCREG_MVFR0: 347 case MISCREG_MVFR1: 348 case MISCREG_MPIDR: 349 case MISCREG_FPSID: 350 return; 351 case MISCREG_TLBIALLIS: 352 case MISCREG_TLBIALL: 353 warn("Need to flush all TLBs in MP\n"); 354 tc->getITBPtr()->flushAll(); 355 tc->getDTBPtr()->flushAll(); 356 return; 357 case MISCREG_ITLBIALL: 358 tc->getITBPtr()->flushAll(); 359 return; 360 case MISCREG_DTLBIALL: 361 tc->getDTBPtr()->flushAll(); 362 return; 363 case MISCREG_TLBIMVAIS: 364 case MISCREG_TLBIMVA: 365 warn("Need to flush all TLBs in MP\n"); 366 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 367 bits(newVal, 7,0)); 368 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 369 bits(newVal, 7,0)); 370 return; 371 case MISCREG_TLBIASIDIS: 372 case MISCREG_TLBIASID: 373 warn("Need to flush all TLBs in MP\n"); 374 tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 375 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 376 return; 377 case MISCREG_TLBIMVAAIS: 378 case MISCREG_TLBIMVAA: 379 warn("Need to flush all TLBs in MP\n"); 380 tc->getITBPtr()->flushMva(mbits(newVal, 31,12)); 381 tc->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 382 return; 383 case MISCREG_ITLBIMVA: 384 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 385 bits(newVal, 7,0)); 386 return; 387 case MISCREG_DTLBIMVA: 388 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 389 bits(newVal, 7,0)); 390 return; 391 case MISCREG_ITLBIASID: 392 tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 393 return; 394 case MISCREG_DTLBIASID: 395 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 396 return; 397 case MISCREG_V2PCWPR: 398 case MISCREG_V2PCWPW: 399 case MISCREG_V2PCWUR: 400 case MISCREG_V2PCWUW: 401 case MISCREG_V2POWPR: 402 case MISCREG_V2POWPW: 403 case MISCREG_V2POWUR: 404 case MISCREG_V2POWUW: 405 { 406 RequestPtr req = new Request; 407 unsigned flags; 408 BaseTLB::Mode mode; 409 Fault fault; 410 switch(misc_reg) { 411 case MISCREG_V2PCWPR: 412 flags = TLB::MustBeOne; 413 mode = BaseTLB::Read; 414 break; 415 case MISCREG_V2PCWPW: 416 flags = TLB::MustBeOne; 417 mode = BaseTLB::Write; 418 break; 419 case MISCREG_V2PCWUR: 420 flags = TLB::MustBeOne | TLB::UserMode; 421 mode = BaseTLB::Read; 422 break; 423 case MISCREG_V2PCWUW: 424 flags = TLB::MustBeOne | TLB::UserMode; 425 mode = BaseTLB::Write; 426 break; 427 default: 428 panic("Security Extensions not implemented!"); 429 } 430 req->setVirt(0, val, 1, flags, tc->readPC()); 431 fault = tc->getDTBPtr()->translateAtomic(req, tc, mode); 432 if (fault == NoFault) { 433 miscRegs[MISCREG_PAR] = 434 (req->getPaddr() & 0xfffff000) | 435 (tc->getDTBPtr()->getAttr() ); 436 DPRINTF(MiscRegs, 437 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 438 val, miscRegs[MISCREG_PAR]); 439 } 440 else { 441 // Set fault bit and FSR 442 FSR fsr = miscRegs[MISCREG_DFSR]; 443 miscRegs[MISCREG_PAR] = 444 (fsr.ext << 6) | 445 (fsr.fsHigh << 5) | 446 (fsr.fsLow << 1) | 447 0x1; // F bit 448 } 449 return; 450 } 451 } 452 } 453 setMiscRegNoEffect(misc_reg, newVal); 454} 455 456} 457