isa.cc revision 7405:7a938baf14be 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 *          Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42
43namespace ArmISA
44{
45
46MiscReg
47ISA::readMiscRegNoEffect(int misc_reg)
48{
49    assert(misc_reg < NumMiscRegs);
50    if (misc_reg == MISCREG_SPSR) {
51        CPSR cpsr = miscRegs[MISCREG_CPSR];
52        switch (cpsr.mode) {
53          case MODE_USER:
54            return miscRegs[MISCREG_SPSR];
55          case MODE_FIQ:
56            return miscRegs[MISCREG_SPSR_FIQ];
57          case MODE_IRQ:
58            return miscRegs[MISCREG_SPSR_IRQ];
59          case MODE_SVC:
60            return miscRegs[MISCREG_SPSR_SVC];
61          case MODE_MON:
62            return miscRegs[MISCREG_SPSR_MON];
63          case MODE_ABORT:
64            return miscRegs[MISCREG_SPSR_ABT];
65          case MODE_UNDEFINED:
66            return miscRegs[MISCREG_SPSR_UND];
67          default:
68            return miscRegs[MISCREG_SPSR];
69        }
70    }
71    return miscRegs[misc_reg];
72}
73
74
75MiscReg
76ISA::readMiscReg(int misc_reg, ThreadContext *tc)
77{
78    if (misc_reg == MISCREG_CPSR) {
79        CPSR cpsr = miscRegs[misc_reg];
80        Addr pc = tc->readPC();
81        if (pc & (ULL(1) << PcJBitShift))
82            cpsr.j = 1;
83        else
84            cpsr.j = 0;
85        if (pc & (ULL(1) << PcTBitShift))
86            cpsr.t = 1;
87        else
88            cpsr.t = 0;
89        return cpsr;
90    }
91    if (misc_reg >= MISCREG_CP15_UNIMP_START &&
92        misc_reg < MISCREG_CP15_END) {
93        panic("Unimplemented CP15 register %s read.\n",
94              miscRegName[misc_reg]);
95    }
96    switch (misc_reg) {
97      case MISCREG_CLIDR:
98        warn("The clidr register always reports 0 caches.\n");
99        break;
100      case MISCREG_CCSIDR:
101        warn("The ccsidr register isn't implemented and "
102                "always reads as 0.\n");
103        break;
104      case MISCREG_ID_PFR0:
105        return 0x1031; // ThumbEE | !Jazelle | Thumb | ARM
106    }
107    return readMiscRegNoEffect(misc_reg);
108}
109
110void
111ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
112{
113    assert(misc_reg < NumMiscRegs);
114    if (misc_reg == MISCREG_SPSR) {
115        CPSR cpsr = miscRegs[MISCREG_CPSR];
116        switch (cpsr.mode) {
117          case MODE_USER:
118            miscRegs[MISCREG_SPSR] = val;
119            return;
120          case MODE_FIQ:
121            miscRegs[MISCREG_SPSR_FIQ] = val;
122            return;
123          case MODE_IRQ:
124            miscRegs[MISCREG_SPSR_IRQ] = val;
125            return;
126          case MODE_SVC:
127            miscRegs[MISCREG_SPSR_SVC] = val;
128            return;
129          case MODE_MON:
130            miscRegs[MISCREG_SPSR_MON] = val;
131            return;
132          case MODE_ABORT:
133            miscRegs[MISCREG_SPSR_ABT] = val;
134            return;
135          case MODE_UNDEFINED:
136            miscRegs[MISCREG_SPSR_UND] = val;
137            return;
138          default:
139            miscRegs[MISCREG_SPSR] = val;
140            return;
141        }
142    }
143    miscRegs[misc_reg] = val;
144}
145
146void
147ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
148{
149    MiscReg newVal = val;
150    if (misc_reg == MISCREG_CPSR) {
151        updateRegMap(val);
152        CPSR cpsr = val;
153        DPRINTF(Arm, "Updating CPSR to %#x f:%d i:%d a:%d mode:%#x\n",
154                cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
155        Addr npc = tc->readNextPC() & ~PcModeMask;
156        if (cpsr.j)
157            npc = npc | (ULL(1) << PcJBitShift);
158        if (cpsr.t)
159            npc = npc | (ULL(1) << PcTBitShift);
160
161        tc->setNextPC(npc);
162    }
163    if (misc_reg >= MISCREG_CP15_UNIMP_START &&
164        misc_reg < MISCREG_CP15_END) {
165        panic("Unimplemented CP15 register %s wrote with %#x.\n",
166              miscRegName[misc_reg], val);
167    }
168    switch (misc_reg) {
169      case MISCREG_CPACR:
170        {
171            CPACR newCpacr = 0;
172            CPACR valCpacr = val;
173            newCpacr.cp10 = valCpacr.cp10;
174            newCpacr.cp11 = valCpacr.cp11;
175            if (newCpacr.cp10 != 0x3 || newCpacr.cp11 != 3) {
176                panic("Disabling coprocessors isn't implemented.\n");
177            }
178            newVal = newCpacr;
179        }
180        break;
181      case MISCREG_CSSELR:
182        warn("The csselr register isn't implemented.\n");
183        break;
184      case MISCREG_FPSCR:
185        {
186            const uint32_t ones = (uint32_t)(-1);
187            FPSCR fpscrMask = 0;
188            fpscrMask.ioc = ones;
189            fpscrMask.dzc = ones;
190            fpscrMask.ofc = ones;
191            fpscrMask.ufc = ones;
192            fpscrMask.ixc = ones;
193            fpscrMask.idc = ones;
194            fpscrMask.len = ones;
195            fpscrMask.stride = ones;
196            fpscrMask.rMode = ones;
197            fpscrMask.fz = ones;
198            fpscrMask.dn = ones;
199            fpscrMask.ahp = ones;
200            fpscrMask.qc = ones;
201            fpscrMask.v = ones;
202            fpscrMask.c = ones;
203            fpscrMask.z = ones;
204            fpscrMask.n = ones;
205            newVal = (newVal & (uint32_t)fpscrMask) |
206                     (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask);
207        }
208        break;
209      case MISCREG_FPEXC:
210        {
211            const uint32_t fpexcMask = 0x60000000;
212            newVal = (newVal & fpexcMask) |
213                     (miscRegs[MISCREG_FPEXC] & ~fpexcMask);
214        }
215        break;
216      case MISCREG_SCTLR:
217        {
218            SCTLR sctlr = miscRegs[MISCREG_SCTLR];
219            SCTLR new_sctlr = newVal;
220            new_sctlr.nmfi =  (bool)sctlr.nmfi;
221            miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr;
222            return;
223        }
224      case MISCREG_TLBTR:
225      case MISCREG_MVFR0:
226      case MISCREG_MVFR1:
227      case MISCREG_MPIDR:
228      case MISCREG_FPSID:
229        return;
230      case MISCREG_TLBIALLIS:
231      case MISCREG_TLBIALL:
232        warn("Need to flush all TLBs in MP\n");
233        tc->getITBPtr()->flushAll();
234        tc->getDTBPtr()->flushAll();
235        return;
236      case MISCREG_ITLBIALL:
237        tc->getITBPtr()->flushAll();
238        return;
239      case MISCREG_DTLBIALL:
240        tc->getDTBPtr()->flushAll();
241        return;
242      case MISCREG_TLBIMVAIS:
243      case MISCREG_TLBIMVA:
244        warn("Need to flush all TLBs in MP\n");
245        tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
246                bits(newVal, 7,0));
247        tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
248                bits(newVal, 7,0));
249        return;
250      case MISCREG_TLBIASIDIS:
251      case MISCREG_TLBIASID:
252        warn("Need to flush all TLBs in MP\n");
253        tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
254        tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
255        return;
256      case MISCREG_TLBIMVAAIS:
257      case MISCREG_TLBIMVAA:
258        warn("Need to flush all TLBs in MP\n");
259        tc->getITBPtr()->flushMva(mbits(newVal, 31,12));
260        tc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
261        return;
262      case MISCREG_ITLBIMVA:
263        tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
264                bits(newVal, 7,0));
265        return;
266      case MISCREG_DTLBIMVA:
267        tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
268                bits(newVal, 7,0));
269        return;
270      case MISCREG_ITLBIASID:
271        tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
272        return;
273      case MISCREG_DTLBIASID:
274        tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
275        return;
276    }
277    setMiscRegNoEffect(misc_reg, newVal);
278}
279
280}
281