isa.cc revision 14282:1a6b51a56fa5
1/* 2 * Copyright (c) 2010-2019 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 */ 40 41#include "arch/arm/isa.hh" 42#include "arch/arm/pmu.hh" 43#include "arch/arm/system.hh" 44#include "arch/arm/tlb.hh" 45#include "arch/arm/tlbi_op.hh" 46#include "cpu/base.hh" 47#include "cpu/checker/cpu.hh" 48#include "debug/Arm.hh" 49#include "debug/MiscRegs.hh" 50#include "dev/arm/generic_timer.hh" 51#include "dev/arm/gic_v3.hh" 52#include "dev/arm/gic_v3_cpu_interface.hh" 53#include "params/ArmISA.hh" 54#include "sim/faults.hh" 55#include "sim/stat_control.hh" 56#include "sim/system.hh" 57 58namespace ArmISA 59{ 60 61ISA::ISA(Params *p) 62 : SimObject(p), 63 system(NULL), 64 _decoderFlavour(p->decoderFlavour), 65 _vecRegRenameMode(Enums::Full), 66 pmu(p->pmu), 67 haveGICv3CPUInterface(false), 68 impdefAsNop(p->impdef_nop), 69 afterStartup(false) 70{ 71 miscRegs[MISCREG_SCTLR_RST] = 0; 72 73 // Hook up a dummy device if we haven't been configured with a 74 // real PMU. By using a dummy device, we don't need to check that 75 // the PMU exist every time we try to access a PMU register. 76 if (!pmu) 77 pmu = &dummyDevice; 78 79 // Give all ISA devices a pointer to this ISA 80 pmu->setISA(this); 81 82 system = dynamic_cast<ArmSystem *>(p->system); 83 84 // Cache system-level properties 85 if (FullSystem && system) { 86 highestELIs64 = system->highestELIs64(); 87 haveSecurity = system->haveSecurity(); 88 haveLPAE = system->haveLPAE(); 89 haveCrypto = system->haveCrypto(); 90 haveVirtualization = system->haveVirtualization(); 91 haveLargeAsid64 = system->haveLargeAsid64(); 92 physAddrRange = system->physAddrRange(); 93 haveSVE = system->haveSVE(); 94 havePAN = system->havePAN(); 95 sveVL = system->sveVL(); 96 haveLSE = system->haveLSE(); 97 } else { 98 highestELIs64 = true; // ArmSystem::highestELIs64 does the same 99 haveSecurity = haveLPAE = haveVirtualization = false; 100 haveCrypto = true; 101 haveLargeAsid64 = false; 102 physAddrRange = 32; // dummy value 103 haveSVE = true; 104 havePAN = false; 105 sveVL = p->sve_vl_se; 106 haveLSE = true; 107 } 108 109 // Initial rename mode depends on highestEL 110 const_cast<Enums::VecRegRenameMode&>(_vecRegRenameMode) = 111 highestELIs64 ? Enums::Full : Enums::Elem; 112 113 initializeMiscRegMetadata(); 114 preUnflattenMiscReg(); 115 116 clear(); 117} 118 119std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS); 120 121const ArmISAParams * 122ISA::params() const 123{ 124 return dynamic_cast<const Params *>(_params); 125} 126 127void 128ISA::clear() 129{ 130 const Params *p(params()); 131 132 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 133 memset(miscRegs, 0, sizeof(miscRegs)); 134 135 initID32(p); 136 137 // We always initialize AArch64 ID registers even 138 // if we are in AArch32. This is done since if we 139 // are in SE mode we don't know if our ArmProcess is 140 // AArch32 or AArch64 141 initID64(p); 142 143 // Start with an event in the mailbox 144 miscRegs[MISCREG_SEV_MAILBOX] = 1; 145 146 // Separate Instruction and Data TLBs 147 miscRegs[MISCREG_TLBTR] = 1; 148 149 MVFR0 mvfr0 = 0; 150 mvfr0.advSimdRegisters = 2; 151 mvfr0.singlePrecision = 2; 152 mvfr0.doublePrecision = 2; 153 mvfr0.vfpExceptionTrapping = 0; 154 mvfr0.divide = 1; 155 mvfr0.squareRoot = 1; 156 mvfr0.shortVectors = 1; 157 mvfr0.roundingModes = 1; 158 miscRegs[MISCREG_MVFR0] = mvfr0; 159 160 MVFR1 mvfr1 = 0; 161 mvfr1.flushToZero = 1; 162 mvfr1.defaultNaN = 1; 163 mvfr1.advSimdLoadStore = 1; 164 mvfr1.advSimdInteger = 1; 165 mvfr1.advSimdSinglePrecision = 1; 166 mvfr1.advSimdHalfPrecision = 1; 167 mvfr1.vfpHalfPrecision = 1; 168 miscRegs[MISCREG_MVFR1] = mvfr1; 169 170 // Reset values of PRRR and NMRR are implementation dependent 171 172 // @todo: PRRR and NMRR in secure state? 173 miscRegs[MISCREG_PRRR_NS] = 174 (1 << 19) | // 19 175 (0 << 18) | // 18 176 (0 << 17) | // 17 177 (1 << 16) | // 16 178 (2 << 14) | // 15:14 179 (0 << 12) | // 13:12 180 (2 << 10) | // 11:10 181 (2 << 8) | // 9:8 182 (2 << 6) | // 7:6 183 (2 << 4) | // 5:4 184 (1 << 2) | // 3:2 185 0; // 1:0 186 187 miscRegs[MISCREG_NMRR_NS] = 188 (1 << 30) | // 31:30 189 (0 << 26) | // 27:26 190 (0 << 24) | // 25:24 191 (3 << 22) | // 23:22 192 (2 << 20) | // 21:20 193 (0 << 18) | // 19:18 194 (0 << 16) | // 17:16 195 (1 << 14) | // 15:14 196 (0 << 12) | // 13:12 197 (2 << 10) | // 11:10 198 (0 << 8) | // 9:8 199 (3 << 6) | // 7:6 200 (2 << 4) | // 5:4 201 (0 << 2) | // 3:2 202 0; // 1:0 203 204 if (FullSystem && system->highestELIs64()) { 205 // Initialize AArch64 state 206 clear64(p); 207 return; 208 } 209 210 // Initialize AArch32 state... 211 clear32(p, sctlr_rst); 212} 213 214void 215ISA::clear32(const ArmISAParams *p, const SCTLR &sctlr_rst) 216{ 217 CPSR cpsr = 0; 218 cpsr.mode = MODE_USER; 219 220 if (FullSystem) { 221 miscRegs[MISCREG_MVBAR] = system->resetAddr(); 222 } 223 224 miscRegs[MISCREG_CPSR] = cpsr; 225 updateRegMap(cpsr); 226 227 SCTLR sctlr = 0; 228 sctlr.te = (bool) sctlr_rst.te; 229 sctlr.nmfi = (bool) sctlr_rst.nmfi; 230 sctlr.v = (bool) sctlr_rst.v; 231 sctlr.u = 1; 232 sctlr.xp = 1; 233 sctlr.rao2 = 1; 234 sctlr.rao3 = 1; 235 sctlr.rao4 = 0xf; // SCTLR[6:3] 236 sctlr.uci = 1; 237 sctlr.dze = 1; 238 miscRegs[MISCREG_SCTLR_NS] = sctlr; 239 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 240 miscRegs[MISCREG_HCPTR] = 0; 241 242 miscRegs[MISCREG_CPACR] = 0; 243 244 miscRegs[MISCREG_FPSID] = p->fpsid; 245 246 if (haveLPAE) { 247 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 248 ttbcr.eae = 0; 249 miscRegs[MISCREG_TTBCR_NS] = ttbcr; 250 // Enforce consistency with system-level settings 251 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 252 } 253 254 if (haveSecurity) { 255 miscRegs[MISCREG_SCTLR_S] = sctlr; 256 miscRegs[MISCREG_SCR] = 0; 257 miscRegs[MISCREG_VBAR_S] = 0; 258 } else { 259 // we're always non-secure 260 miscRegs[MISCREG_SCR] = 1; 261 } 262 263 //XXX We need to initialize the rest of the state. 264} 265 266void 267ISA::clear64(const ArmISAParams *p) 268{ 269 CPSR cpsr = 0; 270 Addr rvbar = system->resetAddr(); 271 switch (system->highestEL()) { 272 // Set initial EL to highest implemented EL using associated stack 273 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 274 // value 275 case EL3: 276 cpsr.mode = MODE_EL3H; 277 miscRegs[MISCREG_RVBAR_EL3] = rvbar; 278 break; 279 case EL2: 280 cpsr.mode = MODE_EL2H; 281 miscRegs[MISCREG_RVBAR_EL2] = rvbar; 282 break; 283 case EL1: 284 cpsr.mode = MODE_EL1H; 285 miscRegs[MISCREG_RVBAR_EL1] = rvbar; 286 break; 287 default: 288 panic("Invalid highest implemented exception level"); 289 break; 290 } 291 292 // Initialize rest of CPSR 293 cpsr.daif = 0xf; // Mask all interrupts 294 cpsr.ss = 0; 295 cpsr.il = 0; 296 miscRegs[MISCREG_CPSR] = cpsr; 297 updateRegMap(cpsr); 298 299 // Initialize other control registers 300 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 301 if (haveSecurity) { 302 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830; 303 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 304 } else if (haveVirtualization) { 305 // also MISCREG_SCTLR_EL2 (by mapping) 306 miscRegs[MISCREG_HSCTLR] = 0x30c50830; 307 } else { 308 // also MISCREG_SCTLR_EL1 (by mapping) 309 miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init 310 // Always non-secure 311 miscRegs[MISCREG_SCR_EL3] = 1; 312 } 313} 314 315void 316ISA::initID32(const ArmISAParams *p) 317{ 318 // Initialize configurable default values 319 miscRegs[MISCREG_MIDR] = p->midr; 320 miscRegs[MISCREG_MIDR_EL1] = p->midr; 321 miscRegs[MISCREG_VPIDR] = p->midr; 322 323 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 324 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 325 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 326 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 327 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 328 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 329 330 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 331 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 332 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 333 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 334 335 miscRegs[MISCREG_ID_ISAR5] = insertBits( 336 miscRegs[MISCREG_ID_ISAR5], 19, 4, 337 haveCrypto ? 0x1112 : 0x0); 338} 339 340void 341ISA::initID64(const ArmISAParams *p) 342{ 343 // Initialize configurable id registers 344 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 345 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 346 miscRegs[MISCREG_ID_AA64DFR0_EL1] = 347 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 348 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 349 350 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 351 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 352 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 353 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 354 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 355 miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p->id_aa64mmfr2_el1; 356 357 miscRegs[MISCREG_ID_DFR0_EL1] = 358 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 359 360 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 361 362 // SVE 363 miscRegs[MISCREG_ID_AA64ZFR0_EL1] = 0; // SVEver 0 364 if (haveSecurity) { 365 miscRegs[MISCREG_ZCR_EL3] = sveVL - 1; 366 } else if (haveVirtualization) { 367 miscRegs[MISCREG_ZCR_EL2] = sveVL - 1; 368 } else { 369 miscRegs[MISCREG_ZCR_EL1] = sveVL - 1; 370 } 371 372 // Enforce consistency with system-level settings... 373 374 // EL3 375 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 376 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 377 haveSecurity ? 0x2 : 0x0); 378 // EL2 379 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 380 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 381 haveVirtualization ? 0x2 : 0x0); 382 // SVE 383 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 384 miscRegs[MISCREG_ID_AA64PFR0_EL1], 35, 32, 385 haveSVE ? 0x1 : 0x0); 386 // Large ASID support 387 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 388 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 389 haveLargeAsid64 ? 0x2 : 0x0); 390 // Physical address size 391 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 392 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 393 encodePhysAddrRange64(physAddrRange)); 394 // Crypto 395 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits( 396 miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4, 397 haveCrypto ? 0x1112 : 0x0); 398 // LSE 399 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits( 400 miscRegs[MISCREG_ID_AA64ISAR0_EL1], 23, 20, 401 haveLSE ? 0x2 : 0x0); 402 // PAN 403 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits( 404 miscRegs[MISCREG_ID_AA64MMFR1_EL1], 23, 20, 405 havePAN ? 0x1 : 0x0); 406} 407 408void 409ISA::startup(ThreadContext *tc) 410{ 411 pmu->setThreadContext(tc); 412 413 if (system) { 414 Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC()); 415 if (gicv3) { 416 haveGICv3CPUInterface = true; 417 gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId())); 418 gicv3CpuInterface->setISA(this); 419 gicv3CpuInterface->setThreadContext(tc); 420 } 421 } 422 423 afterStartup = true; 424} 425 426 427RegVal 428ISA::readMiscRegNoEffect(int misc_reg) const 429{ 430 assert(misc_reg < NumMiscRegs); 431 432 const auto ® = lookUpMiscReg[misc_reg]; // bit masks 433 const auto &map = getMiscIndices(misc_reg); 434 int lower = map.first, upper = map.second; 435 // NB!: apply architectural masks according to desired register, 436 // despite possibly getting value from different (mapped) register. 437 auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32)) 438 |(miscRegs[upper] << 32)); 439 if (val & reg.res0()) { 440 DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n", 441 miscRegName[misc_reg], val & reg.res0()); 442 } 443 if ((val & reg.res1()) != reg.res1()) { 444 DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n", 445 miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1()); 446 } 447 return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao 448} 449 450 451RegVal 452ISA::readMiscReg(int misc_reg, ThreadContext *tc) 453{ 454 CPSR cpsr = 0; 455 PCState pc = 0; 456 SCR scr = 0; 457 458 if (misc_reg == MISCREG_CPSR) { 459 cpsr = miscRegs[misc_reg]; 460 pc = tc->pcState(); 461 cpsr.j = pc.jazelle() ? 1 : 0; 462 cpsr.t = pc.thumb() ? 1 : 0; 463 return cpsr; 464 } 465 466#ifndef NDEBUG 467 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 468 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 469 warn("Unimplemented system register %s read.\n", 470 miscRegName[misc_reg]); 471 else 472 panic("Unimplemented system register %s read.\n", 473 miscRegName[misc_reg]); 474 } 475#endif 476 477 switch (unflattenMiscReg(misc_reg)) { 478 case MISCREG_HCR: 479 { 480 if (!haveVirtualization) 481 return 0; 482 else 483 return readMiscRegNoEffect(MISCREG_HCR); 484 } 485 case MISCREG_CPACR: 486 { 487 const uint32_t ones = (uint32_t)(-1); 488 CPACR cpacrMask = 0; 489 // Only cp10, cp11, and ase are implemented, nothing else should 490 // be readable? (straight copy from the write code) 491 cpacrMask.cp10 = ones; 492 cpacrMask.cp11 = ones; 493 cpacrMask.asedis = ones; 494 495 // Security Extensions may limit the readability of CPACR 496 if (haveSecurity) { 497 scr = readMiscRegNoEffect(MISCREG_SCR); 498 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 499 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 500 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 501 // NB: Skipping the full loop, here 502 if (!nsacr.cp10) cpacrMask.cp10 = 0; 503 if (!nsacr.cp11) cpacrMask.cp11 = 0; 504 } 505 } 506 RegVal val = readMiscRegNoEffect(MISCREG_CPACR); 507 val &= cpacrMask; 508 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 509 miscRegName[misc_reg], val); 510 return val; 511 } 512 case MISCREG_MPIDR: 513 case MISCREG_MPIDR_EL1: 514 return readMPIDR(system, tc); 515 case MISCREG_VMPIDR: 516 case MISCREG_VMPIDR_EL2: 517 // top bit defined as RES1 518 return readMiscRegNoEffect(misc_reg) | 0x80000000; 519 case MISCREG_ID_AFR0: // not implemented, so alias MIDR 520 case MISCREG_REVIDR: // not implemented, so alias MIDR 521 case MISCREG_MIDR: 522 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 523 scr = readMiscRegNoEffect(MISCREG_SCR); 524 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 525 return readMiscRegNoEffect(misc_reg); 526 } else { 527 return readMiscRegNoEffect(MISCREG_VPIDR); 528 } 529 break; 530 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 531 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 532 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 533 case MISCREG_AIDR: // AUX ID set to 0 534 case MISCREG_TCMTR: // No TCM's 535 return 0; 536 537 case MISCREG_CLIDR: 538 warn_once("The clidr register always reports 0 caches.\n"); 539 warn_once("clidr LoUIS field of 0b001 to match current " 540 "ARM implementations.\n"); 541 return 0x00200000; 542 case MISCREG_CCSIDR: 543 warn_once("The ccsidr register isn't implemented and " 544 "always reads as 0.\n"); 545 break; 546 case MISCREG_CTR: // AArch32, ARMv7, top bit set 547 case MISCREG_CTR_EL0: // AArch64 548 { 549 //all caches have the same line size in gem5 550 //4 byte words in ARM 551 unsigned lineSizeWords = 552 tc->getSystemPtr()->cacheLineSize() / 4; 553 unsigned log2LineSizeWords = 0; 554 555 while (lineSizeWords >>= 1) { 556 ++log2LineSizeWords; 557 } 558 559 CTR ctr = 0; 560 //log2 of minimun i-cache line size (words) 561 ctr.iCacheLineSize = log2LineSizeWords; 562 //b11 - gem5 uses pipt 563 ctr.l1IndexPolicy = 0x3; 564 //log2 of minimum d-cache line size (words) 565 ctr.dCacheLineSize = log2LineSizeWords; 566 //log2 of max reservation size (words) 567 ctr.erg = log2LineSizeWords; 568 //log2 of max writeback size (words) 569 ctr.cwg = log2LineSizeWords; 570 //b100 - gem5 format is ARMv7 571 ctr.format = 0x4; 572 573 return ctr; 574 } 575 case MISCREG_ACTLR: 576 warn("Not doing anything for miscreg ACTLR\n"); 577 break; 578 579 case MISCREG_PMXEVTYPER_PMCCFILTR: 580 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 581 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 582 case MISCREG_PMCR ... MISCREG_PMOVSSET: 583 return pmu->readMiscReg(misc_reg); 584 585 case MISCREG_CPSR_Q: 586 panic("shouldn't be reading this register seperately\n"); 587 case MISCREG_FPSCR_QC: 588 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 589 case MISCREG_FPSCR_EXC: 590 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 591 case MISCREG_FPSR: 592 { 593 const uint32_t ones = (uint32_t)(-1); 594 FPSCR fpscrMask = 0; 595 fpscrMask.ioc = ones; 596 fpscrMask.dzc = ones; 597 fpscrMask.ofc = ones; 598 fpscrMask.ufc = ones; 599 fpscrMask.ixc = ones; 600 fpscrMask.idc = ones; 601 fpscrMask.qc = ones; 602 fpscrMask.v = ones; 603 fpscrMask.c = ones; 604 fpscrMask.z = ones; 605 fpscrMask.n = ones; 606 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 607 } 608 case MISCREG_FPCR: 609 { 610 const uint32_t ones = (uint32_t)(-1); 611 FPSCR fpscrMask = 0; 612 fpscrMask.len = ones; 613 fpscrMask.fz16 = ones; 614 fpscrMask.stride = ones; 615 fpscrMask.rMode = ones; 616 fpscrMask.fz = ones; 617 fpscrMask.dn = ones; 618 fpscrMask.ahp = ones; 619 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 620 } 621 case MISCREG_NZCV: 622 { 623 CPSR cpsr = 0; 624 cpsr.nz = tc->readCCReg(CCREG_NZ); 625 cpsr.c = tc->readCCReg(CCREG_C); 626 cpsr.v = tc->readCCReg(CCREG_V); 627 return cpsr; 628 } 629 case MISCREG_DAIF: 630 { 631 CPSR cpsr = 0; 632 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 633 return cpsr; 634 } 635 case MISCREG_SP_EL0: 636 { 637 return tc->readIntReg(INTREG_SP0); 638 } 639 case MISCREG_SP_EL1: 640 { 641 return tc->readIntReg(INTREG_SP1); 642 } 643 case MISCREG_SP_EL2: 644 { 645 return tc->readIntReg(INTREG_SP2); 646 } 647 case MISCREG_SPSEL: 648 { 649 return miscRegs[MISCREG_CPSR] & 0x1; 650 } 651 case MISCREG_CURRENTEL: 652 { 653 return miscRegs[MISCREG_CPSR] & 0xc; 654 } 655 case MISCREG_PAN: 656 { 657 return miscRegs[MISCREG_CPSR] & 0x400000; 658 } 659 case MISCREG_L2CTLR: 660 { 661 // mostly unimplemented, just set NumCPUs field from sim and return 662 L2CTLR l2ctlr = 0; 663 // b00:1CPU to b11:4CPUs 664 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 665 return l2ctlr; 666 } 667 case MISCREG_DBGDIDR: 668 /* For now just implement the version number. 669 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 670 */ 671 return 0x5 << 16; 672 case MISCREG_DBGDSCRint: 673 return 0; 674 case MISCREG_ISR: 675 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 676 readMiscRegNoEffect(MISCREG_HCR), 677 readMiscRegNoEffect(MISCREG_CPSR), 678 readMiscRegNoEffect(MISCREG_SCR)); 679 case MISCREG_ISR_EL1: 680 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 681 readMiscRegNoEffect(MISCREG_HCR_EL2), 682 readMiscRegNoEffect(MISCREG_CPSR), 683 readMiscRegNoEffect(MISCREG_SCR_EL3)); 684 case MISCREG_DCZID_EL0: 685 return 0x04; // DC ZVA clear 64-byte chunks 686 case MISCREG_HCPTR: 687 { 688 RegVal val = readMiscRegNoEffect(misc_reg); 689 // The trap bit associated with CP14 is defined as RAZ 690 val &= ~(1 << 14); 691 // If a CP bit in NSACR is 0 then the corresponding bit in 692 // HCPTR is RAO/WI 693 bool secure_lookup = haveSecurity && 694 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 695 readMiscRegNoEffect(MISCREG_CPSR)); 696 if (!secure_lookup) { 697 RegVal mask = readMiscRegNoEffect(MISCREG_NSACR); 698 val |= (mask ^ 0x7FFF) & 0xBFFF; 699 } 700 // Set the bits for unimplemented coprocessors to RAO/WI 701 val |= 0x33FF; 702 return (val); 703 } 704 case MISCREG_HDFAR: // alias for secure DFAR 705 return readMiscRegNoEffect(MISCREG_DFAR_S); 706 case MISCREG_HIFAR: // alias for secure IFAR 707 return readMiscRegNoEffect(MISCREG_IFAR_S); 708 709 case MISCREG_ID_PFR0: 710 // !ThumbEE | !Jazelle | Thumb | ARM 711 return 0x00000031; 712 case MISCREG_ID_PFR1: 713 { // Timer | Virti | !M Profile | TrustZone | ARMv4 714 bool haveTimer = (system->getGenericTimer() != NULL); 715 return 0x00000001 716 | (haveSecurity ? 0x00000010 : 0x0) 717 | (haveVirtualization ? 0x00001000 : 0x0) 718 | (haveTimer ? 0x00010000 : 0x0); 719 } 720 case MISCREG_ID_AA64PFR0_EL1: 721 return 0x0000000000000002 | // AArch{64,32} supported at EL0 722 0x0000000000000020 | // EL1 723 (haveVirtualization ? 0x0000000000000200 : 0) | // EL2 724 (haveSecurity ? 0x0000000000002000 : 0) | // EL3 725 (haveSVE ? 0x0000000100000000 : 0) | // SVE 726 (haveGICv3CPUInterface ? 0x0000000001000000 : 0); 727 case MISCREG_ID_AA64PFR1_EL1: 728 return 0; // bits [63:0] RES0 (reserved for future use) 729 730 // Generic Timer registers 731 case MISCREG_CNTHV_CTL_EL2: 732 case MISCREG_CNTHV_CVAL_EL2: 733 case MISCREG_CNTHV_TVAL_EL2: 734 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 735 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 736 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 737 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 738 return getGenericTimer(tc).readMiscReg(misc_reg); 739 740 case MISCREG_ICC_AP0R0 ... MISCREG_ICH_LRC15: 741 case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3: 742 case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2: 743 return getGICv3CPUInterface(tc).readMiscReg(misc_reg); 744 745 default: 746 break; 747 748 } 749 return readMiscRegNoEffect(misc_reg); 750} 751 752void 753ISA::setMiscRegNoEffect(int misc_reg, RegVal val) 754{ 755 assert(misc_reg < NumMiscRegs); 756 757 const auto ® = lookUpMiscReg[misc_reg]; // bit masks 758 const auto &map = getMiscIndices(misc_reg); 759 int lower = map.first, upper = map.second; 760 761 auto v = (val & ~reg.wi()) | reg.rao(); 762 if (upper > 0) { 763 miscRegs[lower] = bits(v, 31, 0); 764 miscRegs[upper] = bits(v, 63, 32); 765 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 766 misc_reg, lower, upper, v); 767 } else { 768 miscRegs[lower] = v; 769 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 770 misc_reg, lower, v); 771 } 772} 773 774void 775ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) 776{ 777 778 RegVal newVal = val; 779 bool secure_lookup; 780 SCR scr; 781 782 if (misc_reg == MISCREG_CPSR) { 783 updateRegMap(val); 784 785 786 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 787 int old_mode = old_cpsr.mode; 788 CPSR cpsr = val; 789 if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) { 790 getITBPtr(tc)->invalidateMiscReg(); 791 getDTBPtr(tc)->invalidateMiscReg(); 792 } 793 794 if (cpsr.pan != old_cpsr.pan) { 795 getDTBPtr(tc)->invalidateMiscReg(); 796 } 797 798 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 799 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 800 PCState pc = tc->pcState(); 801 pc.nextThumb(cpsr.t); 802 pc.nextJazelle(cpsr.j); 803 pc.illegalExec(cpsr.il == 1); 804 805 tc->getDecoderPtr()->setSveLen((getCurSveVecLenInBits(tc) >> 7) - 1); 806 807 // Follow slightly different semantics if a CheckerCPU object 808 // is connected 809 CheckerCPU *checker = tc->getCheckerCpuPtr(); 810 if (checker) { 811 tc->pcStateNoRecord(pc); 812 } else { 813 tc->pcState(pc); 814 } 815 } else { 816#ifndef NDEBUG 817 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 818 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 819 warn("Unimplemented system register %s write with %#x.\n", 820 miscRegName[misc_reg], val); 821 else 822 panic("Unimplemented system register %s write with %#x.\n", 823 miscRegName[misc_reg], val); 824 } 825#endif 826 switch (unflattenMiscReg(misc_reg)) { 827 case MISCREG_CPACR: 828 { 829 830 const uint32_t ones = (uint32_t)(-1); 831 CPACR cpacrMask = 0; 832 // Only cp10, cp11, and ase are implemented, nothing else should 833 // be writable 834 cpacrMask.cp10 = ones; 835 cpacrMask.cp11 = ones; 836 cpacrMask.asedis = ones; 837 838 // Security Extensions may limit the writability of CPACR 839 if (haveSecurity) { 840 scr = readMiscRegNoEffect(MISCREG_SCR); 841 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 842 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 843 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 844 // NB: Skipping the full loop, here 845 if (!nsacr.cp10) cpacrMask.cp10 = 0; 846 if (!nsacr.cp11) cpacrMask.cp11 = 0; 847 } 848 } 849 850 RegVal old_val = readMiscRegNoEffect(MISCREG_CPACR); 851 newVal &= cpacrMask; 852 newVal |= old_val & ~cpacrMask; 853 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 854 miscRegName[misc_reg], newVal); 855 } 856 break; 857 case MISCREG_CPACR_EL1: 858 { 859 const uint32_t ones = (uint32_t)(-1); 860 CPACR cpacrMask = 0; 861 cpacrMask.tta = ones; 862 cpacrMask.fpen = ones; 863 if (haveSVE) { 864 cpacrMask.zen = ones; 865 } 866 newVal &= cpacrMask; 867 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 868 miscRegName[misc_reg], newVal); 869 } 870 break; 871 case MISCREG_CPTR_EL2: 872 { 873 const uint32_t ones = (uint32_t)(-1); 874 CPTR cptrMask = 0; 875 cptrMask.tcpac = ones; 876 cptrMask.tta = ones; 877 cptrMask.tfp = ones; 878 if (haveSVE) { 879 cptrMask.tz = ones; 880 } 881 newVal &= cptrMask; 882 cptrMask = 0; 883 cptrMask.res1_13_12_el2 = ones; 884 cptrMask.res1_7_0_el2 = ones; 885 if (!haveSVE) { 886 cptrMask.res1_8_el2 = ones; 887 } 888 cptrMask.res1_9_el2 = ones; 889 newVal |= cptrMask; 890 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 891 miscRegName[misc_reg], newVal); 892 } 893 break; 894 case MISCREG_CPTR_EL3: 895 { 896 const uint32_t ones = (uint32_t)(-1); 897 CPTR cptrMask = 0; 898 cptrMask.tcpac = ones; 899 cptrMask.tta = ones; 900 cptrMask.tfp = ones; 901 if (haveSVE) { 902 cptrMask.ez = ones; 903 } 904 newVal &= cptrMask; 905 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 906 miscRegName[misc_reg], newVal); 907 } 908 break; 909 case MISCREG_CSSELR: 910 warn_once("The csselr register isn't implemented.\n"); 911 return; 912 913 case MISCREG_DC_ZVA_Xt: 914 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 915 return; 916 917 case MISCREG_FPSCR: 918 { 919 const uint32_t ones = (uint32_t)(-1); 920 FPSCR fpscrMask = 0; 921 fpscrMask.ioc = ones; 922 fpscrMask.dzc = ones; 923 fpscrMask.ofc = ones; 924 fpscrMask.ufc = ones; 925 fpscrMask.ixc = ones; 926 fpscrMask.idc = ones; 927 fpscrMask.ioe = ones; 928 fpscrMask.dze = ones; 929 fpscrMask.ofe = ones; 930 fpscrMask.ufe = ones; 931 fpscrMask.ixe = ones; 932 fpscrMask.ide = ones; 933 fpscrMask.len = ones; 934 fpscrMask.fz16 = ones; 935 fpscrMask.stride = ones; 936 fpscrMask.rMode = ones; 937 fpscrMask.fz = ones; 938 fpscrMask.dn = ones; 939 fpscrMask.ahp = ones; 940 fpscrMask.qc = ones; 941 fpscrMask.v = ones; 942 fpscrMask.c = ones; 943 fpscrMask.z = ones; 944 fpscrMask.n = ones; 945 newVal = (newVal & (uint32_t)fpscrMask) | 946 (readMiscRegNoEffect(MISCREG_FPSCR) & 947 ~(uint32_t)fpscrMask); 948 tc->getDecoderPtr()->setContext(newVal); 949 } 950 break; 951 case MISCREG_FPSR: 952 { 953 const uint32_t ones = (uint32_t)(-1); 954 FPSCR fpscrMask = 0; 955 fpscrMask.ioc = ones; 956 fpscrMask.dzc = ones; 957 fpscrMask.ofc = ones; 958 fpscrMask.ufc = ones; 959 fpscrMask.ixc = ones; 960 fpscrMask.idc = ones; 961 fpscrMask.qc = ones; 962 fpscrMask.v = ones; 963 fpscrMask.c = ones; 964 fpscrMask.z = ones; 965 fpscrMask.n = ones; 966 newVal = (newVal & (uint32_t)fpscrMask) | 967 (readMiscRegNoEffect(MISCREG_FPSCR) & 968 ~(uint32_t)fpscrMask); 969 misc_reg = MISCREG_FPSCR; 970 } 971 break; 972 case MISCREG_FPCR: 973 { 974 const uint32_t ones = (uint32_t)(-1); 975 FPSCR fpscrMask = 0; 976 fpscrMask.len = ones; 977 fpscrMask.fz16 = ones; 978 fpscrMask.stride = ones; 979 fpscrMask.rMode = ones; 980 fpscrMask.fz = ones; 981 fpscrMask.dn = ones; 982 fpscrMask.ahp = ones; 983 newVal = (newVal & (uint32_t)fpscrMask) | 984 (readMiscRegNoEffect(MISCREG_FPSCR) & 985 ~(uint32_t)fpscrMask); 986 misc_reg = MISCREG_FPSCR; 987 } 988 break; 989 case MISCREG_CPSR_Q: 990 { 991 assert(!(newVal & ~CpsrMaskQ)); 992 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 993 misc_reg = MISCREG_CPSR; 994 } 995 break; 996 case MISCREG_FPSCR_QC: 997 { 998 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 999 (newVal & FpscrQcMask); 1000 misc_reg = MISCREG_FPSCR; 1001 } 1002 break; 1003 case MISCREG_FPSCR_EXC: 1004 { 1005 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 1006 (newVal & FpscrExcMask); 1007 misc_reg = MISCREG_FPSCR; 1008 } 1009 break; 1010 case MISCREG_FPEXC: 1011 { 1012 // vfpv3 architecture, section B.6.1 of DDI04068 1013 // bit 29 - valid only if fpexc[31] is 0 1014 const uint32_t fpexcMask = 0x60000000; 1015 newVal = (newVal & fpexcMask) | 1016 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 1017 } 1018 break; 1019 case MISCREG_HCR: 1020 { 1021 if (!haveVirtualization) 1022 return; 1023 } 1024 break; 1025 case MISCREG_IFSR: 1026 { 1027 // ARM ARM (ARM DDI 0406C.b) B4.1.96 1028 const uint32_t ifsrMask = 1029 mask(31, 13) | mask(11, 11) | mask(8, 6); 1030 newVal = newVal & ~ifsrMask; 1031 } 1032 break; 1033 case MISCREG_DFSR: 1034 { 1035 // ARM ARM (ARM DDI 0406C.b) B4.1.52 1036 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 1037 newVal = newVal & ~dfsrMask; 1038 } 1039 break; 1040 case MISCREG_AMAIR0: 1041 case MISCREG_AMAIR1: 1042 { 1043 // ARM ARM (ARM DDI 0406C.b) B4.1.5 1044 // Valid only with LPAE 1045 if (!haveLPAE) 1046 return; 1047 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 1048 } 1049 break; 1050 case MISCREG_SCR: 1051 getITBPtr(tc)->invalidateMiscReg(); 1052 getDTBPtr(tc)->invalidateMiscReg(); 1053 break; 1054 case MISCREG_SCTLR: 1055 { 1056 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 1057 scr = readMiscRegNoEffect(MISCREG_SCR); 1058 1059 MiscRegIndex sctlr_idx; 1060 if (haveSecurity && !highestELIs64 && !scr.ns) { 1061 sctlr_idx = MISCREG_SCTLR_S; 1062 } else { 1063 sctlr_idx = MISCREG_SCTLR_NS; 1064 } 1065 1066 SCTLR sctlr = miscRegs[sctlr_idx]; 1067 SCTLR new_sctlr = newVal; 1068 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 1069 miscRegs[sctlr_idx] = (RegVal)new_sctlr; 1070 getITBPtr(tc)->invalidateMiscReg(); 1071 getDTBPtr(tc)->invalidateMiscReg(); 1072 } 1073 case MISCREG_MIDR: 1074 case MISCREG_ID_PFR0: 1075 case MISCREG_ID_PFR1: 1076 case MISCREG_ID_DFR0: 1077 case MISCREG_ID_MMFR0: 1078 case MISCREG_ID_MMFR1: 1079 case MISCREG_ID_MMFR2: 1080 case MISCREG_ID_MMFR3: 1081 case MISCREG_ID_ISAR0: 1082 case MISCREG_ID_ISAR1: 1083 case MISCREG_ID_ISAR2: 1084 case MISCREG_ID_ISAR3: 1085 case MISCREG_ID_ISAR4: 1086 case MISCREG_ID_ISAR5: 1087 1088 case MISCREG_MPIDR: 1089 case MISCREG_FPSID: 1090 case MISCREG_TLBTR: 1091 case MISCREG_MVFR0: 1092 case MISCREG_MVFR1: 1093 1094 case MISCREG_ID_AA64AFR0_EL1: 1095 case MISCREG_ID_AA64AFR1_EL1: 1096 case MISCREG_ID_AA64DFR0_EL1: 1097 case MISCREG_ID_AA64DFR1_EL1: 1098 case MISCREG_ID_AA64ISAR0_EL1: 1099 case MISCREG_ID_AA64ISAR1_EL1: 1100 case MISCREG_ID_AA64MMFR0_EL1: 1101 case MISCREG_ID_AA64MMFR1_EL1: 1102 case MISCREG_ID_AA64MMFR2_EL1: 1103 case MISCREG_ID_AA64PFR0_EL1: 1104 case MISCREG_ID_AA64PFR1_EL1: 1105 // ID registers are constants. 1106 return; 1107 1108 // TLB Invalidate All 1109 case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 1110 { 1111 assert32(tc); 1112 scr = readMiscReg(MISCREG_SCR, tc); 1113 1114 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1115 tlbiOp(tc); 1116 return; 1117 } 1118 // TLB Invalidate All, Inner Shareable 1119 case MISCREG_TLBIALLIS: 1120 { 1121 assert32(tc); 1122 scr = readMiscReg(MISCREG_SCR, tc); 1123 1124 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1125 tlbiOp.broadcast(tc); 1126 return; 1127 } 1128 // Instruction TLB Invalidate All 1129 case MISCREG_ITLBIALL: 1130 { 1131 assert32(tc); 1132 scr = readMiscReg(MISCREG_SCR, tc); 1133 1134 ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1135 tlbiOp(tc); 1136 return; 1137 } 1138 // Data TLB Invalidate All 1139 case MISCREG_DTLBIALL: 1140 { 1141 assert32(tc); 1142 scr = readMiscReg(MISCREG_SCR, tc); 1143 1144 DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1145 tlbiOp(tc); 1146 return; 1147 } 1148 // TLB Invalidate by VA 1149 // mcr tlbimval(is) is invalidating all matching entries 1150 // regardless of the level of lookup, since in gem5 we cache 1151 // in the tlb the last level of lookup only. 1152 case MISCREG_TLBIMVA: 1153 case MISCREG_TLBIMVAL: 1154 { 1155 assert32(tc); 1156 scr = readMiscReg(MISCREG_SCR, tc); 1157 1158 TLBIMVA tlbiOp(EL1, 1159 haveSecurity && !scr.ns, 1160 mbits(newVal, 31, 12), 1161 bits(newVal, 7,0)); 1162 1163 tlbiOp(tc); 1164 return; 1165 } 1166 // TLB Invalidate by VA, Inner Shareable 1167 case MISCREG_TLBIMVAIS: 1168 case MISCREG_TLBIMVALIS: 1169 { 1170 assert32(tc); 1171 scr = readMiscReg(MISCREG_SCR, tc); 1172 1173 TLBIMVA tlbiOp(EL1, 1174 haveSecurity && !scr.ns, 1175 mbits(newVal, 31, 12), 1176 bits(newVal, 7,0)); 1177 1178 tlbiOp.broadcast(tc); 1179 return; 1180 } 1181 // TLB Invalidate by ASID match 1182 case MISCREG_TLBIASID: 1183 { 1184 assert32(tc); 1185 scr = readMiscReg(MISCREG_SCR, tc); 1186 1187 TLBIASID tlbiOp(EL1, 1188 haveSecurity && !scr.ns, 1189 bits(newVal, 7,0)); 1190 1191 tlbiOp(tc); 1192 return; 1193 } 1194 // TLB Invalidate by ASID match, Inner Shareable 1195 case MISCREG_TLBIASIDIS: 1196 { 1197 assert32(tc); 1198 scr = readMiscReg(MISCREG_SCR, tc); 1199 1200 TLBIASID tlbiOp(EL1, 1201 haveSecurity && !scr.ns, 1202 bits(newVal, 7,0)); 1203 1204 tlbiOp.broadcast(tc); 1205 return; 1206 } 1207 // mcr tlbimvaal(is) is invalidating all matching entries 1208 // regardless of the level of lookup, since in gem5 we cache 1209 // in the tlb the last level of lookup only. 1210 // TLB Invalidate by VA, All ASID 1211 case MISCREG_TLBIMVAA: 1212 case MISCREG_TLBIMVAAL: 1213 { 1214 assert32(tc); 1215 scr = readMiscReg(MISCREG_SCR, tc); 1216 1217 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1218 mbits(newVal, 31,12)); 1219 1220 tlbiOp(tc); 1221 return; 1222 } 1223 // TLB Invalidate by VA, All ASID, Inner Shareable 1224 case MISCREG_TLBIMVAAIS: 1225 case MISCREG_TLBIMVAALIS: 1226 { 1227 assert32(tc); 1228 scr = readMiscReg(MISCREG_SCR, tc); 1229 1230 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1231 mbits(newVal, 31,12)); 1232 1233 tlbiOp.broadcast(tc); 1234 return; 1235 } 1236 // mcr tlbimvalh(is) is invalidating all matching entries 1237 // regardless of the level of lookup, since in gem5 we cache 1238 // in the tlb the last level of lookup only. 1239 // TLB Invalidate by VA, Hyp mode 1240 case MISCREG_TLBIMVAH: 1241 case MISCREG_TLBIMVALH: 1242 { 1243 assert32(tc); 1244 scr = readMiscReg(MISCREG_SCR, tc); 1245 1246 TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns, 1247 mbits(newVal, 31,12)); 1248 1249 tlbiOp(tc); 1250 return; 1251 } 1252 // TLB Invalidate by VA, Hyp mode, Inner Shareable 1253 case MISCREG_TLBIMVAHIS: 1254 case MISCREG_TLBIMVALHIS: 1255 { 1256 assert32(tc); 1257 scr = readMiscReg(MISCREG_SCR, tc); 1258 1259 TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns, 1260 mbits(newVal, 31,12)); 1261 1262 tlbiOp.broadcast(tc); 1263 return; 1264 } 1265 // mcr tlbiipas2l(is) is invalidating all matching entries 1266 // regardless of the level of lookup, since in gem5 we cache 1267 // in the tlb the last level of lookup only. 1268 // TLB Invalidate by Intermediate Physical Address, Stage 2 1269 case MISCREG_TLBIIPAS2: 1270 case MISCREG_TLBIIPAS2L: 1271 { 1272 assert32(tc); 1273 scr = readMiscReg(MISCREG_SCR, tc); 1274 1275 TLBIIPA tlbiOp(EL1, 1276 haveSecurity && !scr.ns, 1277 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1278 1279 tlbiOp(tc); 1280 return; 1281 } 1282 // TLB Invalidate by Intermediate Physical Address, Stage 2, 1283 // Inner Shareable 1284 case MISCREG_TLBIIPAS2IS: 1285 case MISCREG_TLBIIPAS2LIS: 1286 { 1287 assert32(tc); 1288 scr = readMiscReg(MISCREG_SCR, tc); 1289 1290 TLBIIPA tlbiOp(EL1, 1291 haveSecurity && !scr.ns, 1292 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1293 1294 tlbiOp.broadcast(tc); 1295 return; 1296 } 1297 // Instruction TLB Invalidate by VA 1298 case MISCREG_ITLBIMVA: 1299 { 1300 assert32(tc); 1301 scr = readMiscReg(MISCREG_SCR, tc); 1302 1303 ITLBIMVA tlbiOp(EL1, 1304 haveSecurity && !scr.ns, 1305 mbits(newVal, 31, 12), 1306 bits(newVal, 7,0)); 1307 1308 tlbiOp(tc); 1309 return; 1310 } 1311 // Data TLB Invalidate by VA 1312 case MISCREG_DTLBIMVA: 1313 { 1314 assert32(tc); 1315 scr = readMiscReg(MISCREG_SCR, tc); 1316 1317 DTLBIMVA tlbiOp(EL1, 1318 haveSecurity && !scr.ns, 1319 mbits(newVal, 31, 12), 1320 bits(newVal, 7,0)); 1321 1322 tlbiOp(tc); 1323 return; 1324 } 1325 // Instruction TLB Invalidate by ASID match 1326 case MISCREG_ITLBIASID: 1327 { 1328 assert32(tc); 1329 scr = readMiscReg(MISCREG_SCR, tc); 1330 1331 ITLBIASID tlbiOp(EL1, 1332 haveSecurity && !scr.ns, 1333 bits(newVal, 7,0)); 1334 1335 tlbiOp(tc); 1336 return; 1337 } 1338 // Data TLB Invalidate by ASID match 1339 case MISCREG_DTLBIASID: 1340 { 1341 assert32(tc); 1342 scr = readMiscReg(MISCREG_SCR, tc); 1343 1344 DTLBIASID tlbiOp(EL1, 1345 haveSecurity && !scr.ns, 1346 bits(newVal, 7,0)); 1347 1348 tlbiOp(tc); 1349 return; 1350 } 1351 // TLB Invalidate All, Non-Secure Non-Hyp 1352 case MISCREG_TLBIALLNSNH: 1353 { 1354 assert32(tc); 1355 1356 TLBIALLN tlbiOp(EL1); 1357 tlbiOp(tc); 1358 return; 1359 } 1360 // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable 1361 case MISCREG_TLBIALLNSNHIS: 1362 { 1363 assert32(tc); 1364 1365 TLBIALLN tlbiOp(EL1); 1366 tlbiOp.broadcast(tc); 1367 return; 1368 } 1369 // TLB Invalidate All, Hyp mode 1370 case MISCREG_TLBIALLH: 1371 { 1372 assert32(tc); 1373 1374 TLBIALLN tlbiOp(EL2); 1375 tlbiOp(tc); 1376 return; 1377 } 1378 // TLB Invalidate All, Hyp mode, Inner Shareable 1379 case MISCREG_TLBIALLHIS: 1380 { 1381 assert32(tc); 1382 1383 TLBIALLN tlbiOp(EL2); 1384 tlbiOp.broadcast(tc); 1385 return; 1386 } 1387 // AArch64 TLB Invalidate All, EL3 1388 case MISCREG_TLBI_ALLE3: 1389 { 1390 assert64(tc); 1391 1392 TLBIALL tlbiOp(EL3, true); 1393 tlbiOp(tc); 1394 return; 1395 } 1396 // AArch64 TLB Invalidate All, EL3, Inner Shareable 1397 case MISCREG_TLBI_ALLE3IS: 1398 { 1399 assert64(tc); 1400 1401 TLBIALL tlbiOp(EL3, true); 1402 tlbiOp.broadcast(tc); 1403 return; 1404 } 1405 // AArch64 TLB Invalidate All, EL2, Inner Shareable 1406 case MISCREG_TLBI_ALLE2: 1407 case MISCREG_TLBI_ALLE2IS: 1408 { 1409 assert64(tc); 1410 scr = readMiscReg(MISCREG_SCR, tc); 1411 1412 TLBIALL tlbiOp(EL2, haveSecurity && !scr.ns); 1413 tlbiOp(tc); 1414 return; 1415 } 1416 // AArch64 TLB Invalidate All, EL1 1417 case MISCREG_TLBI_ALLE1: 1418 case MISCREG_TLBI_VMALLE1: 1419 case MISCREG_TLBI_VMALLS12E1: 1420 // @todo: handle VMID and stage 2 to enable Virtualization 1421 { 1422 assert64(tc); 1423 scr = readMiscReg(MISCREG_SCR, tc); 1424 1425 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1426 tlbiOp(tc); 1427 return; 1428 } 1429 // AArch64 TLB Invalidate All, EL1, Inner Shareable 1430 case MISCREG_TLBI_ALLE1IS: 1431 case MISCREG_TLBI_VMALLE1IS: 1432 case MISCREG_TLBI_VMALLS12E1IS: 1433 // @todo: handle VMID and stage 2 to enable Virtualization 1434 { 1435 assert64(tc); 1436 scr = readMiscReg(MISCREG_SCR, tc); 1437 1438 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1439 tlbiOp.broadcast(tc); 1440 return; 1441 } 1442 // VAEx(IS) and VALEx(IS) are the same because TLBs 1443 // only store entries 1444 // from the last level of translation table walks 1445 // @todo: handle VMID to enable Virtualization 1446 // AArch64 TLB Invalidate by VA, EL3 1447 case MISCREG_TLBI_VAE3_Xt: 1448 case MISCREG_TLBI_VALE3_Xt: 1449 { 1450 assert64(tc); 1451 1452 TLBIMVA tlbiOp(EL3, true, 1453 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1454 0xbeef); 1455 tlbiOp(tc); 1456 return; 1457 } 1458 // AArch64 TLB Invalidate by VA, EL3, Inner Shareable 1459 case MISCREG_TLBI_VAE3IS_Xt: 1460 case MISCREG_TLBI_VALE3IS_Xt: 1461 { 1462 assert64(tc); 1463 1464 TLBIMVA tlbiOp(EL3, true, 1465 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1466 0xbeef); 1467 1468 tlbiOp.broadcast(tc); 1469 return; 1470 } 1471 // AArch64 TLB Invalidate by VA, EL2 1472 case MISCREG_TLBI_VAE2_Xt: 1473 case MISCREG_TLBI_VALE2_Xt: 1474 { 1475 assert64(tc); 1476 scr = readMiscReg(MISCREG_SCR, tc); 1477 1478 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1479 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1480 0xbeef); 1481 tlbiOp(tc); 1482 return; 1483 } 1484 // AArch64 TLB Invalidate by VA, EL2, Inner Shareable 1485 case MISCREG_TLBI_VAE2IS_Xt: 1486 case MISCREG_TLBI_VALE2IS_Xt: 1487 { 1488 assert64(tc); 1489 scr = readMiscReg(MISCREG_SCR, tc); 1490 1491 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1492 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1493 0xbeef); 1494 1495 tlbiOp.broadcast(tc); 1496 return; 1497 } 1498 // AArch64 TLB Invalidate by VA, EL1 1499 case MISCREG_TLBI_VAE1_Xt: 1500 case MISCREG_TLBI_VALE1_Xt: 1501 { 1502 assert64(tc); 1503 scr = readMiscReg(MISCREG_SCR, tc); 1504 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1505 bits(newVal, 55, 48); 1506 1507 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1508 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1509 asid); 1510 1511 tlbiOp(tc); 1512 return; 1513 } 1514 // AArch64 TLB Invalidate by VA, EL1, Inner Shareable 1515 case MISCREG_TLBI_VAE1IS_Xt: 1516 case MISCREG_TLBI_VALE1IS_Xt: 1517 { 1518 assert64(tc); 1519 scr = readMiscReg(MISCREG_SCR, tc); 1520 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1521 bits(newVal, 55, 48); 1522 1523 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1524 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1525 asid); 1526 1527 tlbiOp.broadcast(tc); 1528 return; 1529 } 1530 // AArch64 TLB Invalidate by ASID, EL1 1531 // @todo: handle VMID to enable Virtualization 1532 case MISCREG_TLBI_ASIDE1_Xt: 1533 { 1534 assert64(tc); 1535 scr = readMiscReg(MISCREG_SCR, tc); 1536 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1537 bits(newVal, 55, 48); 1538 1539 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1540 tlbiOp(tc); 1541 return; 1542 } 1543 // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable 1544 case MISCREG_TLBI_ASIDE1IS_Xt: 1545 { 1546 assert64(tc); 1547 scr = readMiscReg(MISCREG_SCR, tc); 1548 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1549 bits(newVal, 55, 48); 1550 1551 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1552 tlbiOp.broadcast(tc); 1553 return; 1554 } 1555 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 1556 // entries from the last level of translation table walks 1557 // AArch64 TLB Invalidate by VA, All ASID, EL1 1558 case MISCREG_TLBI_VAAE1_Xt: 1559 case MISCREG_TLBI_VAALE1_Xt: 1560 { 1561 assert64(tc); 1562 scr = readMiscReg(MISCREG_SCR, tc); 1563 1564 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1565 static_cast<Addr>(bits(newVal, 43, 0)) << 12); 1566 1567 tlbiOp(tc); 1568 return; 1569 } 1570 // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable 1571 case MISCREG_TLBI_VAAE1IS_Xt: 1572 case MISCREG_TLBI_VAALE1IS_Xt: 1573 { 1574 assert64(tc); 1575 scr = readMiscReg(MISCREG_SCR, tc); 1576 1577 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1578 static_cast<Addr>(bits(newVal, 43, 0)) << 12); 1579 1580 tlbiOp.broadcast(tc); 1581 return; 1582 } 1583 // AArch64 TLB Invalidate by Intermediate Physical Address, 1584 // Stage 2, EL1 1585 case MISCREG_TLBI_IPAS2E1_Xt: 1586 case MISCREG_TLBI_IPAS2LE1_Xt: 1587 { 1588 assert64(tc); 1589 scr = readMiscReg(MISCREG_SCR, tc); 1590 1591 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1592 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1593 1594 tlbiOp(tc); 1595 return; 1596 } 1597 // AArch64 TLB Invalidate by Intermediate Physical Address, 1598 // Stage 2, EL1, Inner Shareable 1599 case MISCREG_TLBI_IPAS2E1IS_Xt: 1600 case MISCREG_TLBI_IPAS2LE1IS_Xt: 1601 { 1602 assert64(tc); 1603 scr = readMiscReg(MISCREG_SCR, tc); 1604 1605 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1606 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1607 1608 tlbiOp.broadcast(tc); 1609 return; 1610 } 1611 case MISCREG_ACTLR: 1612 warn("Not doing anything for write of miscreg ACTLR\n"); 1613 break; 1614 1615 case MISCREG_PMXEVTYPER_PMCCFILTR: 1616 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 1617 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 1618 case MISCREG_PMCR ... MISCREG_PMOVSSET: 1619 pmu->setMiscReg(misc_reg, newVal); 1620 break; 1621 1622 1623 case MISCREG_HSTR: // TJDBX, now redifined to be RES0 1624 { 1625 HSTR hstrMask = 0; 1626 hstrMask.tjdbx = 1; 1627 newVal &= ~((uint32_t) hstrMask); 1628 break; 1629 } 1630 case MISCREG_HCPTR: 1631 { 1632 // If a CP bit in NSACR is 0 then the corresponding bit in 1633 // HCPTR is RAO/WI. Same applies to NSASEDIS 1634 secure_lookup = haveSecurity && 1635 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 1636 readMiscRegNoEffect(MISCREG_CPSR)); 1637 if (!secure_lookup) { 1638 RegVal oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 1639 RegVal mask = 1640 (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 1641 newVal = (newVal & ~mask) | (oldValue & mask); 1642 } 1643 break; 1644 } 1645 case MISCREG_HDFAR: // alias for secure DFAR 1646 misc_reg = MISCREG_DFAR_S; 1647 break; 1648 case MISCREG_HIFAR: // alias for secure IFAR 1649 misc_reg = MISCREG_IFAR_S; 1650 break; 1651 case MISCREG_ATS1CPR: 1652 case MISCREG_ATS1CPW: 1653 case MISCREG_ATS1CUR: 1654 case MISCREG_ATS1CUW: 1655 case MISCREG_ATS12NSOPR: 1656 case MISCREG_ATS12NSOPW: 1657 case MISCREG_ATS12NSOUR: 1658 case MISCREG_ATS12NSOUW: 1659 case MISCREG_ATS1HR: 1660 case MISCREG_ATS1HW: 1661 { 1662 Request::Flags flags = 0; 1663 BaseTLB::Mode mode = BaseTLB::Read; 1664 TLB::ArmTranslationType tranType = TLB::NormalTran; 1665 Fault fault; 1666 switch(misc_reg) { 1667 case MISCREG_ATS1CPR: 1668 flags = TLB::MustBeOne; 1669 tranType = TLB::S1CTran; 1670 mode = BaseTLB::Read; 1671 break; 1672 case MISCREG_ATS1CPW: 1673 flags = TLB::MustBeOne; 1674 tranType = TLB::S1CTran; 1675 mode = BaseTLB::Write; 1676 break; 1677 case MISCREG_ATS1CUR: 1678 flags = TLB::MustBeOne | TLB::UserMode; 1679 tranType = TLB::S1CTran; 1680 mode = BaseTLB::Read; 1681 break; 1682 case MISCREG_ATS1CUW: 1683 flags = TLB::MustBeOne | TLB::UserMode; 1684 tranType = TLB::S1CTran; 1685 mode = BaseTLB::Write; 1686 break; 1687 case MISCREG_ATS12NSOPR: 1688 if (!haveSecurity) 1689 panic("Security Extensions required for ATS12NSOPR"); 1690 flags = TLB::MustBeOne; 1691 tranType = TLB::S1S2NsTran; 1692 mode = BaseTLB::Read; 1693 break; 1694 case MISCREG_ATS12NSOPW: 1695 if (!haveSecurity) 1696 panic("Security Extensions required for ATS12NSOPW"); 1697 flags = TLB::MustBeOne; 1698 tranType = TLB::S1S2NsTran; 1699 mode = BaseTLB::Write; 1700 break; 1701 case MISCREG_ATS12NSOUR: 1702 if (!haveSecurity) 1703 panic("Security Extensions required for ATS12NSOUR"); 1704 flags = TLB::MustBeOne | TLB::UserMode; 1705 tranType = TLB::S1S2NsTran; 1706 mode = BaseTLB::Read; 1707 break; 1708 case MISCREG_ATS12NSOUW: 1709 if (!haveSecurity) 1710 panic("Security Extensions required for ATS12NSOUW"); 1711 flags = TLB::MustBeOne | TLB::UserMode; 1712 tranType = TLB::S1S2NsTran; 1713 mode = BaseTLB::Write; 1714 break; 1715 case MISCREG_ATS1HR: // only really useful from secure mode. 1716 flags = TLB::MustBeOne; 1717 tranType = TLB::HypMode; 1718 mode = BaseTLB::Read; 1719 break; 1720 case MISCREG_ATS1HW: 1721 flags = TLB::MustBeOne; 1722 tranType = TLB::HypMode; 1723 mode = BaseTLB::Write; 1724 break; 1725 } 1726 // If we're in timing mode then doing the translation in 1727 // functional mode then we're slightly distorting performance 1728 // results obtained from simulations. The translation should be 1729 // done in the same mode the core is running in. NOTE: This 1730 // can't be an atomic translation because that causes problems 1731 // with unexpected atomic snoop requests. 1732 warn("Translating via %s in functional mode! Fix Me!\n", 1733 miscRegName[misc_reg]); 1734 1735 auto req = std::make_shared<Request>( 1736 0, val, 0, flags, Request::funcMasterId, 1737 tc->pcState().pc(), tc->contextId()); 1738 1739 fault = getDTBPtr(tc)->translateFunctional( 1740 req, tc, mode, tranType); 1741 1742 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1743 HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 1744 1745 RegVal newVal; 1746 if (fault == NoFault) { 1747 Addr paddr = req->getPaddr(); 1748 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 1749 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 1750 newVal = (paddr & mask(39, 12)) | 1751 (getDTBPtr(tc)->getAttr()); 1752 } else { 1753 newVal = (paddr & 0xfffff000) | 1754 (getDTBPtr(tc)->getAttr()); 1755 } 1756 DPRINTF(MiscRegs, 1757 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 1758 val, newVal); 1759 } else { 1760 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1761 armFault->update(tc); 1762 // Set fault bit and FSR 1763 FSR fsr = armFault->getFsr(tc); 1764 1765 newVal = ((fsr >> 9) & 1) << 11; 1766 if (newVal) { 1767 // LPAE - rearange fault status 1768 newVal |= ((fsr >> 0) & 0x3f) << 1; 1769 } else { 1770 // VMSA - rearange fault status 1771 newVal |= ((fsr >> 0) & 0xf) << 1; 1772 newVal |= ((fsr >> 10) & 0x1) << 5; 1773 newVal |= ((fsr >> 12) & 0x1) << 6; 1774 } 1775 newVal |= 0x1; // F bit 1776 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1777 newVal |= armFault->isStage2() ? 0x200 : 0; 1778 DPRINTF(MiscRegs, 1779 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 1780 val, fsr, newVal); 1781 } 1782 setMiscRegNoEffect(MISCREG_PAR, newVal); 1783 return; 1784 } 1785 case MISCREG_TTBCR: 1786 { 1787 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1788 const uint32_t ones = (uint32_t)(-1); 1789 TTBCR ttbcrMask = 0; 1790 TTBCR ttbcrNew = newVal; 1791 1792 // ARM DDI 0406C.b, ARMv7-32 1793 ttbcrMask.n = ones; // T0SZ 1794 if (haveSecurity) { 1795 ttbcrMask.pd0 = ones; 1796 ttbcrMask.pd1 = ones; 1797 } 1798 ttbcrMask.epd0 = ones; 1799 ttbcrMask.irgn0 = ones; 1800 ttbcrMask.orgn0 = ones; 1801 ttbcrMask.sh0 = ones; 1802 ttbcrMask.ps = ones; // T1SZ 1803 ttbcrMask.a1 = ones; 1804 ttbcrMask.epd1 = ones; 1805 ttbcrMask.irgn1 = ones; 1806 ttbcrMask.orgn1 = ones; 1807 ttbcrMask.sh1 = ones; 1808 if (haveLPAE) 1809 ttbcrMask.eae = ones; 1810 1811 if (haveLPAE && ttbcrNew.eae) { 1812 newVal = newVal & ttbcrMask; 1813 } else { 1814 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 1815 } 1816 // Invalidate TLB MiscReg 1817 getITBPtr(tc)->invalidateMiscReg(); 1818 getDTBPtr(tc)->invalidateMiscReg(); 1819 break; 1820 } 1821 case MISCREG_TTBR0: 1822 case MISCREG_TTBR1: 1823 { 1824 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1825 if (haveLPAE) { 1826 if (ttbcr.eae) { 1827 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 1828 // ARMv8 AArch32 bit 63-56 only 1829 uint64_t ttbrMask = mask(63,56) | mask(47,40); 1830 newVal = (newVal & (~ttbrMask)); 1831 } 1832 } 1833 // Invalidate TLB MiscReg 1834 getITBPtr(tc)->invalidateMiscReg(); 1835 getDTBPtr(tc)->invalidateMiscReg(); 1836 break; 1837 } 1838 case MISCREG_SCTLR_EL1: 1839 case MISCREG_CONTEXTIDR: 1840 case MISCREG_PRRR: 1841 case MISCREG_NMRR: 1842 case MISCREG_MAIR0: 1843 case MISCREG_MAIR1: 1844 case MISCREG_DACR: 1845 case MISCREG_VTTBR: 1846 case MISCREG_SCR_EL3: 1847 case MISCREG_HCR_EL2: 1848 case MISCREG_TCR_EL1: 1849 case MISCREG_TCR_EL2: 1850 case MISCREG_TCR_EL3: 1851 case MISCREG_SCTLR_EL2: 1852 case MISCREG_SCTLR_EL3: 1853 case MISCREG_HSCTLR: 1854 case MISCREG_TTBR0_EL1: 1855 case MISCREG_TTBR1_EL1: 1856 case MISCREG_TTBR0_EL2: 1857 case MISCREG_TTBR1_EL2: 1858 case MISCREG_TTBR0_EL3: 1859 getITBPtr(tc)->invalidateMiscReg(); 1860 getDTBPtr(tc)->invalidateMiscReg(); 1861 break; 1862 case MISCREG_NZCV: 1863 { 1864 CPSR cpsr = val; 1865 1866 tc->setCCReg(CCREG_NZ, cpsr.nz); 1867 tc->setCCReg(CCREG_C, cpsr.c); 1868 tc->setCCReg(CCREG_V, cpsr.v); 1869 } 1870 break; 1871 case MISCREG_DAIF: 1872 { 1873 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1874 cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 1875 newVal = cpsr; 1876 misc_reg = MISCREG_CPSR; 1877 } 1878 break; 1879 case MISCREG_SP_EL0: 1880 tc->setIntReg(INTREG_SP0, newVal); 1881 break; 1882 case MISCREG_SP_EL1: 1883 tc->setIntReg(INTREG_SP1, newVal); 1884 break; 1885 case MISCREG_SP_EL2: 1886 tc->setIntReg(INTREG_SP2, newVal); 1887 break; 1888 case MISCREG_SPSEL: 1889 { 1890 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1891 cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 1892 newVal = cpsr; 1893 misc_reg = MISCREG_CPSR; 1894 } 1895 break; 1896 case MISCREG_CURRENTEL: 1897 { 1898 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1899 cpsr.el = (uint8_t) ((CPSR) newVal).el; 1900 newVal = cpsr; 1901 misc_reg = MISCREG_CPSR; 1902 } 1903 break; 1904 case MISCREG_PAN: 1905 { 1906 // PAN is affecting data accesses 1907 getDTBPtr(tc)->invalidateMiscReg(); 1908 1909 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1910 cpsr.pan = (uint8_t) ((CPSR) newVal).pan; 1911 newVal = cpsr; 1912 misc_reg = MISCREG_CPSR; 1913 } 1914 break; 1915 case MISCREG_AT_S1E1R_Xt: 1916 case MISCREG_AT_S1E1W_Xt: 1917 case MISCREG_AT_S1E0R_Xt: 1918 case MISCREG_AT_S1E0W_Xt: 1919 case MISCREG_AT_S1E2R_Xt: 1920 case MISCREG_AT_S1E2W_Xt: 1921 case MISCREG_AT_S12E1R_Xt: 1922 case MISCREG_AT_S12E1W_Xt: 1923 case MISCREG_AT_S12E0R_Xt: 1924 case MISCREG_AT_S12E0W_Xt: 1925 case MISCREG_AT_S1E3R_Xt: 1926 case MISCREG_AT_S1E3W_Xt: 1927 { 1928 RequestPtr req = std::make_shared<Request>(); 1929 Request::Flags flags = 0; 1930 BaseTLB::Mode mode = BaseTLB::Read; 1931 TLB::ArmTranslationType tranType = TLB::NormalTran; 1932 Fault fault; 1933 switch(misc_reg) { 1934 case MISCREG_AT_S1E1R_Xt: 1935 flags = TLB::MustBeOne; 1936 tranType = TLB::S1E1Tran; 1937 mode = BaseTLB::Read; 1938 break; 1939 case MISCREG_AT_S1E1W_Xt: 1940 flags = TLB::MustBeOne; 1941 tranType = TLB::S1E1Tran; 1942 mode = BaseTLB::Write; 1943 break; 1944 case MISCREG_AT_S1E0R_Xt: 1945 flags = TLB::MustBeOne | TLB::UserMode; 1946 tranType = TLB::S1E0Tran; 1947 mode = BaseTLB::Read; 1948 break; 1949 case MISCREG_AT_S1E0W_Xt: 1950 flags = TLB::MustBeOne | TLB::UserMode; 1951 tranType = TLB::S1E0Tran; 1952 mode = BaseTLB::Write; 1953 break; 1954 case MISCREG_AT_S1E2R_Xt: 1955 flags = TLB::MustBeOne; 1956 tranType = TLB::S1E2Tran; 1957 mode = BaseTLB::Read; 1958 break; 1959 case MISCREG_AT_S1E2W_Xt: 1960 flags = TLB::MustBeOne; 1961 tranType = TLB::S1E2Tran; 1962 mode = BaseTLB::Write; 1963 break; 1964 case MISCREG_AT_S12E0R_Xt: 1965 flags = TLB::MustBeOne | TLB::UserMode; 1966 tranType = TLB::S12E0Tran; 1967 mode = BaseTLB::Read; 1968 break; 1969 case MISCREG_AT_S12E0W_Xt: 1970 flags = TLB::MustBeOne | TLB::UserMode; 1971 tranType = TLB::S12E0Tran; 1972 mode = BaseTLB::Write; 1973 break; 1974 case MISCREG_AT_S12E1R_Xt: 1975 flags = TLB::MustBeOne; 1976 tranType = TLB::S12E1Tran; 1977 mode = BaseTLB::Read; 1978 break; 1979 case MISCREG_AT_S12E1W_Xt: 1980 flags = TLB::MustBeOne; 1981 tranType = TLB::S12E1Tran; 1982 mode = BaseTLB::Write; 1983 break; 1984 case MISCREG_AT_S1E3R_Xt: 1985 flags = TLB::MustBeOne; 1986 tranType = TLB::S1E3Tran; 1987 mode = BaseTLB::Read; 1988 break; 1989 case MISCREG_AT_S1E3W_Xt: 1990 flags = TLB::MustBeOne; 1991 tranType = TLB::S1E3Tran; 1992 mode = BaseTLB::Write; 1993 break; 1994 } 1995 // If we're in timing mode then doing the translation in 1996 // functional mode then we're slightly distorting performance 1997 // results obtained from simulations. The translation should be 1998 // done in the same mode the core is running in. NOTE: This 1999 // can't be an atomic translation because that causes problems 2000 // with unexpected atomic snoop requests. 2001 warn("Translating via %s in functional mode! Fix Me!\n", 2002 miscRegName[misc_reg]); 2003 2004 req->setVirt(0, val, 0, flags, Request::funcMasterId, 2005 tc->pcState().pc()); 2006 req->setContext(tc->contextId()); 2007 fault = getDTBPtr(tc)->translateFunctional(req, tc, mode, 2008 tranType); 2009 2010 RegVal newVal; 2011 if (fault == NoFault) { 2012 Addr paddr = req->getPaddr(); 2013 uint64_t attr = getDTBPtr(tc)->getAttr(); 2014 uint64_t attr1 = attr >> 56; 2015 if (!attr1 || attr1 ==0x44) { 2016 attr |= 0x100; 2017 attr &= ~ uint64_t(0x80); 2018 } 2019 newVal = (paddr & mask(47, 12)) | attr; 2020 DPRINTF(MiscRegs, 2021 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 2022 val, newVal); 2023 } else { 2024 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 2025 armFault->update(tc); 2026 // Set fault bit and FSR 2027 FSR fsr = armFault->getFsr(tc); 2028 2029 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 2030 if (cpsr.width) { // AArch32 2031 newVal = ((fsr >> 9) & 1) << 11; 2032 // rearrange fault status 2033 newVal |= ((fsr >> 0) & 0x3f) << 1; 2034 newVal |= 0x1; // F bit 2035 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 2036 newVal |= armFault->isStage2() ? 0x200 : 0; 2037 } else { // AArch64 2038 newVal = 1; // F bit 2039 newVal |= fsr << 1; // FST 2040 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit. 2041 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 2042 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 2043 newVal |= 1 << 11; // RES1 2044 } 2045 DPRINTF(MiscRegs, 2046 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 2047 val, fsr, newVal); 2048 } 2049 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 2050 return; 2051 } 2052 case MISCREG_SPSR_EL3: 2053 case MISCREG_SPSR_EL2: 2054 case MISCREG_SPSR_EL1: 2055 { 2056 RegVal spsr_mask = havePAN ? 2057 ~(0x5 << 21) : ~(0x7 << 21); 2058 2059 newVal = val & spsr_mask; 2060 break; 2061 } 2062 case MISCREG_L2CTLR: 2063 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 2064 miscRegName[misc_reg], uint32_t(val)); 2065 break; 2066 2067 // Generic Timer registers 2068 case MISCREG_CNTHV_CTL_EL2: 2069 case MISCREG_CNTHV_CVAL_EL2: 2070 case MISCREG_CNTHV_TVAL_EL2: 2071 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 2072 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 2073 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 2074 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 2075 getGenericTimer(tc).setMiscReg(misc_reg, newVal); 2076 break; 2077 case MISCREG_ICC_AP0R0 ... MISCREG_ICH_LRC15: 2078 case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3: 2079 case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2: 2080 getGICv3CPUInterface(tc).setMiscReg(misc_reg, newVal); 2081 return; 2082 case MISCREG_ZCR_EL3: 2083 case MISCREG_ZCR_EL2: 2084 case MISCREG_ZCR_EL1: 2085 tc->getDecoderPtr()->setSveLen( 2086 (getCurSveVecLenInBits(tc) >> 7) - 1); 2087 break; 2088 } 2089 } 2090 setMiscRegNoEffect(misc_reg, newVal); 2091} 2092 2093BaseISADevice & 2094ISA::getGenericTimer(ThreadContext *tc) 2095{ 2096 // We only need to create an ISA interface the first time we try 2097 // to access the timer. 2098 if (timer) 2099 return *timer.get(); 2100 2101 assert(system); 2102 GenericTimer *generic_timer(system->getGenericTimer()); 2103 if (!generic_timer) { 2104 panic("Trying to get a generic timer from a system that hasn't " 2105 "been configured to use a generic timer.\n"); 2106 } 2107 2108 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 2109 timer->setThreadContext(tc); 2110 2111 return *timer.get(); 2112} 2113 2114BaseISADevice & 2115ISA::getGICv3CPUInterface(ThreadContext *tc) 2116{ 2117 panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!"); 2118 return *gicv3CpuInterface.get(); 2119} 2120 2121unsigned 2122ISA::getCurSveVecLenInBits(ThreadContext *tc) const 2123{ 2124 if (!FullSystem) { 2125 return sveVL * 128; 2126 } 2127 2128 panic_if(!tc, 2129 "A ThreadContext is needed to determine the SVE vector length " 2130 "in full-system mode"); 2131 2132 CPSR cpsr = miscRegs[MISCREG_CPSR]; 2133 ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el; 2134 2135 unsigned len = 0; 2136 2137 if (el == EL1 || (el == EL0 && !ELIsInHost(tc, el))) { 2138 len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL1]).len; 2139 } 2140 2141 if (el == EL2 || (el == EL0 && ELIsInHost(tc, el))) { 2142 len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL2]).len; 2143 } else if (haveVirtualization && !inSecureState(tc) && 2144 (el == EL0 || el == EL1)) { 2145 len = std::min( 2146 len, 2147 static_cast<unsigned>( 2148 static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL2]).len)); 2149 } 2150 2151 if (el == EL3) { 2152 len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL3]).len; 2153 } else if (haveSecurity) { 2154 len = std::min( 2155 len, 2156 static_cast<unsigned>( 2157 static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL3]).len)); 2158 } 2159 2160 len = std::min(len, sveVL - 1); 2161 2162 return (len + 1) * 128; 2163} 2164 2165void 2166ISA::zeroSveVecRegUpperPart(VecRegContainer &vc, unsigned eCount) 2167{ 2168 auto vv = vc.as<uint64_t>(); 2169 for (int i = 2; i < eCount; ++i) { 2170 vv[i] = 0; 2171 } 2172} 2173 2174} // namespace ArmISA 2175 2176ArmISA::ISA * 2177ArmISAParams::create() 2178{ 2179 return new ArmISA::ISA(this); 2180} 2181