isa.cc revision 14228
1/*
2 * Copyright (c) 2010-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 *          Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42#include "arch/arm/pmu.hh"
43#include "arch/arm/system.hh"
44#include "arch/arm/tlb.hh"
45#include "arch/arm/tlbi_op.hh"
46#include "cpu/base.hh"
47#include "cpu/checker/cpu.hh"
48#include "debug/Arm.hh"
49#include "debug/MiscRegs.hh"
50#include "dev/arm/generic_timer.hh"
51#include "dev/arm/gic_v3.hh"
52#include "dev/arm/gic_v3_cpu_interface.hh"
53#include "params/ArmISA.hh"
54#include "sim/faults.hh"
55#include "sim/stat_control.hh"
56#include "sim/system.hh"
57
58namespace ArmISA
59{
60
61ISA::ISA(Params *p)
62    : SimObject(p),
63      system(NULL),
64      _decoderFlavour(p->decoderFlavour),
65      _vecRegRenameMode(Enums::Full),
66      pmu(p->pmu),
67      haveGICv3CPUInterface(false),
68      impdefAsNop(p->impdef_nop),
69      afterStartup(false)
70{
71    miscRegs[MISCREG_SCTLR_RST] = 0;
72
73    // Hook up a dummy device if we haven't been configured with a
74    // real PMU. By using a dummy device, we don't need to check that
75    // the PMU exist every time we try to access a PMU register.
76    if (!pmu)
77        pmu = &dummyDevice;
78
79    // Give all ISA devices a pointer to this ISA
80    pmu->setISA(this);
81
82    system = dynamic_cast<ArmSystem *>(p->system);
83
84    // Cache system-level properties
85    if (FullSystem && system) {
86        highestELIs64 = system->highestELIs64();
87        haveSecurity = system->haveSecurity();
88        haveLPAE = system->haveLPAE();
89        haveCrypto = system->haveCrypto();
90        haveVirtualization = system->haveVirtualization();
91        haveLargeAsid64 = system->haveLargeAsid64();
92        physAddrRange = system->physAddrRange();
93        haveSVE = system->haveSVE();
94        havePAN = system->havePAN();
95        sveVL = system->sveVL();
96        haveLSE = system->haveLSE();
97    } else {
98        highestELIs64 = true; // ArmSystem::highestELIs64 does the same
99        haveSecurity = haveLPAE = haveVirtualization = false;
100        haveCrypto = true;
101        haveLargeAsid64 = false;
102        physAddrRange = 32;  // dummy value
103        haveSVE = true;
104        havePAN = false;
105        sveVL = p->sve_vl_se;
106        haveLSE = true;
107    }
108
109    // Initial rename mode depends on highestEL
110    const_cast<Enums::VecRegRenameMode&>(_vecRegRenameMode) =
111        highestELIs64 ? Enums::Full : Enums::Elem;
112
113    initializeMiscRegMetadata();
114    preUnflattenMiscReg();
115
116    clear();
117}
118
119std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS);
120
121const ArmISAParams *
122ISA::params() const
123{
124    return dynamic_cast<const Params *>(_params);
125}
126
127void
128ISA::clear()
129{
130    const Params *p(params());
131
132    SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
133    memset(miscRegs, 0, sizeof(miscRegs));
134
135    initID32(p);
136
137    // We always initialize AArch64 ID registers even
138    // if we are in AArch32. This is done since if we
139    // are in SE mode we don't know if our ArmProcess is
140    // AArch32 or AArch64
141    initID64(p);
142
143    // Start with an event in the mailbox
144    miscRegs[MISCREG_SEV_MAILBOX] = 1;
145
146    // Separate Instruction and Data TLBs
147    miscRegs[MISCREG_TLBTR] = 1;
148
149    MVFR0 mvfr0 = 0;
150    mvfr0.advSimdRegisters = 2;
151    mvfr0.singlePrecision = 2;
152    mvfr0.doublePrecision = 2;
153    mvfr0.vfpExceptionTrapping = 0;
154    mvfr0.divide = 1;
155    mvfr0.squareRoot = 1;
156    mvfr0.shortVectors = 1;
157    mvfr0.roundingModes = 1;
158    miscRegs[MISCREG_MVFR0] = mvfr0;
159
160    MVFR1 mvfr1 = 0;
161    mvfr1.flushToZero = 1;
162    mvfr1.defaultNaN = 1;
163    mvfr1.advSimdLoadStore = 1;
164    mvfr1.advSimdInteger = 1;
165    mvfr1.advSimdSinglePrecision = 1;
166    mvfr1.advSimdHalfPrecision = 1;
167    mvfr1.vfpHalfPrecision = 1;
168    miscRegs[MISCREG_MVFR1] = mvfr1;
169
170    // Reset values of PRRR and NMRR are implementation dependent
171
172    // @todo: PRRR and NMRR in secure state?
173    miscRegs[MISCREG_PRRR_NS] =
174        (1 << 19) | // 19
175        (0 << 18) | // 18
176        (0 << 17) | // 17
177        (1 << 16) | // 16
178        (2 << 14) | // 15:14
179        (0 << 12) | // 13:12
180        (2 << 10) | // 11:10
181        (2 << 8)  | // 9:8
182        (2 << 6)  | // 7:6
183        (2 << 4)  | // 5:4
184        (1 << 2)  | // 3:2
185        0;          // 1:0
186
187    miscRegs[MISCREG_NMRR_NS] =
188        (1 << 30) | // 31:30
189        (0 << 26) | // 27:26
190        (0 << 24) | // 25:24
191        (3 << 22) | // 23:22
192        (2 << 20) | // 21:20
193        (0 << 18) | // 19:18
194        (0 << 16) | // 17:16
195        (1 << 14) | // 15:14
196        (0 << 12) | // 13:12
197        (2 << 10) | // 11:10
198        (0 << 8)  | // 9:8
199        (3 << 6)  | // 7:6
200        (2 << 4)  | // 5:4
201        (0 << 2)  | // 3:2
202        0;          // 1:0
203
204    if (FullSystem && system->highestELIs64()) {
205        // Initialize AArch64 state
206        clear64(p);
207        return;
208    }
209
210    // Initialize AArch32 state...
211    clear32(p, sctlr_rst);
212}
213
214void
215ISA::clear32(const ArmISAParams *p, const SCTLR &sctlr_rst)
216{
217    CPSR cpsr = 0;
218    cpsr.mode = MODE_USER;
219
220    if (FullSystem) {
221        miscRegs[MISCREG_MVBAR] = system->resetAddr();
222    }
223
224    miscRegs[MISCREG_CPSR] = cpsr;
225    updateRegMap(cpsr);
226
227    SCTLR sctlr = 0;
228    sctlr.te = (bool) sctlr_rst.te;
229    sctlr.nmfi = (bool) sctlr_rst.nmfi;
230    sctlr.v = (bool) sctlr_rst.v;
231    sctlr.u = 1;
232    sctlr.xp = 1;
233    sctlr.rao2 = 1;
234    sctlr.rao3 = 1;
235    sctlr.rao4 = 0xf;  // SCTLR[6:3]
236    sctlr.uci = 1;
237    sctlr.dze = 1;
238    miscRegs[MISCREG_SCTLR_NS] = sctlr;
239    miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
240    miscRegs[MISCREG_HCPTR] = 0;
241
242    miscRegs[MISCREG_CPACR] = 0;
243
244    miscRegs[MISCREG_FPSID] = p->fpsid;
245
246    if (haveLPAE) {
247        TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS];
248        ttbcr.eae = 0;
249        miscRegs[MISCREG_TTBCR_NS] = ttbcr;
250        // Enforce consistency with system-level settings
251        miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5;
252    }
253
254    if (haveSecurity) {
255        miscRegs[MISCREG_SCTLR_S] = sctlr;
256        miscRegs[MISCREG_SCR] = 0;
257        miscRegs[MISCREG_VBAR_S] = 0;
258    } else {
259        // we're always non-secure
260        miscRegs[MISCREG_SCR] = 1;
261    }
262
263    //XXX We need to initialize the rest of the state.
264}
265
266void
267ISA::clear64(const ArmISAParams *p)
268{
269    CPSR cpsr = 0;
270    Addr rvbar = system->resetAddr();
271    switch (system->highestEL()) {
272        // Set initial EL to highest implemented EL using associated stack
273        // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
274        // value
275      case EL3:
276        cpsr.mode = MODE_EL3H;
277        miscRegs[MISCREG_RVBAR_EL3] = rvbar;
278        break;
279      case EL2:
280        cpsr.mode = MODE_EL2H;
281        miscRegs[MISCREG_RVBAR_EL2] = rvbar;
282        break;
283      case EL1:
284        cpsr.mode = MODE_EL1H;
285        miscRegs[MISCREG_RVBAR_EL1] = rvbar;
286        break;
287      default:
288        panic("Invalid highest implemented exception level");
289        break;
290    }
291
292    // Initialize rest of CPSR
293    cpsr.daif = 0xf;  // Mask all interrupts
294    cpsr.ss = 0;
295    cpsr.il = 0;
296    miscRegs[MISCREG_CPSR] = cpsr;
297    updateRegMap(cpsr);
298
299    // Initialize other control registers
300    miscRegs[MISCREG_MPIDR_EL1] = 0x80000000;
301    if (haveSecurity) {
302        miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830;
303        miscRegs[MISCREG_SCR_EL3]   = 0x00000030;  // RES1 fields
304    } else if (haveVirtualization) {
305        // also  MISCREG_SCTLR_EL2 (by mapping)
306        miscRegs[MISCREG_HSCTLR] = 0x30c50830;
307    } else {
308        // also  MISCREG_SCTLR_EL1 (by mapping)
309        miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init
310        // Always non-secure
311        miscRegs[MISCREG_SCR_EL3] = 1;
312    }
313}
314
315void
316ISA::initID32(const ArmISAParams *p)
317{
318    // Initialize configurable default values
319    miscRegs[MISCREG_MIDR] = p->midr;
320    miscRegs[MISCREG_MIDR_EL1] = p->midr;
321    miscRegs[MISCREG_VPIDR] = p->midr;
322
323    miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
324    miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
325    miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
326    miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
327    miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
328    miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
329
330    miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
331    miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
332    miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
333    miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
334
335    miscRegs[MISCREG_ID_ISAR5] = insertBits(
336        miscRegs[MISCREG_ID_ISAR5], 19, 4,
337        haveCrypto ? 0x1112 : 0x0);
338}
339
340void
341ISA::initID64(const ArmISAParams *p)
342{
343    // Initialize configurable id registers
344    miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1;
345    miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1;
346    miscRegs[MISCREG_ID_AA64DFR0_EL1] =
347        (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) |
348        (p->pmu ?             0x0000000000000100ULL : 0); // Enable PMUv3
349
350    miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1;
351    miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1;
352    miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1;
353    miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1;
354    miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1;
355    miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p->id_aa64mmfr2_el1;
356
357    miscRegs[MISCREG_ID_DFR0_EL1] =
358        (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3
359
360    miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1];
361
362    // SVE
363    miscRegs[MISCREG_ID_AA64ZFR0_EL1] = 0;  // SVEver 0
364    if (haveSecurity) {
365        miscRegs[MISCREG_ZCR_EL3] = sveVL - 1;
366    } else if (haveVirtualization) {
367        miscRegs[MISCREG_ZCR_EL2] = sveVL - 1;
368    } else {
369        miscRegs[MISCREG_ZCR_EL1] = sveVL - 1;
370    }
371
372    // Enforce consistency with system-level settings...
373
374    // EL3
375    miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
376        miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12,
377        haveSecurity ? 0x2 : 0x0);
378    // EL2
379    miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
380        miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8,
381        haveVirtualization ? 0x2 : 0x0);
382    // SVE
383    miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
384        miscRegs[MISCREG_ID_AA64PFR0_EL1], 35, 32,
385        haveSVE ? 0x1 : 0x0);
386    // Large ASID support
387    miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
388        miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4,
389        haveLargeAsid64 ? 0x2 : 0x0);
390    // Physical address size
391    miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
392        miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0,
393        encodePhysAddrRange64(physAddrRange));
394    // Crypto
395    miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
396        miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4,
397        haveCrypto ? 0x1112 : 0x0);
398    // LSE
399    miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
400        miscRegs[MISCREG_ID_AA64ISAR0_EL1], 23, 20,
401        haveLSE ? 0x2 : 0x0);
402    // PAN
403    miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
404        miscRegs[MISCREG_ID_AA64MMFR1_EL1], 23, 20,
405        havePAN ? 0x1 : 0x0);
406}
407
408void
409ISA::startup(ThreadContext *tc)
410{
411    pmu->setThreadContext(tc);
412
413    if (system) {
414        Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC());
415        if (gicv3) {
416            haveGICv3CPUInterface = true;
417            gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
418            gicv3CpuInterface->setISA(this);
419            gicv3CpuInterface->setThreadContext(tc);
420        }
421    }
422
423    afterStartup = true;
424}
425
426
427RegVal
428ISA::readMiscRegNoEffect(int misc_reg) const
429{
430    assert(misc_reg < NumMiscRegs);
431
432    const auto &reg = lookUpMiscReg[misc_reg]; // bit masks
433    const auto &map = getMiscIndices(misc_reg);
434    int lower = map.first, upper = map.second;
435    // NB!: apply architectural masks according to desired register,
436    // despite possibly getting value from different (mapped) register.
437    auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32))
438                                          |(miscRegs[upper] << 32));
439    if (val & reg.res0()) {
440        DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n",
441                miscRegName[misc_reg], val & reg.res0());
442    }
443    if ((val & reg.res1()) != reg.res1()) {
444        DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n",
445                miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1());
446    }
447    return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao
448}
449
450
451RegVal
452ISA::readMiscReg(int misc_reg, ThreadContext *tc)
453{
454    CPSR cpsr = 0;
455    PCState pc = 0;
456    SCR scr = 0;
457
458    if (misc_reg == MISCREG_CPSR) {
459        cpsr = miscRegs[misc_reg];
460        pc = tc->pcState();
461        cpsr.j = pc.jazelle() ? 1 : 0;
462        cpsr.t = pc.thumb() ? 1 : 0;
463        return cpsr;
464    }
465
466#ifndef NDEBUG
467    if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
468        if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
469            warn("Unimplemented system register %s read.\n",
470                 miscRegName[misc_reg]);
471        else
472            panic("Unimplemented system register %s read.\n",
473                  miscRegName[misc_reg]);
474    }
475#endif
476
477    switch (unflattenMiscReg(misc_reg)) {
478      case MISCREG_HCR:
479        {
480            if (!haveVirtualization)
481                return 0;
482            else
483                return readMiscRegNoEffect(MISCREG_HCR);
484        }
485      case MISCREG_CPACR:
486        {
487            const uint32_t ones = (uint32_t)(-1);
488            CPACR cpacrMask = 0;
489            // Only cp10, cp11, and ase are implemented, nothing else should
490            // be readable? (straight copy from the write code)
491            cpacrMask.cp10 = ones;
492            cpacrMask.cp11 = ones;
493            cpacrMask.asedis = ones;
494
495            // Security Extensions may limit the readability of CPACR
496            if (haveSecurity) {
497                scr = readMiscRegNoEffect(MISCREG_SCR);
498                cpsr = readMiscRegNoEffect(MISCREG_CPSR);
499                if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) {
500                    NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
501                    // NB: Skipping the full loop, here
502                    if (!nsacr.cp10) cpacrMask.cp10 = 0;
503                    if (!nsacr.cp11) cpacrMask.cp11 = 0;
504                }
505            }
506            RegVal val = readMiscRegNoEffect(MISCREG_CPACR);
507            val &= cpacrMask;
508            DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n",
509                    miscRegName[misc_reg], val);
510            return val;
511        }
512      case MISCREG_MPIDR:
513      case MISCREG_MPIDR_EL1:
514        return readMPIDR(system, tc);
515      case MISCREG_VMPIDR:
516      case MISCREG_VMPIDR_EL2:
517        // top bit defined as RES1
518        return readMiscRegNoEffect(misc_reg) | 0x80000000;
519      case MISCREG_ID_AFR0: // not implemented, so alias MIDR
520      case MISCREG_REVIDR:  // not implemented, so alias MIDR
521      case MISCREG_MIDR:
522        cpsr = readMiscRegNoEffect(MISCREG_CPSR);
523        scr  = readMiscRegNoEffect(MISCREG_SCR);
524        if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) {
525            return readMiscRegNoEffect(misc_reg);
526        } else {
527            return readMiscRegNoEffect(MISCREG_VPIDR);
528        }
529        break;
530      case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI
531      case MISCREG_JMCR:  // Jazelle trivial implementation, RAZ/WI
532      case MISCREG_JIDR:  // Jazelle trivial implementation, RAZ/WI
533      case MISCREG_AIDR:  // AUX ID set to 0
534      case MISCREG_TCMTR: // No TCM's
535        return 0;
536
537      case MISCREG_CLIDR:
538        warn_once("The clidr register always reports 0 caches.\n");
539        warn_once("clidr LoUIS field of 0b001 to match current "
540                  "ARM implementations.\n");
541        return 0x00200000;
542      case MISCREG_CCSIDR:
543        warn_once("The ccsidr register isn't implemented and "
544                "always reads as 0.\n");
545        break;
546      case MISCREG_CTR:                 // AArch32, ARMv7, top bit set
547      case MISCREG_CTR_EL0:             // AArch64
548        {
549            //all caches have the same line size in gem5
550            //4 byte words in ARM
551            unsigned lineSizeWords =
552                tc->getSystemPtr()->cacheLineSize() / 4;
553            unsigned log2LineSizeWords = 0;
554
555            while (lineSizeWords >>= 1) {
556                ++log2LineSizeWords;
557            }
558
559            CTR ctr = 0;
560            //log2 of minimun i-cache line size (words)
561            ctr.iCacheLineSize = log2LineSizeWords;
562            //b11 - gem5 uses pipt
563            ctr.l1IndexPolicy = 0x3;
564            //log2 of minimum d-cache line size (words)
565            ctr.dCacheLineSize = log2LineSizeWords;
566            //log2 of max reservation size (words)
567            ctr.erg = log2LineSizeWords;
568            //log2 of max writeback size (words)
569            ctr.cwg = log2LineSizeWords;
570            //b100 - gem5 format is ARMv7
571            ctr.format = 0x4;
572
573            return ctr;
574        }
575      case MISCREG_ACTLR:
576        warn("Not doing anything for miscreg ACTLR\n");
577        break;
578
579      case MISCREG_PMXEVTYPER_PMCCFILTR:
580      case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
581      case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
582      case MISCREG_PMCR ... MISCREG_PMOVSSET:
583        return pmu->readMiscReg(misc_reg);
584
585      case MISCREG_CPSR_Q:
586        panic("shouldn't be reading this register seperately\n");
587      case MISCREG_FPSCR_QC:
588        return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
589      case MISCREG_FPSCR_EXC:
590        return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
591      case MISCREG_FPSR:
592        {
593            const uint32_t ones = (uint32_t)(-1);
594            FPSCR fpscrMask = 0;
595            fpscrMask.ioc = ones;
596            fpscrMask.dzc = ones;
597            fpscrMask.ofc = ones;
598            fpscrMask.ufc = ones;
599            fpscrMask.ixc = ones;
600            fpscrMask.idc = ones;
601            fpscrMask.qc = ones;
602            fpscrMask.v = ones;
603            fpscrMask.c = ones;
604            fpscrMask.z = ones;
605            fpscrMask.n = ones;
606            return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
607        }
608      case MISCREG_FPCR:
609        {
610            const uint32_t ones = (uint32_t)(-1);
611            FPSCR fpscrMask  = 0;
612            fpscrMask.len    = ones;
613            fpscrMask.fz16   = ones;
614            fpscrMask.stride = ones;
615            fpscrMask.rMode  = ones;
616            fpscrMask.fz     = ones;
617            fpscrMask.dn     = ones;
618            fpscrMask.ahp    = ones;
619            return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
620        }
621      case MISCREG_NZCV:
622        {
623            CPSR cpsr = 0;
624            cpsr.nz   = tc->readCCReg(CCREG_NZ);
625            cpsr.c    = tc->readCCReg(CCREG_C);
626            cpsr.v    = tc->readCCReg(CCREG_V);
627            return cpsr;
628        }
629      case MISCREG_DAIF:
630        {
631            CPSR cpsr = 0;
632            cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif;
633            return cpsr;
634        }
635      case MISCREG_SP_EL0:
636        {
637            return tc->readIntReg(INTREG_SP0);
638        }
639      case MISCREG_SP_EL1:
640        {
641            return tc->readIntReg(INTREG_SP1);
642        }
643      case MISCREG_SP_EL2:
644        {
645            return tc->readIntReg(INTREG_SP2);
646        }
647      case MISCREG_SPSEL:
648        {
649            return miscRegs[MISCREG_CPSR] & 0x1;
650        }
651      case MISCREG_CURRENTEL:
652        {
653            return miscRegs[MISCREG_CPSR] & 0xc;
654        }
655      case MISCREG_PAN:
656        {
657            return miscRegs[MISCREG_CPSR] & 0x400000;
658        }
659      case MISCREG_L2CTLR:
660        {
661            // mostly unimplemented, just set NumCPUs field from sim and return
662            L2CTLR l2ctlr = 0;
663            // b00:1CPU to b11:4CPUs
664            l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1;
665            return l2ctlr;
666        }
667      case MISCREG_DBGDIDR:
668        /* For now just implement the version number.
669         * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
670         */
671        return 0x5 << 16;
672      case MISCREG_DBGDSCRint:
673        return 0;
674      case MISCREG_ISR:
675        return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR(
676            readMiscRegNoEffect(MISCREG_HCR),
677            readMiscRegNoEffect(MISCREG_CPSR),
678            readMiscRegNoEffect(MISCREG_SCR));
679      case MISCREG_ISR_EL1:
680        return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR(
681            readMiscRegNoEffect(MISCREG_HCR_EL2),
682            readMiscRegNoEffect(MISCREG_CPSR),
683            readMiscRegNoEffect(MISCREG_SCR_EL3));
684      case MISCREG_DCZID_EL0:
685        return 0x04;  // DC ZVA clear 64-byte chunks
686      case MISCREG_HCPTR:
687        {
688            RegVal val = readMiscRegNoEffect(misc_reg);
689            // The trap bit associated with CP14 is defined as RAZ
690            val &= ~(1 << 14);
691            // If a CP bit in NSACR is 0 then the corresponding bit in
692            // HCPTR is RAO/WI
693            bool secure_lookup = haveSecurity &&
694                inSecureState(readMiscRegNoEffect(MISCREG_SCR),
695                              readMiscRegNoEffect(MISCREG_CPSR));
696            if (!secure_lookup) {
697                RegVal mask = readMiscRegNoEffect(MISCREG_NSACR);
698                val |= (mask ^ 0x7FFF) & 0xBFFF;
699            }
700            // Set the bits for unimplemented coprocessors to RAO/WI
701            val |= 0x33FF;
702            return (val);
703        }
704      case MISCREG_HDFAR: // alias for secure DFAR
705        return readMiscRegNoEffect(MISCREG_DFAR_S);
706      case MISCREG_HIFAR: // alias for secure IFAR
707        return readMiscRegNoEffect(MISCREG_IFAR_S);
708
709      case MISCREG_ID_PFR0:
710        // !ThumbEE | !Jazelle | Thumb | ARM
711        return 0x00000031;
712      case MISCREG_ID_PFR1:
713        {   // Timer | Virti | !M Profile | TrustZone | ARMv4
714            bool haveTimer = (system->getGenericTimer() != NULL);
715            return 0x00000001
716                 | (haveSecurity       ? 0x00000010 : 0x0)
717                 | (haveVirtualization ? 0x00001000 : 0x0)
718                 | (haveTimer          ? 0x00010000 : 0x0);
719        }
720      case MISCREG_ID_AA64PFR0_EL1:
721        return 0x0000000000000002 | // AArch{64,32} supported at EL0
722               0x0000000000000020                               | // EL1
723               (haveVirtualization    ? 0x0000000000000200 : 0) | // EL2
724               (haveSecurity          ? 0x0000000000002000 : 0) | // EL3
725               (haveSVE               ? 0x0000000100000000 : 0) | // SVE
726               (haveGICv3CPUInterface ? 0x0000000001000000 : 0);
727      case MISCREG_ID_AA64PFR1_EL1:
728        return 0; // bits [63:0] RES0 (reserved for future use)
729
730      // Generic Timer registers
731      case MISCREG_CNTHV_CTL_EL2:
732      case MISCREG_CNTHV_CVAL_EL2:
733      case MISCREG_CNTHV_TVAL_EL2:
734      case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
735      case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
736      case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:
737      case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1:
738        return getGenericTimer(tc).readMiscReg(misc_reg);
739
740      case MISCREG_ICC_AP0R0 ... MISCREG_ICH_LRC15:
741      case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3:
742      case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2:
743        return getGICv3CPUInterface(tc).readMiscReg(misc_reg);
744
745      default:
746        break;
747
748    }
749    return readMiscRegNoEffect(misc_reg);
750}
751
752void
753ISA::setMiscRegNoEffect(int misc_reg, RegVal val)
754{
755    assert(misc_reg < NumMiscRegs);
756
757    const auto &reg = lookUpMiscReg[misc_reg]; // bit masks
758    const auto &map = getMiscIndices(misc_reg);
759    int lower = map.first, upper = map.second;
760
761    auto v = (val & ~reg.wi()) | reg.rao();
762    if (upper > 0) {
763        miscRegs[lower] = bits(v, 31, 0);
764        miscRegs[upper] = bits(v, 63, 32);
765        DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n",
766                misc_reg, lower, upper, v);
767    } else {
768        miscRegs[lower] = v;
769        DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n",
770                misc_reg, lower, v);
771    }
772}
773
774void
775ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
776{
777
778    RegVal newVal = val;
779    bool secure_lookup;
780    SCR scr;
781
782    if (misc_reg == MISCREG_CPSR) {
783        updateRegMap(val);
784
785
786        CPSR old_cpsr = miscRegs[MISCREG_CPSR];
787        int old_mode = old_cpsr.mode;
788        CPSR cpsr = val;
789        if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) {
790            getITBPtr(tc)->invalidateMiscReg();
791            getDTBPtr(tc)->invalidateMiscReg();
792        }
793
794        DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
795                miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
796        PCState pc = tc->pcState();
797        pc.nextThumb(cpsr.t);
798        pc.nextJazelle(cpsr.j);
799        pc.illegalExec(cpsr.il == 1);
800
801        tc->getDecoderPtr()->setSveLen((getCurSveVecLenInBits(tc) >> 7) - 1);
802
803        // Follow slightly different semantics if a CheckerCPU object
804        // is connected
805        CheckerCPU *checker = tc->getCheckerCpuPtr();
806        if (checker) {
807            tc->pcStateNoRecord(pc);
808        } else {
809            tc->pcState(pc);
810        }
811    } else {
812#ifndef NDEBUG
813        if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
814            if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
815                warn("Unimplemented system register %s write with %#x.\n",
816                    miscRegName[misc_reg], val);
817            else
818                panic("Unimplemented system register %s write with %#x.\n",
819                    miscRegName[misc_reg], val);
820        }
821#endif
822        switch (unflattenMiscReg(misc_reg)) {
823          case MISCREG_CPACR:
824            {
825
826                const uint32_t ones = (uint32_t)(-1);
827                CPACR cpacrMask = 0;
828                // Only cp10, cp11, and ase are implemented, nothing else should
829                // be writable
830                cpacrMask.cp10 = ones;
831                cpacrMask.cp11 = ones;
832                cpacrMask.asedis = ones;
833
834                // Security Extensions may limit the writability of CPACR
835                if (haveSecurity) {
836                    scr = readMiscRegNoEffect(MISCREG_SCR);
837                    CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR);
838                    if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) {
839                        NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
840                        // NB: Skipping the full loop, here
841                        if (!nsacr.cp10) cpacrMask.cp10 = 0;
842                        if (!nsacr.cp11) cpacrMask.cp11 = 0;
843                    }
844                }
845
846                RegVal old_val = readMiscRegNoEffect(MISCREG_CPACR);
847                newVal &= cpacrMask;
848                newVal |= old_val & ~cpacrMask;
849                DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
850                        miscRegName[misc_reg], newVal);
851            }
852            break;
853          case MISCREG_CPACR_EL1:
854            {
855                const uint32_t ones = (uint32_t)(-1);
856                CPACR cpacrMask = 0;
857                cpacrMask.tta = ones;
858                cpacrMask.fpen = ones;
859                if (haveSVE) {
860                    cpacrMask.zen = ones;
861                }
862                newVal &= cpacrMask;
863                DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
864                        miscRegName[misc_reg], newVal);
865            }
866            break;
867          case MISCREG_CPTR_EL2:
868            {
869                const uint32_t ones = (uint32_t)(-1);
870                CPTR cptrMask = 0;
871                cptrMask.tcpac = ones;
872                cptrMask.tta = ones;
873                cptrMask.tfp = ones;
874                if (haveSVE) {
875                    cptrMask.tz = ones;
876                }
877                newVal &= cptrMask;
878                cptrMask = 0;
879                cptrMask.res1_13_12_el2 = ones;
880                cptrMask.res1_7_0_el2 = ones;
881                if (!haveSVE) {
882                    cptrMask.res1_8_el2 = ones;
883                }
884                cptrMask.res1_9_el2 = ones;
885                newVal |= cptrMask;
886                DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
887                        miscRegName[misc_reg], newVal);
888            }
889            break;
890          case MISCREG_CPTR_EL3:
891            {
892                const uint32_t ones = (uint32_t)(-1);
893                CPTR cptrMask = 0;
894                cptrMask.tcpac = ones;
895                cptrMask.tta = ones;
896                cptrMask.tfp = ones;
897                if (haveSVE) {
898                    cptrMask.ez = ones;
899                }
900                newVal &= cptrMask;
901                DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
902                        miscRegName[misc_reg], newVal);
903            }
904            break;
905          case MISCREG_CSSELR:
906            warn_once("The csselr register isn't implemented.\n");
907            return;
908
909          case MISCREG_DC_ZVA_Xt:
910            warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n");
911            return;
912
913          case MISCREG_FPSCR:
914            {
915                const uint32_t ones = (uint32_t)(-1);
916                FPSCR fpscrMask = 0;
917                fpscrMask.ioc = ones;
918                fpscrMask.dzc = ones;
919                fpscrMask.ofc = ones;
920                fpscrMask.ufc = ones;
921                fpscrMask.ixc = ones;
922                fpscrMask.idc = ones;
923                fpscrMask.ioe = ones;
924                fpscrMask.dze = ones;
925                fpscrMask.ofe = ones;
926                fpscrMask.ufe = ones;
927                fpscrMask.ixe = ones;
928                fpscrMask.ide = ones;
929                fpscrMask.len = ones;
930                fpscrMask.fz16 = ones;
931                fpscrMask.stride = ones;
932                fpscrMask.rMode = ones;
933                fpscrMask.fz = ones;
934                fpscrMask.dn = ones;
935                fpscrMask.ahp = ones;
936                fpscrMask.qc = ones;
937                fpscrMask.v = ones;
938                fpscrMask.c = ones;
939                fpscrMask.z = ones;
940                fpscrMask.n = ones;
941                newVal = (newVal & (uint32_t)fpscrMask) |
942                         (readMiscRegNoEffect(MISCREG_FPSCR) &
943                          ~(uint32_t)fpscrMask);
944                tc->getDecoderPtr()->setContext(newVal);
945            }
946            break;
947          case MISCREG_FPSR:
948            {
949                const uint32_t ones = (uint32_t)(-1);
950                FPSCR fpscrMask = 0;
951                fpscrMask.ioc = ones;
952                fpscrMask.dzc = ones;
953                fpscrMask.ofc = ones;
954                fpscrMask.ufc = ones;
955                fpscrMask.ixc = ones;
956                fpscrMask.idc = ones;
957                fpscrMask.qc = ones;
958                fpscrMask.v = ones;
959                fpscrMask.c = ones;
960                fpscrMask.z = ones;
961                fpscrMask.n = ones;
962                newVal = (newVal & (uint32_t)fpscrMask) |
963                         (readMiscRegNoEffect(MISCREG_FPSCR) &
964                          ~(uint32_t)fpscrMask);
965                misc_reg = MISCREG_FPSCR;
966            }
967            break;
968          case MISCREG_FPCR:
969            {
970                const uint32_t ones = (uint32_t)(-1);
971                FPSCR fpscrMask  = 0;
972                fpscrMask.len    = ones;
973                fpscrMask.fz16   = ones;
974                fpscrMask.stride = ones;
975                fpscrMask.rMode  = ones;
976                fpscrMask.fz     = ones;
977                fpscrMask.dn     = ones;
978                fpscrMask.ahp    = ones;
979                newVal = (newVal & (uint32_t)fpscrMask) |
980                         (readMiscRegNoEffect(MISCREG_FPSCR) &
981                          ~(uint32_t)fpscrMask);
982                misc_reg = MISCREG_FPSCR;
983            }
984            break;
985          case MISCREG_CPSR_Q:
986            {
987                assert(!(newVal & ~CpsrMaskQ));
988                newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal;
989                misc_reg = MISCREG_CPSR;
990            }
991            break;
992          case MISCREG_FPSCR_QC:
993            {
994                newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
995                         (newVal & FpscrQcMask);
996                misc_reg = MISCREG_FPSCR;
997            }
998            break;
999          case MISCREG_FPSCR_EXC:
1000            {
1001                newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
1002                         (newVal & FpscrExcMask);
1003                misc_reg = MISCREG_FPSCR;
1004            }
1005            break;
1006          case MISCREG_FPEXC:
1007            {
1008                // vfpv3 architecture, section B.6.1 of DDI04068
1009                // bit 29 - valid only if fpexc[31] is 0
1010                const uint32_t fpexcMask = 0x60000000;
1011                newVal = (newVal & fpexcMask) |
1012                         (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask);
1013            }
1014            break;
1015          case MISCREG_HCR:
1016            {
1017                if (!haveVirtualization)
1018                    return;
1019            }
1020            break;
1021          case MISCREG_IFSR:
1022            {
1023                // ARM ARM (ARM DDI 0406C.b) B4.1.96
1024                const uint32_t ifsrMask =
1025                    mask(31, 13) | mask(11, 11) | mask(8, 6);
1026                newVal = newVal & ~ifsrMask;
1027            }
1028            break;
1029          case MISCREG_DFSR:
1030            {
1031                // ARM ARM (ARM DDI 0406C.b) B4.1.52
1032                const uint32_t dfsrMask = mask(31, 14) | mask(8, 8);
1033                newVal = newVal & ~dfsrMask;
1034            }
1035            break;
1036          case MISCREG_AMAIR0:
1037          case MISCREG_AMAIR1:
1038            {
1039                // ARM ARM (ARM DDI 0406C.b) B4.1.5
1040                // Valid only with LPAE
1041                if (!haveLPAE)
1042                    return;
1043                DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal);
1044            }
1045            break;
1046          case MISCREG_SCR:
1047            getITBPtr(tc)->invalidateMiscReg();
1048            getDTBPtr(tc)->invalidateMiscReg();
1049            break;
1050          case MISCREG_SCTLR:
1051            {
1052                DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
1053                scr = readMiscRegNoEffect(MISCREG_SCR);
1054
1055                MiscRegIndex sctlr_idx;
1056                if (haveSecurity && !highestELIs64 && !scr.ns) {
1057                    sctlr_idx = MISCREG_SCTLR_S;
1058                } else {
1059                    sctlr_idx =  MISCREG_SCTLR_NS;
1060                }
1061
1062                SCTLR sctlr = miscRegs[sctlr_idx];
1063                SCTLR new_sctlr = newVal;
1064                new_sctlr.nmfi =  ((bool)sctlr.nmfi) && !haveVirtualization;
1065                miscRegs[sctlr_idx] = (RegVal)new_sctlr;
1066                getITBPtr(tc)->invalidateMiscReg();
1067                getDTBPtr(tc)->invalidateMiscReg();
1068            }
1069          case MISCREG_MIDR:
1070          case MISCREG_ID_PFR0:
1071          case MISCREG_ID_PFR1:
1072          case MISCREG_ID_DFR0:
1073          case MISCREG_ID_MMFR0:
1074          case MISCREG_ID_MMFR1:
1075          case MISCREG_ID_MMFR2:
1076          case MISCREG_ID_MMFR3:
1077          case MISCREG_ID_ISAR0:
1078          case MISCREG_ID_ISAR1:
1079          case MISCREG_ID_ISAR2:
1080          case MISCREG_ID_ISAR3:
1081          case MISCREG_ID_ISAR4:
1082          case MISCREG_ID_ISAR5:
1083
1084          case MISCREG_MPIDR:
1085          case MISCREG_FPSID:
1086          case MISCREG_TLBTR:
1087          case MISCREG_MVFR0:
1088          case MISCREG_MVFR1:
1089
1090          case MISCREG_ID_AA64AFR0_EL1:
1091          case MISCREG_ID_AA64AFR1_EL1:
1092          case MISCREG_ID_AA64DFR0_EL1:
1093          case MISCREG_ID_AA64DFR1_EL1:
1094          case MISCREG_ID_AA64ISAR0_EL1:
1095          case MISCREG_ID_AA64ISAR1_EL1:
1096          case MISCREG_ID_AA64MMFR0_EL1:
1097          case MISCREG_ID_AA64MMFR1_EL1:
1098          case MISCREG_ID_AA64MMFR2_EL1:
1099          case MISCREG_ID_AA64PFR0_EL1:
1100          case MISCREG_ID_AA64PFR1_EL1:
1101            // ID registers are constants.
1102            return;
1103
1104          // TLB Invalidate All
1105          case MISCREG_TLBIALL: // TLBI all entries, EL0&1,
1106            {
1107                assert32(tc);
1108                scr = readMiscReg(MISCREG_SCR, tc);
1109
1110                TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1111                tlbiOp(tc);
1112                return;
1113            }
1114          // TLB Invalidate All, Inner Shareable
1115          case MISCREG_TLBIALLIS:
1116            {
1117                assert32(tc);
1118                scr = readMiscReg(MISCREG_SCR, tc);
1119
1120                TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1121                tlbiOp.broadcast(tc);
1122                return;
1123            }
1124          // Instruction TLB Invalidate All
1125          case MISCREG_ITLBIALL:
1126            {
1127                assert32(tc);
1128                scr = readMiscReg(MISCREG_SCR, tc);
1129
1130                ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1131                tlbiOp(tc);
1132                return;
1133            }
1134          // Data TLB Invalidate All
1135          case MISCREG_DTLBIALL:
1136            {
1137                assert32(tc);
1138                scr = readMiscReg(MISCREG_SCR, tc);
1139
1140                DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1141                tlbiOp(tc);
1142                return;
1143            }
1144          // TLB Invalidate by VA
1145          // mcr tlbimval(is) is invalidating all matching entries
1146          // regardless of the level of lookup, since in gem5 we cache
1147          // in the tlb the last level of lookup only.
1148          case MISCREG_TLBIMVA:
1149          case MISCREG_TLBIMVAL:
1150            {
1151                assert32(tc);
1152                scr = readMiscReg(MISCREG_SCR, tc);
1153
1154                TLBIMVA tlbiOp(EL1,
1155                               haveSecurity && !scr.ns,
1156                               mbits(newVal, 31, 12),
1157                               bits(newVal, 7,0));
1158
1159                tlbiOp(tc);
1160                return;
1161            }
1162          // TLB Invalidate by VA, Inner Shareable
1163          case MISCREG_TLBIMVAIS:
1164          case MISCREG_TLBIMVALIS:
1165            {
1166                assert32(tc);
1167                scr = readMiscReg(MISCREG_SCR, tc);
1168
1169                TLBIMVA tlbiOp(EL1,
1170                               haveSecurity && !scr.ns,
1171                               mbits(newVal, 31, 12),
1172                               bits(newVal, 7,0));
1173
1174                tlbiOp.broadcast(tc);
1175                return;
1176            }
1177          // TLB Invalidate by ASID match
1178          case MISCREG_TLBIASID:
1179            {
1180                assert32(tc);
1181                scr = readMiscReg(MISCREG_SCR, tc);
1182
1183                TLBIASID tlbiOp(EL1,
1184                                haveSecurity && !scr.ns,
1185                                bits(newVal, 7,0));
1186
1187                tlbiOp(tc);
1188                return;
1189            }
1190          // TLB Invalidate by ASID match, Inner Shareable
1191          case MISCREG_TLBIASIDIS:
1192            {
1193                assert32(tc);
1194                scr = readMiscReg(MISCREG_SCR, tc);
1195
1196                TLBIASID tlbiOp(EL1,
1197                                haveSecurity && !scr.ns,
1198                                bits(newVal, 7,0));
1199
1200                tlbiOp.broadcast(tc);
1201                return;
1202            }
1203          // mcr tlbimvaal(is) is invalidating all matching entries
1204          // regardless of the level of lookup, since in gem5 we cache
1205          // in the tlb the last level of lookup only.
1206          // TLB Invalidate by VA, All ASID
1207          case MISCREG_TLBIMVAA:
1208          case MISCREG_TLBIMVAAL:
1209            {
1210                assert32(tc);
1211                scr = readMiscReg(MISCREG_SCR, tc);
1212
1213                TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1214                                mbits(newVal, 31,12));
1215
1216                tlbiOp(tc);
1217                return;
1218            }
1219          // TLB Invalidate by VA, All ASID, Inner Shareable
1220          case MISCREG_TLBIMVAAIS:
1221          case MISCREG_TLBIMVAALIS:
1222            {
1223                assert32(tc);
1224                scr = readMiscReg(MISCREG_SCR, tc);
1225
1226                TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1227                                mbits(newVal, 31,12));
1228
1229                tlbiOp.broadcast(tc);
1230                return;
1231            }
1232          // mcr tlbimvalh(is) is invalidating all matching entries
1233          // regardless of the level of lookup, since in gem5 we cache
1234          // in the tlb the last level of lookup only.
1235          // TLB Invalidate by VA, Hyp mode
1236          case MISCREG_TLBIMVAH:
1237          case MISCREG_TLBIMVALH:
1238            {
1239                assert32(tc);
1240                scr = readMiscReg(MISCREG_SCR, tc);
1241
1242                TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns,
1243                                mbits(newVal, 31,12));
1244
1245                tlbiOp(tc);
1246                return;
1247            }
1248          // TLB Invalidate by VA, Hyp mode, Inner Shareable
1249          case MISCREG_TLBIMVAHIS:
1250          case MISCREG_TLBIMVALHIS:
1251            {
1252                assert32(tc);
1253                scr = readMiscReg(MISCREG_SCR, tc);
1254
1255                TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns,
1256                                mbits(newVal, 31,12));
1257
1258                tlbiOp.broadcast(tc);
1259                return;
1260            }
1261          // mcr tlbiipas2l(is) is invalidating all matching entries
1262          // regardless of the level of lookup, since in gem5 we cache
1263          // in the tlb the last level of lookup only.
1264          // TLB Invalidate by Intermediate Physical Address, Stage 2
1265          case MISCREG_TLBIIPAS2:
1266          case MISCREG_TLBIIPAS2L:
1267            {
1268                assert32(tc);
1269                scr = readMiscReg(MISCREG_SCR, tc);
1270
1271                TLBIIPA tlbiOp(EL1,
1272                               haveSecurity && !scr.ns,
1273                               static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1274
1275                tlbiOp(tc);
1276                return;
1277            }
1278          // TLB Invalidate by Intermediate Physical Address, Stage 2,
1279          // Inner Shareable
1280          case MISCREG_TLBIIPAS2IS:
1281          case MISCREG_TLBIIPAS2LIS:
1282            {
1283                assert32(tc);
1284                scr = readMiscReg(MISCREG_SCR, tc);
1285
1286                TLBIIPA tlbiOp(EL1,
1287                               haveSecurity && !scr.ns,
1288                               static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1289
1290                tlbiOp.broadcast(tc);
1291                return;
1292            }
1293          // Instruction TLB Invalidate by VA
1294          case MISCREG_ITLBIMVA:
1295            {
1296                assert32(tc);
1297                scr = readMiscReg(MISCREG_SCR, tc);
1298
1299                ITLBIMVA tlbiOp(EL1,
1300                                haveSecurity && !scr.ns,
1301                                mbits(newVal, 31, 12),
1302                                bits(newVal, 7,0));
1303
1304                tlbiOp(tc);
1305                return;
1306            }
1307          // Data TLB Invalidate by VA
1308          case MISCREG_DTLBIMVA:
1309            {
1310                assert32(tc);
1311                scr = readMiscReg(MISCREG_SCR, tc);
1312
1313                DTLBIMVA tlbiOp(EL1,
1314                                haveSecurity && !scr.ns,
1315                                mbits(newVal, 31, 12),
1316                                bits(newVal, 7,0));
1317
1318                tlbiOp(tc);
1319                return;
1320            }
1321          // Instruction TLB Invalidate by ASID match
1322          case MISCREG_ITLBIASID:
1323            {
1324                assert32(tc);
1325                scr = readMiscReg(MISCREG_SCR, tc);
1326
1327                ITLBIASID tlbiOp(EL1,
1328                                 haveSecurity && !scr.ns,
1329                                 bits(newVal, 7,0));
1330
1331                tlbiOp(tc);
1332                return;
1333            }
1334          // Data TLB Invalidate by ASID match
1335          case MISCREG_DTLBIASID:
1336            {
1337                assert32(tc);
1338                scr = readMiscReg(MISCREG_SCR, tc);
1339
1340                DTLBIASID tlbiOp(EL1,
1341                                 haveSecurity && !scr.ns,
1342                                 bits(newVal, 7,0));
1343
1344                tlbiOp(tc);
1345                return;
1346            }
1347          // TLB Invalidate All, Non-Secure Non-Hyp
1348          case MISCREG_TLBIALLNSNH:
1349            {
1350                assert32(tc);
1351
1352                TLBIALLN tlbiOp(EL1);
1353                tlbiOp(tc);
1354                return;
1355            }
1356          // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable
1357          case MISCREG_TLBIALLNSNHIS:
1358            {
1359                assert32(tc);
1360
1361                TLBIALLN tlbiOp(EL1);
1362                tlbiOp.broadcast(tc);
1363                return;
1364            }
1365          // TLB Invalidate All, Hyp mode
1366          case MISCREG_TLBIALLH:
1367            {
1368                assert32(tc);
1369
1370                TLBIALLN tlbiOp(EL2);
1371                tlbiOp(tc);
1372                return;
1373            }
1374          // TLB Invalidate All, Hyp mode, Inner Shareable
1375          case MISCREG_TLBIALLHIS:
1376            {
1377                assert32(tc);
1378
1379                TLBIALLN tlbiOp(EL2);
1380                tlbiOp.broadcast(tc);
1381                return;
1382            }
1383          // AArch64 TLB Invalidate All, EL3
1384          case MISCREG_TLBI_ALLE3:
1385            {
1386                assert64(tc);
1387
1388                TLBIALL tlbiOp(EL3, true);
1389                tlbiOp(tc);
1390                return;
1391            }
1392          // AArch64 TLB Invalidate All, EL3, Inner Shareable
1393          case MISCREG_TLBI_ALLE3IS:
1394            {
1395                assert64(tc);
1396
1397                TLBIALL tlbiOp(EL3, true);
1398                tlbiOp.broadcast(tc);
1399                return;
1400            }
1401          // AArch64 TLB Invalidate All, EL2, Inner Shareable
1402          case MISCREG_TLBI_ALLE2:
1403          case MISCREG_TLBI_ALLE2IS:
1404            {
1405                assert64(tc);
1406                scr = readMiscReg(MISCREG_SCR, tc);
1407
1408                TLBIALL tlbiOp(EL2, haveSecurity && !scr.ns);
1409                tlbiOp(tc);
1410                return;
1411            }
1412          // AArch64 TLB Invalidate All, EL1
1413          case MISCREG_TLBI_ALLE1:
1414          case MISCREG_TLBI_VMALLE1:
1415          case MISCREG_TLBI_VMALLS12E1:
1416            // @todo: handle VMID and stage 2 to enable Virtualization
1417            {
1418                assert64(tc);
1419                scr = readMiscReg(MISCREG_SCR, tc);
1420
1421                TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1422                tlbiOp(tc);
1423                return;
1424            }
1425          // AArch64 TLB Invalidate All, EL1, Inner Shareable
1426          case MISCREG_TLBI_ALLE1IS:
1427          case MISCREG_TLBI_VMALLE1IS:
1428          case MISCREG_TLBI_VMALLS12E1IS:
1429            // @todo: handle VMID and stage 2 to enable Virtualization
1430            {
1431                assert64(tc);
1432                scr = readMiscReg(MISCREG_SCR, tc);
1433
1434                TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1435                tlbiOp.broadcast(tc);
1436                return;
1437            }
1438          // VAEx(IS) and VALEx(IS) are the same because TLBs
1439          // only store entries
1440          // from the last level of translation table walks
1441          // @todo: handle VMID to enable Virtualization
1442          // AArch64 TLB Invalidate by VA, EL3
1443          case MISCREG_TLBI_VAE3_Xt:
1444          case MISCREG_TLBI_VALE3_Xt:
1445            {
1446                assert64(tc);
1447
1448                TLBIMVA tlbiOp(EL3, true,
1449                               static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1450                               0xbeef);
1451                tlbiOp(tc);
1452                return;
1453            }
1454          // AArch64 TLB Invalidate by VA, EL3, Inner Shareable
1455          case MISCREG_TLBI_VAE3IS_Xt:
1456          case MISCREG_TLBI_VALE3IS_Xt:
1457            {
1458                assert64(tc);
1459
1460                TLBIMVA tlbiOp(EL3, true,
1461                               static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1462                               0xbeef);
1463
1464                tlbiOp.broadcast(tc);
1465                return;
1466            }
1467          // AArch64 TLB Invalidate by VA, EL2
1468          case MISCREG_TLBI_VAE2_Xt:
1469          case MISCREG_TLBI_VALE2_Xt:
1470            {
1471                assert64(tc);
1472                scr = readMiscReg(MISCREG_SCR, tc);
1473
1474                TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns,
1475                               static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1476                               0xbeef);
1477                tlbiOp(tc);
1478                return;
1479            }
1480          // AArch64 TLB Invalidate by VA, EL2, Inner Shareable
1481          case MISCREG_TLBI_VAE2IS_Xt:
1482          case MISCREG_TLBI_VALE2IS_Xt:
1483            {
1484                assert64(tc);
1485                scr = readMiscReg(MISCREG_SCR, tc);
1486
1487                TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns,
1488                               static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1489                               0xbeef);
1490
1491                tlbiOp.broadcast(tc);
1492                return;
1493            }
1494          // AArch64 TLB Invalidate by VA, EL1
1495          case MISCREG_TLBI_VAE1_Xt:
1496          case MISCREG_TLBI_VALE1_Xt:
1497            {
1498                assert64(tc);
1499                scr = readMiscReg(MISCREG_SCR, tc);
1500                auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1501                                              bits(newVal, 55, 48);
1502
1503                TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns,
1504                               static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1505                               asid);
1506
1507                tlbiOp(tc);
1508                return;
1509            }
1510          // AArch64 TLB Invalidate by VA, EL1, Inner Shareable
1511          case MISCREG_TLBI_VAE1IS_Xt:
1512          case MISCREG_TLBI_VALE1IS_Xt:
1513            {
1514                assert64(tc);
1515                scr = readMiscReg(MISCREG_SCR, tc);
1516                auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1517                                              bits(newVal, 55, 48);
1518
1519                TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns,
1520                               static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1521                               asid);
1522
1523                tlbiOp.broadcast(tc);
1524                return;
1525            }
1526          // AArch64 TLB Invalidate by ASID, EL1
1527          // @todo: handle VMID to enable Virtualization
1528          case MISCREG_TLBI_ASIDE1_Xt:
1529            {
1530                assert64(tc);
1531                scr = readMiscReg(MISCREG_SCR, tc);
1532                auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1533                                              bits(newVal, 55, 48);
1534
1535                TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid);
1536                tlbiOp(tc);
1537                return;
1538            }
1539          // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable
1540          case MISCREG_TLBI_ASIDE1IS_Xt:
1541            {
1542                assert64(tc);
1543                scr = readMiscReg(MISCREG_SCR, tc);
1544                auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1545                                              bits(newVal, 55, 48);
1546
1547                TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid);
1548                tlbiOp.broadcast(tc);
1549                return;
1550            }
1551          // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store
1552          // entries from the last level of translation table walks
1553          // AArch64 TLB Invalidate by VA, All ASID, EL1
1554          case MISCREG_TLBI_VAAE1_Xt:
1555          case MISCREG_TLBI_VAALE1_Xt:
1556            {
1557                assert64(tc);
1558                scr = readMiscReg(MISCREG_SCR, tc);
1559
1560                TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1561                    static_cast<Addr>(bits(newVal, 43, 0)) << 12);
1562
1563                tlbiOp(tc);
1564                return;
1565            }
1566          // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable
1567          case MISCREG_TLBI_VAAE1IS_Xt:
1568          case MISCREG_TLBI_VAALE1IS_Xt:
1569            {
1570                assert64(tc);
1571                scr = readMiscReg(MISCREG_SCR, tc);
1572
1573                TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1574                    static_cast<Addr>(bits(newVal, 43, 0)) << 12);
1575
1576                tlbiOp.broadcast(tc);
1577                return;
1578            }
1579          // AArch64 TLB Invalidate by Intermediate Physical Address,
1580          // Stage 2, EL1
1581          case MISCREG_TLBI_IPAS2E1_Xt:
1582          case MISCREG_TLBI_IPAS2LE1_Xt:
1583            {
1584                assert64(tc);
1585                scr = readMiscReg(MISCREG_SCR, tc);
1586
1587                TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns,
1588                               static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1589
1590                tlbiOp(tc);
1591                return;
1592            }
1593          // AArch64 TLB Invalidate by Intermediate Physical Address,
1594          // Stage 2, EL1, Inner Shareable
1595          case MISCREG_TLBI_IPAS2E1IS_Xt:
1596          case MISCREG_TLBI_IPAS2LE1IS_Xt:
1597            {
1598                assert64(tc);
1599                scr = readMiscReg(MISCREG_SCR, tc);
1600
1601                TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns,
1602                               static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1603
1604                tlbiOp.broadcast(tc);
1605                return;
1606            }
1607          case MISCREG_ACTLR:
1608            warn("Not doing anything for write of miscreg ACTLR\n");
1609            break;
1610
1611          case MISCREG_PMXEVTYPER_PMCCFILTR:
1612          case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
1613          case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
1614          case MISCREG_PMCR ... MISCREG_PMOVSSET:
1615            pmu->setMiscReg(misc_reg, newVal);
1616            break;
1617
1618
1619          case MISCREG_HSTR: // TJDBX, now redifined to be RES0
1620            {
1621                HSTR hstrMask = 0;
1622                hstrMask.tjdbx = 1;
1623                newVal &= ~((uint32_t) hstrMask);
1624                break;
1625            }
1626          case MISCREG_HCPTR:
1627            {
1628                // If a CP bit in NSACR is 0 then the corresponding bit in
1629                // HCPTR is RAO/WI. Same applies to NSASEDIS
1630                secure_lookup = haveSecurity &&
1631                    inSecureState(readMiscRegNoEffect(MISCREG_SCR),
1632                                  readMiscRegNoEffect(MISCREG_CPSR));
1633                if (!secure_lookup) {
1634                    RegVal oldValue = readMiscRegNoEffect(MISCREG_HCPTR);
1635                    RegVal mask =
1636                        (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF;
1637                    newVal = (newVal & ~mask) | (oldValue & mask);
1638                }
1639                break;
1640            }
1641          case MISCREG_HDFAR: // alias for secure DFAR
1642            misc_reg = MISCREG_DFAR_S;
1643            break;
1644          case MISCREG_HIFAR: // alias for secure IFAR
1645            misc_reg = MISCREG_IFAR_S;
1646            break;
1647          case MISCREG_ATS1CPR:
1648          case MISCREG_ATS1CPW:
1649          case MISCREG_ATS1CUR:
1650          case MISCREG_ATS1CUW:
1651          case MISCREG_ATS12NSOPR:
1652          case MISCREG_ATS12NSOPW:
1653          case MISCREG_ATS12NSOUR:
1654          case MISCREG_ATS12NSOUW:
1655          case MISCREG_ATS1HR:
1656          case MISCREG_ATS1HW:
1657            {
1658              Request::Flags flags = 0;
1659              BaseTLB::Mode mode = BaseTLB::Read;
1660              TLB::ArmTranslationType tranType = TLB::NormalTran;
1661              Fault fault;
1662              switch(misc_reg) {
1663                case MISCREG_ATS1CPR:
1664                  flags    = TLB::MustBeOne;
1665                  tranType = TLB::S1CTran;
1666                  mode     = BaseTLB::Read;
1667                  break;
1668                case MISCREG_ATS1CPW:
1669                  flags    = TLB::MustBeOne;
1670                  tranType = TLB::S1CTran;
1671                  mode     = BaseTLB::Write;
1672                  break;
1673                case MISCREG_ATS1CUR:
1674                  flags    = TLB::MustBeOne | TLB::UserMode;
1675                  tranType = TLB::S1CTran;
1676                  mode     = BaseTLB::Read;
1677                  break;
1678                case MISCREG_ATS1CUW:
1679                  flags    = TLB::MustBeOne | TLB::UserMode;
1680                  tranType = TLB::S1CTran;
1681                  mode     = BaseTLB::Write;
1682                  break;
1683                case MISCREG_ATS12NSOPR:
1684                  if (!haveSecurity)
1685                      panic("Security Extensions required for ATS12NSOPR");
1686                  flags    = TLB::MustBeOne;
1687                  tranType = TLB::S1S2NsTran;
1688                  mode     = BaseTLB::Read;
1689                  break;
1690                case MISCREG_ATS12NSOPW:
1691                  if (!haveSecurity)
1692                      panic("Security Extensions required for ATS12NSOPW");
1693                  flags    = TLB::MustBeOne;
1694                  tranType = TLB::S1S2NsTran;
1695                  mode     = BaseTLB::Write;
1696                  break;
1697                case MISCREG_ATS12NSOUR:
1698                  if (!haveSecurity)
1699                      panic("Security Extensions required for ATS12NSOUR");
1700                  flags    = TLB::MustBeOne | TLB::UserMode;
1701                  tranType = TLB::S1S2NsTran;
1702                  mode     = BaseTLB::Read;
1703                  break;
1704                case MISCREG_ATS12NSOUW:
1705                  if (!haveSecurity)
1706                      panic("Security Extensions required for ATS12NSOUW");
1707                  flags    = TLB::MustBeOne | TLB::UserMode;
1708                  tranType = TLB::S1S2NsTran;
1709                  mode     = BaseTLB::Write;
1710                  break;
1711                case MISCREG_ATS1HR: // only really useful from secure mode.
1712                  flags    = TLB::MustBeOne;
1713                  tranType = TLB::HypMode;
1714                  mode     = BaseTLB::Read;
1715                  break;
1716                case MISCREG_ATS1HW:
1717                  flags    = TLB::MustBeOne;
1718                  tranType = TLB::HypMode;
1719                  mode     = BaseTLB::Write;
1720                  break;
1721              }
1722              // If we're in timing mode then doing the translation in
1723              // functional mode then we're slightly distorting performance
1724              // results obtained from simulations. The translation should be
1725              // done in the same mode the core is running in. NOTE: This
1726              // can't be an atomic translation because that causes problems
1727              // with unexpected atomic snoop requests.
1728              warn("Translating via %s in functional mode! Fix Me!\n",
1729                   miscRegName[misc_reg]);
1730
1731              auto req = std::make_shared<Request>(
1732                  0, val, 0, flags,  Request::funcMasterId,
1733                  tc->pcState().pc(), tc->contextId());
1734
1735              fault = getDTBPtr(tc)->translateFunctional(
1736                      req, tc, mode, tranType);
1737
1738              TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1739              HCR   hcr   = readMiscRegNoEffect(MISCREG_HCR);
1740
1741              RegVal newVal;
1742              if (fault == NoFault) {
1743                  Addr paddr = req->getPaddr();
1744                  if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode ||
1745                     ((tranType & TLB::S1S2NsTran) && hcr.vm) )) {
1746                      newVal = (paddr & mask(39, 12)) |
1747                               (getDTBPtr(tc)->getAttr());
1748                  } else {
1749                      newVal = (paddr & 0xfffff000) |
1750                               (getDTBPtr(tc)->getAttr());
1751                  }
1752                  DPRINTF(MiscRegs,
1753                          "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
1754                          val, newVal);
1755              } else {
1756                  ArmFault *armFault = static_cast<ArmFault *>(fault.get());
1757                  armFault->update(tc);
1758                  // Set fault bit and FSR
1759                  FSR fsr = armFault->getFsr(tc);
1760
1761                  newVal = ((fsr >> 9) & 1) << 11;
1762                  if (newVal) {
1763                    // LPAE - rearange fault status
1764                    newVal |= ((fsr >>  0) & 0x3f) << 1;
1765                  } else {
1766                    // VMSA - rearange fault status
1767                    newVal |= ((fsr >>  0) & 0xf) << 1;
1768                    newVal |= ((fsr >> 10) & 0x1) << 5;
1769                    newVal |= ((fsr >> 12) & 0x1) << 6;
1770                  }
1771                  newVal |= 0x1; // F bit
1772                  newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
1773                  newVal |= armFault->isStage2() ? 0x200 : 0;
1774                  DPRINTF(MiscRegs,
1775                          "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n",
1776                          val, fsr, newVal);
1777              }
1778              setMiscRegNoEffect(MISCREG_PAR, newVal);
1779              return;
1780            }
1781          case MISCREG_TTBCR:
1782            {
1783                TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1784                const uint32_t ones = (uint32_t)(-1);
1785                TTBCR ttbcrMask = 0;
1786                TTBCR ttbcrNew = newVal;
1787
1788                // ARM DDI 0406C.b, ARMv7-32
1789                ttbcrMask.n = ones; // T0SZ
1790                if (haveSecurity) {
1791                    ttbcrMask.pd0 = ones;
1792                    ttbcrMask.pd1 = ones;
1793                }
1794                ttbcrMask.epd0 = ones;
1795                ttbcrMask.irgn0 = ones;
1796                ttbcrMask.orgn0 = ones;
1797                ttbcrMask.sh0 = ones;
1798                ttbcrMask.ps = ones; // T1SZ
1799                ttbcrMask.a1 = ones;
1800                ttbcrMask.epd1 = ones;
1801                ttbcrMask.irgn1 = ones;
1802                ttbcrMask.orgn1 = ones;
1803                ttbcrMask.sh1 = ones;
1804                if (haveLPAE)
1805                    ttbcrMask.eae = ones;
1806
1807                if (haveLPAE && ttbcrNew.eae) {
1808                    newVal = newVal & ttbcrMask;
1809                } else {
1810                    newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask));
1811                }
1812                // Invalidate TLB MiscReg
1813                getITBPtr(tc)->invalidateMiscReg();
1814                getDTBPtr(tc)->invalidateMiscReg();
1815                break;
1816            }
1817          case MISCREG_TTBR0:
1818          case MISCREG_TTBR1:
1819            {
1820                TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1821                if (haveLPAE) {
1822                    if (ttbcr.eae) {
1823                        // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP
1824                        // ARMv8 AArch32 bit 63-56 only
1825                        uint64_t ttbrMask = mask(63,56) | mask(47,40);
1826                        newVal = (newVal & (~ttbrMask));
1827                    }
1828                }
1829                // Invalidate TLB MiscReg
1830                getITBPtr(tc)->invalidateMiscReg();
1831                getDTBPtr(tc)->invalidateMiscReg();
1832                break;
1833            }
1834          case MISCREG_SCTLR_EL1:
1835          case MISCREG_CONTEXTIDR:
1836          case MISCREG_PRRR:
1837          case MISCREG_NMRR:
1838          case MISCREG_MAIR0:
1839          case MISCREG_MAIR1:
1840          case MISCREG_DACR:
1841          case MISCREG_VTTBR:
1842          case MISCREG_SCR_EL3:
1843          case MISCREG_HCR_EL2:
1844          case MISCREG_TCR_EL1:
1845          case MISCREG_TCR_EL2:
1846          case MISCREG_TCR_EL3:
1847          case MISCREG_SCTLR_EL2:
1848          case MISCREG_SCTLR_EL3:
1849          case MISCREG_HSCTLR:
1850          case MISCREG_TTBR0_EL1:
1851          case MISCREG_TTBR1_EL1:
1852          case MISCREG_TTBR0_EL2:
1853          case MISCREG_TTBR1_EL2:
1854          case MISCREG_TTBR0_EL3:
1855            getITBPtr(tc)->invalidateMiscReg();
1856            getDTBPtr(tc)->invalidateMiscReg();
1857            break;
1858          case MISCREG_NZCV:
1859            {
1860                CPSR cpsr = val;
1861
1862                tc->setCCReg(CCREG_NZ, cpsr.nz);
1863                tc->setCCReg(CCREG_C,  cpsr.c);
1864                tc->setCCReg(CCREG_V,  cpsr.v);
1865            }
1866            break;
1867          case MISCREG_DAIF:
1868            {
1869                CPSR cpsr = miscRegs[MISCREG_CPSR];
1870                cpsr.daif = (uint8_t) ((CPSR) newVal).daif;
1871                newVal = cpsr;
1872                misc_reg = MISCREG_CPSR;
1873            }
1874            break;
1875          case MISCREG_SP_EL0:
1876            tc->setIntReg(INTREG_SP0, newVal);
1877            break;
1878          case MISCREG_SP_EL1:
1879            tc->setIntReg(INTREG_SP1, newVal);
1880            break;
1881          case MISCREG_SP_EL2:
1882            tc->setIntReg(INTREG_SP2, newVal);
1883            break;
1884          case MISCREG_SPSEL:
1885            {
1886                CPSR cpsr = miscRegs[MISCREG_CPSR];
1887                cpsr.sp = (uint8_t) ((CPSR) newVal).sp;
1888                newVal = cpsr;
1889                misc_reg = MISCREG_CPSR;
1890            }
1891            break;
1892          case MISCREG_CURRENTEL:
1893            {
1894                CPSR cpsr = miscRegs[MISCREG_CPSR];
1895                cpsr.el = (uint8_t) ((CPSR) newVal).el;
1896                newVal = cpsr;
1897                misc_reg = MISCREG_CPSR;
1898            }
1899            break;
1900          case MISCREG_PAN:
1901            {
1902                // PAN is affecting data accesses
1903                getDTBPtr(tc)->invalidateMiscReg();
1904
1905                CPSR cpsr = miscRegs[MISCREG_CPSR];
1906                cpsr.pan = (uint8_t) ((CPSR) newVal).pan;
1907                newVal = cpsr;
1908                misc_reg = MISCREG_CPSR;
1909            }
1910            break;
1911          case MISCREG_AT_S1E1R_Xt:
1912          case MISCREG_AT_S1E1W_Xt:
1913          case MISCREG_AT_S1E0R_Xt:
1914          case MISCREG_AT_S1E0W_Xt:
1915          case MISCREG_AT_S1E2R_Xt:
1916          case MISCREG_AT_S1E2W_Xt:
1917          case MISCREG_AT_S12E1R_Xt:
1918          case MISCREG_AT_S12E1W_Xt:
1919          case MISCREG_AT_S12E0R_Xt:
1920          case MISCREG_AT_S12E0W_Xt:
1921          case MISCREG_AT_S1E3R_Xt:
1922          case MISCREG_AT_S1E3W_Xt:
1923            {
1924                RequestPtr req = std::make_shared<Request>();
1925                Request::Flags flags = 0;
1926                BaseTLB::Mode mode = BaseTLB::Read;
1927                TLB::ArmTranslationType tranType = TLB::NormalTran;
1928                Fault fault;
1929                switch(misc_reg) {
1930                  case MISCREG_AT_S1E1R_Xt:
1931                    flags    = TLB::MustBeOne;
1932                    tranType = TLB::S1E1Tran;
1933                    mode     = BaseTLB::Read;
1934                    break;
1935                  case MISCREG_AT_S1E1W_Xt:
1936                    flags    = TLB::MustBeOne;
1937                    tranType = TLB::S1E1Tran;
1938                    mode     = BaseTLB::Write;
1939                    break;
1940                  case MISCREG_AT_S1E0R_Xt:
1941                    flags    = TLB::MustBeOne | TLB::UserMode;
1942                    tranType = TLB::S1E0Tran;
1943                    mode     = BaseTLB::Read;
1944                    break;
1945                  case MISCREG_AT_S1E0W_Xt:
1946                    flags    = TLB::MustBeOne | TLB::UserMode;
1947                    tranType = TLB::S1E0Tran;
1948                    mode     = BaseTLB::Write;
1949                    break;
1950                  case MISCREG_AT_S1E2R_Xt:
1951                    flags    = TLB::MustBeOne;
1952                    tranType = TLB::S1E2Tran;
1953                    mode     = BaseTLB::Read;
1954                    break;
1955                  case MISCREG_AT_S1E2W_Xt:
1956                    flags    = TLB::MustBeOne;
1957                    tranType = TLB::S1E2Tran;
1958                    mode     = BaseTLB::Write;
1959                    break;
1960                  case MISCREG_AT_S12E0R_Xt:
1961                    flags    = TLB::MustBeOne | TLB::UserMode;
1962                    tranType = TLB::S12E0Tran;
1963                    mode     = BaseTLB::Read;
1964                    break;
1965                  case MISCREG_AT_S12E0W_Xt:
1966                    flags    = TLB::MustBeOne | TLB::UserMode;
1967                    tranType = TLB::S12E0Tran;
1968                    mode     = BaseTLB::Write;
1969                    break;
1970                  case MISCREG_AT_S12E1R_Xt:
1971                    flags    = TLB::MustBeOne;
1972                    tranType = TLB::S12E1Tran;
1973                    mode     = BaseTLB::Read;
1974                    break;
1975                  case MISCREG_AT_S12E1W_Xt:
1976                    flags    = TLB::MustBeOne;
1977                    tranType = TLB::S12E1Tran;
1978                    mode     = BaseTLB::Write;
1979                    break;
1980                  case MISCREG_AT_S1E3R_Xt:
1981                    flags    = TLB::MustBeOne;
1982                    tranType = TLB::S1E3Tran;
1983                    mode     = BaseTLB::Read;
1984                    break;
1985                  case MISCREG_AT_S1E3W_Xt:
1986                    flags    = TLB::MustBeOne;
1987                    tranType = TLB::S1E3Tran;
1988                    mode     = BaseTLB::Write;
1989                    break;
1990                }
1991                // If we're in timing mode then doing the translation in
1992                // functional mode then we're slightly distorting performance
1993                // results obtained from simulations. The translation should be
1994                // done in the same mode the core is running in. NOTE: This
1995                // can't be an atomic translation because that causes problems
1996                // with unexpected atomic snoop requests.
1997                warn("Translating via %s in functional mode! Fix Me!\n",
1998                     miscRegName[misc_reg]);
1999
2000                req->setVirt(0, val, 0, flags,  Request::funcMasterId,
2001                               tc->pcState().pc());
2002                req->setContext(tc->contextId());
2003                fault = getDTBPtr(tc)->translateFunctional(req, tc, mode,
2004                                                           tranType);
2005
2006                RegVal newVal;
2007                if (fault == NoFault) {
2008                    Addr paddr = req->getPaddr();
2009                    uint64_t attr = getDTBPtr(tc)->getAttr();
2010                    uint64_t attr1 = attr >> 56;
2011                    if (!attr1 || attr1 ==0x44) {
2012                        attr |= 0x100;
2013                        attr &= ~ uint64_t(0x80);
2014                    }
2015                    newVal = (paddr & mask(47, 12)) | attr;
2016                    DPRINTF(MiscRegs,
2017                          "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
2018                          val, newVal);
2019                } else {
2020                    ArmFault *armFault = static_cast<ArmFault *>(fault.get());
2021                    armFault->update(tc);
2022                    // Set fault bit and FSR
2023                    FSR fsr = armFault->getFsr(tc);
2024
2025                    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
2026                    if (cpsr.width) { // AArch32
2027                        newVal = ((fsr >> 9) & 1) << 11;
2028                        // rearrange fault status
2029                        newVal |= ((fsr >>  0) & 0x3f) << 1;
2030                        newVal |= 0x1; // F bit
2031                        newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
2032                        newVal |= armFault->isStage2() ? 0x200 : 0;
2033                    } else { // AArch64
2034                        newVal = 1; // F bit
2035                        newVal |= fsr << 1; // FST
2036                        // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit.
2037                        newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW
2038                        newVal |= armFault->isStage2() ? 1 << 9 : 0; // S
2039                        newVal |= 1 << 11; // RES1
2040                    }
2041                    DPRINTF(MiscRegs,
2042                            "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
2043                            val, fsr, newVal);
2044                }
2045                setMiscRegNoEffect(MISCREG_PAR_EL1, newVal);
2046                return;
2047            }
2048          case MISCREG_SPSR_EL3:
2049          case MISCREG_SPSR_EL2:
2050          case MISCREG_SPSR_EL1:
2051            {
2052                RegVal spsr_mask = havePAN ?
2053                    ~(0x5 << 21) : ~(0x7 << 21);
2054
2055                newVal = val & spsr_mask;
2056                break;
2057            }
2058          case MISCREG_L2CTLR:
2059            warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
2060                 miscRegName[misc_reg], uint32_t(val));
2061            break;
2062
2063          // Generic Timer registers
2064          case MISCREG_CNTHV_CTL_EL2:
2065          case MISCREG_CNTHV_CVAL_EL2:
2066          case MISCREG_CNTHV_TVAL_EL2:
2067          case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
2068          case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
2069          case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:
2070          case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1:
2071            getGenericTimer(tc).setMiscReg(misc_reg, newVal);
2072            break;
2073          case MISCREG_ICC_AP0R0 ... MISCREG_ICH_LRC15:
2074          case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3:
2075          case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2:
2076            getGICv3CPUInterface(tc).setMiscReg(misc_reg, newVal);
2077            return;
2078          case MISCREG_ZCR_EL3:
2079          case MISCREG_ZCR_EL2:
2080          case MISCREG_ZCR_EL1:
2081            tc->getDecoderPtr()->setSveLen(
2082                (getCurSveVecLenInBits(tc) >> 7) - 1);
2083            break;
2084        }
2085    }
2086    setMiscRegNoEffect(misc_reg, newVal);
2087}
2088
2089BaseISADevice &
2090ISA::getGenericTimer(ThreadContext *tc)
2091{
2092    // We only need to create an ISA interface the first time we try
2093    // to access the timer.
2094    if (timer)
2095        return *timer.get();
2096
2097    assert(system);
2098    GenericTimer *generic_timer(system->getGenericTimer());
2099    if (!generic_timer) {
2100        panic("Trying to get a generic timer from a system that hasn't "
2101              "been configured to use a generic timer.\n");
2102    }
2103
2104    timer.reset(new GenericTimerISA(*generic_timer, tc->contextId()));
2105    timer->setThreadContext(tc);
2106
2107    return *timer.get();
2108}
2109
2110BaseISADevice &
2111ISA::getGICv3CPUInterface(ThreadContext *tc)
2112{
2113    panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!");
2114    return *gicv3CpuInterface.get();
2115}
2116
2117unsigned
2118ISA::getCurSveVecLenInBits(ThreadContext *tc) const
2119{
2120    if (!FullSystem) {
2121        return sveVL * 128;
2122    }
2123
2124    panic_if(!tc,
2125             "A ThreadContext is needed to determine the SVE vector length "
2126             "in full-system mode");
2127
2128    CPSR cpsr = miscRegs[MISCREG_CPSR];
2129    ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
2130
2131    unsigned len = 0;
2132
2133    if (el == EL1 || (el == EL0 && !ELIsInHost(tc, el))) {
2134        len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL1]).len;
2135    }
2136
2137    if (el == EL2 || (el == EL0 && ELIsInHost(tc, el))) {
2138        len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL2]).len;
2139    } else if (haveVirtualization && !inSecureState(tc) &&
2140               (el == EL0 || el == EL1)) {
2141        len = std::min(
2142            len,
2143            static_cast<unsigned>(
2144                static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL2]).len));
2145    }
2146
2147    if (el == EL3) {
2148        len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL3]).len;
2149    } else if (haveSecurity) {
2150        len = std::min(
2151            len,
2152            static_cast<unsigned>(
2153                static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL3]).len));
2154    }
2155
2156    len = std::min(len, sveVL - 1);
2157
2158    return (len + 1) * 128;
2159}
2160
2161void
2162ISA::zeroSveVecRegUpperPart(VecRegContainer &vc, unsigned eCount)
2163{
2164    auto vv = vc.as<uint64_t>();
2165    for (int i = 2; i < eCount; ++i) {
2166        vv[i] = 0;
2167    }
2168}
2169
2170}  // namespace ArmISA
2171
2172ArmISA::ISA *
2173ArmISAParams::create()
2174{
2175    return new ArmISA::ISA(this);
2176}
2177