isa.cc revision 14133:f3e7e7c3803d
1/* 2 * Copyright (c) 2010-2019 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 */ 40 41#include "arch/arm/isa.hh" 42#include "arch/arm/pmu.hh" 43#include "arch/arm/system.hh" 44#include "arch/arm/tlb.hh" 45#include "arch/arm/tlbi_op.hh" 46#include "cpu/base.hh" 47#include "cpu/checker/cpu.hh" 48#include "debug/Arm.hh" 49#include "debug/MiscRegs.hh" 50#include "dev/arm/generic_timer.hh" 51#include "dev/arm/gic_v3.hh" 52#include "dev/arm/gic_v3_cpu_interface.hh" 53#include "params/ArmISA.hh" 54#include "sim/faults.hh" 55#include "sim/stat_control.hh" 56#include "sim/system.hh" 57 58namespace ArmISA 59{ 60 61ISA::ISA(Params *p) 62 : SimObject(p), 63 system(NULL), 64 _decoderFlavour(p->decoderFlavour), 65 _vecRegRenameMode(Enums::Full), 66 pmu(p->pmu), 67 haveGICv3CPUInterface(false), 68 impdefAsNop(p->impdef_nop), 69 afterStartup(false) 70{ 71 miscRegs[MISCREG_SCTLR_RST] = 0; 72 73 // Hook up a dummy device if we haven't been configured with a 74 // real PMU. By using a dummy device, we don't need to check that 75 // the PMU exist every time we try to access a PMU register. 76 if (!pmu) 77 pmu = &dummyDevice; 78 79 // Give all ISA devices a pointer to this ISA 80 pmu->setISA(this); 81 82 system = dynamic_cast<ArmSystem *>(p->system); 83 84 // Cache system-level properties 85 if (FullSystem && system) { 86 highestELIs64 = system->highestELIs64(); 87 haveSecurity = system->haveSecurity(); 88 haveLPAE = system->haveLPAE(); 89 haveCrypto = system->haveCrypto(); 90 haveVirtualization = system->haveVirtualization(); 91 haveLargeAsid64 = system->haveLargeAsid64(); 92 physAddrRange = system->physAddrRange(); 93 haveSVE = system->haveSVE(); 94 havePAN = system->havePAN(); 95 sveVL = system->sveVL(); 96 haveLSE = system->haveLSE(); 97 } else { 98 highestELIs64 = true; // ArmSystem::highestELIs64 does the same 99 haveSecurity = haveLPAE = haveVirtualization = false; 100 haveCrypto = true; 101 haveLargeAsid64 = false; 102 physAddrRange = 32; // dummy value 103 haveSVE = true; 104 havePAN = false; 105 sveVL = p->sve_vl_se; 106 haveLSE = true; 107 } 108 109 // Initial rename mode depends on highestEL 110 const_cast<Enums::VecRegRenameMode&>(_vecRegRenameMode) = 111 highestELIs64 ? Enums::Full : Enums::Elem; 112 113 initializeMiscRegMetadata(); 114 preUnflattenMiscReg(); 115 116 clear(); 117} 118 119std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS); 120 121const ArmISAParams * 122ISA::params() const 123{ 124 return dynamic_cast<const Params *>(_params); 125} 126 127void 128ISA::clear() 129{ 130 const Params *p(params()); 131 132 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 133 memset(miscRegs, 0, sizeof(miscRegs)); 134 135 initID32(p); 136 137 // We always initialize AArch64 ID registers even 138 // if we are in AArch32. This is done since if we 139 // are in SE mode we don't know if our ArmProcess is 140 // AArch32 or AArch64 141 initID64(p); 142 143 // Start with an event in the mailbox 144 miscRegs[MISCREG_SEV_MAILBOX] = 1; 145 146 // Separate Instruction and Data TLBs 147 miscRegs[MISCREG_TLBTR] = 1; 148 149 MVFR0 mvfr0 = 0; 150 mvfr0.advSimdRegisters = 2; 151 mvfr0.singlePrecision = 2; 152 mvfr0.doublePrecision = 2; 153 mvfr0.vfpExceptionTrapping = 0; 154 mvfr0.divide = 1; 155 mvfr0.squareRoot = 1; 156 mvfr0.shortVectors = 1; 157 mvfr0.roundingModes = 1; 158 miscRegs[MISCREG_MVFR0] = mvfr0; 159 160 MVFR1 mvfr1 = 0; 161 mvfr1.flushToZero = 1; 162 mvfr1.defaultNaN = 1; 163 mvfr1.advSimdLoadStore = 1; 164 mvfr1.advSimdInteger = 1; 165 mvfr1.advSimdSinglePrecision = 1; 166 mvfr1.advSimdHalfPrecision = 1; 167 mvfr1.vfpHalfPrecision = 1; 168 miscRegs[MISCREG_MVFR1] = mvfr1; 169 170 // Reset values of PRRR and NMRR are implementation dependent 171 172 // @todo: PRRR and NMRR in secure state? 173 miscRegs[MISCREG_PRRR_NS] = 174 (1 << 19) | // 19 175 (0 << 18) | // 18 176 (0 << 17) | // 17 177 (1 << 16) | // 16 178 (2 << 14) | // 15:14 179 (0 << 12) | // 13:12 180 (2 << 10) | // 11:10 181 (2 << 8) | // 9:8 182 (2 << 6) | // 7:6 183 (2 << 4) | // 5:4 184 (1 << 2) | // 3:2 185 0; // 1:0 186 187 miscRegs[MISCREG_NMRR_NS] = 188 (1 << 30) | // 31:30 189 (0 << 26) | // 27:26 190 (0 << 24) | // 25:24 191 (3 << 22) | // 23:22 192 (2 << 20) | // 21:20 193 (0 << 18) | // 19:18 194 (0 << 16) | // 17:16 195 (1 << 14) | // 15:14 196 (0 << 12) | // 13:12 197 (2 << 10) | // 11:10 198 (0 << 8) | // 9:8 199 (3 << 6) | // 7:6 200 (2 << 4) | // 5:4 201 (0 << 2) | // 3:2 202 0; // 1:0 203 204 if (FullSystem && system->highestELIs64()) { 205 // Initialize AArch64 state 206 clear64(p); 207 return; 208 } 209 210 // Initialize AArch32 state... 211 clear32(p, sctlr_rst); 212} 213 214void 215ISA::clear32(const ArmISAParams *p, const SCTLR &sctlr_rst) 216{ 217 CPSR cpsr = 0; 218 cpsr.mode = MODE_USER; 219 220 if (FullSystem) { 221 miscRegs[MISCREG_MVBAR] = system->resetAddr(); 222 } 223 224 miscRegs[MISCREG_CPSR] = cpsr; 225 updateRegMap(cpsr); 226 227 SCTLR sctlr = 0; 228 sctlr.te = (bool) sctlr_rst.te; 229 sctlr.nmfi = (bool) sctlr_rst.nmfi; 230 sctlr.v = (bool) sctlr_rst.v; 231 sctlr.u = 1; 232 sctlr.xp = 1; 233 sctlr.rao2 = 1; 234 sctlr.rao3 = 1; 235 sctlr.rao4 = 0xf; // SCTLR[6:3] 236 sctlr.uci = 1; 237 sctlr.dze = 1; 238 miscRegs[MISCREG_SCTLR_NS] = sctlr; 239 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 240 miscRegs[MISCREG_HCPTR] = 0; 241 242 miscRegs[MISCREG_CPACR] = 0; 243 244 miscRegs[MISCREG_FPSID] = p->fpsid; 245 246 if (haveLPAE) { 247 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 248 ttbcr.eae = 0; 249 miscRegs[MISCREG_TTBCR_NS] = ttbcr; 250 // Enforce consistency with system-level settings 251 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 252 } 253 254 if (haveSecurity) { 255 miscRegs[MISCREG_SCTLR_S] = sctlr; 256 miscRegs[MISCREG_SCR] = 0; 257 miscRegs[MISCREG_VBAR_S] = 0; 258 } else { 259 // we're always non-secure 260 miscRegs[MISCREG_SCR] = 1; 261 } 262 263 //XXX We need to initialize the rest of the state. 264} 265 266void 267ISA::clear64(const ArmISAParams *p) 268{ 269 CPSR cpsr = 0; 270 Addr rvbar = system->resetAddr(); 271 switch (system->highestEL()) { 272 // Set initial EL to highest implemented EL using associated stack 273 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 274 // value 275 case EL3: 276 cpsr.mode = MODE_EL3H; 277 miscRegs[MISCREG_RVBAR_EL3] = rvbar; 278 break; 279 case EL2: 280 cpsr.mode = MODE_EL2H; 281 miscRegs[MISCREG_RVBAR_EL2] = rvbar; 282 break; 283 case EL1: 284 cpsr.mode = MODE_EL1H; 285 miscRegs[MISCREG_RVBAR_EL1] = rvbar; 286 break; 287 default: 288 panic("Invalid highest implemented exception level"); 289 break; 290 } 291 292 // Initialize rest of CPSR 293 cpsr.daif = 0xf; // Mask all interrupts 294 cpsr.ss = 0; 295 cpsr.il = 0; 296 miscRegs[MISCREG_CPSR] = cpsr; 297 updateRegMap(cpsr); 298 299 // Initialize other control registers 300 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 301 if (haveSecurity) { 302 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830; 303 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 304 } else if (haveVirtualization) { 305 // also MISCREG_SCTLR_EL2 (by mapping) 306 miscRegs[MISCREG_HSCTLR] = 0x30c50830; 307 } else { 308 // also MISCREG_SCTLR_EL1 (by mapping) 309 miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init 310 // Always non-secure 311 miscRegs[MISCREG_SCR_EL3] = 1; 312 } 313} 314 315void 316ISA::initID32(const ArmISAParams *p) 317{ 318 // Initialize configurable default values 319 miscRegs[MISCREG_MIDR] = p->midr; 320 miscRegs[MISCREG_MIDR_EL1] = p->midr; 321 miscRegs[MISCREG_VPIDR] = p->midr; 322 323 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 324 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 325 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 326 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 327 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 328 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 329 330 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 331 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 332 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 333 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 334 335 miscRegs[MISCREG_ID_ISAR5] = insertBits( 336 miscRegs[MISCREG_ID_ISAR5], 19, 4, 337 haveCrypto ? 0x1112 : 0x0); 338} 339 340void 341ISA::initID64(const ArmISAParams *p) 342{ 343 // Initialize configurable id registers 344 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 345 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 346 miscRegs[MISCREG_ID_AA64DFR0_EL1] = 347 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 348 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 349 350 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 351 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 352 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 353 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 354 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 355 miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p->id_aa64mmfr2_el1; 356 357 miscRegs[MISCREG_ID_DFR0_EL1] = 358 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 359 360 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 361 362 // SVE 363 miscRegs[MISCREG_ID_AA64ZFR0_EL1] = 0; // SVEver 0 364 if (haveSecurity) { 365 miscRegs[MISCREG_ZCR_EL3] = sveVL - 1; 366 } else if (haveVirtualization) { 367 miscRegs[MISCREG_ZCR_EL2] = sveVL - 1; 368 } else { 369 miscRegs[MISCREG_ZCR_EL1] = sveVL - 1; 370 } 371 372 // Enforce consistency with system-level settings... 373 374 // EL3 375 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 376 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 377 haveSecurity ? 0x2 : 0x0); 378 // EL2 379 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 380 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 381 haveVirtualization ? 0x2 : 0x0); 382 // SVE 383 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 384 miscRegs[MISCREG_ID_AA64PFR0_EL1], 35, 32, 385 haveSVE ? 0x1 : 0x0); 386 // Large ASID support 387 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 388 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 389 haveLargeAsid64 ? 0x2 : 0x0); 390 // Physical address size 391 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 392 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 393 encodePhysAddrRange64(physAddrRange)); 394 // Crypto 395 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits( 396 miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4, 397 haveCrypto ? 0x1112 : 0x0); 398 // LSE 399 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits( 400 miscRegs[MISCREG_ID_AA64ISAR0_EL1], 23, 20, 401 haveLSE ? 0x2 : 0x0); 402 // PAN 403 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits( 404 miscRegs[MISCREG_ID_AA64MMFR1_EL1], 23, 20, 405 havePAN ? 0x1 : 0x0); 406} 407 408void 409ISA::startup(ThreadContext *tc) 410{ 411 pmu->setThreadContext(tc); 412 413 if (system) { 414 Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC()); 415 if (gicv3) { 416 haveGICv3CPUInterface = true; 417 gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId())); 418 gicv3CpuInterface->setISA(this); 419 gicv3CpuInterface->setThreadContext(tc); 420 } 421 } 422 423 afterStartup = true; 424} 425 426 427RegVal 428ISA::readMiscRegNoEffect(int misc_reg) const 429{ 430 assert(misc_reg < NumMiscRegs); 431 432 const auto ® = lookUpMiscReg[misc_reg]; // bit masks 433 const auto &map = getMiscIndices(misc_reg); 434 int lower = map.first, upper = map.second; 435 // NB!: apply architectural masks according to desired register, 436 // despite possibly getting value from different (mapped) register. 437 auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32)) 438 |(miscRegs[upper] << 32)); 439 if (val & reg.res0()) { 440 DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n", 441 miscRegName[misc_reg], val & reg.res0()); 442 } 443 if ((val & reg.res1()) != reg.res1()) { 444 DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n", 445 miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1()); 446 } 447 return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao 448} 449 450 451RegVal 452ISA::readMiscReg(int misc_reg, ThreadContext *tc) 453{ 454 CPSR cpsr = 0; 455 PCState pc = 0; 456 SCR scr = 0; 457 458 if (misc_reg == MISCREG_CPSR) { 459 cpsr = miscRegs[misc_reg]; 460 pc = tc->pcState(); 461 cpsr.j = pc.jazelle() ? 1 : 0; 462 cpsr.t = pc.thumb() ? 1 : 0; 463 return cpsr; 464 } 465 466#ifndef NDEBUG 467 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 468 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 469 warn("Unimplemented system register %s read.\n", 470 miscRegName[misc_reg]); 471 else 472 panic("Unimplemented system register %s read.\n", 473 miscRegName[misc_reg]); 474 } 475#endif 476 477 switch (unflattenMiscReg(misc_reg)) { 478 case MISCREG_HCR: 479 { 480 if (!haveVirtualization) 481 return 0; 482 else 483 return readMiscRegNoEffect(MISCREG_HCR); 484 } 485 case MISCREG_CPACR: 486 { 487 const uint32_t ones = (uint32_t)(-1); 488 CPACR cpacrMask = 0; 489 // Only cp10, cp11, and ase are implemented, nothing else should 490 // be readable? (straight copy from the write code) 491 cpacrMask.cp10 = ones; 492 cpacrMask.cp11 = ones; 493 cpacrMask.asedis = ones; 494 495 // Security Extensions may limit the readability of CPACR 496 if (haveSecurity) { 497 scr = readMiscRegNoEffect(MISCREG_SCR); 498 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 499 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 500 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 501 // NB: Skipping the full loop, here 502 if (!nsacr.cp10) cpacrMask.cp10 = 0; 503 if (!nsacr.cp11) cpacrMask.cp11 = 0; 504 } 505 } 506 RegVal val = readMiscRegNoEffect(MISCREG_CPACR); 507 val &= cpacrMask; 508 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 509 miscRegName[misc_reg], val); 510 return val; 511 } 512 case MISCREG_MPIDR: 513 case MISCREG_MPIDR_EL1: 514 return readMPIDR(system, tc); 515 case MISCREG_VMPIDR: 516 case MISCREG_VMPIDR_EL2: 517 // top bit defined as RES1 518 return readMiscRegNoEffect(misc_reg) | 0x80000000; 519 case MISCREG_ID_AFR0: // not implemented, so alias MIDR 520 case MISCREG_REVIDR: // not implemented, so alias MIDR 521 case MISCREG_MIDR: 522 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 523 scr = readMiscRegNoEffect(MISCREG_SCR); 524 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 525 return readMiscRegNoEffect(misc_reg); 526 } else { 527 return readMiscRegNoEffect(MISCREG_VPIDR); 528 } 529 break; 530 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 531 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 532 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 533 case MISCREG_AIDR: // AUX ID set to 0 534 case MISCREG_TCMTR: // No TCM's 535 return 0; 536 537 case MISCREG_CLIDR: 538 warn_once("The clidr register always reports 0 caches.\n"); 539 warn_once("clidr LoUIS field of 0b001 to match current " 540 "ARM implementations.\n"); 541 return 0x00200000; 542 case MISCREG_CCSIDR: 543 warn_once("The ccsidr register isn't implemented and " 544 "always reads as 0.\n"); 545 break; 546 case MISCREG_CTR: // AArch32, ARMv7, top bit set 547 case MISCREG_CTR_EL0: // AArch64 548 { 549 //all caches have the same line size in gem5 550 //4 byte words in ARM 551 unsigned lineSizeWords = 552 tc->getSystemPtr()->cacheLineSize() / 4; 553 unsigned log2LineSizeWords = 0; 554 555 while (lineSizeWords >>= 1) { 556 ++log2LineSizeWords; 557 } 558 559 CTR ctr = 0; 560 //log2 of minimun i-cache line size (words) 561 ctr.iCacheLineSize = log2LineSizeWords; 562 //b11 - gem5 uses pipt 563 ctr.l1IndexPolicy = 0x3; 564 //log2 of minimum d-cache line size (words) 565 ctr.dCacheLineSize = log2LineSizeWords; 566 //log2 of max reservation size (words) 567 ctr.erg = log2LineSizeWords; 568 //log2 of max writeback size (words) 569 ctr.cwg = log2LineSizeWords; 570 //b100 - gem5 format is ARMv7 571 ctr.format = 0x4; 572 573 return ctr; 574 } 575 case MISCREG_ACTLR: 576 warn("Not doing anything for miscreg ACTLR\n"); 577 break; 578 579 case MISCREG_PMXEVTYPER_PMCCFILTR: 580 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 581 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 582 case MISCREG_PMCR ... MISCREG_PMOVSSET: 583 return pmu->readMiscReg(misc_reg); 584 585 case MISCREG_CPSR_Q: 586 panic("shouldn't be reading this register seperately\n"); 587 case MISCREG_FPSCR_QC: 588 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 589 case MISCREG_FPSCR_EXC: 590 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 591 case MISCREG_FPSR: 592 { 593 const uint32_t ones = (uint32_t)(-1); 594 FPSCR fpscrMask = 0; 595 fpscrMask.ioc = ones; 596 fpscrMask.dzc = ones; 597 fpscrMask.ofc = ones; 598 fpscrMask.ufc = ones; 599 fpscrMask.ixc = ones; 600 fpscrMask.idc = ones; 601 fpscrMask.qc = ones; 602 fpscrMask.v = ones; 603 fpscrMask.c = ones; 604 fpscrMask.z = ones; 605 fpscrMask.n = ones; 606 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 607 } 608 case MISCREG_FPCR: 609 { 610 const uint32_t ones = (uint32_t)(-1); 611 FPSCR fpscrMask = 0; 612 fpscrMask.len = ones; 613 fpscrMask.fz16 = ones; 614 fpscrMask.stride = ones; 615 fpscrMask.rMode = ones; 616 fpscrMask.fz = ones; 617 fpscrMask.dn = ones; 618 fpscrMask.ahp = ones; 619 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 620 } 621 case MISCREG_NZCV: 622 { 623 CPSR cpsr = 0; 624 cpsr.nz = tc->readCCReg(CCREG_NZ); 625 cpsr.c = tc->readCCReg(CCREG_C); 626 cpsr.v = tc->readCCReg(CCREG_V); 627 return cpsr; 628 } 629 case MISCREG_DAIF: 630 { 631 CPSR cpsr = 0; 632 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 633 return cpsr; 634 } 635 case MISCREG_SP_EL0: 636 { 637 return tc->readIntReg(INTREG_SP0); 638 } 639 case MISCREG_SP_EL1: 640 { 641 return tc->readIntReg(INTREG_SP1); 642 } 643 case MISCREG_SP_EL2: 644 { 645 return tc->readIntReg(INTREG_SP2); 646 } 647 case MISCREG_SPSEL: 648 { 649 return miscRegs[MISCREG_CPSR] & 0x1; 650 } 651 case MISCREG_CURRENTEL: 652 { 653 return miscRegs[MISCREG_CPSR] & 0xc; 654 } 655 case MISCREG_PAN: 656 { 657 return miscRegs[MISCREG_CPSR] & 0x400000; 658 } 659 case MISCREG_L2CTLR: 660 { 661 // mostly unimplemented, just set NumCPUs field from sim and return 662 L2CTLR l2ctlr = 0; 663 // b00:1CPU to b11:4CPUs 664 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 665 return l2ctlr; 666 } 667 case MISCREG_DBGDIDR: 668 /* For now just implement the version number. 669 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 670 */ 671 return 0x5 << 16; 672 case MISCREG_DBGDSCRint: 673 return 0; 674 case MISCREG_ISR: 675 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 676 readMiscRegNoEffect(MISCREG_HCR), 677 readMiscRegNoEffect(MISCREG_CPSR), 678 readMiscRegNoEffect(MISCREG_SCR)); 679 case MISCREG_ISR_EL1: 680 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 681 readMiscRegNoEffect(MISCREG_HCR_EL2), 682 readMiscRegNoEffect(MISCREG_CPSR), 683 readMiscRegNoEffect(MISCREG_SCR_EL3)); 684 case MISCREG_DCZID_EL0: 685 return 0x04; // DC ZVA clear 64-byte chunks 686 case MISCREG_HCPTR: 687 { 688 RegVal val = readMiscRegNoEffect(misc_reg); 689 // The trap bit associated with CP14 is defined as RAZ 690 val &= ~(1 << 14); 691 // If a CP bit in NSACR is 0 then the corresponding bit in 692 // HCPTR is RAO/WI 693 bool secure_lookup = haveSecurity && 694 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 695 readMiscRegNoEffect(MISCREG_CPSR)); 696 if (!secure_lookup) { 697 RegVal mask = readMiscRegNoEffect(MISCREG_NSACR); 698 val |= (mask ^ 0x7FFF) & 0xBFFF; 699 } 700 // Set the bits for unimplemented coprocessors to RAO/WI 701 val |= 0x33FF; 702 return (val); 703 } 704 case MISCREG_HDFAR: // alias for secure DFAR 705 return readMiscRegNoEffect(MISCREG_DFAR_S); 706 case MISCREG_HIFAR: // alias for secure IFAR 707 return readMiscRegNoEffect(MISCREG_IFAR_S); 708 709 case MISCREG_ID_PFR0: 710 // !ThumbEE | !Jazelle | Thumb | ARM 711 return 0x00000031; 712 case MISCREG_ID_PFR1: 713 { // Timer | Virti | !M Profile | TrustZone | ARMv4 714 bool haveTimer = (system->getGenericTimer() != NULL); 715 return 0x00000001 716 | (haveSecurity ? 0x00000010 : 0x0) 717 | (haveVirtualization ? 0x00001000 : 0x0) 718 | (haveTimer ? 0x00010000 : 0x0); 719 } 720 case MISCREG_ID_AA64PFR0_EL1: 721 return 0x0000000000000002 | // AArch{64,32} supported at EL0 722 0x0000000000000020 | // EL1 723 (haveVirtualization ? 0x0000000000000200 : 0) | // EL2 724 (haveSecurity ? 0x0000000000002000 : 0) | // EL3 725 (haveSVE ? 0x0000000100000000 : 0) | // SVE 726 (haveGICv3CPUInterface ? 0x0000000001000000 : 0); 727 case MISCREG_ID_AA64PFR1_EL1: 728 return 0; // bits [63:0] RES0 (reserved for future use) 729 730 // Generic Timer registers 731 case MISCREG_CNTHV_CTL_EL2: 732 case MISCREG_CNTHV_CVAL_EL2: 733 case MISCREG_CNTHV_TVAL_EL2: 734 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 735 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 736 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 737 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 738 return getGenericTimer(tc).readMiscReg(misc_reg); 739 740 case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3: 741 case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2: 742 return getGICv3CPUInterface(tc).readMiscReg(misc_reg); 743 744 default: 745 break; 746 747 } 748 return readMiscRegNoEffect(misc_reg); 749} 750 751void 752ISA::setMiscRegNoEffect(int misc_reg, RegVal val) 753{ 754 assert(misc_reg < NumMiscRegs); 755 756 const auto ® = lookUpMiscReg[misc_reg]; // bit masks 757 const auto &map = getMiscIndices(misc_reg); 758 int lower = map.first, upper = map.second; 759 760 auto v = (val & ~reg.wi()) | reg.rao(); 761 if (upper > 0) { 762 miscRegs[lower] = bits(v, 31, 0); 763 miscRegs[upper] = bits(v, 63, 32); 764 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 765 misc_reg, lower, upper, v); 766 } else { 767 miscRegs[lower] = v; 768 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 769 misc_reg, lower, v); 770 } 771} 772 773void 774ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) 775{ 776 777 RegVal newVal = val; 778 bool secure_lookup; 779 SCR scr; 780 781 if (misc_reg == MISCREG_CPSR) { 782 updateRegMap(val); 783 784 785 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 786 int old_mode = old_cpsr.mode; 787 CPSR cpsr = val; 788 if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) { 789 getITBPtr(tc)->invalidateMiscReg(); 790 getDTBPtr(tc)->invalidateMiscReg(); 791 } 792 793 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 794 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 795 PCState pc = tc->pcState(); 796 pc.nextThumb(cpsr.t); 797 pc.nextJazelle(cpsr.j); 798 pc.illegalExec(cpsr.il == 1); 799 800 tc->getDecoderPtr()->setSveLen((getCurSveVecLenInBits(tc) >> 7) - 1); 801 802 // Follow slightly different semantics if a CheckerCPU object 803 // is connected 804 CheckerCPU *checker = tc->getCheckerCpuPtr(); 805 if (checker) { 806 tc->pcStateNoRecord(pc); 807 } else { 808 tc->pcState(pc); 809 } 810 } else { 811#ifndef NDEBUG 812 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 813 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 814 warn("Unimplemented system register %s write with %#x.\n", 815 miscRegName[misc_reg], val); 816 else 817 panic("Unimplemented system register %s write with %#x.\n", 818 miscRegName[misc_reg], val); 819 } 820#endif 821 switch (unflattenMiscReg(misc_reg)) { 822 case MISCREG_CPACR: 823 { 824 825 const uint32_t ones = (uint32_t)(-1); 826 CPACR cpacrMask = 0; 827 // Only cp10, cp11, and ase are implemented, nothing else should 828 // be writable 829 cpacrMask.cp10 = ones; 830 cpacrMask.cp11 = ones; 831 cpacrMask.asedis = ones; 832 833 // Security Extensions may limit the writability of CPACR 834 if (haveSecurity) { 835 scr = readMiscRegNoEffect(MISCREG_SCR); 836 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 837 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 838 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 839 // NB: Skipping the full loop, here 840 if (!nsacr.cp10) cpacrMask.cp10 = 0; 841 if (!nsacr.cp11) cpacrMask.cp11 = 0; 842 } 843 } 844 845 RegVal old_val = readMiscRegNoEffect(MISCREG_CPACR); 846 newVal &= cpacrMask; 847 newVal |= old_val & ~cpacrMask; 848 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 849 miscRegName[misc_reg], newVal); 850 } 851 break; 852 case MISCREG_CPACR_EL1: 853 { 854 const uint32_t ones = (uint32_t)(-1); 855 CPACR cpacrMask = 0; 856 cpacrMask.tta = ones; 857 cpacrMask.fpen = ones; 858 if (haveSVE) { 859 cpacrMask.zen = ones; 860 } 861 newVal &= cpacrMask; 862 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 863 miscRegName[misc_reg], newVal); 864 } 865 break; 866 case MISCREG_CPTR_EL2: 867 { 868 const uint32_t ones = (uint32_t)(-1); 869 CPTR cptrMask = 0; 870 cptrMask.tcpac = ones; 871 cptrMask.tta = ones; 872 cptrMask.tfp = ones; 873 if (haveSVE) { 874 cptrMask.tz = ones; 875 } 876 newVal &= cptrMask; 877 cptrMask = 0; 878 cptrMask.res1_13_12_el2 = ones; 879 cptrMask.res1_7_0_el2 = ones; 880 if (!haveSVE) { 881 cptrMask.res1_8_el2 = ones; 882 } 883 cptrMask.res1_9_el2 = ones; 884 newVal |= cptrMask; 885 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 886 miscRegName[misc_reg], newVal); 887 } 888 break; 889 case MISCREG_CPTR_EL3: 890 { 891 const uint32_t ones = (uint32_t)(-1); 892 CPTR cptrMask = 0; 893 cptrMask.tcpac = ones; 894 cptrMask.tta = ones; 895 cptrMask.tfp = ones; 896 if (haveSVE) { 897 cptrMask.ez = ones; 898 } 899 newVal &= cptrMask; 900 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 901 miscRegName[misc_reg], newVal); 902 } 903 break; 904 case MISCREG_CSSELR: 905 warn_once("The csselr register isn't implemented.\n"); 906 return; 907 908 case MISCREG_DC_ZVA_Xt: 909 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 910 return; 911 912 case MISCREG_FPSCR: 913 { 914 const uint32_t ones = (uint32_t)(-1); 915 FPSCR fpscrMask = 0; 916 fpscrMask.ioc = ones; 917 fpscrMask.dzc = ones; 918 fpscrMask.ofc = ones; 919 fpscrMask.ufc = ones; 920 fpscrMask.ixc = ones; 921 fpscrMask.idc = ones; 922 fpscrMask.ioe = ones; 923 fpscrMask.dze = ones; 924 fpscrMask.ofe = ones; 925 fpscrMask.ufe = ones; 926 fpscrMask.ixe = ones; 927 fpscrMask.ide = ones; 928 fpscrMask.len = ones; 929 fpscrMask.fz16 = ones; 930 fpscrMask.stride = ones; 931 fpscrMask.rMode = ones; 932 fpscrMask.fz = ones; 933 fpscrMask.dn = ones; 934 fpscrMask.ahp = ones; 935 fpscrMask.qc = ones; 936 fpscrMask.v = ones; 937 fpscrMask.c = ones; 938 fpscrMask.z = ones; 939 fpscrMask.n = ones; 940 newVal = (newVal & (uint32_t)fpscrMask) | 941 (readMiscRegNoEffect(MISCREG_FPSCR) & 942 ~(uint32_t)fpscrMask); 943 tc->getDecoderPtr()->setContext(newVal); 944 } 945 break; 946 case MISCREG_FPSR: 947 { 948 const uint32_t ones = (uint32_t)(-1); 949 FPSCR fpscrMask = 0; 950 fpscrMask.ioc = ones; 951 fpscrMask.dzc = ones; 952 fpscrMask.ofc = ones; 953 fpscrMask.ufc = ones; 954 fpscrMask.ixc = ones; 955 fpscrMask.idc = ones; 956 fpscrMask.qc = ones; 957 fpscrMask.v = ones; 958 fpscrMask.c = ones; 959 fpscrMask.z = ones; 960 fpscrMask.n = ones; 961 newVal = (newVal & (uint32_t)fpscrMask) | 962 (readMiscRegNoEffect(MISCREG_FPSCR) & 963 ~(uint32_t)fpscrMask); 964 misc_reg = MISCREG_FPSCR; 965 } 966 break; 967 case MISCREG_FPCR: 968 { 969 const uint32_t ones = (uint32_t)(-1); 970 FPSCR fpscrMask = 0; 971 fpscrMask.len = ones; 972 fpscrMask.fz16 = ones; 973 fpscrMask.stride = ones; 974 fpscrMask.rMode = ones; 975 fpscrMask.fz = ones; 976 fpscrMask.dn = ones; 977 fpscrMask.ahp = ones; 978 newVal = (newVal & (uint32_t)fpscrMask) | 979 (readMiscRegNoEffect(MISCREG_FPSCR) & 980 ~(uint32_t)fpscrMask); 981 misc_reg = MISCREG_FPSCR; 982 } 983 break; 984 case MISCREG_CPSR_Q: 985 { 986 assert(!(newVal & ~CpsrMaskQ)); 987 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 988 misc_reg = MISCREG_CPSR; 989 } 990 break; 991 case MISCREG_FPSCR_QC: 992 { 993 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 994 (newVal & FpscrQcMask); 995 misc_reg = MISCREG_FPSCR; 996 } 997 break; 998 case MISCREG_FPSCR_EXC: 999 { 1000 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 1001 (newVal & FpscrExcMask); 1002 misc_reg = MISCREG_FPSCR; 1003 } 1004 break; 1005 case MISCREG_FPEXC: 1006 { 1007 // vfpv3 architecture, section B.6.1 of DDI04068 1008 // bit 29 - valid only if fpexc[31] is 0 1009 const uint32_t fpexcMask = 0x60000000; 1010 newVal = (newVal & fpexcMask) | 1011 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 1012 } 1013 break; 1014 case MISCREG_HCR: 1015 { 1016 if (!haveVirtualization) 1017 return; 1018 } 1019 break; 1020 case MISCREG_IFSR: 1021 { 1022 // ARM ARM (ARM DDI 0406C.b) B4.1.96 1023 const uint32_t ifsrMask = 1024 mask(31, 13) | mask(11, 11) | mask(8, 6); 1025 newVal = newVal & ~ifsrMask; 1026 } 1027 break; 1028 case MISCREG_DFSR: 1029 { 1030 // ARM ARM (ARM DDI 0406C.b) B4.1.52 1031 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 1032 newVal = newVal & ~dfsrMask; 1033 } 1034 break; 1035 case MISCREG_AMAIR0: 1036 case MISCREG_AMAIR1: 1037 { 1038 // ARM ARM (ARM DDI 0406C.b) B4.1.5 1039 // Valid only with LPAE 1040 if (!haveLPAE) 1041 return; 1042 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 1043 } 1044 break; 1045 case MISCREG_SCR: 1046 getITBPtr(tc)->invalidateMiscReg(); 1047 getDTBPtr(tc)->invalidateMiscReg(); 1048 break; 1049 case MISCREG_SCTLR: 1050 { 1051 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 1052 scr = readMiscRegNoEffect(MISCREG_SCR); 1053 1054 MiscRegIndex sctlr_idx; 1055 if (haveSecurity && !highestELIs64 && !scr.ns) { 1056 sctlr_idx = MISCREG_SCTLR_S; 1057 } else { 1058 sctlr_idx = MISCREG_SCTLR_NS; 1059 } 1060 1061 SCTLR sctlr = miscRegs[sctlr_idx]; 1062 SCTLR new_sctlr = newVal; 1063 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 1064 miscRegs[sctlr_idx] = (RegVal)new_sctlr; 1065 getITBPtr(tc)->invalidateMiscReg(); 1066 getDTBPtr(tc)->invalidateMiscReg(); 1067 } 1068 case MISCREG_MIDR: 1069 case MISCREG_ID_PFR0: 1070 case MISCREG_ID_PFR1: 1071 case MISCREG_ID_DFR0: 1072 case MISCREG_ID_MMFR0: 1073 case MISCREG_ID_MMFR1: 1074 case MISCREG_ID_MMFR2: 1075 case MISCREG_ID_MMFR3: 1076 case MISCREG_ID_ISAR0: 1077 case MISCREG_ID_ISAR1: 1078 case MISCREG_ID_ISAR2: 1079 case MISCREG_ID_ISAR3: 1080 case MISCREG_ID_ISAR4: 1081 case MISCREG_ID_ISAR5: 1082 1083 case MISCREG_MPIDR: 1084 case MISCREG_FPSID: 1085 case MISCREG_TLBTR: 1086 case MISCREG_MVFR0: 1087 case MISCREG_MVFR1: 1088 1089 case MISCREG_ID_AA64AFR0_EL1: 1090 case MISCREG_ID_AA64AFR1_EL1: 1091 case MISCREG_ID_AA64DFR0_EL1: 1092 case MISCREG_ID_AA64DFR1_EL1: 1093 case MISCREG_ID_AA64ISAR0_EL1: 1094 case MISCREG_ID_AA64ISAR1_EL1: 1095 case MISCREG_ID_AA64MMFR0_EL1: 1096 case MISCREG_ID_AA64MMFR1_EL1: 1097 case MISCREG_ID_AA64MMFR2_EL1: 1098 case MISCREG_ID_AA64PFR0_EL1: 1099 case MISCREG_ID_AA64PFR1_EL1: 1100 // ID registers are constants. 1101 return; 1102 1103 // TLB Invalidate All 1104 case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 1105 { 1106 assert32(tc); 1107 scr = readMiscReg(MISCREG_SCR, tc); 1108 1109 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1110 tlbiOp(tc); 1111 return; 1112 } 1113 // TLB Invalidate All, Inner Shareable 1114 case MISCREG_TLBIALLIS: 1115 { 1116 assert32(tc); 1117 scr = readMiscReg(MISCREG_SCR, tc); 1118 1119 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1120 tlbiOp.broadcast(tc); 1121 return; 1122 } 1123 // Instruction TLB Invalidate All 1124 case MISCREG_ITLBIALL: 1125 { 1126 assert32(tc); 1127 scr = readMiscReg(MISCREG_SCR, tc); 1128 1129 ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1130 tlbiOp(tc); 1131 return; 1132 } 1133 // Data TLB Invalidate All 1134 case MISCREG_DTLBIALL: 1135 { 1136 assert32(tc); 1137 scr = readMiscReg(MISCREG_SCR, tc); 1138 1139 DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1140 tlbiOp(tc); 1141 return; 1142 } 1143 // TLB Invalidate by VA 1144 // mcr tlbimval(is) is invalidating all matching entries 1145 // regardless of the level of lookup, since in gem5 we cache 1146 // in the tlb the last level of lookup only. 1147 case MISCREG_TLBIMVA: 1148 case MISCREG_TLBIMVAL: 1149 { 1150 assert32(tc); 1151 scr = readMiscReg(MISCREG_SCR, tc); 1152 1153 TLBIMVA tlbiOp(EL1, 1154 haveSecurity && !scr.ns, 1155 mbits(newVal, 31, 12), 1156 bits(newVal, 7,0)); 1157 1158 tlbiOp(tc); 1159 return; 1160 } 1161 // TLB Invalidate by VA, Inner Shareable 1162 case MISCREG_TLBIMVAIS: 1163 case MISCREG_TLBIMVALIS: 1164 { 1165 assert32(tc); 1166 scr = readMiscReg(MISCREG_SCR, tc); 1167 1168 TLBIMVA tlbiOp(EL1, 1169 haveSecurity && !scr.ns, 1170 mbits(newVal, 31, 12), 1171 bits(newVal, 7,0)); 1172 1173 tlbiOp.broadcast(tc); 1174 return; 1175 } 1176 // TLB Invalidate by ASID match 1177 case MISCREG_TLBIASID: 1178 { 1179 assert32(tc); 1180 scr = readMiscReg(MISCREG_SCR, tc); 1181 1182 TLBIASID tlbiOp(EL1, 1183 haveSecurity && !scr.ns, 1184 bits(newVal, 7,0)); 1185 1186 tlbiOp(tc); 1187 return; 1188 } 1189 // TLB Invalidate by ASID match, Inner Shareable 1190 case MISCREG_TLBIASIDIS: 1191 { 1192 assert32(tc); 1193 scr = readMiscReg(MISCREG_SCR, tc); 1194 1195 TLBIASID tlbiOp(EL1, 1196 haveSecurity && !scr.ns, 1197 bits(newVal, 7,0)); 1198 1199 tlbiOp.broadcast(tc); 1200 return; 1201 } 1202 // mcr tlbimvaal(is) is invalidating all matching entries 1203 // regardless of the level of lookup, since in gem5 we cache 1204 // in the tlb the last level of lookup only. 1205 // TLB Invalidate by VA, All ASID 1206 case MISCREG_TLBIMVAA: 1207 case MISCREG_TLBIMVAAL: 1208 { 1209 assert32(tc); 1210 scr = readMiscReg(MISCREG_SCR, tc); 1211 1212 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1213 mbits(newVal, 31,12)); 1214 1215 tlbiOp(tc); 1216 return; 1217 } 1218 // TLB Invalidate by VA, All ASID, Inner Shareable 1219 case MISCREG_TLBIMVAAIS: 1220 case MISCREG_TLBIMVAALIS: 1221 { 1222 assert32(tc); 1223 scr = readMiscReg(MISCREG_SCR, tc); 1224 1225 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1226 mbits(newVal, 31,12)); 1227 1228 tlbiOp.broadcast(tc); 1229 return; 1230 } 1231 // mcr tlbimvalh(is) is invalidating all matching entries 1232 // regardless of the level of lookup, since in gem5 we cache 1233 // in the tlb the last level of lookup only. 1234 // TLB Invalidate by VA, Hyp mode 1235 case MISCREG_TLBIMVAH: 1236 case MISCREG_TLBIMVALH: 1237 { 1238 assert32(tc); 1239 scr = readMiscReg(MISCREG_SCR, tc); 1240 1241 TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns, 1242 mbits(newVal, 31,12)); 1243 1244 tlbiOp(tc); 1245 return; 1246 } 1247 // TLB Invalidate by VA, Hyp mode, Inner Shareable 1248 case MISCREG_TLBIMVAHIS: 1249 case MISCREG_TLBIMVALHIS: 1250 { 1251 assert32(tc); 1252 scr = readMiscReg(MISCREG_SCR, tc); 1253 1254 TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns, 1255 mbits(newVal, 31,12)); 1256 1257 tlbiOp.broadcast(tc); 1258 return; 1259 } 1260 // mcr tlbiipas2l(is) is invalidating all matching entries 1261 // regardless of the level of lookup, since in gem5 we cache 1262 // in the tlb the last level of lookup only. 1263 // TLB Invalidate by Intermediate Physical Address, Stage 2 1264 case MISCREG_TLBIIPAS2: 1265 case MISCREG_TLBIIPAS2L: 1266 { 1267 assert32(tc); 1268 scr = readMiscReg(MISCREG_SCR, tc); 1269 1270 TLBIIPA tlbiOp(EL1, 1271 haveSecurity && !scr.ns, 1272 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1273 1274 tlbiOp(tc); 1275 return; 1276 } 1277 // TLB Invalidate by Intermediate Physical Address, Stage 2, 1278 // Inner Shareable 1279 case MISCREG_TLBIIPAS2IS: 1280 case MISCREG_TLBIIPAS2LIS: 1281 { 1282 assert32(tc); 1283 scr = readMiscReg(MISCREG_SCR, tc); 1284 1285 TLBIIPA tlbiOp(EL1, 1286 haveSecurity && !scr.ns, 1287 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1288 1289 tlbiOp.broadcast(tc); 1290 return; 1291 } 1292 // Instruction TLB Invalidate by VA 1293 case MISCREG_ITLBIMVA: 1294 { 1295 assert32(tc); 1296 scr = readMiscReg(MISCREG_SCR, tc); 1297 1298 ITLBIMVA tlbiOp(EL1, 1299 haveSecurity && !scr.ns, 1300 mbits(newVal, 31, 12), 1301 bits(newVal, 7,0)); 1302 1303 tlbiOp(tc); 1304 return; 1305 } 1306 // Data TLB Invalidate by VA 1307 case MISCREG_DTLBIMVA: 1308 { 1309 assert32(tc); 1310 scr = readMiscReg(MISCREG_SCR, tc); 1311 1312 DTLBIMVA tlbiOp(EL1, 1313 haveSecurity && !scr.ns, 1314 mbits(newVal, 31, 12), 1315 bits(newVal, 7,0)); 1316 1317 tlbiOp(tc); 1318 return; 1319 } 1320 // Instruction TLB Invalidate by ASID match 1321 case MISCREG_ITLBIASID: 1322 { 1323 assert32(tc); 1324 scr = readMiscReg(MISCREG_SCR, tc); 1325 1326 ITLBIASID tlbiOp(EL1, 1327 haveSecurity && !scr.ns, 1328 bits(newVal, 7,0)); 1329 1330 tlbiOp(tc); 1331 return; 1332 } 1333 // Data TLB Invalidate by ASID match 1334 case MISCREG_DTLBIASID: 1335 { 1336 assert32(tc); 1337 scr = readMiscReg(MISCREG_SCR, tc); 1338 1339 DTLBIASID tlbiOp(EL1, 1340 haveSecurity && !scr.ns, 1341 bits(newVal, 7,0)); 1342 1343 tlbiOp(tc); 1344 return; 1345 } 1346 // TLB Invalidate All, Non-Secure Non-Hyp 1347 case MISCREG_TLBIALLNSNH: 1348 { 1349 assert32(tc); 1350 1351 TLBIALLN tlbiOp(EL1); 1352 tlbiOp(tc); 1353 return; 1354 } 1355 // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable 1356 case MISCREG_TLBIALLNSNHIS: 1357 { 1358 assert32(tc); 1359 1360 TLBIALLN tlbiOp(EL1); 1361 tlbiOp.broadcast(tc); 1362 return; 1363 } 1364 // TLB Invalidate All, Hyp mode 1365 case MISCREG_TLBIALLH: 1366 { 1367 assert32(tc); 1368 1369 TLBIALLN tlbiOp(EL2); 1370 tlbiOp(tc); 1371 return; 1372 } 1373 // TLB Invalidate All, Hyp mode, Inner Shareable 1374 case MISCREG_TLBIALLHIS: 1375 { 1376 assert32(tc); 1377 1378 TLBIALLN tlbiOp(EL2); 1379 tlbiOp.broadcast(tc); 1380 return; 1381 } 1382 // AArch64 TLB Invalidate All, EL3 1383 case MISCREG_TLBI_ALLE3: 1384 { 1385 assert64(tc); 1386 1387 TLBIALL tlbiOp(EL3, true); 1388 tlbiOp(tc); 1389 return; 1390 } 1391 // AArch64 TLB Invalidate All, EL3, Inner Shareable 1392 case MISCREG_TLBI_ALLE3IS: 1393 { 1394 assert64(tc); 1395 1396 TLBIALL tlbiOp(EL3, true); 1397 tlbiOp.broadcast(tc); 1398 return; 1399 } 1400 // AArch64 TLB Invalidate All, EL2, Inner Shareable 1401 case MISCREG_TLBI_ALLE2: 1402 case MISCREG_TLBI_ALLE2IS: 1403 { 1404 assert64(tc); 1405 scr = readMiscReg(MISCREG_SCR, tc); 1406 1407 TLBIALL tlbiOp(EL2, haveSecurity && !scr.ns); 1408 tlbiOp(tc); 1409 return; 1410 } 1411 // AArch64 TLB Invalidate All, EL1 1412 case MISCREG_TLBI_ALLE1: 1413 case MISCREG_TLBI_VMALLE1: 1414 case MISCREG_TLBI_VMALLS12E1: 1415 // @todo: handle VMID and stage 2 to enable Virtualization 1416 { 1417 assert64(tc); 1418 scr = readMiscReg(MISCREG_SCR, tc); 1419 1420 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1421 tlbiOp(tc); 1422 return; 1423 } 1424 // AArch64 TLB Invalidate All, EL1, Inner Shareable 1425 case MISCREG_TLBI_ALLE1IS: 1426 case MISCREG_TLBI_VMALLE1IS: 1427 case MISCREG_TLBI_VMALLS12E1IS: 1428 // @todo: handle VMID and stage 2 to enable Virtualization 1429 { 1430 assert64(tc); 1431 scr = readMiscReg(MISCREG_SCR, tc); 1432 1433 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1434 tlbiOp.broadcast(tc); 1435 return; 1436 } 1437 // VAEx(IS) and VALEx(IS) are the same because TLBs 1438 // only store entries 1439 // from the last level of translation table walks 1440 // @todo: handle VMID to enable Virtualization 1441 // AArch64 TLB Invalidate by VA, EL3 1442 case MISCREG_TLBI_VAE3_Xt: 1443 case MISCREG_TLBI_VALE3_Xt: 1444 { 1445 assert64(tc); 1446 1447 TLBIMVA tlbiOp(EL3, true, 1448 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1449 0xbeef); 1450 tlbiOp(tc); 1451 return; 1452 } 1453 // AArch64 TLB Invalidate by VA, EL3, Inner Shareable 1454 case MISCREG_TLBI_VAE3IS_Xt: 1455 case MISCREG_TLBI_VALE3IS_Xt: 1456 { 1457 assert64(tc); 1458 1459 TLBIMVA tlbiOp(EL3, true, 1460 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1461 0xbeef); 1462 1463 tlbiOp.broadcast(tc); 1464 return; 1465 } 1466 // AArch64 TLB Invalidate by VA, EL2 1467 case MISCREG_TLBI_VAE2_Xt: 1468 case MISCREG_TLBI_VALE2_Xt: 1469 { 1470 assert64(tc); 1471 scr = readMiscReg(MISCREG_SCR, tc); 1472 1473 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1474 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1475 0xbeef); 1476 tlbiOp(tc); 1477 return; 1478 } 1479 // AArch64 TLB Invalidate by VA, EL2, Inner Shareable 1480 case MISCREG_TLBI_VAE2IS_Xt: 1481 case MISCREG_TLBI_VALE2IS_Xt: 1482 { 1483 assert64(tc); 1484 scr = readMiscReg(MISCREG_SCR, tc); 1485 1486 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1487 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1488 0xbeef); 1489 1490 tlbiOp.broadcast(tc); 1491 return; 1492 } 1493 // AArch64 TLB Invalidate by VA, EL1 1494 case MISCREG_TLBI_VAE1_Xt: 1495 case MISCREG_TLBI_VALE1_Xt: 1496 { 1497 assert64(tc); 1498 scr = readMiscReg(MISCREG_SCR, tc); 1499 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1500 bits(newVal, 55, 48); 1501 1502 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1503 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1504 asid); 1505 1506 tlbiOp(tc); 1507 return; 1508 } 1509 // AArch64 TLB Invalidate by VA, EL1, Inner Shareable 1510 case MISCREG_TLBI_VAE1IS_Xt: 1511 case MISCREG_TLBI_VALE1IS_Xt: 1512 { 1513 assert64(tc); 1514 scr = readMiscReg(MISCREG_SCR, tc); 1515 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1516 bits(newVal, 55, 48); 1517 1518 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1519 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1520 asid); 1521 1522 tlbiOp.broadcast(tc); 1523 return; 1524 } 1525 // AArch64 TLB Invalidate by ASID, EL1 1526 // @todo: handle VMID to enable Virtualization 1527 case MISCREG_TLBI_ASIDE1_Xt: 1528 { 1529 assert64(tc); 1530 scr = readMiscReg(MISCREG_SCR, tc); 1531 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1532 bits(newVal, 55, 48); 1533 1534 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1535 tlbiOp(tc); 1536 return; 1537 } 1538 // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable 1539 case MISCREG_TLBI_ASIDE1IS_Xt: 1540 { 1541 assert64(tc); 1542 scr = readMiscReg(MISCREG_SCR, tc); 1543 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1544 bits(newVal, 55, 48); 1545 1546 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1547 tlbiOp.broadcast(tc); 1548 return; 1549 } 1550 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 1551 // entries from the last level of translation table walks 1552 // AArch64 TLB Invalidate by VA, All ASID, EL1 1553 case MISCREG_TLBI_VAAE1_Xt: 1554 case MISCREG_TLBI_VAALE1_Xt: 1555 { 1556 assert64(tc); 1557 scr = readMiscReg(MISCREG_SCR, tc); 1558 1559 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1560 static_cast<Addr>(bits(newVal, 43, 0)) << 12); 1561 1562 tlbiOp(tc); 1563 return; 1564 } 1565 // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable 1566 case MISCREG_TLBI_VAAE1IS_Xt: 1567 case MISCREG_TLBI_VAALE1IS_Xt: 1568 { 1569 assert64(tc); 1570 scr = readMiscReg(MISCREG_SCR, tc); 1571 1572 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1573 static_cast<Addr>(bits(newVal, 43, 0)) << 12); 1574 1575 tlbiOp.broadcast(tc); 1576 return; 1577 } 1578 // AArch64 TLB Invalidate by Intermediate Physical Address, 1579 // Stage 2, EL1 1580 case MISCREG_TLBI_IPAS2E1_Xt: 1581 case MISCREG_TLBI_IPAS2LE1_Xt: 1582 { 1583 assert64(tc); 1584 scr = readMiscReg(MISCREG_SCR, tc); 1585 1586 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1587 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1588 1589 tlbiOp(tc); 1590 return; 1591 } 1592 // AArch64 TLB Invalidate by Intermediate Physical Address, 1593 // Stage 2, EL1, Inner Shareable 1594 case MISCREG_TLBI_IPAS2E1IS_Xt: 1595 case MISCREG_TLBI_IPAS2LE1IS_Xt: 1596 { 1597 assert64(tc); 1598 scr = readMiscReg(MISCREG_SCR, tc); 1599 1600 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1601 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1602 1603 tlbiOp.broadcast(tc); 1604 return; 1605 } 1606 case MISCREG_ACTLR: 1607 warn("Not doing anything for write of miscreg ACTLR\n"); 1608 break; 1609 1610 case MISCREG_PMXEVTYPER_PMCCFILTR: 1611 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 1612 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 1613 case MISCREG_PMCR ... MISCREG_PMOVSSET: 1614 pmu->setMiscReg(misc_reg, newVal); 1615 break; 1616 1617 1618 case MISCREG_HSTR: // TJDBX, now redifined to be RES0 1619 { 1620 HSTR hstrMask = 0; 1621 hstrMask.tjdbx = 1; 1622 newVal &= ~((uint32_t) hstrMask); 1623 break; 1624 } 1625 case MISCREG_HCPTR: 1626 { 1627 // If a CP bit in NSACR is 0 then the corresponding bit in 1628 // HCPTR is RAO/WI. Same applies to NSASEDIS 1629 secure_lookup = haveSecurity && 1630 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 1631 readMiscRegNoEffect(MISCREG_CPSR)); 1632 if (!secure_lookup) { 1633 RegVal oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 1634 RegVal mask = 1635 (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 1636 newVal = (newVal & ~mask) | (oldValue & mask); 1637 } 1638 break; 1639 } 1640 case MISCREG_HDFAR: // alias for secure DFAR 1641 misc_reg = MISCREG_DFAR_S; 1642 break; 1643 case MISCREG_HIFAR: // alias for secure IFAR 1644 misc_reg = MISCREG_IFAR_S; 1645 break; 1646 case MISCREG_ATS1CPR: 1647 case MISCREG_ATS1CPW: 1648 case MISCREG_ATS1CUR: 1649 case MISCREG_ATS1CUW: 1650 case MISCREG_ATS12NSOPR: 1651 case MISCREG_ATS12NSOPW: 1652 case MISCREG_ATS12NSOUR: 1653 case MISCREG_ATS12NSOUW: 1654 case MISCREG_ATS1HR: 1655 case MISCREG_ATS1HW: 1656 { 1657 Request::Flags flags = 0; 1658 BaseTLB::Mode mode = BaseTLB::Read; 1659 TLB::ArmTranslationType tranType = TLB::NormalTran; 1660 Fault fault; 1661 switch(misc_reg) { 1662 case MISCREG_ATS1CPR: 1663 flags = TLB::MustBeOne; 1664 tranType = TLB::S1CTran; 1665 mode = BaseTLB::Read; 1666 break; 1667 case MISCREG_ATS1CPW: 1668 flags = TLB::MustBeOne; 1669 tranType = TLB::S1CTran; 1670 mode = BaseTLB::Write; 1671 break; 1672 case MISCREG_ATS1CUR: 1673 flags = TLB::MustBeOne | TLB::UserMode; 1674 tranType = TLB::S1CTran; 1675 mode = BaseTLB::Read; 1676 break; 1677 case MISCREG_ATS1CUW: 1678 flags = TLB::MustBeOne | TLB::UserMode; 1679 tranType = TLB::S1CTran; 1680 mode = BaseTLB::Write; 1681 break; 1682 case MISCREG_ATS12NSOPR: 1683 if (!haveSecurity) 1684 panic("Security Extensions required for ATS12NSOPR"); 1685 flags = TLB::MustBeOne; 1686 tranType = TLB::S1S2NsTran; 1687 mode = BaseTLB::Read; 1688 break; 1689 case MISCREG_ATS12NSOPW: 1690 if (!haveSecurity) 1691 panic("Security Extensions required for ATS12NSOPW"); 1692 flags = TLB::MustBeOne; 1693 tranType = TLB::S1S2NsTran; 1694 mode = BaseTLB::Write; 1695 break; 1696 case MISCREG_ATS12NSOUR: 1697 if (!haveSecurity) 1698 panic("Security Extensions required for ATS12NSOUR"); 1699 flags = TLB::MustBeOne | TLB::UserMode; 1700 tranType = TLB::S1S2NsTran; 1701 mode = BaseTLB::Read; 1702 break; 1703 case MISCREG_ATS12NSOUW: 1704 if (!haveSecurity) 1705 panic("Security Extensions required for ATS12NSOUW"); 1706 flags = TLB::MustBeOne | TLB::UserMode; 1707 tranType = TLB::S1S2NsTran; 1708 mode = BaseTLB::Write; 1709 break; 1710 case MISCREG_ATS1HR: // only really useful from secure mode. 1711 flags = TLB::MustBeOne; 1712 tranType = TLB::HypMode; 1713 mode = BaseTLB::Read; 1714 break; 1715 case MISCREG_ATS1HW: 1716 flags = TLB::MustBeOne; 1717 tranType = TLB::HypMode; 1718 mode = BaseTLB::Write; 1719 break; 1720 } 1721 // If we're in timing mode then doing the translation in 1722 // functional mode then we're slightly distorting performance 1723 // results obtained from simulations. The translation should be 1724 // done in the same mode the core is running in. NOTE: This 1725 // can't be an atomic translation because that causes problems 1726 // with unexpected atomic snoop requests. 1727 warn("Translating via %s in functional mode! Fix Me!\n", 1728 miscRegName[misc_reg]); 1729 1730 auto req = std::make_shared<Request>( 1731 0, val, 0, flags, Request::funcMasterId, 1732 tc->pcState().pc(), tc->contextId()); 1733 1734 fault = getDTBPtr(tc)->translateFunctional( 1735 req, tc, mode, tranType); 1736 1737 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1738 HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 1739 1740 RegVal newVal; 1741 if (fault == NoFault) { 1742 Addr paddr = req->getPaddr(); 1743 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 1744 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 1745 newVal = (paddr & mask(39, 12)) | 1746 (getDTBPtr(tc)->getAttr()); 1747 } else { 1748 newVal = (paddr & 0xfffff000) | 1749 (getDTBPtr(tc)->getAttr()); 1750 } 1751 DPRINTF(MiscRegs, 1752 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 1753 val, newVal); 1754 } else { 1755 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1756 armFault->update(tc); 1757 // Set fault bit and FSR 1758 FSR fsr = armFault->getFsr(tc); 1759 1760 newVal = ((fsr >> 9) & 1) << 11; 1761 if (newVal) { 1762 // LPAE - rearange fault status 1763 newVal |= ((fsr >> 0) & 0x3f) << 1; 1764 } else { 1765 // VMSA - rearange fault status 1766 newVal |= ((fsr >> 0) & 0xf) << 1; 1767 newVal |= ((fsr >> 10) & 0x1) << 5; 1768 newVal |= ((fsr >> 12) & 0x1) << 6; 1769 } 1770 newVal |= 0x1; // F bit 1771 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1772 newVal |= armFault->isStage2() ? 0x200 : 0; 1773 DPRINTF(MiscRegs, 1774 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 1775 val, fsr, newVal); 1776 } 1777 setMiscRegNoEffect(MISCREG_PAR, newVal); 1778 return; 1779 } 1780 case MISCREG_TTBCR: 1781 { 1782 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1783 const uint32_t ones = (uint32_t)(-1); 1784 TTBCR ttbcrMask = 0; 1785 TTBCR ttbcrNew = newVal; 1786 1787 // ARM DDI 0406C.b, ARMv7-32 1788 ttbcrMask.n = ones; // T0SZ 1789 if (haveSecurity) { 1790 ttbcrMask.pd0 = ones; 1791 ttbcrMask.pd1 = ones; 1792 } 1793 ttbcrMask.epd0 = ones; 1794 ttbcrMask.irgn0 = ones; 1795 ttbcrMask.orgn0 = ones; 1796 ttbcrMask.sh0 = ones; 1797 ttbcrMask.ps = ones; // T1SZ 1798 ttbcrMask.a1 = ones; 1799 ttbcrMask.epd1 = ones; 1800 ttbcrMask.irgn1 = ones; 1801 ttbcrMask.orgn1 = ones; 1802 ttbcrMask.sh1 = ones; 1803 if (haveLPAE) 1804 ttbcrMask.eae = ones; 1805 1806 if (haveLPAE && ttbcrNew.eae) { 1807 newVal = newVal & ttbcrMask; 1808 } else { 1809 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 1810 } 1811 // Invalidate TLB MiscReg 1812 getITBPtr(tc)->invalidateMiscReg(); 1813 getDTBPtr(tc)->invalidateMiscReg(); 1814 break; 1815 } 1816 case MISCREG_TTBR0: 1817 case MISCREG_TTBR1: 1818 { 1819 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1820 if (haveLPAE) { 1821 if (ttbcr.eae) { 1822 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 1823 // ARMv8 AArch32 bit 63-56 only 1824 uint64_t ttbrMask = mask(63,56) | mask(47,40); 1825 newVal = (newVal & (~ttbrMask)); 1826 } 1827 } 1828 // Invalidate TLB MiscReg 1829 getITBPtr(tc)->invalidateMiscReg(); 1830 getDTBPtr(tc)->invalidateMiscReg(); 1831 break; 1832 } 1833 case MISCREG_SCTLR_EL1: 1834 case MISCREG_CONTEXTIDR: 1835 case MISCREG_PRRR: 1836 case MISCREG_NMRR: 1837 case MISCREG_MAIR0: 1838 case MISCREG_MAIR1: 1839 case MISCREG_DACR: 1840 case MISCREG_VTTBR: 1841 case MISCREG_SCR_EL3: 1842 case MISCREG_HCR_EL2: 1843 case MISCREG_TCR_EL1: 1844 case MISCREG_TCR_EL2: 1845 case MISCREG_TCR_EL3: 1846 case MISCREG_SCTLR_EL2: 1847 case MISCREG_SCTLR_EL3: 1848 case MISCREG_HSCTLR: 1849 case MISCREG_TTBR0_EL1: 1850 case MISCREG_TTBR1_EL1: 1851 case MISCREG_TTBR0_EL2: 1852 case MISCREG_TTBR1_EL2: 1853 case MISCREG_TTBR0_EL3: 1854 getITBPtr(tc)->invalidateMiscReg(); 1855 getDTBPtr(tc)->invalidateMiscReg(); 1856 break; 1857 case MISCREG_NZCV: 1858 { 1859 CPSR cpsr = val; 1860 1861 tc->setCCReg(CCREG_NZ, cpsr.nz); 1862 tc->setCCReg(CCREG_C, cpsr.c); 1863 tc->setCCReg(CCREG_V, cpsr.v); 1864 } 1865 break; 1866 case MISCREG_DAIF: 1867 { 1868 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1869 cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 1870 newVal = cpsr; 1871 misc_reg = MISCREG_CPSR; 1872 } 1873 break; 1874 case MISCREG_SP_EL0: 1875 tc->setIntReg(INTREG_SP0, newVal); 1876 break; 1877 case MISCREG_SP_EL1: 1878 tc->setIntReg(INTREG_SP1, newVal); 1879 break; 1880 case MISCREG_SP_EL2: 1881 tc->setIntReg(INTREG_SP2, newVal); 1882 break; 1883 case MISCREG_SPSEL: 1884 { 1885 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1886 cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 1887 newVal = cpsr; 1888 misc_reg = MISCREG_CPSR; 1889 } 1890 break; 1891 case MISCREG_CURRENTEL: 1892 { 1893 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1894 cpsr.el = (uint8_t) ((CPSR) newVal).el; 1895 newVal = cpsr; 1896 misc_reg = MISCREG_CPSR; 1897 } 1898 break; 1899 case MISCREG_PAN: 1900 { 1901 // PAN is affecting data accesses 1902 getDTBPtr(tc)->invalidateMiscReg(); 1903 1904 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1905 cpsr.pan = (uint8_t) ((CPSR) newVal).pan; 1906 newVal = cpsr; 1907 misc_reg = MISCREG_CPSR; 1908 } 1909 break; 1910 case MISCREG_AT_S1E1R_Xt: 1911 case MISCREG_AT_S1E1W_Xt: 1912 case MISCREG_AT_S1E0R_Xt: 1913 case MISCREG_AT_S1E0W_Xt: 1914 case MISCREG_AT_S1E2R_Xt: 1915 case MISCREG_AT_S1E2W_Xt: 1916 case MISCREG_AT_S12E1R_Xt: 1917 case MISCREG_AT_S12E1W_Xt: 1918 case MISCREG_AT_S12E0R_Xt: 1919 case MISCREG_AT_S12E0W_Xt: 1920 case MISCREG_AT_S1E3R_Xt: 1921 case MISCREG_AT_S1E3W_Xt: 1922 { 1923 RequestPtr req = std::make_shared<Request>(); 1924 Request::Flags flags = 0; 1925 BaseTLB::Mode mode = BaseTLB::Read; 1926 TLB::ArmTranslationType tranType = TLB::NormalTran; 1927 Fault fault; 1928 switch(misc_reg) { 1929 case MISCREG_AT_S1E1R_Xt: 1930 flags = TLB::MustBeOne; 1931 tranType = TLB::S1E1Tran; 1932 mode = BaseTLB::Read; 1933 break; 1934 case MISCREG_AT_S1E1W_Xt: 1935 flags = TLB::MustBeOne; 1936 tranType = TLB::S1E1Tran; 1937 mode = BaseTLB::Write; 1938 break; 1939 case MISCREG_AT_S1E0R_Xt: 1940 flags = TLB::MustBeOne | TLB::UserMode; 1941 tranType = TLB::S1E0Tran; 1942 mode = BaseTLB::Read; 1943 break; 1944 case MISCREG_AT_S1E0W_Xt: 1945 flags = TLB::MustBeOne | TLB::UserMode; 1946 tranType = TLB::S1E0Tran; 1947 mode = BaseTLB::Write; 1948 break; 1949 case MISCREG_AT_S1E2R_Xt: 1950 flags = TLB::MustBeOne; 1951 tranType = TLB::S1E2Tran; 1952 mode = BaseTLB::Read; 1953 break; 1954 case MISCREG_AT_S1E2W_Xt: 1955 flags = TLB::MustBeOne; 1956 tranType = TLB::S1E2Tran; 1957 mode = BaseTLB::Write; 1958 break; 1959 case MISCREG_AT_S12E0R_Xt: 1960 flags = TLB::MustBeOne | TLB::UserMode; 1961 tranType = TLB::S12E0Tran; 1962 mode = BaseTLB::Read; 1963 break; 1964 case MISCREG_AT_S12E0W_Xt: 1965 flags = TLB::MustBeOne | TLB::UserMode; 1966 tranType = TLB::S12E0Tran; 1967 mode = BaseTLB::Write; 1968 break; 1969 case MISCREG_AT_S12E1R_Xt: 1970 flags = TLB::MustBeOne; 1971 tranType = TLB::S12E1Tran; 1972 mode = BaseTLB::Read; 1973 break; 1974 case MISCREG_AT_S12E1W_Xt: 1975 flags = TLB::MustBeOne; 1976 tranType = TLB::S12E1Tran; 1977 mode = BaseTLB::Write; 1978 break; 1979 case MISCREG_AT_S1E3R_Xt: 1980 flags = TLB::MustBeOne; 1981 tranType = TLB::S1E3Tran; 1982 mode = BaseTLB::Read; 1983 break; 1984 case MISCREG_AT_S1E3W_Xt: 1985 flags = TLB::MustBeOne; 1986 tranType = TLB::S1E3Tran; 1987 mode = BaseTLB::Write; 1988 break; 1989 } 1990 // If we're in timing mode then doing the translation in 1991 // functional mode then we're slightly distorting performance 1992 // results obtained from simulations. The translation should be 1993 // done in the same mode the core is running in. NOTE: This 1994 // can't be an atomic translation because that causes problems 1995 // with unexpected atomic snoop requests. 1996 warn("Translating via %s in functional mode! Fix Me!\n", 1997 miscRegName[misc_reg]); 1998 1999 req->setVirt(0, val, 0, flags, Request::funcMasterId, 2000 tc->pcState().pc()); 2001 req->setContext(tc->contextId()); 2002 fault = getDTBPtr(tc)->translateFunctional(req, tc, mode, 2003 tranType); 2004 2005 RegVal newVal; 2006 if (fault == NoFault) { 2007 Addr paddr = req->getPaddr(); 2008 uint64_t attr = getDTBPtr(tc)->getAttr(); 2009 uint64_t attr1 = attr >> 56; 2010 if (!attr1 || attr1 ==0x44) { 2011 attr |= 0x100; 2012 attr &= ~ uint64_t(0x80); 2013 } 2014 newVal = (paddr & mask(47, 12)) | attr; 2015 DPRINTF(MiscRegs, 2016 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 2017 val, newVal); 2018 } else { 2019 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 2020 armFault->update(tc); 2021 // Set fault bit and FSR 2022 FSR fsr = armFault->getFsr(tc); 2023 2024 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 2025 if (cpsr.width) { // AArch32 2026 newVal = ((fsr >> 9) & 1) << 11; 2027 // rearrange fault status 2028 newVal |= ((fsr >> 0) & 0x3f) << 1; 2029 newVal |= 0x1; // F bit 2030 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 2031 newVal |= armFault->isStage2() ? 0x200 : 0; 2032 } else { // AArch64 2033 newVal = 1; // F bit 2034 newVal |= fsr << 1; // FST 2035 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit. 2036 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 2037 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 2038 newVal |= 1 << 11; // RES1 2039 } 2040 DPRINTF(MiscRegs, 2041 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 2042 val, fsr, newVal); 2043 } 2044 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 2045 return; 2046 } 2047 case MISCREG_SPSR_EL3: 2048 case MISCREG_SPSR_EL2: 2049 case MISCREG_SPSR_EL1: 2050 { 2051 RegVal spsr_mask = havePAN ? 2052 ~(0x5 << 21) : ~(0x7 << 21); 2053 2054 newVal = val & spsr_mask; 2055 break; 2056 } 2057 case MISCREG_L2CTLR: 2058 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 2059 miscRegName[misc_reg], uint32_t(val)); 2060 break; 2061 2062 // Generic Timer registers 2063 case MISCREG_CNTHV_CTL_EL2: 2064 case MISCREG_CNTHV_CVAL_EL2: 2065 case MISCREG_CNTHV_TVAL_EL2: 2066 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 2067 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 2068 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 2069 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 2070 getGenericTimer(tc).setMiscReg(misc_reg, newVal); 2071 break; 2072 case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3: 2073 case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2: 2074 getGICv3CPUInterface(tc).setMiscReg(misc_reg, newVal); 2075 return; 2076 case MISCREG_ZCR_EL3: 2077 case MISCREG_ZCR_EL2: 2078 case MISCREG_ZCR_EL1: 2079 tc->getDecoderPtr()->setSveLen( 2080 (getCurSveVecLenInBits(tc) >> 7) - 1); 2081 break; 2082 } 2083 } 2084 setMiscRegNoEffect(misc_reg, newVal); 2085} 2086 2087BaseISADevice & 2088ISA::getGenericTimer(ThreadContext *tc) 2089{ 2090 // We only need to create an ISA interface the first time we try 2091 // to access the timer. 2092 if (timer) 2093 return *timer.get(); 2094 2095 assert(system); 2096 GenericTimer *generic_timer(system->getGenericTimer()); 2097 if (!generic_timer) { 2098 panic("Trying to get a generic timer from a system that hasn't " 2099 "been configured to use a generic timer.\n"); 2100 } 2101 2102 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 2103 timer->setThreadContext(tc); 2104 2105 return *timer.get(); 2106} 2107 2108BaseISADevice & 2109ISA::getGICv3CPUInterface(ThreadContext *tc) 2110{ 2111 panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!"); 2112 return *gicv3CpuInterface.get(); 2113} 2114 2115unsigned 2116ISA::getCurSveVecLenInBits(ThreadContext *tc) const 2117{ 2118 if (!FullSystem) { 2119 return sveVL * 128; 2120 } 2121 2122 panic_if(!tc, 2123 "A ThreadContext is needed to determine the SVE vector length " 2124 "in full-system mode"); 2125 2126 CPSR cpsr = miscRegs[MISCREG_CPSR]; 2127 ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el; 2128 2129 unsigned len = 0; 2130 2131 if (el == EL1 || (el == EL0 && !ELIsInHost(tc, el))) { 2132 len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL1]).len; 2133 } 2134 2135 if (el == EL2 || (el == EL0 && ELIsInHost(tc, el))) { 2136 len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL2]).len; 2137 } else if (haveVirtualization && !inSecureState(tc) && 2138 (el == EL0 || el == EL1)) { 2139 len = std::min( 2140 len, 2141 static_cast<unsigned>( 2142 static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL2]).len)); 2143 } 2144 2145 if (el == EL3) { 2146 len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL3]).len; 2147 } else if (haveSecurity) { 2148 len = std::min( 2149 len, 2150 static_cast<unsigned>( 2151 static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL3]).len)); 2152 } 2153 2154 len = std::min(len, sveVL - 1); 2155 2156 return (len + 1) * 128; 2157} 2158 2159void 2160ISA::zeroSveVecRegUpperPart(VecRegContainer &vc, unsigned eCount) 2161{ 2162 auto vv = vc.as<uint64_t>(); 2163 for (int i = 2; i < eCount; ++i) { 2164 vv[i] = 0; 2165 } 2166} 2167 2168} // namespace ArmISA 2169 2170ArmISA::ISA * 2171ArmISAParams::create() 2172{ 2173 return new ArmISA::ISA(this); 2174} 2175