isa.cc revision 14000:d85c61dc0b5c
1/* 2 * Copyright (c) 2010-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 */ 40 41#include "arch/arm/isa.hh" 42#include "arch/arm/pmu.hh" 43#include "arch/arm/system.hh" 44#include "arch/arm/tlb.hh" 45#include "arch/arm/tlbi_op.hh" 46#include "cpu/base.hh" 47#include "cpu/checker/cpu.hh" 48#include "debug/Arm.hh" 49#include "debug/MiscRegs.hh" 50#include "dev/arm/generic_timer.hh" 51#include "dev/arm/gic_v3.hh" 52#include "dev/arm/gic_v3_cpu_interface.hh" 53#include "params/ArmISA.hh" 54#include "sim/faults.hh" 55#include "sim/stat_control.hh" 56#include "sim/system.hh" 57 58namespace ArmISA 59{ 60 61ISA::ISA(Params *p) 62 : SimObject(p), 63 system(NULL), 64 _decoderFlavour(p->decoderFlavour), 65 _vecRegRenameMode(Enums::Full), 66 pmu(p->pmu), 67 haveGICv3CPUInterface(false), 68 impdefAsNop(p->impdef_nop), 69 afterStartup(false) 70{ 71 miscRegs[MISCREG_SCTLR_RST] = 0; 72 73 // Hook up a dummy device if we haven't been configured with a 74 // real PMU. By using a dummy device, we don't need to check that 75 // the PMU exist every time we try to access a PMU register. 76 if (!pmu) 77 pmu = &dummyDevice; 78 79 // Give all ISA devices a pointer to this ISA 80 pmu->setISA(this); 81 82 system = dynamic_cast<ArmSystem *>(p->system); 83 84 // Cache system-level properties 85 if (FullSystem && system) { 86 highestELIs64 = system->highestELIs64(); 87 haveSecurity = system->haveSecurity(); 88 haveLPAE = system->haveLPAE(); 89 haveCrypto = system->haveCrypto(); 90 haveVirtualization = system->haveVirtualization(); 91 haveLargeAsid64 = system->haveLargeAsid64(); 92 physAddrRange = system->physAddrRange(); 93 haveSVE = system->haveSVE(); 94 sveVL = system->sveVL(); 95 } else { 96 highestELIs64 = true; // ArmSystem::highestELIs64 does the same 97 haveSecurity = haveLPAE = haveVirtualization = false; 98 haveCrypto = true; 99 haveLargeAsid64 = false; 100 physAddrRange = 32; // dummy value 101 haveSVE = true; 102 sveVL = p->sve_vl_se; 103 } 104 105 // Initial rename mode depends on highestEL 106 const_cast<Enums::VecRegRenameMode&>(_vecRegRenameMode) = 107 highestELIs64 ? Enums::Full : Enums::Elem; 108 109 initializeMiscRegMetadata(); 110 preUnflattenMiscReg(); 111 112 clear(); 113} 114 115std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS); 116 117const ArmISAParams * 118ISA::params() const 119{ 120 return dynamic_cast<const Params *>(_params); 121} 122 123void 124ISA::clear() 125{ 126 const Params *p(params()); 127 128 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 129 memset(miscRegs, 0, sizeof(miscRegs)); 130 131 initID32(p); 132 133 // We always initialize AArch64 ID registers even 134 // if we are in AArch32. This is done since if we 135 // are in SE mode we don't know if our ArmProcess is 136 // AArch32 or AArch64 137 initID64(p); 138 139 // Start with an event in the mailbox 140 miscRegs[MISCREG_SEV_MAILBOX] = 1; 141 142 // Separate Instruction and Data TLBs 143 miscRegs[MISCREG_TLBTR] = 1; 144 145 MVFR0 mvfr0 = 0; 146 mvfr0.advSimdRegisters = 2; 147 mvfr0.singlePrecision = 2; 148 mvfr0.doublePrecision = 2; 149 mvfr0.vfpExceptionTrapping = 0; 150 mvfr0.divide = 1; 151 mvfr0.squareRoot = 1; 152 mvfr0.shortVectors = 1; 153 mvfr0.roundingModes = 1; 154 miscRegs[MISCREG_MVFR0] = mvfr0; 155 156 MVFR1 mvfr1 = 0; 157 mvfr1.flushToZero = 1; 158 mvfr1.defaultNaN = 1; 159 mvfr1.advSimdLoadStore = 1; 160 mvfr1.advSimdInteger = 1; 161 mvfr1.advSimdSinglePrecision = 1; 162 mvfr1.advSimdHalfPrecision = 1; 163 mvfr1.vfpHalfPrecision = 1; 164 miscRegs[MISCREG_MVFR1] = mvfr1; 165 166 // Reset values of PRRR and NMRR are implementation dependent 167 168 // @todo: PRRR and NMRR in secure state? 169 miscRegs[MISCREG_PRRR_NS] = 170 (1 << 19) | // 19 171 (0 << 18) | // 18 172 (0 << 17) | // 17 173 (1 << 16) | // 16 174 (2 << 14) | // 15:14 175 (0 << 12) | // 13:12 176 (2 << 10) | // 11:10 177 (2 << 8) | // 9:8 178 (2 << 6) | // 7:6 179 (2 << 4) | // 5:4 180 (1 << 2) | // 3:2 181 0; // 1:0 182 183 miscRegs[MISCREG_NMRR_NS] = 184 (1 << 30) | // 31:30 185 (0 << 26) | // 27:26 186 (0 << 24) | // 25:24 187 (3 << 22) | // 23:22 188 (2 << 20) | // 21:20 189 (0 << 18) | // 19:18 190 (0 << 16) | // 17:16 191 (1 << 14) | // 15:14 192 (0 << 12) | // 13:12 193 (2 << 10) | // 11:10 194 (0 << 8) | // 9:8 195 (3 << 6) | // 7:6 196 (2 << 4) | // 5:4 197 (0 << 2) | // 3:2 198 0; // 1:0 199 200 if (FullSystem && system->highestELIs64()) { 201 // Initialize AArch64 state 202 clear64(p); 203 return; 204 } 205 206 // Initialize AArch32 state... 207 clear32(p, sctlr_rst); 208} 209 210void 211ISA::clear32(const ArmISAParams *p, const SCTLR &sctlr_rst) 212{ 213 CPSR cpsr = 0; 214 cpsr.mode = MODE_USER; 215 216 if (FullSystem) { 217 miscRegs[MISCREG_MVBAR] = system->resetAddr(); 218 } 219 220 miscRegs[MISCREG_CPSR] = cpsr; 221 updateRegMap(cpsr); 222 223 SCTLR sctlr = 0; 224 sctlr.te = (bool) sctlr_rst.te; 225 sctlr.nmfi = (bool) sctlr_rst.nmfi; 226 sctlr.v = (bool) sctlr_rst.v; 227 sctlr.u = 1; 228 sctlr.xp = 1; 229 sctlr.rao2 = 1; 230 sctlr.rao3 = 1; 231 sctlr.rao4 = 0xf; // SCTLR[6:3] 232 sctlr.uci = 1; 233 sctlr.dze = 1; 234 miscRegs[MISCREG_SCTLR_NS] = sctlr; 235 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 236 miscRegs[MISCREG_HCPTR] = 0; 237 238 miscRegs[MISCREG_CPACR] = 0; 239 240 miscRegs[MISCREG_FPSID] = p->fpsid; 241 242 if (haveLPAE) { 243 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 244 ttbcr.eae = 0; 245 miscRegs[MISCREG_TTBCR_NS] = ttbcr; 246 // Enforce consistency with system-level settings 247 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 248 } 249 250 if (haveSecurity) { 251 miscRegs[MISCREG_SCTLR_S] = sctlr; 252 miscRegs[MISCREG_SCR] = 0; 253 miscRegs[MISCREG_VBAR_S] = 0; 254 } else { 255 // we're always non-secure 256 miscRegs[MISCREG_SCR] = 1; 257 } 258 259 //XXX We need to initialize the rest of the state. 260} 261 262void 263ISA::clear64(const ArmISAParams *p) 264{ 265 CPSR cpsr = 0; 266 Addr rvbar = system->resetAddr(); 267 switch (system->highestEL()) { 268 // Set initial EL to highest implemented EL using associated stack 269 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 270 // value 271 case EL3: 272 cpsr.mode = MODE_EL3H; 273 miscRegs[MISCREG_RVBAR_EL3] = rvbar; 274 break; 275 case EL2: 276 cpsr.mode = MODE_EL2H; 277 miscRegs[MISCREG_RVBAR_EL2] = rvbar; 278 break; 279 case EL1: 280 cpsr.mode = MODE_EL1H; 281 miscRegs[MISCREG_RVBAR_EL1] = rvbar; 282 break; 283 default: 284 panic("Invalid highest implemented exception level"); 285 break; 286 } 287 288 // Initialize rest of CPSR 289 cpsr.daif = 0xf; // Mask all interrupts 290 cpsr.ss = 0; 291 cpsr.il = 0; 292 miscRegs[MISCREG_CPSR] = cpsr; 293 updateRegMap(cpsr); 294 295 // Initialize other control registers 296 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 297 if (haveSecurity) { 298 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830; 299 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 300 } else if (haveVirtualization) { 301 // also MISCREG_SCTLR_EL2 (by mapping) 302 miscRegs[MISCREG_HSCTLR] = 0x30c50830; 303 } else { 304 // also MISCREG_SCTLR_EL1 (by mapping) 305 miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init 306 // Always non-secure 307 miscRegs[MISCREG_SCR_EL3] = 1; 308 } 309} 310 311void 312ISA::initID32(const ArmISAParams *p) 313{ 314 // Initialize configurable default values 315 miscRegs[MISCREG_MIDR] = p->midr; 316 miscRegs[MISCREG_MIDR_EL1] = p->midr; 317 miscRegs[MISCREG_VPIDR] = p->midr; 318 319 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 320 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 321 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 322 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 323 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 324 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 325 326 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 327 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 328 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 329 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 330 331 miscRegs[MISCREG_ID_ISAR5] = insertBits( 332 miscRegs[MISCREG_ID_ISAR5], 19, 4, 333 haveCrypto ? 0x1112 : 0x0); 334} 335 336void 337ISA::initID64(const ArmISAParams *p) 338{ 339 // Initialize configurable id registers 340 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 341 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 342 miscRegs[MISCREG_ID_AA64DFR0_EL1] = 343 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 344 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 345 346 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 347 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 348 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 349 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 350 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 351 miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p->id_aa64mmfr2_el1; 352 353 miscRegs[MISCREG_ID_DFR0_EL1] = 354 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 355 356 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 357 358 // SVE 359 miscRegs[MISCREG_ID_AA64ZFR0_EL1] = 0; // SVEver 0 360 if (haveSecurity) { 361 miscRegs[MISCREG_ZCR_EL3] = sveVL - 1; 362 } else if (haveVirtualization) { 363 miscRegs[MISCREG_ZCR_EL2] = sveVL - 1; 364 } else { 365 miscRegs[MISCREG_ZCR_EL1] = sveVL - 1; 366 } 367 368 // Enforce consistency with system-level settings... 369 370 // EL3 371 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 372 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 373 haveSecurity ? 0x2 : 0x0); 374 // EL2 375 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 376 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 377 haveVirtualization ? 0x2 : 0x0); 378 // SVE 379 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 380 miscRegs[MISCREG_ID_AA64PFR0_EL1], 35, 32, 381 haveSVE ? 0x1 : 0x0); 382 // Large ASID support 383 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 384 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 385 haveLargeAsid64 ? 0x2 : 0x0); 386 // Physical address size 387 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 388 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 389 encodePhysAddrRange64(physAddrRange)); 390 // Crypto 391 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits( 392 miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4, 393 haveCrypto ? 0x1112 : 0x0); 394} 395 396void 397ISA::startup(ThreadContext *tc) 398{ 399 pmu->setThreadContext(tc); 400 401 if (system) { 402 Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC()); 403 if (gicv3) { 404 haveGICv3CPUInterface = true; 405 gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId())); 406 gicv3CpuInterface->setISA(this); 407 gicv3CpuInterface->setThreadContext(tc); 408 } 409 } 410 411 afterStartup = true; 412} 413 414 415RegVal 416ISA::readMiscRegNoEffect(int misc_reg) const 417{ 418 assert(misc_reg < NumMiscRegs); 419 420 const auto ® = lookUpMiscReg[misc_reg]; // bit masks 421 const auto &map = getMiscIndices(misc_reg); 422 int lower = map.first, upper = map.second; 423 // NB!: apply architectural masks according to desired register, 424 // despite possibly getting value from different (mapped) register. 425 auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32)) 426 |(miscRegs[upper] << 32)); 427 if (val & reg.res0()) { 428 DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n", 429 miscRegName[misc_reg], val & reg.res0()); 430 } 431 if ((val & reg.res1()) != reg.res1()) { 432 DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n", 433 miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1()); 434 } 435 return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao 436} 437 438 439RegVal 440ISA::readMiscReg(int misc_reg, ThreadContext *tc) 441{ 442 CPSR cpsr = 0; 443 PCState pc = 0; 444 SCR scr = 0; 445 446 if (misc_reg == MISCREG_CPSR) { 447 cpsr = miscRegs[misc_reg]; 448 pc = tc->pcState(); 449 cpsr.j = pc.jazelle() ? 1 : 0; 450 cpsr.t = pc.thumb() ? 1 : 0; 451 return cpsr; 452 } 453 454#ifndef NDEBUG 455 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 456 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 457 warn("Unimplemented system register %s read.\n", 458 miscRegName[misc_reg]); 459 else 460 panic("Unimplemented system register %s read.\n", 461 miscRegName[misc_reg]); 462 } 463#endif 464 465 switch (unflattenMiscReg(misc_reg)) { 466 case MISCREG_HCR: 467 { 468 if (!haveVirtualization) 469 return 0; 470 else 471 return readMiscRegNoEffect(MISCREG_HCR); 472 } 473 case MISCREG_CPACR: 474 { 475 const uint32_t ones = (uint32_t)(-1); 476 CPACR cpacrMask = 0; 477 // Only cp10, cp11, and ase are implemented, nothing else should 478 // be readable? (straight copy from the write code) 479 cpacrMask.cp10 = ones; 480 cpacrMask.cp11 = ones; 481 cpacrMask.asedis = ones; 482 483 // Security Extensions may limit the readability of CPACR 484 if (haveSecurity) { 485 scr = readMiscRegNoEffect(MISCREG_SCR); 486 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 487 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 488 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 489 // NB: Skipping the full loop, here 490 if (!nsacr.cp10) cpacrMask.cp10 = 0; 491 if (!nsacr.cp11) cpacrMask.cp11 = 0; 492 } 493 } 494 RegVal val = readMiscRegNoEffect(MISCREG_CPACR); 495 val &= cpacrMask; 496 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 497 miscRegName[misc_reg], val); 498 return val; 499 } 500 case MISCREG_MPIDR: 501 case MISCREG_MPIDR_EL1: 502 return readMPIDR(system, tc); 503 case MISCREG_VMPIDR: 504 case MISCREG_VMPIDR_EL2: 505 // top bit defined as RES1 506 return readMiscRegNoEffect(misc_reg) | 0x80000000; 507 case MISCREG_ID_AFR0: // not implemented, so alias MIDR 508 case MISCREG_REVIDR: // not implemented, so alias MIDR 509 case MISCREG_MIDR: 510 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 511 scr = readMiscRegNoEffect(MISCREG_SCR); 512 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 513 return readMiscRegNoEffect(misc_reg); 514 } else { 515 return readMiscRegNoEffect(MISCREG_VPIDR); 516 } 517 break; 518 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 519 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 520 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 521 case MISCREG_AIDR: // AUX ID set to 0 522 case MISCREG_TCMTR: // No TCM's 523 return 0; 524 525 case MISCREG_CLIDR: 526 warn_once("The clidr register always reports 0 caches.\n"); 527 warn_once("clidr LoUIS field of 0b001 to match current " 528 "ARM implementations.\n"); 529 return 0x00200000; 530 case MISCREG_CCSIDR: 531 warn_once("The ccsidr register isn't implemented and " 532 "always reads as 0.\n"); 533 break; 534 case MISCREG_CTR: // AArch32, ARMv7, top bit set 535 case MISCREG_CTR_EL0: // AArch64 536 { 537 //all caches have the same line size in gem5 538 //4 byte words in ARM 539 unsigned lineSizeWords = 540 tc->getSystemPtr()->cacheLineSize() / 4; 541 unsigned log2LineSizeWords = 0; 542 543 while (lineSizeWords >>= 1) { 544 ++log2LineSizeWords; 545 } 546 547 CTR ctr = 0; 548 //log2 of minimun i-cache line size (words) 549 ctr.iCacheLineSize = log2LineSizeWords; 550 //b11 - gem5 uses pipt 551 ctr.l1IndexPolicy = 0x3; 552 //log2 of minimum d-cache line size (words) 553 ctr.dCacheLineSize = log2LineSizeWords; 554 //log2 of max reservation size (words) 555 ctr.erg = log2LineSizeWords; 556 //log2 of max writeback size (words) 557 ctr.cwg = log2LineSizeWords; 558 //b100 - gem5 format is ARMv7 559 ctr.format = 0x4; 560 561 return ctr; 562 } 563 case MISCREG_ACTLR: 564 warn("Not doing anything for miscreg ACTLR\n"); 565 break; 566 567 case MISCREG_PMXEVTYPER_PMCCFILTR: 568 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 569 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 570 case MISCREG_PMCR ... MISCREG_PMOVSSET: 571 return pmu->readMiscReg(misc_reg); 572 573 case MISCREG_CPSR_Q: 574 panic("shouldn't be reading this register seperately\n"); 575 case MISCREG_FPSCR_QC: 576 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 577 case MISCREG_FPSCR_EXC: 578 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 579 case MISCREG_FPSR: 580 { 581 const uint32_t ones = (uint32_t)(-1); 582 FPSCR fpscrMask = 0; 583 fpscrMask.ioc = ones; 584 fpscrMask.dzc = ones; 585 fpscrMask.ofc = ones; 586 fpscrMask.ufc = ones; 587 fpscrMask.ixc = ones; 588 fpscrMask.idc = ones; 589 fpscrMask.qc = ones; 590 fpscrMask.v = ones; 591 fpscrMask.c = ones; 592 fpscrMask.z = ones; 593 fpscrMask.n = ones; 594 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 595 } 596 case MISCREG_FPCR: 597 { 598 const uint32_t ones = (uint32_t)(-1); 599 FPSCR fpscrMask = 0; 600 fpscrMask.len = ones; 601 fpscrMask.fz16 = ones; 602 fpscrMask.stride = ones; 603 fpscrMask.rMode = ones; 604 fpscrMask.fz = ones; 605 fpscrMask.dn = ones; 606 fpscrMask.ahp = ones; 607 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 608 } 609 case MISCREG_NZCV: 610 { 611 CPSR cpsr = 0; 612 cpsr.nz = tc->readCCReg(CCREG_NZ); 613 cpsr.c = tc->readCCReg(CCREG_C); 614 cpsr.v = tc->readCCReg(CCREG_V); 615 return cpsr; 616 } 617 case MISCREG_DAIF: 618 { 619 CPSR cpsr = 0; 620 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 621 return cpsr; 622 } 623 case MISCREG_SP_EL0: 624 { 625 return tc->readIntReg(INTREG_SP0); 626 } 627 case MISCREG_SP_EL1: 628 { 629 return tc->readIntReg(INTREG_SP1); 630 } 631 case MISCREG_SP_EL2: 632 { 633 return tc->readIntReg(INTREG_SP2); 634 } 635 case MISCREG_SPSEL: 636 { 637 return miscRegs[MISCREG_CPSR] & 0x1; 638 } 639 case MISCREG_CURRENTEL: 640 { 641 return miscRegs[MISCREG_CPSR] & 0xc; 642 } 643 case MISCREG_L2CTLR: 644 { 645 // mostly unimplemented, just set NumCPUs field from sim and return 646 L2CTLR l2ctlr = 0; 647 // b00:1CPU to b11:4CPUs 648 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 649 return l2ctlr; 650 } 651 case MISCREG_DBGDIDR: 652 /* For now just implement the version number. 653 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 654 */ 655 return 0x5 << 16; 656 case MISCREG_DBGDSCRint: 657 return 0; 658 case MISCREG_ISR: 659 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 660 readMiscRegNoEffect(MISCREG_HCR), 661 readMiscRegNoEffect(MISCREG_CPSR), 662 readMiscRegNoEffect(MISCREG_SCR)); 663 case MISCREG_ISR_EL1: 664 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 665 readMiscRegNoEffect(MISCREG_HCR_EL2), 666 readMiscRegNoEffect(MISCREG_CPSR), 667 readMiscRegNoEffect(MISCREG_SCR_EL3)); 668 case MISCREG_DCZID_EL0: 669 return 0x04; // DC ZVA clear 64-byte chunks 670 case MISCREG_HCPTR: 671 { 672 RegVal val = readMiscRegNoEffect(misc_reg); 673 // The trap bit associated with CP14 is defined as RAZ 674 val &= ~(1 << 14); 675 // If a CP bit in NSACR is 0 then the corresponding bit in 676 // HCPTR is RAO/WI 677 bool secure_lookup = haveSecurity && 678 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 679 readMiscRegNoEffect(MISCREG_CPSR)); 680 if (!secure_lookup) { 681 RegVal mask = readMiscRegNoEffect(MISCREG_NSACR); 682 val |= (mask ^ 0x7FFF) & 0xBFFF; 683 } 684 // Set the bits for unimplemented coprocessors to RAO/WI 685 val |= 0x33FF; 686 return (val); 687 } 688 case MISCREG_HDFAR: // alias for secure DFAR 689 return readMiscRegNoEffect(MISCREG_DFAR_S); 690 case MISCREG_HIFAR: // alias for secure IFAR 691 return readMiscRegNoEffect(MISCREG_IFAR_S); 692 693 case MISCREG_ID_PFR0: 694 // !ThumbEE | !Jazelle | Thumb | ARM 695 return 0x00000031; 696 case MISCREG_ID_PFR1: 697 { // Timer | Virti | !M Profile | TrustZone | ARMv4 698 bool haveTimer = (system->getGenericTimer() != NULL); 699 return 0x00000001 700 | (haveSecurity ? 0x00000010 : 0x0) 701 | (haveVirtualization ? 0x00001000 : 0x0) 702 | (haveTimer ? 0x00010000 : 0x0); 703 } 704 case MISCREG_ID_AA64PFR0_EL1: 705 return 0x0000000000000002 | // AArch{64,32} supported at EL0 706 0x0000000000000020 | // EL1 707 (haveVirtualization ? 0x0000000000000200 : 0) | // EL2 708 (haveSecurity ? 0x0000000000002000 : 0) | // EL3 709 (haveSVE ? 0x0000000100000000 : 0) | // SVE 710 (haveGICv3CPUInterface ? 0x0000000001000000 : 0); 711 case MISCREG_ID_AA64PFR1_EL1: 712 return 0; // bits [63:0] RES0 (reserved for future use) 713 714 // Generic Timer registers 715 case MISCREG_CNTHV_CTL_EL2: 716 case MISCREG_CNTHV_CVAL_EL2: 717 case MISCREG_CNTHV_TVAL_EL2: 718 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 719 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 720 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 721 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 722 return getGenericTimer(tc).readMiscReg(misc_reg); 723 724 case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3: 725 case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2: 726 return getGICv3CPUInterface(tc).readMiscReg(misc_reg); 727 728 default: 729 break; 730 731 } 732 return readMiscRegNoEffect(misc_reg); 733} 734 735void 736ISA::setMiscRegNoEffect(int misc_reg, RegVal val) 737{ 738 assert(misc_reg < NumMiscRegs); 739 740 const auto ® = lookUpMiscReg[misc_reg]; // bit masks 741 const auto &map = getMiscIndices(misc_reg); 742 int lower = map.first, upper = map.second; 743 744 auto v = (val & ~reg.wi()) | reg.rao(); 745 if (upper > 0) { 746 miscRegs[lower] = bits(v, 31, 0); 747 miscRegs[upper] = bits(v, 63, 32); 748 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 749 misc_reg, lower, upper, v); 750 } else { 751 miscRegs[lower] = v; 752 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 753 misc_reg, lower, v); 754 } 755} 756 757void 758ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) 759{ 760 761 RegVal newVal = val; 762 bool secure_lookup; 763 SCR scr; 764 765 if (misc_reg == MISCREG_CPSR) { 766 updateRegMap(val); 767 768 769 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 770 int old_mode = old_cpsr.mode; 771 CPSR cpsr = val; 772 if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) { 773 getITBPtr(tc)->invalidateMiscReg(); 774 getDTBPtr(tc)->invalidateMiscReg(); 775 } 776 777 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 778 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 779 PCState pc = tc->pcState(); 780 pc.nextThumb(cpsr.t); 781 pc.nextJazelle(cpsr.j); 782 pc.illegalExec(cpsr.il == 1); 783 784 tc->getDecoderPtr()->setSveLen((getCurSveVecLenInBits(tc) >> 7) - 1); 785 786 // Follow slightly different semantics if a CheckerCPU object 787 // is connected 788 CheckerCPU *checker = tc->getCheckerCpuPtr(); 789 if (checker) { 790 tc->pcStateNoRecord(pc); 791 } else { 792 tc->pcState(pc); 793 } 794 } else { 795#ifndef NDEBUG 796 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 797 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 798 warn("Unimplemented system register %s write with %#x.\n", 799 miscRegName[misc_reg], val); 800 else 801 panic("Unimplemented system register %s write with %#x.\n", 802 miscRegName[misc_reg], val); 803 } 804#endif 805 switch (unflattenMiscReg(misc_reg)) { 806 case MISCREG_CPACR: 807 { 808 809 const uint32_t ones = (uint32_t)(-1); 810 CPACR cpacrMask = 0; 811 // Only cp10, cp11, and ase are implemented, nothing else should 812 // be writable 813 cpacrMask.cp10 = ones; 814 cpacrMask.cp11 = ones; 815 cpacrMask.asedis = ones; 816 817 // Security Extensions may limit the writability of CPACR 818 if (haveSecurity) { 819 scr = readMiscRegNoEffect(MISCREG_SCR); 820 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 821 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 822 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 823 // NB: Skipping the full loop, here 824 if (!nsacr.cp10) cpacrMask.cp10 = 0; 825 if (!nsacr.cp11) cpacrMask.cp11 = 0; 826 } 827 } 828 829 RegVal old_val = readMiscRegNoEffect(MISCREG_CPACR); 830 newVal &= cpacrMask; 831 newVal |= old_val & ~cpacrMask; 832 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 833 miscRegName[misc_reg], newVal); 834 } 835 break; 836 case MISCREG_CPACR_EL1: 837 { 838 const uint32_t ones = (uint32_t)(-1); 839 CPACR cpacrMask = 0; 840 cpacrMask.tta = ones; 841 cpacrMask.fpen = ones; 842 if (haveSVE) { 843 cpacrMask.zen = ones; 844 } 845 newVal &= cpacrMask; 846 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 847 miscRegName[misc_reg], newVal); 848 } 849 break; 850 case MISCREG_CPTR_EL2: 851 { 852 const uint32_t ones = (uint32_t)(-1); 853 CPTR cptrMask = 0; 854 cptrMask.tcpac = ones; 855 cptrMask.tta = ones; 856 cptrMask.tfp = ones; 857 if (haveSVE) { 858 cptrMask.tz = ones; 859 } 860 newVal &= cptrMask; 861 cptrMask = 0; 862 cptrMask.res1_13_12_el2 = ones; 863 cptrMask.res1_7_0_el2 = ones; 864 if (!haveSVE) { 865 cptrMask.res1_8_el2 = ones; 866 } 867 cptrMask.res1_9_el2 = ones; 868 newVal |= cptrMask; 869 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 870 miscRegName[misc_reg], newVal); 871 } 872 break; 873 case MISCREG_CPTR_EL3: 874 { 875 const uint32_t ones = (uint32_t)(-1); 876 CPTR cptrMask = 0; 877 cptrMask.tcpac = ones; 878 cptrMask.tta = ones; 879 cptrMask.tfp = ones; 880 if (haveSVE) { 881 cptrMask.ez = ones; 882 } 883 newVal &= cptrMask; 884 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 885 miscRegName[misc_reg], newVal); 886 } 887 break; 888 case MISCREG_CSSELR: 889 warn_once("The csselr register isn't implemented.\n"); 890 return; 891 892 case MISCREG_DC_ZVA_Xt: 893 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 894 return; 895 896 case MISCREG_FPSCR: 897 { 898 const uint32_t ones = (uint32_t)(-1); 899 FPSCR fpscrMask = 0; 900 fpscrMask.ioc = ones; 901 fpscrMask.dzc = ones; 902 fpscrMask.ofc = ones; 903 fpscrMask.ufc = ones; 904 fpscrMask.ixc = ones; 905 fpscrMask.idc = ones; 906 fpscrMask.ioe = ones; 907 fpscrMask.dze = ones; 908 fpscrMask.ofe = ones; 909 fpscrMask.ufe = ones; 910 fpscrMask.ixe = ones; 911 fpscrMask.ide = ones; 912 fpscrMask.len = ones; 913 fpscrMask.fz16 = ones; 914 fpscrMask.stride = ones; 915 fpscrMask.rMode = ones; 916 fpscrMask.fz = ones; 917 fpscrMask.dn = ones; 918 fpscrMask.ahp = ones; 919 fpscrMask.qc = ones; 920 fpscrMask.v = ones; 921 fpscrMask.c = ones; 922 fpscrMask.z = ones; 923 fpscrMask.n = ones; 924 newVal = (newVal & (uint32_t)fpscrMask) | 925 (readMiscRegNoEffect(MISCREG_FPSCR) & 926 ~(uint32_t)fpscrMask); 927 tc->getDecoderPtr()->setContext(newVal); 928 } 929 break; 930 case MISCREG_FPSR: 931 { 932 const uint32_t ones = (uint32_t)(-1); 933 FPSCR fpscrMask = 0; 934 fpscrMask.ioc = ones; 935 fpscrMask.dzc = ones; 936 fpscrMask.ofc = ones; 937 fpscrMask.ufc = ones; 938 fpscrMask.ixc = ones; 939 fpscrMask.idc = ones; 940 fpscrMask.qc = ones; 941 fpscrMask.v = ones; 942 fpscrMask.c = ones; 943 fpscrMask.z = ones; 944 fpscrMask.n = ones; 945 newVal = (newVal & (uint32_t)fpscrMask) | 946 (readMiscRegNoEffect(MISCREG_FPSCR) & 947 ~(uint32_t)fpscrMask); 948 misc_reg = MISCREG_FPSCR; 949 } 950 break; 951 case MISCREG_FPCR: 952 { 953 const uint32_t ones = (uint32_t)(-1); 954 FPSCR fpscrMask = 0; 955 fpscrMask.len = ones; 956 fpscrMask.fz16 = ones; 957 fpscrMask.stride = ones; 958 fpscrMask.rMode = ones; 959 fpscrMask.fz = ones; 960 fpscrMask.dn = ones; 961 fpscrMask.ahp = ones; 962 newVal = (newVal & (uint32_t)fpscrMask) | 963 (readMiscRegNoEffect(MISCREG_FPSCR) & 964 ~(uint32_t)fpscrMask); 965 misc_reg = MISCREG_FPSCR; 966 } 967 break; 968 case MISCREG_CPSR_Q: 969 { 970 assert(!(newVal & ~CpsrMaskQ)); 971 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 972 misc_reg = MISCREG_CPSR; 973 } 974 break; 975 case MISCREG_FPSCR_QC: 976 { 977 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 978 (newVal & FpscrQcMask); 979 misc_reg = MISCREG_FPSCR; 980 } 981 break; 982 case MISCREG_FPSCR_EXC: 983 { 984 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 985 (newVal & FpscrExcMask); 986 misc_reg = MISCREG_FPSCR; 987 } 988 break; 989 case MISCREG_FPEXC: 990 { 991 // vfpv3 architecture, section B.6.1 of DDI04068 992 // bit 29 - valid only if fpexc[31] is 0 993 const uint32_t fpexcMask = 0x60000000; 994 newVal = (newVal & fpexcMask) | 995 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 996 } 997 break; 998 case MISCREG_HCR: 999 { 1000 if (!haveVirtualization) 1001 return; 1002 } 1003 break; 1004 case MISCREG_IFSR: 1005 { 1006 // ARM ARM (ARM DDI 0406C.b) B4.1.96 1007 const uint32_t ifsrMask = 1008 mask(31, 13) | mask(11, 11) | mask(8, 6); 1009 newVal = newVal & ~ifsrMask; 1010 } 1011 break; 1012 case MISCREG_DFSR: 1013 { 1014 // ARM ARM (ARM DDI 0406C.b) B4.1.52 1015 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 1016 newVal = newVal & ~dfsrMask; 1017 } 1018 break; 1019 case MISCREG_AMAIR0: 1020 case MISCREG_AMAIR1: 1021 { 1022 // ARM ARM (ARM DDI 0406C.b) B4.1.5 1023 // Valid only with LPAE 1024 if (!haveLPAE) 1025 return; 1026 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 1027 } 1028 break; 1029 case MISCREG_SCR: 1030 getITBPtr(tc)->invalidateMiscReg(); 1031 getDTBPtr(tc)->invalidateMiscReg(); 1032 break; 1033 case MISCREG_SCTLR: 1034 { 1035 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 1036 scr = readMiscRegNoEffect(MISCREG_SCR); 1037 1038 MiscRegIndex sctlr_idx; 1039 if (haveSecurity && !highestELIs64 && !scr.ns) { 1040 sctlr_idx = MISCREG_SCTLR_S; 1041 } else { 1042 sctlr_idx = MISCREG_SCTLR_NS; 1043 } 1044 1045 SCTLR sctlr = miscRegs[sctlr_idx]; 1046 SCTLR new_sctlr = newVal; 1047 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 1048 miscRegs[sctlr_idx] = (RegVal)new_sctlr; 1049 getITBPtr(tc)->invalidateMiscReg(); 1050 getDTBPtr(tc)->invalidateMiscReg(); 1051 } 1052 case MISCREG_MIDR: 1053 case MISCREG_ID_PFR0: 1054 case MISCREG_ID_PFR1: 1055 case MISCREG_ID_DFR0: 1056 case MISCREG_ID_MMFR0: 1057 case MISCREG_ID_MMFR1: 1058 case MISCREG_ID_MMFR2: 1059 case MISCREG_ID_MMFR3: 1060 case MISCREG_ID_ISAR0: 1061 case MISCREG_ID_ISAR1: 1062 case MISCREG_ID_ISAR2: 1063 case MISCREG_ID_ISAR3: 1064 case MISCREG_ID_ISAR4: 1065 case MISCREG_ID_ISAR5: 1066 1067 case MISCREG_MPIDR: 1068 case MISCREG_FPSID: 1069 case MISCREG_TLBTR: 1070 case MISCREG_MVFR0: 1071 case MISCREG_MVFR1: 1072 1073 case MISCREG_ID_AA64AFR0_EL1: 1074 case MISCREG_ID_AA64AFR1_EL1: 1075 case MISCREG_ID_AA64DFR0_EL1: 1076 case MISCREG_ID_AA64DFR1_EL1: 1077 case MISCREG_ID_AA64ISAR0_EL1: 1078 case MISCREG_ID_AA64ISAR1_EL1: 1079 case MISCREG_ID_AA64MMFR0_EL1: 1080 case MISCREG_ID_AA64MMFR1_EL1: 1081 case MISCREG_ID_AA64MMFR2_EL1: 1082 case MISCREG_ID_AA64PFR0_EL1: 1083 case MISCREG_ID_AA64PFR1_EL1: 1084 // ID registers are constants. 1085 return; 1086 1087 // TLB Invalidate All 1088 case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 1089 { 1090 assert32(tc); 1091 scr = readMiscReg(MISCREG_SCR, tc); 1092 1093 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1094 tlbiOp(tc); 1095 return; 1096 } 1097 // TLB Invalidate All, Inner Shareable 1098 case MISCREG_TLBIALLIS: 1099 { 1100 assert32(tc); 1101 scr = readMiscReg(MISCREG_SCR, tc); 1102 1103 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1104 tlbiOp.broadcast(tc); 1105 return; 1106 } 1107 // Instruction TLB Invalidate All 1108 case MISCREG_ITLBIALL: 1109 { 1110 assert32(tc); 1111 scr = readMiscReg(MISCREG_SCR, tc); 1112 1113 ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1114 tlbiOp(tc); 1115 return; 1116 } 1117 // Data TLB Invalidate All 1118 case MISCREG_DTLBIALL: 1119 { 1120 assert32(tc); 1121 scr = readMiscReg(MISCREG_SCR, tc); 1122 1123 DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1124 tlbiOp(tc); 1125 return; 1126 } 1127 // TLB Invalidate by VA 1128 // mcr tlbimval(is) is invalidating all matching entries 1129 // regardless of the level of lookup, since in gem5 we cache 1130 // in the tlb the last level of lookup only. 1131 case MISCREG_TLBIMVA: 1132 case MISCREG_TLBIMVAL: 1133 { 1134 assert32(tc); 1135 scr = readMiscReg(MISCREG_SCR, tc); 1136 1137 TLBIMVA tlbiOp(EL1, 1138 haveSecurity && !scr.ns, 1139 mbits(newVal, 31, 12), 1140 bits(newVal, 7,0)); 1141 1142 tlbiOp(tc); 1143 return; 1144 } 1145 // TLB Invalidate by VA, Inner Shareable 1146 case MISCREG_TLBIMVAIS: 1147 case MISCREG_TLBIMVALIS: 1148 { 1149 assert32(tc); 1150 scr = readMiscReg(MISCREG_SCR, tc); 1151 1152 TLBIMVA tlbiOp(EL1, 1153 haveSecurity && !scr.ns, 1154 mbits(newVal, 31, 12), 1155 bits(newVal, 7,0)); 1156 1157 tlbiOp.broadcast(tc); 1158 return; 1159 } 1160 // TLB Invalidate by ASID match 1161 case MISCREG_TLBIASID: 1162 { 1163 assert32(tc); 1164 scr = readMiscReg(MISCREG_SCR, tc); 1165 1166 TLBIASID tlbiOp(EL1, 1167 haveSecurity && !scr.ns, 1168 bits(newVal, 7,0)); 1169 1170 tlbiOp(tc); 1171 return; 1172 } 1173 // TLB Invalidate by ASID match, Inner Shareable 1174 case MISCREG_TLBIASIDIS: 1175 { 1176 assert32(tc); 1177 scr = readMiscReg(MISCREG_SCR, tc); 1178 1179 TLBIASID tlbiOp(EL1, 1180 haveSecurity && !scr.ns, 1181 bits(newVal, 7,0)); 1182 1183 tlbiOp.broadcast(tc); 1184 return; 1185 } 1186 // mcr tlbimvaal(is) is invalidating all matching entries 1187 // regardless of the level of lookup, since in gem5 we cache 1188 // in the tlb the last level of lookup only. 1189 // TLB Invalidate by VA, All ASID 1190 case MISCREG_TLBIMVAA: 1191 case MISCREG_TLBIMVAAL: 1192 { 1193 assert32(tc); 1194 scr = readMiscReg(MISCREG_SCR, tc); 1195 1196 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1197 mbits(newVal, 31,12)); 1198 1199 tlbiOp(tc); 1200 return; 1201 } 1202 // TLB Invalidate by VA, All ASID, Inner Shareable 1203 case MISCREG_TLBIMVAAIS: 1204 case MISCREG_TLBIMVAALIS: 1205 { 1206 assert32(tc); 1207 scr = readMiscReg(MISCREG_SCR, tc); 1208 1209 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1210 mbits(newVal, 31,12)); 1211 1212 tlbiOp.broadcast(tc); 1213 return; 1214 } 1215 // mcr tlbimvalh(is) is invalidating all matching entries 1216 // regardless of the level of lookup, since in gem5 we cache 1217 // in the tlb the last level of lookup only. 1218 // TLB Invalidate by VA, Hyp mode 1219 case MISCREG_TLBIMVAH: 1220 case MISCREG_TLBIMVALH: 1221 { 1222 assert32(tc); 1223 scr = readMiscReg(MISCREG_SCR, tc); 1224 1225 TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns, 1226 mbits(newVal, 31,12)); 1227 1228 tlbiOp(tc); 1229 return; 1230 } 1231 // TLB Invalidate by VA, Hyp mode, Inner Shareable 1232 case MISCREG_TLBIMVAHIS: 1233 case MISCREG_TLBIMVALHIS: 1234 { 1235 assert32(tc); 1236 scr = readMiscReg(MISCREG_SCR, tc); 1237 1238 TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns, 1239 mbits(newVal, 31,12)); 1240 1241 tlbiOp.broadcast(tc); 1242 return; 1243 } 1244 // mcr tlbiipas2l(is) is invalidating all matching entries 1245 // regardless of the level of lookup, since in gem5 we cache 1246 // in the tlb the last level of lookup only. 1247 // TLB Invalidate by Intermediate Physical Address, Stage 2 1248 case MISCREG_TLBIIPAS2: 1249 case MISCREG_TLBIIPAS2L: 1250 { 1251 assert32(tc); 1252 scr = readMiscReg(MISCREG_SCR, tc); 1253 1254 TLBIIPA tlbiOp(EL1, 1255 haveSecurity && !scr.ns, 1256 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1257 1258 tlbiOp(tc); 1259 return; 1260 } 1261 // TLB Invalidate by Intermediate Physical Address, Stage 2, 1262 // Inner Shareable 1263 case MISCREG_TLBIIPAS2IS: 1264 case MISCREG_TLBIIPAS2LIS: 1265 { 1266 assert32(tc); 1267 scr = readMiscReg(MISCREG_SCR, tc); 1268 1269 TLBIIPA tlbiOp(EL1, 1270 haveSecurity && !scr.ns, 1271 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1272 1273 tlbiOp.broadcast(tc); 1274 return; 1275 } 1276 // Instruction TLB Invalidate by VA 1277 case MISCREG_ITLBIMVA: 1278 { 1279 assert32(tc); 1280 scr = readMiscReg(MISCREG_SCR, tc); 1281 1282 ITLBIMVA tlbiOp(EL1, 1283 haveSecurity && !scr.ns, 1284 mbits(newVal, 31, 12), 1285 bits(newVal, 7,0)); 1286 1287 tlbiOp(tc); 1288 return; 1289 } 1290 // Data TLB Invalidate by VA 1291 case MISCREG_DTLBIMVA: 1292 { 1293 assert32(tc); 1294 scr = readMiscReg(MISCREG_SCR, tc); 1295 1296 DTLBIMVA tlbiOp(EL1, 1297 haveSecurity && !scr.ns, 1298 mbits(newVal, 31, 12), 1299 bits(newVal, 7,0)); 1300 1301 tlbiOp(tc); 1302 return; 1303 } 1304 // Instruction TLB Invalidate by ASID match 1305 case MISCREG_ITLBIASID: 1306 { 1307 assert32(tc); 1308 scr = readMiscReg(MISCREG_SCR, tc); 1309 1310 ITLBIASID tlbiOp(EL1, 1311 haveSecurity && !scr.ns, 1312 bits(newVal, 7,0)); 1313 1314 tlbiOp(tc); 1315 return; 1316 } 1317 // Data TLB Invalidate by ASID match 1318 case MISCREG_DTLBIASID: 1319 { 1320 assert32(tc); 1321 scr = readMiscReg(MISCREG_SCR, tc); 1322 1323 DTLBIASID tlbiOp(EL1, 1324 haveSecurity && !scr.ns, 1325 bits(newVal, 7,0)); 1326 1327 tlbiOp(tc); 1328 return; 1329 } 1330 // TLB Invalidate All, Non-Secure Non-Hyp 1331 case MISCREG_TLBIALLNSNH: 1332 { 1333 assert32(tc); 1334 1335 TLBIALLN tlbiOp(EL1); 1336 tlbiOp(tc); 1337 return; 1338 } 1339 // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable 1340 case MISCREG_TLBIALLNSNHIS: 1341 { 1342 assert32(tc); 1343 1344 TLBIALLN tlbiOp(EL1); 1345 tlbiOp.broadcast(tc); 1346 return; 1347 } 1348 // TLB Invalidate All, Hyp mode 1349 case MISCREG_TLBIALLH: 1350 { 1351 assert32(tc); 1352 1353 TLBIALLN tlbiOp(EL2); 1354 tlbiOp(tc); 1355 return; 1356 } 1357 // TLB Invalidate All, Hyp mode, Inner Shareable 1358 case MISCREG_TLBIALLHIS: 1359 { 1360 assert32(tc); 1361 1362 TLBIALLN tlbiOp(EL2); 1363 tlbiOp.broadcast(tc); 1364 return; 1365 } 1366 // AArch64 TLB Invalidate All, EL3 1367 case MISCREG_TLBI_ALLE3: 1368 { 1369 assert64(tc); 1370 1371 TLBIALL tlbiOp(EL3, true); 1372 tlbiOp(tc); 1373 return; 1374 } 1375 // AArch64 TLB Invalidate All, EL3, Inner Shareable 1376 case MISCREG_TLBI_ALLE3IS: 1377 { 1378 assert64(tc); 1379 1380 TLBIALL tlbiOp(EL3, true); 1381 tlbiOp.broadcast(tc); 1382 return; 1383 } 1384 // AArch64 TLB Invalidate All, EL2, Inner Shareable 1385 case MISCREG_TLBI_ALLE2: 1386 case MISCREG_TLBI_ALLE2IS: 1387 { 1388 assert64(tc); 1389 scr = readMiscReg(MISCREG_SCR, tc); 1390 1391 TLBIALL tlbiOp(EL2, haveSecurity && !scr.ns); 1392 tlbiOp(tc); 1393 return; 1394 } 1395 // AArch64 TLB Invalidate All, EL1 1396 case MISCREG_TLBI_ALLE1: 1397 case MISCREG_TLBI_VMALLE1: 1398 case MISCREG_TLBI_VMALLS12E1: 1399 // @todo: handle VMID and stage 2 to enable Virtualization 1400 { 1401 assert64(tc); 1402 scr = readMiscReg(MISCREG_SCR, tc); 1403 1404 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1405 tlbiOp(tc); 1406 return; 1407 } 1408 // AArch64 TLB Invalidate All, EL1, Inner Shareable 1409 case MISCREG_TLBI_ALLE1IS: 1410 case MISCREG_TLBI_VMALLE1IS: 1411 case MISCREG_TLBI_VMALLS12E1IS: 1412 // @todo: handle VMID and stage 2 to enable Virtualization 1413 { 1414 assert64(tc); 1415 scr = readMiscReg(MISCREG_SCR, tc); 1416 1417 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1418 tlbiOp.broadcast(tc); 1419 return; 1420 } 1421 // VAEx(IS) and VALEx(IS) are the same because TLBs 1422 // only store entries 1423 // from the last level of translation table walks 1424 // @todo: handle VMID to enable Virtualization 1425 // AArch64 TLB Invalidate by VA, EL3 1426 case MISCREG_TLBI_VAE3_Xt: 1427 case MISCREG_TLBI_VALE3_Xt: 1428 { 1429 assert64(tc); 1430 1431 TLBIMVA tlbiOp(EL3, true, 1432 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1433 0xbeef); 1434 tlbiOp(tc); 1435 return; 1436 } 1437 // AArch64 TLB Invalidate by VA, EL3, Inner Shareable 1438 case MISCREG_TLBI_VAE3IS_Xt: 1439 case MISCREG_TLBI_VALE3IS_Xt: 1440 { 1441 assert64(tc); 1442 1443 TLBIMVA tlbiOp(EL3, true, 1444 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1445 0xbeef); 1446 1447 tlbiOp.broadcast(tc); 1448 return; 1449 } 1450 // AArch64 TLB Invalidate by VA, EL2 1451 case MISCREG_TLBI_VAE2_Xt: 1452 case MISCREG_TLBI_VALE2_Xt: 1453 { 1454 assert64(tc); 1455 scr = readMiscReg(MISCREG_SCR, tc); 1456 1457 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1458 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1459 0xbeef); 1460 tlbiOp(tc); 1461 return; 1462 } 1463 // AArch64 TLB Invalidate by VA, EL2, Inner Shareable 1464 case MISCREG_TLBI_VAE2IS_Xt: 1465 case MISCREG_TLBI_VALE2IS_Xt: 1466 { 1467 assert64(tc); 1468 scr = readMiscReg(MISCREG_SCR, tc); 1469 1470 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1471 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1472 0xbeef); 1473 1474 tlbiOp.broadcast(tc); 1475 return; 1476 } 1477 // AArch64 TLB Invalidate by VA, EL1 1478 case MISCREG_TLBI_VAE1_Xt: 1479 case MISCREG_TLBI_VALE1_Xt: 1480 { 1481 assert64(tc); 1482 scr = readMiscReg(MISCREG_SCR, tc); 1483 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1484 bits(newVal, 55, 48); 1485 1486 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1487 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1488 asid); 1489 1490 tlbiOp(tc); 1491 return; 1492 } 1493 // AArch64 TLB Invalidate by VA, EL1, Inner Shareable 1494 case MISCREG_TLBI_VAE1IS_Xt: 1495 case MISCREG_TLBI_VALE1IS_Xt: 1496 { 1497 assert64(tc); 1498 scr = readMiscReg(MISCREG_SCR, tc); 1499 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1500 bits(newVal, 55, 48); 1501 1502 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1503 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1504 asid); 1505 1506 tlbiOp.broadcast(tc); 1507 return; 1508 } 1509 // AArch64 TLB Invalidate by ASID, EL1 1510 // @todo: handle VMID to enable Virtualization 1511 case MISCREG_TLBI_ASIDE1_Xt: 1512 { 1513 assert64(tc); 1514 scr = readMiscReg(MISCREG_SCR, tc); 1515 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1516 bits(newVal, 55, 48); 1517 1518 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1519 tlbiOp(tc); 1520 return; 1521 } 1522 // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable 1523 case MISCREG_TLBI_ASIDE1IS_Xt: 1524 { 1525 assert64(tc); 1526 scr = readMiscReg(MISCREG_SCR, tc); 1527 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1528 bits(newVal, 55, 48); 1529 1530 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1531 tlbiOp.broadcast(tc); 1532 return; 1533 } 1534 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 1535 // entries from the last level of translation table walks 1536 // AArch64 TLB Invalidate by VA, All ASID, EL1 1537 case MISCREG_TLBI_VAAE1_Xt: 1538 case MISCREG_TLBI_VAALE1_Xt: 1539 { 1540 assert64(tc); 1541 scr = readMiscReg(MISCREG_SCR, tc); 1542 1543 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1544 static_cast<Addr>(bits(newVal, 43, 0)) << 12); 1545 1546 tlbiOp(tc); 1547 return; 1548 } 1549 // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable 1550 case MISCREG_TLBI_VAAE1IS_Xt: 1551 case MISCREG_TLBI_VAALE1IS_Xt: 1552 { 1553 assert64(tc); 1554 scr = readMiscReg(MISCREG_SCR, tc); 1555 1556 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1557 static_cast<Addr>(bits(newVal, 43, 0)) << 12); 1558 1559 tlbiOp.broadcast(tc); 1560 return; 1561 } 1562 // AArch64 TLB Invalidate by Intermediate Physical Address, 1563 // Stage 2, EL1 1564 case MISCREG_TLBI_IPAS2E1_Xt: 1565 case MISCREG_TLBI_IPAS2LE1_Xt: 1566 { 1567 assert64(tc); 1568 scr = readMiscReg(MISCREG_SCR, tc); 1569 1570 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1571 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1572 1573 tlbiOp(tc); 1574 return; 1575 } 1576 // AArch64 TLB Invalidate by Intermediate Physical Address, 1577 // Stage 2, EL1, Inner Shareable 1578 case MISCREG_TLBI_IPAS2E1IS_Xt: 1579 case MISCREG_TLBI_IPAS2LE1IS_Xt: 1580 { 1581 assert64(tc); 1582 scr = readMiscReg(MISCREG_SCR, tc); 1583 1584 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1585 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1586 1587 tlbiOp.broadcast(tc); 1588 return; 1589 } 1590 case MISCREG_ACTLR: 1591 warn("Not doing anything for write of miscreg ACTLR\n"); 1592 break; 1593 1594 case MISCREG_PMXEVTYPER_PMCCFILTR: 1595 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 1596 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 1597 case MISCREG_PMCR ... MISCREG_PMOVSSET: 1598 pmu->setMiscReg(misc_reg, newVal); 1599 break; 1600 1601 1602 case MISCREG_HSTR: // TJDBX, now redifined to be RES0 1603 { 1604 HSTR hstrMask = 0; 1605 hstrMask.tjdbx = 1; 1606 newVal &= ~((uint32_t) hstrMask); 1607 break; 1608 } 1609 case MISCREG_HCPTR: 1610 { 1611 // If a CP bit in NSACR is 0 then the corresponding bit in 1612 // HCPTR is RAO/WI. Same applies to NSASEDIS 1613 secure_lookup = haveSecurity && 1614 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 1615 readMiscRegNoEffect(MISCREG_CPSR)); 1616 if (!secure_lookup) { 1617 RegVal oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 1618 RegVal mask = 1619 (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 1620 newVal = (newVal & ~mask) | (oldValue & mask); 1621 } 1622 break; 1623 } 1624 case MISCREG_HDFAR: // alias for secure DFAR 1625 misc_reg = MISCREG_DFAR_S; 1626 break; 1627 case MISCREG_HIFAR: // alias for secure IFAR 1628 misc_reg = MISCREG_IFAR_S; 1629 break; 1630 case MISCREG_ATS1CPR: 1631 case MISCREG_ATS1CPW: 1632 case MISCREG_ATS1CUR: 1633 case MISCREG_ATS1CUW: 1634 case MISCREG_ATS12NSOPR: 1635 case MISCREG_ATS12NSOPW: 1636 case MISCREG_ATS12NSOUR: 1637 case MISCREG_ATS12NSOUW: 1638 case MISCREG_ATS1HR: 1639 case MISCREG_ATS1HW: 1640 { 1641 Request::Flags flags = 0; 1642 BaseTLB::Mode mode = BaseTLB::Read; 1643 TLB::ArmTranslationType tranType = TLB::NormalTran; 1644 Fault fault; 1645 switch(misc_reg) { 1646 case MISCREG_ATS1CPR: 1647 flags = TLB::MustBeOne; 1648 tranType = TLB::S1CTran; 1649 mode = BaseTLB::Read; 1650 break; 1651 case MISCREG_ATS1CPW: 1652 flags = TLB::MustBeOne; 1653 tranType = TLB::S1CTran; 1654 mode = BaseTLB::Write; 1655 break; 1656 case MISCREG_ATS1CUR: 1657 flags = TLB::MustBeOne | TLB::UserMode; 1658 tranType = TLB::S1CTran; 1659 mode = BaseTLB::Read; 1660 break; 1661 case MISCREG_ATS1CUW: 1662 flags = TLB::MustBeOne | TLB::UserMode; 1663 tranType = TLB::S1CTran; 1664 mode = BaseTLB::Write; 1665 break; 1666 case MISCREG_ATS12NSOPR: 1667 if (!haveSecurity) 1668 panic("Security Extensions required for ATS12NSOPR"); 1669 flags = TLB::MustBeOne; 1670 tranType = TLB::S1S2NsTran; 1671 mode = BaseTLB::Read; 1672 break; 1673 case MISCREG_ATS12NSOPW: 1674 if (!haveSecurity) 1675 panic("Security Extensions required for ATS12NSOPW"); 1676 flags = TLB::MustBeOne; 1677 tranType = TLB::S1S2NsTran; 1678 mode = BaseTLB::Write; 1679 break; 1680 case MISCREG_ATS12NSOUR: 1681 if (!haveSecurity) 1682 panic("Security Extensions required for ATS12NSOUR"); 1683 flags = TLB::MustBeOne | TLB::UserMode; 1684 tranType = TLB::S1S2NsTran; 1685 mode = BaseTLB::Read; 1686 break; 1687 case MISCREG_ATS12NSOUW: 1688 if (!haveSecurity) 1689 panic("Security Extensions required for ATS12NSOUW"); 1690 flags = TLB::MustBeOne | TLB::UserMode; 1691 tranType = TLB::S1S2NsTran; 1692 mode = BaseTLB::Write; 1693 break; 1694 case MISCREG_ATS1HR: // only really useful from secure mode. 1695 flags = TLB::MustBeOne; 1696 tranType = TLB::HypMode; 1697 mode = BaseTLB::Read; 1698 break; 1699 case MISCREG_ATS1HW: 1700 flags = TLB::MustBeOne; 1701 tranType = TLB::HypMode; 1702 mode = BaseTLB::Write; 1703 break; 1704 } 1705 // If we're in timing mode then doing the translation in 1706 // functional mode then we're slightly distorting performance 1707 // results obtained from simulations. The translation should be 1708 // done in the same mode the core is running in. NOTE: This 1709 // can't be an atomic translation because that causes problems 1710 // with unexpected atomic snoop requests. 1711 warn("Translating via %s in functional mode! Fix Me!\n", 1712 miscRegName[misc_reg]); 1713 1714 auto req = std::make_shared<Request>( 1715 0, val, 0, flags, Request::funcMasterId, 1716 tc->pcState().pc(), tc->contextId()); 1717 1718 fault = getDTBPtr(tc)->translateFunctional( 1719 req, tc, mode, tranType); 1720 1721 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1722 HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 1723 1724 RegVal newVal; 1725 if (fault == NoFault) { 1726 Addr paddr = req->getPaddr(); 1727 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 1728 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 1729 newVal = (paddr & mask(39, 12)) | 1730 (getDTBPtr(tc)->getAttr()); 1731 } else { 1732 newVal = (paddr & 0xfffff000) | 1733 (getDTBPtr(tc)->getAttr()); 1734 } 1735 DPRINTF(MiscRegs, 1736 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 1737 val, newVal); 1738 } else { 1739 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1740 armFault->update(tc); 1741 // Set fault bit and FSR 1742 FSR fsr = armFault->getFsr(tc); 1743 1744 newVal = ((fsr >> 9) & 1) << 11; 1745 if (newVal) { 1746 // LPAE - rearange fault status 1747 newVal |= ((fsr >> 0) & 0x3f) << 1; 1748 } else { 1749 // VMSA - rearange fault status 1750 newVal |= ((fsr >> 0) & 0xf) << 1; 1751 newVal |= ((fsr >> 10) & 0x1) << 5; 1752 newVal |= ((fsr >> 12) & 0x1) << 6; 1753 } 1754 newVal |= 0x1; // F bit 1755 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1756 newVal |= armFault->isStage2() ? 0x200 : 0; 1757 DPRINTF(MiscRegs, 1758 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 1759 val, fsr, newVal); 1760 } 1761 setMiscRegNoEffect(MISCREG_PAR, newVal); 1762 return; 1763 } 1764 case MISCREG_TTBCR: 1765 { 1766 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1767 const uint32_t ones = (uint32_t)(-1); 1768 TTBCR ttbcrMask = 0; 1769 TTBCR ttbcrNew = newVal; 1770 1771 // ARM DDI 0406C.b, ARMv7-32 1772 ttbcrMask.n = ones; // T0SZ 1773 if (haveSecurity) { 1774 ttbcrMask.pd0 = ones; 1775 ttbcrMask.pd1 = ones; 1776 } 1777 ttbcrMask.epd0 = ones; 1778 ttbcrMask.irgn0 = ones; 1779 ttbcrMask.orgn0 = ones; 1780 ttbcrMask.sh0 = ones; 1781 ttbcrMask.ps = ones; // T1SZ 1782 ttbcrMask.a1 = ones; 1783 ttbcrMask.epd1 = ones; 1784 ttbcrMask.irgn1 = ones; 1785 ttbcrMask.orgn1 = ones; 1786 ttbcrMask.sh1 = ones; 1787 if (haveLPAE) 1788 ttbcrMask.eae = ones; 1789 1790 if (haveLPAE && ttbcrNew.eae) { 1791 newVal = newVal & ttbcrMask; 1792 } else { 1793 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 1794 } 1795 // Invalidate TLB MiscReg 1796 getITBPtr(tc)->invalidateMiscReg(); 1797 getDTBPtr(tc)->invalidateMiscReg(); 1798 break; 1799 } 1800 case MISCREG_TTBR0: 1801 case MISCREG_TTBR1: 1802 { 1803 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1804 if (haveLPAE) { 1805 if (ttbcr.eae) { 1806 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 1807 // ARMv8 AArch32 bit 63-56 only 1808 uint64_t ttbrMask = mask(63,56) | mask(47,40); 1809 newVal = (newVal & (~ttbrMask)); 1810 } 1811 } 1812 // Invalidate TLB MiscReg 1813 getITBPtr(tc)->invalidateMiscReg(); 1814 getDTBPtr(tc)->invalidateMiscReg(); 1815 break; 1816 } 1817 case MISCREG_SCTLR_EL1: 1818 case MISCREG_CONTEXTIDR: 1819 case MISCREG_PRRR: 1820 case MISCREG_NMRR: 1821 case MISCREG_MAIR0: 1822 case MISCREG_MAIR1: 1823 case MISCREG_DACR: 1824 case MISCREG_VTTBR: 1825 case MISCREG_SCR_EL3: 1826 case MISCREG_HCR_EL2: 1827 case MISCREG_TCR_EL1: 1828 case MISCREG_TCR_EL2: 1829 case MISCREG_TCR_EL3: 1830 case MISCREG_SCTLR_EL2: 1831 case MISCREG_SCTLR_EL3: 1832 case MISCREG_HSCTLR: 1833 case MISCREG_TTBR0_EL1: 1834 case MISCREG_TTBR1_EL1: 1835 case MISCREG_TTBR0_EL2: 1836 case MISCREG_TTBR1_EL2: 1837 case MISCREG_TTBR0_EL3: 1838 getITBPtr(tc)->invalidateMiscReg(); 1839 getDTBPtr(tc)->invalidateMiscReg(); 1840 break; 1841 case MISCREG_NZCV: 1842 { 1843 CPSR cpsr = val; 1844 1845 tc->setCCReg(CCREG_NZ, cpsr.nz); 1846 tc->setCCReg(CCREG_C, cpsr.c); 1847 tc->setCCReg(CCREG_V, cpsr.v); 1848 } 1849 break; 1850 case MISCREG_DAIF: 1851 { 1852 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1853 cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 1854 newVal = cpsr; 1855 misc_reg = MISCREG_CPSR; 1856 } 1857 break; 1858 case MISCREG_SP_EL0: 1859 tc->setIntReg(INTREG_SP0, newVal); 1860 break; 1861 case MISCREG_SP_EL1: 1862 tc->setIntReg(INTREG_SP1, newVal); 1863 break; 1864 case MISCREG_SP_EL2: 1865 tc->setIntReg(INTREG_SP2, newVal); 1866 break; 1867 case MISCREG_SPSEL: 1868 { 1869 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1870 cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 1871 newVal = cpsr; 1872 misc_reg = MISCREG_CPSR; 1873 } 1874 break; 1875 case MISCREG_CURRENTEL: 1876 { 1877 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1878 cpsr.el = (uint8_t) ((CPSR) newVal).el; 1879 newVal = cpsr; 1880 misc_reg = MISCREG_CPSR; 1881 } 1882 break; 1883 case MISCREG_AT_S1E1R_Xt: 1884 case MISCREG_AT_S1E1W_Xt: 1885 case MISCREG_AT_S1E0R_Xt: 1886 case MISCREG_AT_S1E0W_Xt: 1887 case MISCREG_AT_S1E2R_Xt: 1888 case MISCREG_AT_S1E2W_Xt: 1889 case MISCREG_AT_S12E1R_Xt: 1890 case MISCREG_AT_S12E1W_Xt: 1891 case MISCREG_AT_S12E0R_Xt: 1892 case MISCREG_AT_S12E0W_Xt: 1893 case MISCREG_AT_S1E3R_Xt: 1894 case MISCREG_AT_S1E3W_Xt: 1895 { 1896 RequestPtr req = std::make_shared<Request>(); 1897 Request::Flags flags = 0; 1898 BaseTLB::Mode mode = BaseTLB::Read; 1899 TLB::ArmTranslationType tranType = TLB::NormalTran; 1900 Fault fault; 1901 switch(misc_reg) { 1902 case MISCREG_AT_S1E1R_Xt: 1903 flags = TLB::MustBeOne; 1904 tranType = TLB::S1E1Tran; 1905 mode = BaseTLB::Read; 1906 break; 1907 case MISCREG_AT_S1E1W_Xt: 1908 flags = TLB::MustBeOne; 1909 tranType = TLB::S1E1Tran; 1910 mode = BaseTLB::Write; 1911 break; 1912 case MISCREG_AT_S1E0R_Xt: 1913 flags = TLB::MustBeOne | TLB::UserMode; 1914 tranType = TLB::S1E0Tran; 1915 mode = BaseTLB::Read; 1916 break; 1917 case MISCREG_AT_S1E0W_Xt: 1918 flags = TLB::MustBeOne | TLB::UserMode; 1919 tranType = TLB::S1E0Tran; 1920 mode = BaseTLB::Write; 1921 break; 1922 case MISCREG_AT_S1E2R_Xt: 1923 flags = TLB::MustBeOne; 1924 tranType = TLB::S1E2Tran; 1925 mode = BaseTLB::Read; 1926 break; 1927 case MISCREG_AT_S1E2W_Xt: 1928 flags = TLB::MustBeOne; 1929 tranType = TLB::S1E2Tran; 1930 mode = BaseTLB::Write; 1931 break; 1932 case MISCREG_AT_S12E0R_Xt: 1933 flags = TLB::MustBeOne | TLB::UserMode; 1934 tranType = TLB::S12E0Tran; 1935 mode = BaseTLB::Read; 1936 break; 1937 case MISCREG_AT_S12E0W_Xt: 1938 flags = TLB::MustBeOne | TLB::UserMode; 1939 tranType = TLB::S12E0Tran; 1940 mode = BaseTLB::Write; 1941 break; 1942 case MISCREG_AT_S12E1R_Xt: 1943 flags = TLB::MustBeOne; 1944 tranType = TLB::S12E1Tran; 1945 mode = BaseTLB::Read; 1946 break; 1947 case MISCREG_AT_S12E1W_Xt: 1948 flags = TLB::MustBeOne; 1949 tranType = TLB::S12E1Tran; 1950 mode = BaseTLB::Write; 1951 break; 1952 case MISCREG_AT_S1E3R_Xt: 1953 flags = TLB::MustBeOne; 1954 tranType = TLB::S1E3Tran; 1955 mode = BaseTLB::Read; 1956 break; 1957 case MISCREG_AT_S1E3W_Xt: 1958 flags = TLB::MustBeOne; 1959 tranType = TLB::S1E3Tran; 1960 mode = BaseTLB::Write; 1961 break; 1962 } 1963 // If we're in timing mode then doing the translation in 1964 // functional mode then we're slightly distorting performance 1965 // results obtained from simulations. The translation should be 1966 // done in the same mode the core is running in. NOTE: This 1967 // can't be an atomic translation because that causes problems 1968 // with unexpected atomic snoop requests. 1969 warn("Translating via %s in functional mode! Fix Me!\n", 1970 miscRegName[misc_reg]); 1971 1972 req->setVirt(0, val, 0, flags, Request::funcMasterId, 1973 tc->pcState().pc()); 1974 req->setContext(tc->contextId()); 1975 fault = getDTBPtr(tc)->translateFunctional(req, tc, mode, 1976 tranType); 1977 1978 RegVal newVal; 1979 if (fault == NoFault) { 1980 Addr paddr = req->getPaddr(); 1981 uint64_t attr = getDTBPtr(tc)->getAttr(); 1982 uint64_t attr1 = attr >> 56; 1983 if (!attr1 || attr1 ==0x44) { 1984 attr |= 0x100; 1985 attr &= ~ uint64_t(0x80); 1986 } 1987 newVal = (paddr & mask(47, 12)) | attr; 1988 DPRINTF(MiscRegs, 1989 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 1990 val, newVal); 1991 } else { 1992 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1993 armFault->update(tc); 1994 // Set fault bit and FSR 1995 FSR fsr = armFault->getFsr(tc); 1996 1997 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1998 if (cpsr.width) { // AArch32 1999 newVal = ((fsr >> 9) & 1) << 11; 2000 // rearrange fault status 2001 newVal |= ((fsr >> 0) & 0x3f) << 1; 2002 newVal |= 0x1; // F bit 2003 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 2004 newVal |= armFault->isStage2() ? 0x200 : 0; 2005 } else { // AArch64 2006 newVal = 1; // F bit 2007 newVal |= fsr << 1; // FST 2008 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit. 2009 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 2010 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 2011 newVal |= 1 << 11; // RES1 2012 } 2013 DPRINTF(MiscRegs, 2014 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 2015 val, fsr, newVal); 2016 } 2017 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 2018 return; 2019 } 2020 case MISCREG_SPSR_EL3: 2021 case MISCREG_SPSR_EL2: 2022 case MISCREG_SPSR_EL1: 2023 // Force bits 23:21 to 0 2024 newVal = val & ~(0x7 << 21); 2025 break; 2026 case MISCREG_L2CTLR: 2027 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 2028 miscRegName[misc_reg], uint32_t(val)); 2029 break; 2030 2031 // Generic Timer registers 2032 case MISCREG_CNTHV_CTL_EL2: 2033 case MISCREG_CNTHV_CVAL_EL2: 2034 case MISCREG_CNTHV_TVAL_EL2: 2035 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 2036 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 2037 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 2038 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 2039 getGenericTimer(tc).setMiscReg(misc_reg, newVal); 2040 break; 2041 case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3: 2042 case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2: 2043 getGICv3CPUInterface(tc).setMiscReg(misc_reg, newVal); 2044 return; 2045 case MISCREG_ZCR_EL3: 2046 case MISCREG_ZCR_EL2: 2047 case MISCREG_ZCR_EL1: 2048 tc->getDecoderPtr()->setSveLen( 2049 (getCurSveVecLenInBits(tc) >> 7) - 1); 2050 break; 2051 } 2052 } 2053 setMiscRegNoEffect(misc_reg, newVal); 2054} 2055 2056BaseISADevice & 2057ISA::getGenericTimer(ThreadContext *tc) 2058{ 2059 // We only need to create an ISA interface the first time we try 2060 // to access the timer. 2061 if (timer) 2062 return *timer.get(); 2063 2064 assert(system); 2065 GenericTimer *generic_timer(system->getGenericTimer()); 2066 if (!generic_timer) { 2067 panic("Trying to get a generic timer from a system that hasn't " 2068 "been configured to use a generic timer.\n"); 2069 } 2070 2071 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 2072 timer->setThreadContext(tc); 2073 2074 return *timer.get(); 2075} 2076 2077BaseISADevice & 2078ISA::getGICv3CPUInterface(ThreadContext *tc) 2079{ 2080 panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!"); 2081 return *gicv3CpuInterface.get(); 2082} 2083 2084unsigned 2085ISA::getCurSveVecLenInBits(ThreadContext *tc) const 2086{ 2087 if (!FullSystem) { 2088 return sveVL * 128; 2089 } 2090 2091 panic_if(!tc, 2092 "A ThreadContext is needed to determine the SVE vector length " 2093 "in full-system mode"); 2094 2095 CPSR cpsr = miscRegs[MISCREG_CPSR]; 2096 ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el; 2097 2098 unsigned len = 0; 2099 2100 if (el == EL1 || (el == EL0 && !ELIsInHost(tc, el))) { 2101 len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL1]).len; 2102 } 2103 2104 if (el == EL2 || (el == EL0 && ELIsInHost(tc, el))) { 2105 len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL2]).len; 2106 } else if (haveVirtualization && !inSecureState(tc) && 2107 (el == EL0 || el == EL1)) { 2108 len = std::min( 2109 len, 2110 static_cast<unsigned>( 2111 static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL2]).len)); 2112 } 2113 2114 if (el == EL3) { 2115 len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL3]).len; 2116 } else if (haveSecurity) { 2117 len = std::min( 2118 len, 2119 static_cast<unsigned>( 2120 static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL3]).len)); 2121 } 2122 2123 len = std::min(len, sveVL - 1); 2124 2125 return (len + 1) * 128; 2126} 2127 2128void 2129ISA::zeroSveVecRegUpperPart(VecRegContainer &vc, unsigned eCount) 2130{ 2131 auto vv = vc.as<uint64_t>(); 2132 for (int i = 2; i < eCount; ++i) { 2133 vv[i] = 0; 2134 } 2135} 2136 2137} // namespace ArmISA 2138 2139ArmISA::ISA * 2140ArmISAParams::create() 2141{ 2142 return new ArmISA::ISA(this); 2143} 2144