isa.cc revision 13882:03fe9a85b435
1/* 2 * Copyright (c) 2010-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 */ 40 41#include "arch/arm/isa.hh" 42#include "arch/arm/pmu.hh" 43#include "arch/arm/system.hh" 44#include "arch/arm/tlb.hh" 45#include "arch/arm/tlbi_op.hh" 46#include "cpu/base.hh" 47#include "cpu/checker/cpu.hh" 48#include "debug/Arm.hh" 49#include "debug/MiscRegs.hh" 50#include "dev/arm/generic_timer.hh" 51#include "dev/arm/gic_v3.hh" 52#include "dev/arm/gic_v3_cpu_interface.hh" 53#include "params/ArmISA.hh" 54#include "sim/faults.hh" 55#include "sim/stat_control.hh" 56#include "sim/system.hh" 57 58namespace ArmISA 59{ 60 61ISA::ISA(Params *p) 62 : SimObject(p), 63 system(NULL), 64 _decoderFlavour(p->decoderFlavour), 65 _vecRegRenameMode(Enums::Full), 66 pmu(p->pmu), 67 haveGICv3CPUInterface(false), 68 impdefAsNop(p->impdef_nop) 69{ 70 miscRegs[MISCREG_SCTLR_RST] = 0; 71 72 // Hook up a dummy device if we haven't been configured with a 73 // real PMU. By using a dummy device, we don't need to check that 74 // the PMU exist every time we try to access a PMU register. 75 if (!pmu) 76 pmu = &dummyDevice; 77 78 // Give all ISA devices a pointer to this ISA 79 pmu->setISA(this); 80 81 system = dynamic_cast<ArmSystem *>(p->system); 82 83 // Cache system-level properties 84 if (FullSystem && system) { 85 highestELIs64 = system->highestELIs64(); 86 haveSecurity = system->haveSecurity(); 87 haveLPAE = system->haveLPAE(); 88 haveCrypto = system->haveCrypto(); 89 haveVirtualization = system->haveVirtualization(); 90 haveLargeAsid64 = system->haveLargeAsid64(); 91 physAddrRange = system->physAddrRange(); 92 haveSVE = system->haveSVE(); 93 sveVL = system->sveVL(); 94 } else { 95 highestELIs64 = true; // ArmSystem::highestELIs64 does the same 96 haveSecurity = haveLPAE = haveVirtualization = false; 97 haveCrypto = true; 98 haveLargeAsid64 = false; 99 physAddrRange = 32; // dummy value 100 haveSVE = true; 101 sveVL = p->sve_vl_se; 102 } 103 104 // Initial rename mode depends on highestEL 105 const_cast<Enums::VecRegRenameMode&>(_vecRegRenameMode) = 106 highestELIs64 ? Enums::Full : Enums::Elem; 107 108 initializeMiscRegMetadata(); 109 preUnflattenMiscReg(); 110 111 clear(); 112} 113 114std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS); 115 116const ArmISAParams * 117ISA::params() const 118{ 119 return dynamic_cast<const Params *>(_params); 120} 121 122void 123ISA::clear() 124{ 125 const Params *p(params()); 126 127 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 128 memset(miscRegs, 0, sizeof(miscRegs)); 129 130 initID32(p); 131 132 // We always initialize AArch64 ID registers even 133 // if we are in AArch32. This is done since if we 134 // are in SE mode we don't know if our ArmProcess is 135 // AArch32 or AArch64 136 initID64(p); 137 138 // Start with an event in the mailbox 139 miscRegs[MISCREG_SEV_MAILBOX] = 1; 140 141 // Separate Instruction and Data TLBs 142 miscRegs[MISCREG_TLBTR] = 1; 143 144 MVFR0 mvfr0 = 0; 145 mvfr0.advSimdRegisters = 2; 146 mvfr0.singlePrecision = 2; 147 mvfr0.doublePrecision = 2; 148 mvfr0.vfpExceptionTrapping = 0; 149 mvfr0.divide = 1; 150 mvfr0.squareRoot = 1; 151 mvfr0.shortVectors = 1; 152 mvfr0.roundingModes = 1; 153 miscRegs[MISCREG_MVFR0] = mvfr0; 154 155 MVFR1 mvfr1 = 0; 156 mvfr1.flushToZero = 1; 157 mvfr1.defaultNaN = 1; 158 mvfr1.advSimdLoadStore = 1; 159 mvfr1.advSimdInteger = 1; 160 mvfr1.advSimdSinglePrecision = 1; 161 mvfr1.advSimdHalfPrecision = 1; 162 mvfr1.vfpHalfPrecision = 1; 163 miscRegs[MISCREG_MVFR1] = mvfr1; 164 165 // Reset values of PRRR and NMRR are implementation dependent 166 167 // @todo: PRRR and NMRR in secure state? 168 miscRegs[MISCREG_PRRR_NS] = 169 (1 << 19) | // 19 170 (0 << 18) | // 18 171 (0 << 17) | // 17 172 (1 << 16) | // 16 173 (2 << 14) | // 15:14 174 (0 << 12) | // 13:12 175 (2 << 10) | // 11:10 176 (2 << 8) | // 9:8 177 (2 << 6) | // 7:6 178 (2 << 4) | // 5:4 179 (1 << 2) | // 3:2 180 0; // 1:0 181 182 miscRegs[MISCREG_NMRR_NS] = 183 (1 << 30) | // 31:30 184 (0 << 26) | // 27:26 185 (0 << 24) | // 25:24 186 (3 << 22) | // 23:22 187 (2 << 20) | // 21:20 188 (0 << 18) | // 19:18 189 (0 << 16) | // 17:16 190 (1 << 14) | // 15:14 191 (0 << 12) | // 13:12 192 (2 << 10) | // 11:10 193 (0 << 8) | // 9:8 194 (3 << 6) | // 7:6 195 (2 << 4) | // 5:4 196 (0 << 2) | // 3:2 197 0; // 1:0 198 199 if (FullSystem && system->highestELIs64()) { 200 // Initialize AArch64 state 201 clear64(p); 202 return; 203 } 204 205 // Initialize AArch32 state... 206 clear32(p, sctlr_rst); 207} 208 209void 210ISA::clear32(const ArmISAParams *p, const SCTLR &sctlr_rst) 211{ 212 CPSR cpsr = 0; 213 cpsr.mode = MODE_USER; 214 215 if (FullSystem) { 216 miscRegs[MISCREG_MVBAR] = system->resetAddr(); 217 } 218 219 miscRegs[MISCREG_CPSR] = cpsr; 220 updateRegMap(cpsr); 221 222 SCTLR sctlr = 0; 223 sctlr.te = (bool) sctlr_rst.te; 224 sctlr.nmfi = (bool) sctlr_rst.nmfi; 225 sctlr.v = (bool) sctlr_rst.v; 226 sctlr.u = 1; 227 sctlr.xp = 1; 228 sctlr.rao2 = 1; 229 sctlr.rao3 = 1; 230 sctlr.rao4 = 0xf; // SCTLR[6:3] 231 sctlr.uci = 1; 232 sctlr.dze = 1; 233 miscRegs[MISCREG_SCTLR_NS] = sctlr; 234 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 235 miscRegs[MISCREG_HCPTR] = 0; 236 237 miscRegs[MISCREG_CPACR] = 0; 238 239 miscRegs[MISCREG_FPSID] = p->fpsid; 240 241 if (haveLPAE) { 242 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 243 ttbcr.eae = 0; 244 miscRegs[MISCREG_TTBCR_NS] = ttbcr; 245 // Enforce consistency with system-level settings 246 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 247 } 248 249 if (haveSecurity) { 250 miscRegs[MISCREG_SCTLR_S] = sctlr; 251 miscRegs[MISCREG_SCR] = 0; 252 miscRegs[MISCREG_VBAR_S] = 0; 253 } else { 254 // we're always non-secure 255 miscRegs[MISCREG_SCR] = 1; 256 } 257 258 //XXX We need to initialize the rest of the state. 259} 260 261void 262ISA::clear64(const ArmISAParams *p) 263{ 264 CPSR cpsr = 0; 265 Addr rvbar = system->resetAddr(); 266 switch (system->highestEL()) { 267 // Set initial EL to highest implemented EL using associated stack 268 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 269 // value 270 case EL3: 271 cpsr.mode = MODE_EL3H; 272 miscRegs[MISCREG_RVBAR_EL3] = rvbar; 273 break; 274 case EL2: 275 cpsr.mode = MODE_EL2H; 276 miscRegs[MISCREG_RVBAR_EL2] = rvbar; 277 break; 278 case EL1: 279 cpsr.mode = MODE_EL1H; 280 miscRegs[MISCREG_RVBAR_EL1] = rvbar; 281 break; 282 default: 283 panic("Invalid highest implemented exception level"); 284 break; 285 } 286 287 // Initialize rest of CPSR 288 cpsr.daif = 0xf; // Mask all interrupts 289 cpsr.ss = 0; 290 cpsr.il = 0; 291 miscRegs[MISCREG_CPSR] = cpsr; 292 updateRegMap(cpsr); 293 294 // Initialize other control registers 295 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 296 if (haveSecurity) { 297 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830; 298 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 299 } else if (haveVirtualization) { 300 // also MISCREG_SCTLR_EL2 (by mapping) 301 miscRegs[MISCREG_HSCTLR] = 0x30c50830; 302 } else { 303 // also MISCREG_SCTLR_EL1 (by mapping) 304 miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init 305 // Always non-secure 306 miscRegs[MISCREG_SCR_EL3] = 1; 307 } 308} 309 310void 311ISA::initID32(const ArmISAParams *p) 312{ 313 // Initialize configurable default values 314 miscRegs[MISCREG_MIDR] = p->midr; 315 miscRegs[MISCREG_MIDR_EL1] = p->midr; 316 miscRegs[MISCREG_VPIDR] = p->midr; 317 318 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 319 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 320 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 321 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 322 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 323 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 324 325 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 326 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 327 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 328 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 329 330 miscRegs[MISCREG_ID_ISAR5] = insertBits( 331 miscRegs[MISCREG_ID_ISAR5], 19, 4, 332 haveCrypto ? 0x1112 : 0x0); 333} 334 335void 336ISA::initID64(const ArmISAParams *p) 337{ 338 // Initialize configurable id registers 339 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 340 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 341 miscRegs[MISCREG_ID_AA64DFR0_EL1] = 342 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 343 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 344 345 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 346 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 347 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 348 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 349 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 350 miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p->id_aa64mmfr2_el1; 351 352 miscRegs[MISCREG_ID_DFR0_EL1] = 353 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 354 355 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 356 357 // SVE 358 miscRegs[MISCREG_ID_AA64ZFR0_EL1] = 0; // SVEver 0 359 if (haveSecurity) { 360 miscRegs[MISCREG_ZCR_EL3] = sveVL - 1; 361 } else if (haveVirtualization) { 362 miscRegs[MISCREG_ZCR_EL2] = sveVL - 1; 363 } else { 364 miscRegs[MISCREG_ZCR_EL1] = sveVL - 1; 365 } 366 367 // Enforce consistency with system-level settings... 368 369 // EL3 370 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 371 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 372 haveSecurity ? 0x2 : 0x0); 373 // EL2 374 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 375 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 376 haveVirtualization ? 0x2 : 0x0); 377 // SVE 378 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 379 miscRegs[MISCREG_ID_AA64PFR0_EL1], 35, 32, 380 haveSVE ? 0x1 : 0x0); 381 // Large ASID support 382 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 383 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 384 haveLargeAsid64 ? 0x2 : 0x0); 385 // Physical address size 386 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 387 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 388 encodePhysAddrRange64(physAddrRange)); 389 // Crypto 390 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits( 391 miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4, 392 haveCrypto ? 0x1112 : 0x0); 393} 394 395void 396ISA::startup(ThreadContext *tc) 397{ 398 pmu->setThreadContext(tc); 399 400 if (system) { 401 Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC()); 402 if (gicv3) { 403 haveGICv3CPUInterface = true; 404 gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId())); 405 gicv3CpuInterface->setISA(this); 406 gicv3CpuInterface->setThreadContext(tc); 407 } 408 } 409} 410 411 412RegVal 413ISA::readMiscRegNoEffect(int misc_reg) const 414{ 415 assert(misc_reg < NumMiscRegs); 416 417 const auto ® = lookUpMiscReg[misc_reg]; // bit masks 418 const auto &map = getMiscIndices(misc_reg); 419 int lower = map.first, upper = map.second; 420 // NB!: apply architectural masks according to desired register, 421 // despite possibly getting value from different (mapped) register. 422 auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32)) 423 |(miscRegs[upper] << 32)); 424 if (val & reg.res0()) { 425 DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n", 426 miscRegName[misc_reg], val & reg.res0()); 427 } 428 if ((val & reg.res1()) != reg.res1()) { 429 DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n", 430 miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1()); 431 } 432 return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao 433} 434 435 436RegVal 437ISA::readMiscReg(int misc_reg, ThreadContext *tc) 438{ 439 CPSR cpsr = 0; 440 PCState pc = 0; 441 SCR scr = 0; 442 443 if (misc_reg == MISCREG_CPSR) { 444 cpsr = miscRegs[misc_reg]; 445 pc = tc->pcState(); 446 cpsr.j = pc.jazelle() ? 1 : 0; 447 cpsr.t = pc.thumb() ? 1 : 0; 448 return cpsr; 449 } 450 451#ifndef NDEBUG 452 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 453 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 454 warn("Unimplemented system register %s read.\n", 455 miscRegName[misc_reg]); 456 else 457 panic("Unimplemented system register %s read.\n", 458 miscRegName[misc_reg]); 459 } 460#endif 461 462 switch (unflattenMiscReg(misc_reg)) { 463 case MISCREG_HCR: 464 { 465 if (!haveVirtualization) 466 return 0; 467 else 468 return readMiscRegNoEffect(MISCREG_HCR); 469 } 470 case MISCREG_CPACR: 471 { 472 const uint32_t ones = (uint32_t)(-1); 473 CPACR cpacrMask = 0; 474 // Only cp10, cp11, and ase are implemented, nothing else should 475 // be readable? (straight copy from the write code) 476 cpacrMask.cp10 = ones; 477 cpacrMask.cp11 = ones; 478 cpacrMask.asedis = ones; 479 480 // Security Extensions may limit the readability of CPACR 481 if (haveSecurity) { 482 scr = readMiscRegNoEffect(MISCREG_SCR); 483 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 484 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 485 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 486 // NB: Skipping the full loop, here 487 if (!nsacr.cp10) cpacrMask.cp10 = 0; 488 if (!nsacr.cp11) cpacrMask.cp11 = 0; 489 } 490 } 491 RegVal val = readMiscRegNoEffect(MISCREG_CPACR); 492 val &= cpacrMask; 493 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 494 miscRegName[misc_reg], val); 495 return val; 496 } 497 case MISCREG_MPIDR: 498 case MISCREG_MPIDR_EL1: 499 return readMPIDR(system, tc); 500 case MISCREG_VMPIDR: 501 case MISCREG_VMPIDR_EL2: 502 // top bit defined as RES1 503 return readMiscRegNoEffect(misc_reg) | 0x80000000; 504 case MISCREG_ID_AFR0: // not implemented, so alias MIDR 505 case MISCREG_REVIDR: // not implemented, so alias MIDR 506 case MISCREG_MIDR: 507 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 508 scr = readMiscRegNoEffect(MISCREG_SCR); 509 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 510 return readMiscRegNoEffect(misc_reg); 511 } else { 512 return readMiscRegNoEffect(MISCREG_VPIDR); 513 } 514 break; 515 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 516 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 517 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 518 case MISCREG_AIDR: // AUX ID set to 0 519 case MISCREG_TCMTR: // No TCM's 520 return 0; 521 522 case MISCREG_CLIDR: 523 warn_once("The clidr register always reports 0 caches.\n"); 524 warn_once("clidr LoUIS field of 0b001 to match current " 525 "ARM implementations.\n"); 526 return 0x00200000; 527 case MISCREG_CCSIDR: 528 warn_once("The ccsidr register isn't implemented and " 529 "always reads as 0.\n"); 530 break; 531 case MISCREG_CTR: // AArch32, ARMv7, top bit set 532 case MISCREG_CTR_EL0: // AArch64 533 { 534 //all caches have the same line size in gem5 535 //4 byte words in ARM 536 unsigned lineSizeWords = 537 tc->getSystemPtr()->cacheLineSize() / 4; 538 unsigned log2LineSizeWords = 0; 539 540 while (lineSizeWords >>= 1) { 541 ++log2LineSizeWords; 542 } 543 544 CTR ctr = 0; 545 //log2 of minimun i-cache line size (words) 546 ctr.iCacheLineSize = log2LineSizeWords; 547 //b11 - gem5 uses pipt 548 ctr.l1IndexPolicy = 0x3; 549 //log2 of minimum d-cache line size (words) 550 ctr.dCacheLineSize = log2LineSizeWords; 551 //log2 of max reservation size (words) 552 ctr.erg = log2LineSizeWords; 553 //log2 of max writeback size (words) 554 ctr.cwg = log2LineSizeWords; 555 //b100 - gem5 format is ARMv7 556 ctr.format = 0x4; 557 558 return ctr; 559 } 560 case MISCREG_ACTLR: 561 warn("Not doing anything for miscreg ACTLR\n"); 562 break; 563 564 case MISCREG_PMXEVTYPER_PMCCFILTR: 565 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 566 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 567 case MISCREG_PMCR ... MISCREG_PMOVSSET: 568 return pmu->readMiscReg(misc_reg); 569 570 case MISCREG_CPSR_Q: 571 panic("shouldn't be reading this register seperately\n"); 572 case MISCREG_FPSCR_QC: 573 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 574 case MISCREG_FPSCR_EXC: 575 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 576 case MISCREG_FPSR: 577 { 578 const uint32_t ones = (uint32_t)(-1); 579 FPSCR fpscrMask = 0; 580 fpscrMask.ioc = ones; 581 fpscrMask.dzc = ones; 582 fpscrMask.ofc = ones; 583 fpscrMask.ufc = ones; 584 fpscrMask.ixc = ones; 585 fpscrMask.idc = ones; 586 fpscrMask.qc = ones; 587 fpscrMask.v = ones; 588 fpscrMask.c = ones; 589 fpscrMask.z = ones; 590 fpscrMask.n = ones; 591 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 592 } 593 case MISCREG_FPCR: 594 { 595 const uint32_t ones = (uint32_t)(-1); 596 FPSCR fpscrMask = 0; 597 fpscrMask.len = ones; 598 fpscrMask.fz16 = ones; 599 fpscrMask.stride = ones; 600 fpscrMask.rMode = ones; 601 fpscrMask.fz = ones; 602 fpscrMask.dn = ones; 603 fpscrMask.ahp = ones; 604 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 605 } 606 case MISCREG_NZCV: 607 { 608 CPSR cpsr = 0; 609 cpsr.nz = tc->readCCReg(CCREG_NZ); 610 cpsr.c = tc->readCCReg(CCREG_C); 611 cpsr.v = tc->readCCReg(CCREG_V); 612 return cpsr; 613 } 614 case MISCREG_DAIF: 615 { 616 CPSR cpsr = 0; 617 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 618 return cpsr; 619 } 620 case MISCREG_SP_EL0: 621 { 622 return tc->readIntReg(INTREG_SP0); 623 } 624 case MISCREG_SP_EL1: 625 { 626 return tc->readIntReg(INTREG_SP1); 627 } 628 case MISCREG_SP_EL2: 629 { 630 return tc->readIntReg(INTREG_SP2); 631 } 632 case MISCREG_SPSEL: 633 { 634 return miscRegs[MISCREG_CPSR] & 0x1; 635 } 636 case MISCREG_CURRENTEL: 637 { 638 return miscRegs[MISCREG_CPSR] & 0xc; 639 } 640 case MISCREG_L2CTLR: 641 { 642 // mostly unimplemented, just set NumCPUs field from sim and return 643 L2CTLR l2ctlr = 0; 644 // b00:1CPU to b11:4CPUs 645 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 646 return l2ctlr; 647 } 648 case MISCREG_DBGDIDR: 649 /* For now just implement the version number. 650 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 651 */ 652 return 0x5 << 16; 653 case MISCREG_DBGDSCRint: 654 return 0; 655 case MISCREG_ISR: 656 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 657 readMiscRegNoEffect(MISCREG_HCR), 658 readMiscRegNoEffect(MISCREG_CPSR), 659 readMiscRegNoEffect(MISCREG_SCR)); 660 case MISCREG_ISR_EL1: 661 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 662 readMiscRegNoEffect(MISCREG_HCR_EL2), 663 readMiscRegNoEffect(MISCREG_CPSR), 664 readMiscRegNoEffect(MISCREG_SCR_EL3)); 665 case MISCREG_DCZID_EL0: 666 return 0x04; // DC ZVA clear 64-byte chunks 667 case MISCREG_HCPTR: 668 { 669 RegVal val = readMiscRegNoEffect(misc_reg); 670 // The trap bit associated with CP14 is defined as RAZ 671 val &= ~(1 << 14); 672 // If a CP bit in NSACR is 0 then the corresponding bit in 673 // HCPTR is RAO/WI 674 bool secure_lookup = haveSecurity && 675 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 676 readMiscRegNoEffect(MISCREG_CPSR)); 677 if (!secure_lookup) { 678 RegVal mask = readMiscRegNoEffect(MISCREG_NSACR); 679 val |= (mask ^ 0x7FFF) & 0xBFFF; 680 } 681 // Set the bits for unimplemented coprocessors to RAO/WI 682 val |= 0x33FF; 683 return (val); 684 } 685 case MISCREG_HDFAR: // alias for secure DFAR 686 return readMiscRegNoEffect(MISCREG_DFAR_S); 687 case MISCREG_HIFAR: // alias for secure IFAR 688 return readMiscRegNoEffect(MISCREG_IFAR_S); 689 690 case MISCREG_ID_PFR0: 691 // !ThumbEE | !Jazelle | Thumb | ARM 692 return 0x00000031; 693 case MISCREG_ID_PFR1: 694 { // Timer | Virti | !M Profile | TrustZone | ARMv4 695 bool haveTimer = (system->getGenericTimer() != NULL); 696 return 0x00000001 697 | (haveSecurity ? 0x00000010 : 0x0) 698 | (haveVirtualization ? 0x00001000 : 0x0) 699 | (haveTimer ? 0x00010000 : 0x0); 700 } 701 case MISCREG_ID_AA64PFR0_EL1: 702 return 0x0000000000000002 | // AArch{64,32} supported at EL0 703 0x0000000000000020 | // EL1 704 (haveVirtualization ? 0x0000000000000200 : 0) | // EL2 705 (haveSecurity ? 0x0000000000002000 : 0) | // EL3 706 (haveSVE ? 0x0000000100000000 : 0) | // SVE 707 (haveGICv3CPUInterface ? 0x0000000001000000 : 0); 708 case MISCREG_ID_AA64PFR1_EL1: 709 return 0; // bits [63:0] RES0 (reserved for future use) 710 711 // Generic Timer registers 712 case MISCREG_CNTHV_CTL_EL2: 713 case MISCREG_CNTHV_CVAL_EL2: 714 case MISCREG_CNTHV_TVAL_EL2: 715 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 716 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 717 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 718 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 719 return getGenericTimer(tc).readMiscReg(misc_reg); 720 721 case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3: 722 case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2: 723 return getGICv3CPUInterface(tc).readMiscReg(misc_reg); 724 725 default: 726 break; 727 728 } 729 return readMiscRegNoEffect(misc_reg); 730} 731 732void 733ISA::setMiscRegNoEffect(int misc_reg, RegVal val) 734{ 735 assert(misc_reg < NumMiscRegs); 736 737 const auto ® = lookUpMiscReg[misc_reg]; // bit masks 738 const auto &map = getMiscIndices(misc_reg); 739 int lower = map.first, upper = map.second; 740 741 auto v = (val & ~reg.wi()) | reg.rao(); 742 if (upper > 0) { 743 miscRegs[lower] = bits(v, 31, 0); 744 miscRegs[upper] = bits(v, 63, 32); 745 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 746 misc_reg, lower, upper, v); 747 } else { 748 miscRegs[lower] = v; 749 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 750 misc_reg, lower, v); 751 } 752} 753 754void 755ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) 756{ 757 758 RegVal newVal = val; 759 bool secure_lookup; 760 SCR scr; 761 762 if (misc_reg == MISCREG_CPSR) { 763 updateRegMap(val); 764 765 766 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 767 int old_mode = old_cpsr.mode; 768 CPSR cpsr = val; 769 if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) { 770 getITBPtr(tc)->invalidateMiscReg(); 771 getDTBPtr(tc)->invalidateMiscReg(); 772 } 773 774 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 775 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 776 PCState pc = tc->pcState(); 777 pc.nextThumb(cpsr.t); 778 pc.nextJazelle(cpsr.j); 779 pc.illegalExec(cpsr.il == 1); 780 781 tc->getDecoderPtr()->setSveLen((getCurSveVecLenInBits(tc) >> 7) - 1); 782 783 // Follow slightly different semantics if a CheckerCPU object 784 // is connected 785 CheckerCPU *checker = tc->getCheckerCpuPtr(); 786 if (checker) { 787 tc->pcStateNoRecord(pc); 788 } else { 789 tc->pcState(pc); 790 } 791 } else { 792#ifndef NDEBUG 793 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 794 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 795 warn("Unimplemented system register %s write with %#x.\n", 796 miscRegName[misc_reg], val); 797 else 798 panic("Unimplemented system register %s write with %#x.\n", 799 miscRegName[misc_reg], val); 800 } 801#endif 802 switch (unflattenMiscReg(misc_reg)) { 803 case MISCREG_CPACR: 804 { 805 806 const uint32_t ones = (uint32_t)(-1); 807 CPACR cpacrMask = 0; 808 // Only cp10, cp11, and ase are implemented, nothing else should 809 // be writable 810 cpacrMask.cp10 = ones; 811 cpacrMask.cp11 = ones; 812 cpacrMask.asedis = ones; 813 814 // Security Extensions may limit the writability of CPACR 815 if (haveSecurity) { 816 scr = readMiscRegNoEffect(MISCREG_SCR); 817 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 818 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 819 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 820 // NB: Skipping the full loop, here 821 if (!nsacr.cp10) cpacrMask.cp10 = 0; 822 if (!nsacr.cp11) cpacrMask.cp11 = 0; 823 } 824 } 825 826 RegVal old_val = readMiscRegNoEffect(MISCREG_CPACR); 827 newVal &= cpacrMask; 828 newVal |= old_val & ~cpacrMask; 829 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 830 miscRegName[misc_reg], newVal); 831 } 832 break; 833 case MISCREG_CPACR_EL1: 834 { 835 const uint32_t ones = (uint32_t)(-1); 836 CPACR cpacrMask = 0; 837 cpacrMask.tta = ones; 838 cpacrMask.fpen = ones; 839 if (haveSVE) { 840 cpacrMask.zen = ones; 841 } 842 newVal &= cpacrMask; 843 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 844 miscRegName[misc_reg], newVal); 845 } 846 break; 847 case MISCREG_CPTR_EL2: 848 { 849 const uint32_t ones = (uint32_t)(-1); 850 CPTR cptrMask = 0; 851 cptrMask.tcpac = ones; 852 cptrMask.tta = ones; 853 cptrMask.tfp = ones; 854 if (haveSVE) { 855 cptrMask.tz = ones; 856 } 857 newVal &= cptrMask; 858 cptrMask = 0; 859 cptrMask.res1_13_12_el2 = ones; 860 cptrMask.res1_7_0_el2 = ones; 861 if (!haveSVE) { 862 cptrMask.res1_8_el2 = ones; 863 } 864 cptrMask.res1_9_el2 = ones; 865 newVal |= cptrMask; 866 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 867 miscRegName[misc_reg], newVal); 868 } 869 break; 870 case MISCREG_CPTR_EL3: 871 { 872 const uint32_t ones = (uint32_t)(-1); 873 CPTR cptrMask = 0; 874 cptrMask.tcpac = ones; 875 cptrMask.tta = ones; 876 cptrMask.tfp = ones; 877 if (haveSVE) { 878 cptrMask.ez = ones; 879 } 880 newVal &= cptrMask; 881 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 882 miscRegName[misc_reg], newVal); 883 } 884 break; 885 case MISCREG_CSSELR: 886 warn_once("The csselr register isn't implemented.\n"); 887 return; 888 889 case MISCREG_DC_ZVA_Xt: 890 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 891 return; 892 893 case MISCREG_FPSCR: 894 { 895 const uint32_t ones = (uint32_t)(-1); 896 FPSCR fpscrMask = 0; 897 fpscrMask.ioc = ones; 898 fpscrMask.dzc = ones; 899 fpscrMask.ofc = ones; 900 fpscrMask.ufc = ones; 901 fpscrMask.ixc = ones; 902 fpscrMask.idc = ones; 903 fpscrMask.ioe = ones; 904 fpscrMask.dze = ones; 905 fpscrMask.ofe = ones; 906 fpscrMask.ufe = ones; 907 fpscrMask.ixe = ones; 908 fpscrMask.ide = ones; 909 fpscrMask.len = ones; 910 fpscrMask.fz16 = ones; 911 fpscrMask.stride = ones; 912 fpscrMask.rMode = ones; 913 fpscrMask.fz = ones; 914 fpscrMask.dn = ones; 915 fpscrMask.ahp = ones; 916 fpscrMask.qc = ones; 917 fpscrMask.v = ones; 918 fpscrMask.c = ones; 919 fpscrMask.z = ones; 920 fpscrMask.n = ones; 921 newVal = (newVal & (uint32_t)fpscrMask) | 922 (readMiscRegNoEffect(MISCREG_FPSCR) & 923 ~(uint32_t)fpscrMask); 924 tc->getDecoderPtr()->setContext(newVal); 925 } 926 break; 927 case MISCREG_FPSR: 928 { 929 const uint32_t ones = (uint32_t)(-1); 930 FPSCR fpscrMask = 0; 931 fpscrMask.ioc = ones; 932 fpscrMask.dzc = ones; 933 fpscrMask.ofc = ones; 934 fpscrMask.ufc = ones; 935 fpscrMask.ixc = ones; 936 fpscrMask.idc = ones; 937 fpscrMask.qc = ones; 938 fpscrMask.v = ones; 939 fpscrMask.c = ones; 940 fpscrMask.z = ones; 941 fpscrMask.n = ones; 942 newVal = (newVal & (uint32_t)fpscrMask) | 943 (readMiscRegNoEffect(MISCREG_FPSCR) & 944 ~(uint32_t)fpscrMask); 945 misc_reg = MISCREG_FPSCR; 946 } 947 break; 948 case MISCREG_FPCR: 949 { 950 const uint32_t ones = (uint32_t)(-1); 951 FPSCR fpscrMask = 0; 952 fpscrMask.len = ones; 953 fpscrMask.fz16 = ones; 954 fpscrMask.stride = ones; 955 fpscrMask.rMode = ones; 956 fpscrMask.fz = ones; 957 fpscrMask.dn = ones; 958 fpscrMask.ahp = ones; 959 newVal = (newVal & (uint32_t)fpscrMask) | 960 (readMiscRegNoEffect(MISCREG_FPSCR) & 961 ~(uint32_t)fpscrMask); 962 misc_reg = MISCREG_FPSCR; 963 } 964 break; 965 case MISCREG_CPSR_Q: 966 { 967 assert(!(newVal & ~CpsrMaskQ)); 968 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 969 misc_reg = MISCREG_CPSR; 970 } 971 break; 972 case MISCREG_FPSCR_QC: 973 { 974 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 975 (newVal & FpscrQcMask); 976 misc_reg = MISCREG_FPSCR; 977 } 978 break; 979 case MISCREG_FPSCR_EXC: 980 { 981 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 982 (newVal & FpscrExcMask); 983 misc_reg = MISCREG_FPSCR; 984 } 985 break; 986 case MISCREG_FPEXC: 987 { 988 // vfpv3 architecture, section B.6.1 of DDI04068 989 // bit 29 - valid only if fpexc[31] is 0 990 const uint32_t fpexcMask = 0x60000000; 991 newVal = (newVal & fpexcMask) | 992 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 993 } 994 break; 995 case MISCREG_HCR: 996 { 997 if (!haveVirtualization) 998 return; 999 } 1000 break; 1001 case MISCREG_IFSR: 1002 { 1003 // ARM ARM (ARM DDI 0406C.b) B4.1.96 1004 const uint32_t ifsrMask = 1005 mask(31, 13) | mask(11, 11) | mask(8, 6); 1006 newVal = newVal & ~ifsrMask; 1007 } 1008 break; 1009 case MISCREG_DFSR: 1010 { 1011 // ARM ARM (ARM DDI 0406C.b) B4.1.52 1012 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 1013 newVal = newVal & ~dfsrMask; 1014 } 1015 break; 1016 case MISCREG_AMAIR0: 1017 case MISCREG_AMAIR1: 1018 { 1019 // ARM ARM (ARM DDI 0406C.b) B4.1.5 1020 // Valid only with LPAE 1021 if (!haveLPAE) 1022 return; 1023 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 1024 } 1025 break; 1026 case MISCREG_SCR: 1027 getITBPtr(tc)->invalidateMiscReg(); 1028 getDTBPtr(tc)->invalidateMiscReg(); 1029 break; 1030 case MISCREG_SCTLR: 1031 { 1032 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 1033 scr = readMiscRegNoEffect(MISCREG_SCR); 1034 1035 MiscRegIndex sctlr_idx; 1036 if (haveSecurity && !highestELIs64 && !scr.ns) { 1037 sctlr_idx = MISCREG_SCTLR_S; 1038 } else { 1039 sctlr_idx = MISCREG_SCTLR_NS; 1040 } 1041 1042 SCTLR sctlr = miscRegs[sctlr_idx]; 1043 SCTLR new_sctlr = newVal; 1044 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 1045 miscRegs[sctlr_idx] = (RegVal)new_sctlr; 1046 getITBPtr(tc)->invalidateMiscReg(); 1047 getDTBPtr(tc)->invalidateMiscReg(); 1048 } 1049 case MISCREG_MIDR: 1050 case MISCREG_ID_PFR0: 1051 case MISCREG_ID_PFR1: 1052 case MISCREG_ID_DFR0: 1053 case MISCREG_ID_MMFR0: 1054 case MISCREG_ID_MMFR1: 1055 case MISCREG_ID_MMFR2: 1056 case MISCREG_ID_MMFR3: 1057 case MISCREG_ID_ISAR0: 1058 case MISCREG_ID_ISAR1: 1059 case MISCREG_ID_ISAR2: 1060 case MISCREG_ID_ISAR3: 1061 case MISCREG_ID_ISAR4: 1062 case MISCREG_ID_ISAR5: 1063 1064 case MISCREG_MPIDR: 1065 case MISCREG_FPSID: 1066 case MISCREG_TLBTR: 1067 case MISCREG_MVFR0: 1068 case MISCREG_MVFR1: 1069 1070 case MISCREG_ID_AA64AFR0_EL1: 1071 case MISCREG_ID_AA64AFR1_EL1: 1072 case MISCREG_ID_AA64DFR0_EL1: 1073 case MISCREG_ID_AA64DFR1_EL1: 1074 case MISCREG_ID_AA64ISAR0_EL1: 1075 case MISCREG_ID_AA64ISAR1_EL1: 1076 case MISCREG_ID_AA64MMFR0_EL1: 1077 case MISCREG_ID_AA64MMFR1_EL1: 1078 case MISCREG_ID_AA64MMFR2_EL1: 1079 case MISCREG_ID_AA64PFR0_EL1: 1080 case MISCREG_ID_AA64PFR1_EL1: 1081 // ID registers are constants. 1082 return; 1083 1084 // TLB Invalidate All 1085 case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 1086 { 1087 assert32(tc); 1088 scr = readMiscReg(MISCREG_SCR, tc); 1089 1090 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1091 tlbiOp(tc); 1092 return; 1093 } 1094 // TLB Invalidate All, Inner Shareable 1095 case MISCREG_TLBIALLIS: 1096 { 1097 assert32(tc); 1098 scr = readMiscReg(MISCREG_SCR, tc); 1099 1100 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1101 tlbiOp.broadcast(tc); 1102 return; 1103 } 1104 // Instruction TLB Invalidate All 1105 case MISCREG_ITLBIALL: 1106 { 1107 assert32(tc); 1108 scr = readMiscReg(MISCREG_SCR, tc); 1109 1110 ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1111 tlbiOp(tc); 1112 return; 1113 } 1114 // Data TLB Invalidate All 1115 case MISCREG_DTLBIALL: 1116 { 1117 assert32(tc); 1118 scr = readMiscReg(MISCREG_SCR, tc); 1119 1120 DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1121 tlbiOp(tc); 1122 return; 1123 } 1124 // TLB Invalidate by VA 1125 // mcr tlbimval(is) is invalidating all matching entries 1126 // regardless of the level of lookup, since in gem5 we cache 1127 // in the tlb the last level of lookup only. 1128 case MISCREG_TLBIMVA: 1129 case MISCREG_TLBIMVAL: 1130 { 1131 assert32(tc); 1132 scr = readMiscReg(MISCREG_SCR, tc); 1133 1134 TLBIMVA tlbiOp(EL1, 1135 haveSecurity && !scr.ns, 1136 mbits(newVal, 31, 12), 1137 bits(newVal, 7,0)); 1138 1139 tlbiOp(tc); 1140 return; 1141 } 1142 // TLB Invalidate by VA, Inner Shareable 1143 case MISCREG_TLBIMVAIS: 1144 case MISCREG_TLBIMVALIS: 1145 { 1146 assert32(tc); 1147 scr = readMiscReg(MISCREG_SCR, tc); 1148 1149 TLBIMVA tlbiOp(EL1, 1150 haveSecurity && !scr.ns, 1151 mbits(newVal, 31, 12), 1152 bits(newVal, 7,0)); 1153 1154 tlbiOp.broadcast(tc); 1155 return; 1156 } 1157 // TLB Invalidate by ASID match 1158 case MISCREG_TLBIASID: 1159 { 1160 assert32(tc); 1161 scr = readMiscReg(MISCREG_SCR, tc); 1162 1163 TLBIASID tlbiOp(EL1, 1164 haveSecurity && !scr.ns, 1165 bits(newVal, 7,0)); 1166 1167 tlbiOp(tc); 1168 return; 1169 } 1170 // TLB Invalidate by ASID match, Inner Shareable 1171 case MISCREG_TLBIASIDIS: 1172 { 1173 assert32(tc); 1174 scr = readMiscReg(MISCREG_SCR, tc); 1175 1176 TLBIASID tlbiOp(EL1, 1177 haveSecurity && !scr.ns, 1178 bits(newVal, 7,0)); 1179 1180 tlbiOp.broadcast(tc); 1181 return; 1182 } 1183 // mcr tlbimvaal(is) is invalidating all matching entries 1184 // regardless of the level of lookup, since in gem5 we cache 1185 // in the tlb the last level of lookup only. 1186 // TLB Invalidate by VA, All ASID 1187 case MISCREG_TLBIMVAA: 1188 case MISCREG_TLBIMVAAL: 1189 { 1190 assert32(tc); 1191 scr = readMiscReg(MISCREG_SCR, tc); 1192 1193 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1194 mbits(newVal, 31,12)); 1195 1196 tlbiOp(tc); 1197 return; 1198 } 1199 // TLB Invalidate by VA, All ASID, Inner Shareable 1200 case MISCREG_TLBIMVAAIS: 1201 case MISCREG_TLBIMVAALIS: 1202 { 1203 assert32(tc); 1204 scr = readMiscReg(MISCREG_SCR, tc); 1205 1206 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1207 mbits(newVal, 31,12)); 1208 1209 tlbiOp.broadcast(tc); 1210 return; 1211 } 1212 // mcr tlbimvalh(is) is invalidating all matching entries 1213 // regardless of the level of lookup, since in gem5 we cache 1214 // in the tlb the last level of lookup only. 1215 // TLB Invalidate by VA, Hyp mode 1216 case MISCREG_TLBIMVAH: 1217 case MISCREG_TLBIMVALH: 1218 { 1219 assert32(tc); 1220 scr = readMiscReg(MISCREG_SCR, tc); 1221 1222 TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns, 1223 mbits(newVal, 31,12)); 1224 1225 tlbiOp(tc); 1226 return; 1227 } 1228 // TLB Invalidate by VA, Hyp mode, Inner Shareable 1229 case MISCREG_TLBIMVAHIS: 1230 case MISCREG_TLBIMVALHIS: 1231 { 1232 assert32(tc); 1233 scr = readMiscReg(MISCREG_SCR, tc); 1234 1235 TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns, 1236 mbits(newVal, 31,12)); 1237 1238 tlbiOp.broadcast(tc); 1239 return; 1240 } 1241 // mcr tlbiipas2l(is) is invalidating all matching entries 1242 // regardless of the level of lookup, since in gem5 we cache 1243 // in the tlb the last level of lookup only. 1244 // TLB Invalidate by Intermediate Physical Address, Stage 2 1245 case MISCREG_TLBIIPAS2: 1246 case MISCREG_TLBIIPAS2L: 1247 { 1248 assert32(tc); 1249 scr = readMiscReg(MISCREG_SCR, tc); 1250 1251 TLBIIPA tlbiOp(EL1, 1252 haveSecurity && !scr.ns, 1253 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1254 1255 tlbiOp(tc); 1256 return; 1257 } 1258 // TLB Invalidate by Intermediate Physical Address, Stage 2, 1259 // Inner Shareable 1260 case MISCREG_TLBIIPAS2IS: 1261 case MISCREG_TLBIIPAS2LIS: 1262 { 1263 assert32(tc); 1264 scr = readMiscReg(MISCREG_SCR, tc); 1265 1266 TLBIIPA tlbiOp(EL1, 1267 haveSecurity && !scr.ns, 1268 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1269 1270 tlbiOp.broadcast(tc); 1271 return; 1272 } 1273 // Instruction TLB Invalidate by VA 1274 case MISCREG_ITLBIMVA: 1275 { 1276 assert32(tc); 1277 scr = readMiscReg(MISCREG_SCR, tc); 1278 1279 ITLBIMVA tlbiOp(EL1, 1280 haveSecurity && !scr.ns, 1281 mbits(newVal, 31, 12), 1282 bits(newVal, 7,0)); 1283 1284 tlbiOp(tc); 1285 return; 1286 } 1287 // Data TLB Invalidate by VA 1288 case MISCREG_DTLBIMVA: 1289 { 1290 assert32(tc); 1291 scr = readMiscReg(MISCREG_SCR, tc); 1292 1293 DTLBIMVA tlbiOp(EL1, 1294 haveSecurity && !scr.ns, 1295 mbits(newVal, 31, 12), 1296 bits(newVal, 7,0)); 1297 1298 tlbiOp(tc); 1299 return; 1300 } 1301 // Instruction TLB Invalidate by ASID match 1302 case MISCREG_ITLBIASID: 1303 { 1304 assert32(tc); 1305 scr = readMiscReg(MISCREG_SCR, tc); 1306 1307 ITLBIASID tlbiOp(EL1, 1308 haveSecurity && !scr.ns, 1309 bits(newVal, 7,0)); 1310 1311 tlbiOp(tc); 1312 return; 1313 } 1314 // Data TLB Invalidate by ASID match 1315 case MISCREG_DTLBIASID: 1316 { 1317 assert32(tc); 1318 scr = readMiscReg(MISCREG_SCR, tc); 1319 1320 DTLBIASID tlbiOp(EL1, 1321 haveSecurity && !scr.ns, 1322 bits(newVal, 7,0)); 1323 1324 tlbiOp(tc); 1325 return; 1326 } 1327 // TLB Invalidate All, Non-Secure Non-Hyp 1328 case MISCREG_TLBIALLNSNH: 1329 { 1330 assert32(tc); 1331 1332 TLBIALLN tlbiOp(EL1); 1333 tlbiOp(tc); 1334 return; 1335 } 1336 // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable 1337 case MISCREG_TLBIALLNSNHIS: 1338 { 1339 assert32(tc); 1340 1341 TLBIALLN tlbiOp(EL1); 1342 tlbiOp.broadcast(tc); 1343 return; 1344 } 1345 // TLB Invalidate All, Hyp mode 1346 case MISCREG_TLBIALLH: 1347 { 1348 assert32(tc); 1349 1350 TLBIALLN tlbiOp(EL2); 1351 tlbiOp(tc); 1352 return; 1353 } 1354 // TLB Invalidate All, Hyp mode, Inner Shareable 1355 case MISCREG_TLBIALLHIS: 1356 { 1357 assert32(tc); 1358 1359 TLBIALLN tlbiOp(EL2); 1360 tlbiOp.broadcast(tc); 1361 return; 1362 } 1363 // AArch64 TLB Invalidate All, EL3 1364 case MISCREG_TLBI_ALLE3: 1365 { 1366 assert64(tc); 1367 1368 TLBIALL tlbiOp(EL3, true); 1369 tlbiOp(tc); 1370 return; 1371 } 1372 // AArch64 TLB Invalidate All, EL3, Inner Shareable 1373 case MISCREG_TLBI_ALLE3IS: 1374 { 1375 assert64(tc); 1376 1377 TLBIALL tlbiOp(EL3, true); 1378 tlbiOp.broadcast(tc); 1379 return; 1380 } 1381 // AArch64 TLB Invalidate All, EL2, Inner Shareable 1382 case MISCREG_TLBI_ALLE2: 1383 case MISCREG_TLBI_ALLE2IS: 1384 { 1385 assert64(tc); 1386 scr = readMiscReg(MISCREG_SCR, tc); 1387 1388 TLBIALL tlbiOp(EL2, haveSecurity && !scr.ns); 1389 tlbiOp(tc); 1390 return; 1391 } 1392 // AArch64 TLB Invalidate All, EL1 1393 case MISCREG_TLBI_ALLE1: 1394 case MISCREG_TLBI_VMALLE1: 1395 case MISCREG_TLBI_VMALLS12E1: 1396 // @todo: handle VMID and stage 2 to enable Virtualization 1397 { 1398 assert64(tc); 1399 scr = readMiscReg(MISCREG_SCR, tc); 1400 1401 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1402 tlbiOp(tc); 1403 return; 1404 } 1405 // AArch64 TLB Invalidate All, EL1, Inner Shareable 1406 case MISCREG_TLBI_ALLE1IS: 1407 case MISCREG_TLBI_VMALLE1IS: 1408 case MISCREG_TLBI_VMALLS12E1IS: 1409 // @todo: handle VMID and stage 2 to enable Virtualization 1410 { 1411 assert64(tc); 1412 scr = readMiscReg(MISCREG_SCR, tc); 1413 1414 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1415 tlbiOp.broadcast(tc); 1416 return; 1417 } 1418 // VAEx(IS) and VALEx(IS) are the same because TLBs 1419 // only store entries 1420 // from the last level of translation table walks 1421 // @todo: handle VMID to enable Virtualization 1422 // AArch64 TLB Invalidate by VA, EL3 1423 case MISCREG_TLBI_VAE3_Xt: 1424 case MISCREG_TLBI_VALE3_Xt: 1425 { 1426 assert64(tc); 1427 1428 TLBIMVA tlbiOp(EL3, true, 1429 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1430 0xbeef); 1431 tlbiOp(tc); 1432 return; 1433 } 1434 // AArch64 TLB Invalidate by VA, EL3, Inner Shareable 1435 case MISCREG_TLBI_VAE3IS_Xt: 1436 case MISCREG_TLBI_VALE3IS_Xt: 1437 { 1438 assert64(tc); 1439 1440 TLBIMVA tlbiOp(EL3, true, 1441 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1442 0xbeef); 1443 1444 tlbiOp.broadcast(tc); 1445 return; 1446 } 1447 // AArch64 TLB Invalidate by VA, EL2 1448 case MISCREG_TLBI_VAE2_Xt: 1449 case MISCREG_TLBI_VALE2_Xt: 1450 { 1451 assert64(tc); 1452 scr = readMiscReg(MISCREG_SCR, tc); 1453 1454 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1455 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1456 0xbeef); 1457 tlbiOp(tc); 1458 return; 1459 } 1460 // AArch64 TLB Invalidate by VA, EL2, Inner Shareable 1461 case MISCREG_TLBI_VAE2IS_Xt: 1462 case MISCREG_TLBI_VALE2IS_Xt: 1463 { 1464 assert64(tc); 1465 scr = readMiscReg(MISCREG_SCR, tc); 1466 1467 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1468 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1469 0xbeef); 1470 1471 tlbiOp.broadcast(tc); 1472 return; 1473 } 1474 // AArch64 TLB Invalidate by VA, EL1 1475 case MISCREG_TLBI_VAE1_Xt: 1476 case MISCREG_TLBI_VALE1_Xt: 1477 { 1478 assert64(tc); 1479 scr = readMiscReg(MISCREG_SCR, tc); 1480 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1481 bits(newVal, 55, 48); 1482 1483 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1484 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1485 asid); 1486 1487 tlbiOp(tc); 1488 return; 1489 } 1490 // AArch64 TLB Invalidate by VA, EL1, Inner Shareable 1491 case MISCREG_TLBI_VAE1IS_Xt: 1492 case MISCREG_TLBI_VALE1IS_Xt: 1493 { 1494 assert64(tc); 1495 scr = readMiscReg(MISCREG_SCR, tc); 1496 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1497 bits(newVal, 55, 48); 1498 1499 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1500 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1501 asid); 1502 1503 tlbiOp.broadcast(tc); 1504 return; 1505 } 1506 // AArch64 TLB Invalidate by ASID, EL1 1507 // @todo: handle VMID to enable Virtualization 1508 case MISCREG_TLBI_ASIDE1_Xt: 1509 { 1510 assert64(tc); 1511 scr = readMiscReg(MISCREG_SCR, tc); 1512 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1513 bits(newVal, 55, 48); 1514 1515 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1516 tlbiOp(tc); 1517 return; 1518 } 1519 // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable 1520 case MISCREG_TLBI_ASIDE1IS_Xt: 1521 { 1522 assert64(tc); 1523 scr = readMiscReg(MISCREG_SCR, tc); 1524 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1525 bits(newVal, 55, 48); 1526 1527 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1528 tlbiOp.broadcast(tc); 1529 return; 1530 } 1531 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 1532 // entries from the last level of translation table walks 1533 // AArch64 TLB Invalidate by VA, All ASID, EL1 1534 case MISCREG_TLBI_VAAE1_Xt: 1535 case MISCREG_TLBI_VAALE1_Xt: 1536 { 1537 assert64(tc); 1538 scr = readMiscReg(MISCREG_SCR, tc); 1539 1540 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1541 static_cast<Addr>(bits(newVal, 43, 0)) << 12); 1542 1543 tlbiOp(tc); 1544 return; 1545 } 1546 // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable 1547 case MISCREG_TLBI_VAAE1IS_Xt: 1548 case MISCREG_TLBI_VAALE1IS_Xt: 1549 { 1550 assert64(tc); 1551 scr = readMiscReg(MISCREG_SCR, tc); 1552 1553 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1554 static_cast<Addr>(bits(newVal, 43, 0)) << 12); 1555 1556 tlbiOp.broadcast(tc); 1557 return; 1558 } 1559 // AArch64 TLB Invalidate by Intermediate Physical Address, 1560 // Stage 2, EL1 1561 case MISCREG_TLBI_IPAS2E1_Xt: 1562 case MISCREG_TLBI_IPAS2LE1_Xt: 1563 { 1564 assert64(tc); 1565 scr = readMiscReg(MISCREG_SCR, tc); 1566 1567 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1568 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1569 1570 tlbiOp(tc); 1571 return; 1572 } 1573 // AArch64 TLB Invalidate by Intermediate Physical Address, 1574 // Stage 2, EL1, Inner Shareable 1575 case MISCREG_TLBI_IPAS2E1IS_Xt: 1576 case MISCREG_TLBI_IPAS2LE1IS_Xt: 1577 { 1578 assert64(tc); 1579 scr = readMiscReg(MISCREG_SCR, tc); 1580 1581 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1582 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1583 1584 tlbiOp.broadcast(tc); 1585 return; 1586 } 1587 case MISCREG_ACTLR: 1588 warn("Not doing anything for write of miscreg ACTLR\n"); 1589 break; 1590 1591 case MISCREG_PMXEVTYPER_PMCCFILTR: 1592 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 1593 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 1594 case MISCREG_PMCR ... MISCREG_PMOVSSET: 1595 pmu->setMiscReg(misc_reg, newVal); 1596 break; 1597 1598 1599 case MISCREG_HSTR: // TJDBX, now redifined to be RES0 1600 { 1601 HSTR hstrMask = 0; 1602 hstrMask.tjdbx = 1; 1603 newVal &= ~((uint32_t) hstrMask); 1604 break; 1605 } 1606 case MISCREG_HCPTR: 1607 { 1608 // If a CP bit in NSACR is 0 then the corresponding bit in 1609 // HCPTR is RAO/WI. Same applies to NSASEDIS 1610 secure_lookup = haveSecurity && 1611 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 1612 readMiscRegNoEffect(MISCREG_CPSR)); 1613 if (!secure_lookup) { 1614 RegVal oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 1615 RegVal mask = 1616 (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 1617 newVal = (newVal & ~mask) | (oldValue & mask); 1618 } 1619 break; 1620 } 1621 case MISCREG_HDFAR: // alias for secure DFAR 1622 misc_reg = MISCREG_DFAR_S; 1623 break; 1624 case MISCREG_HIFAR: // alias for secure IFAR 1625 misc_reg = MISCREG_IFAR_S; 1626 break; 1627 case MISCREG_ATS1CPR: 1628 case MISCREG_ATS1CPW: 1629 case MISCREG_ATS1CUR: 1630 case MISCREG_ATS1CUW: 1631 case MISCREG_ATS12NSOPR: 1632 case MISCREG_ATS12NSOPW: 1633 case MISCREG_ATS12NSOUR: 1634 case MISCREG_ATS12NSOUW: 1635 case MISCREG_ATS1HR: 1636 case MISCREG_ATS1HW: 1637 { 1638 Request::Flags flags = 0; 1639 BaseTLB::Mode mode = BaseTLB::Read; 1640 TLB::ArmTranslationType tranType = TLB::NormalTran; 1641 Fault fault; 1642 switch(misc_reg) { 1643 case MISCREG_ATS1CPR: 1644 flags = TLB::MustBeOne; 1645 tranType = TLB::S1CTran; 1646 mode = BaseTLB::Read; 1647 break; 1648 case MISCREG_ATS1CPW: 1649 flags = TLB::MustBeOne; 1650 tranType = TLB::S1CTran; 1651 mode = BaseTLB::Write; 1652 break; 1653 case MISCREG_ATS1CUR: 1654 flags = TLB::MustBeOne | TLB::UserMode; 1655 tranType = TLB::S1CTran; 1656 mode = BaseTLB::Read; 1657 break; 1658 case MISCREG_ATS1CUW: 1659 flags = TLB::MustBeOne | TLB::UserMode; 1660 tranType = TLB::S1CTran; 1661 mode = BaseTLB::Write; 1662 break; 1663 case MISCREG_ATS12NSOPR: 1664 if (!haveSecurity) 1665 panic("Security Extensions required for ATS12NSOPR"); 1666 flags = TLB::MustBeOne; 1667 tranType = TLB::S1S2NsTran; 1668 mode = BaseTLB::Read; 1669 break; 1670 case MISCREG_ATS12NSOPW: 1671 if (!haveSecurity) 1672 panic("Security Extensions required for ATS12NSOPW"); 1673 flags = TLB::MustBeOne; 1674 tranType = TLB::S1S2NsTran; 1675 mode = BaseTLB::Write; 1676 break; 1677 case MISCREG_ATS12NSOUR: 1678 if (!haveSecurity) 1679 panic("Security Extensions required for ATS12NSOUR"); 1680 flags = TLB::MustBeOne | TLB::UserMode; 1681 tranType = TLB::S1S2NsTran; 1682 mode = BaseTLB::Read; 1683 break; 1684 case MISCREG_ATS12NSOUW: 1685 if (!haveSecurity) 1686 panic("Security Extensions required for ATS12NSOUW"); 1687 flags = TLB::MustBeOne | TLB::UserMode; 1688 tranType = TLB::S1S2NsTran; 1689 mode = BaseTLB::Write; 1690 break; 1691 case MISCREG_ATS1HR: // only really useful from secure mode. 1692 flags = TLB::MustBeOne; 1693 tranType = TLB::HypMode; 1694 mode = BaseTLB::Read; 1695 break; 1696 case MISCREG_ATS1HW: 1697 flags = TLB::MustBeOne; 1698 tranType = TLB::HypMode; 1699 mode = BaseTLB::Write; 1700 break; 1701 } 1702 // If we're in timing mode then doing the translation in 1703 // functional mode then we're slightly distorting performance 1704 // results obtained from simulations. The translation should be 1705 // done in the same mode the core is running in. NOTE: This 1706 // can't be an atomic translation because that causes problems 1707 // with unexpected atomic snoop requests. 1708 warn("Translating via %s in functional mode! Fix Me!\n", 1709 miscRegName[misc_reg]); 1710 1711 auto req = std::make_shared<Request>( 1712 0, val, 0, flags, Request::funcMasterId, 1713 tc->pcState().pc(), tc->contextId()); 1714 1715 fault = getDTBPtr(tc)->translateFunctional( 1716 req, tc, mode, tranType); 1717 1718 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1719 HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 1720 1721 RegVal newVal; 1722 if (fault == NoFault) { 1723 Addr paddr = req->getPaddr(); 1724 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 1725 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 1726 newVal = (paddr & mask(39, 12)) | 1727 (getDTBPtr(tc)->getAttr()); 1728 } else { 1729 newVal = (paddr & 0xfffff000) | 1730 (getDTBPtr(tc)->getAttr()); 1731 } 1732 DPRINTF(MiscRegs, 1733 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 1734 val, newVal); 1735 } else { 1736 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1737 armFault->update(tc); 1738 // Set fault bit and FSR 1739 FSR fsr = armFault->getFsr(tc); 1740 1741 newVal = ((fsr >> 9) & 1) << 11; 1742 if (newVal) { 1743 // LPAE - rearange fault status 1744 newVal |= ((fsr >> 0) & 0x3f) << 1; 1745 } else { 1746 // VMSA - rearange fault status 1747 newVal |= ((fsr >> 0) & 0xf) << 1; 1748 newVal |= ((fsr >> 10) & 0x1) << 5; 1749 newVal |= ((fsr >> 12) & 0x1) << 6; 1750 } 1751 newVal |= 0x1; // F bit 1752 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1753 newVal |= armFault->isStage2() ? 0x200 : 0; 1754 DPRINTF(MiscRegs, 1755 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 1756 val, fsr, newVal); 1757 } 1758 setMiscRegNoEffect(MISCREG_PAR, newVal); 1759 return; 1760 } 1761 case MISCREG_TTBCR: 1762 { 1763 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1764 const uint32_t ones = (uint32_t)(-1); 1765 TTBCR ttbcrMask = 0; 1766 TTBCR ttbcrNew = newVal; 1767 1768 // ARM DDI 0406C.b, ARMv7-32 1769 ttbcrMask.n = ones; // T0SZ 1770 if (haveSecurity) { 1771 ttbcrMask.pd0 = ones; 1772 ttbcrMask.pd1 = ones; 1773 } 1774 ttbcrMask.epd0 = ones; 1775 ttbcrMask.irgn0 = ones; 1776 ttbcrMask.orgn0 = ones; 1777 ttbcrMask.sh0 = ones; 1778 ttbcrMask.ps = ones; // T1SZ 1779 ttbcrMask.a1 = ones; 1780 ttbcrMask.epd1 = ones; 1781 ttbcrMask.irgn1 = ones; 1782 ttbcrMask.orgn1 = ones; 1783 ttbcrMask.sh1 = ones; 1784 if (haveLPAE) 1785 ttbcrMask.eae = ones; 1786 1787 if (haveLPAE && ttbcrNew.eae) { 1788 newVal = newVal & ttbcrMask; 1789 } else { 1790 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 1791 } 1792 // Invalidate TLB MiscReg 1793 getITBPtr(tc)->invalidateMiscReg(); 1794 getDTBPtr(tc)->invalidateMiscReg(); 1795 break; 1796 } 1797 case MISCREG_TTBR0: 1798 case MISCREG_TTBR1: 1799 { 1800 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1801 if (haveLPAE) { 1802 if (ttbcr.eae) { 1803 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 1804 // ARMv8 AArch32 bit 63-56 only 1805 uint64_t ttbrMask = mask(63,56) | mask(47,40); 1806 newVal = (newVal & (~ttbrMask)); 1807 } 1808 } 1809 // Invalidate TLB MiscReg 1810 getITBPtr(tc)->invalidateMiscReg(); 1811 getDTBPtr(tc)->invalidateMiscReg(); 1812 break; 1813 } 1814 case MISCREG_SCTLR_EL1: 1815 case MISCREG_CONTEXTIDR: 1816 case MISCREG_PRRR: 1817 case MISCREG_NMRR: 1818 case MISCREG_MAIR0: 1819 case MISCREG_MAIR1: 1820 case MISCREG_DACR: 1821 case MISCREG_VTTBR: 1822 case MISCREG_SCR_EL3: 1823 case MISCREG_HCR_EL2: 1824 case MISCREG_TCR_EL1: 1825 case MISCREG_TCR_EL2: 1826 case MISCREG_TCR_EL3: 1827 case MISCREG_SCTLR_EL2: 1828 case MISCREG_SCTLR_EL3: 1829 case MISCREG_HSCTLR: 1830 case MISCREG_TTBR0_EL1: 1831 case MISCREG_TTBR1_EL1: 1832 case MISCREG_TTBR0_EL2: 1833 case MISCREG_TTBR1_EL2: 1834 case MISCREG_TTBR0_EL3: 1835 getITBPtr(tc)->invalidateMiscReg(); 1836 getDTBPtr(tc)->invalidateMiscReg(); 1837 break; 1838 case MISCREG_NZCV: 1839 { 1840 CPSR cpsr = val; 1841 1842 tc->setCCReg(CCREG_NZ, cpsr.nz); 1843 tc->setCCReg(CCREG_C, cpsr.c); 1844 tc->setCCReg(CCREG_V, cpsr.v); 1845 } 1846 break; 1847 case MISCREG_DAIF: 1848 { 1849 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1850 cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 1851 newVal = cpsr; 1852 misc_reg = MISCREG_CPSR; 1853 } 1854 break; 1855 case MISCREG_SP_EL0: 1856 tc->setIntReg(INTREG_SP0, newVal); 1857 break; 1858 case MISCREG_SP_EL1: 1859 tc->setIntReg(INTREG_SP1, newVal); 1860 break; 1861 case MISCREG_SP_EL2: 1862 tc->setIntReg(INTREG_SP2, newVal); 1863 break; 1864 case MISCREG_SPSEL: 1865 { 1866 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1867 cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 1868 newVal = cpsr; 1869 misc_reg = MISCREG_CPSR; 1870 } 1871 break; 1872 case MISCREG_CURRENTEL: 1873 { 1874 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1875 cpsr.el = (uint8_t) ((CPSR) newVal).el; 1876 newVal = cpsr; 1877 misc_reg = MISCREG_CPSR; 1878 } 1879 break; 1880 case MISCREG_AT_S1E1R_Xt: 1881 case MISCREG_AT_S1E1W_Xt: 1882 case MISCREG_AT_S1E0R_Xt: 1883 case MISCREG_AT_S1E0W_Xt: 1884 case MISCREG_AT_S1E2R_Xt: 1885 case MISCREG_AT_S1E2W_Xt: 1886 case MISCREG_AT_S12E1R_Xt: 1887 case MISCREG_AT_S12E1W_Xt: 1888 case MISCREG_AT_S12E0R_Xt: 1889 case MISCREG_AT_S12E0W_Xt: 1890 case MISCREG_AT_S1E3R_Xt: 1891 case MISCREG_AT_S1E3W_Xt: 1892 { 1893 RequestPtr req = std::make_shared<Request>(); 1894 Request::Flags flags = 0; 1895 BaseTLB::Mode mode = BaseTLB::Read; 1896 TLB::ArmTranslationType tranType = TLB::NormalTran; 1897 Fault fault; 1898 switch(misc_reg) { 1899 case MISCREG_AT_S1E1R_Xt: 1900 flags = TLB::MustBeOne; 1901 tranType = TLB::S1E1Tran; 1902 mode = BaseTLB::Read; 1903 break; 1904 case MISCREG_AT_S1E1W_Xt: 1905 flags = TLB::MustBeOne; 1906 tranType = TLB::S1E1Tran; 1907 mode = BaseTLB::Write; 1908 break; 1909 case MISCREG_AT_S1E0R_Xt: 1910 flags = TLB::MustBeOne | TLB::UserMode; 1911 tranType = TLB::S1E0Tran; 1912 mode = BaseTLB::Read; 1913 break; 1914 case MISCREG_AT_S1E0W_Xt: 1915 flags = TLB::MustBeOne | TLB::UserMode; 1916 tranType = TLB::S1E0Tran; 1917 mode = BaseTLB::Write; 1918 break; 1919 case MISCREG_AT_S1E2R_Xt: 1920 flags = TLB::MustBeOne; 1921 tranType = TLB::S1E2Tran; 1922 mode = BaseTLB::Read; 1923 break; 1924 case MISCREG_AT_S1E2W_Xt: 1925 flags = TLB::MustBeOne; 1926 tranType = TLB::S1E2Tran; 1927 mode = BaseTLB::Write; 1928 break; 1929 case MISCREG_AT_S12E0R_Xt: 1930 flags = TLB::MustBeOne | TLB::UserMode; 1931 tranType = TLB::S12E0Tran; 1932 mode = BaseTLB::Read; 1933 break; 1934 case MISCREG_AT_S12E0W_Xt: 1935 flags = TLB::MustBeOne | TLB::UserMode; 1936 tranType = TLB::S12E0Tran; 1937 mode = BaseTLB::Write; 1938 break; 1939 case MISCREG_AT_S12E1R_Xt: 1940 flags = TLB::MustBeOne; 1941 tranType = TLB::S12E1Tran; 1942 mode = BaseTLB::Read; 1943 break; 1944 case MISCREG_AT_S12E1W_Xt: 1945 flags = TLB::MustBeOne; 1946 tranType = TLB::S12E1Tran; 1947 mode = BaseTLB::Write; 1948 break; 1949 case MISCREG_AT_S1E3R_Xt: 1950 flags = TLB::MustBeOne; 1951 tranType = TLB::S1E3Tran; 1952 mode = BaseTLB::Read; 1953 break; 1954 case MISCREG_AT_S1E3W_Xt: 1955 flags = TLB::MustBeOne; 1956 tranType = TLB::S1E3Tran; 1957 mode = BaseTLB::Write; 1958 break; 1959 } 1960 // If we're in timing mode then doing the translation in 1961 // functional mode then we're slightly distorting performance 1962 // results obtained from simulations. The translation should be 1963 // done in the same mode the core is running in. NOTE: This 1964 // can't be an atomic translation because that causes problems 1965 // with unexpected atomic snoop requests. 1966 warn("Translating via %s in functional mode! Fix Me!\n", 1967 miscRegName[misc_reg]); 1968 1969 req->setVirt(0, val, 0, flags, Request::funcMasterId, 1970 tc->pcState().pc()); 1971 req->setContext(tc->contextId()); 1972 fault = getDTBPtr(tc)->translateFunctional(req, tc, mode, 1973 tranType); 1974 1975 RegVal newVal; 1976 if (fault == NoFault) { 1977 Addr paddr = req->getPaddr(); 1978 uint64_t attr = getDTBPtr(tc)->getAttr(); 1979 uint64_t attr1 = attr >> 56; 1980 if (!attr1 || attr1 ==0x44) { 1981 attr |= 0x100; 1982 attr &= ~ uint64_t(0x80); 1983 } 1984 newVal = (paddr & mask(47, 12)) | attr; 1985 DPRINTF(MiscRegs, 1986 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 1987 val, newVal); 1988 } else { 1989 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1990 armFault->update(tc); 1991 // Set fault bit and FSR 1992 FSR fsr = armFault->getFsr(tc); 1993 1994 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1995 if (cpsr.width) { // AArch32 1996 newVal = ((fsr >> 9) & 1) << 11; 1997 // rearrange fault status 1998 newVal |= ((fsr >> 0) & 0x3f) << 1; 1999 newVal |= 0x1; // F bit 2000 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 2001 newVal |= armFault->isStage2() ? 0x200 : 0; 2002 } else { // AArch64 2003 newVal = 1; // F bit 2004 newVal |= fsr << 1; // FST 2005 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit. 2006 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 2007 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 2008 newVal |= 1 << 11; // RES1 2009 } 2010 DPRINTF(MiscRegs, 2011 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 2012 val, fsr, newVal); 2013 } 2014 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 2015 return; 2016 } 2017 case MISCREG_SPSR_EL3: 2018 case MISCREG_SPSR_EL2: 2019 case MISCREG_SPSR_EL1: 2020 // Force bits 23:21 to 0 2021 newVal = val & ~(0x7 << 21); 2022 break; 2023 case MISCREG_L2CTLR: 2024 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 2025 miscRegName[misc_reg], uint32_t(val)); 2026 break; 2027 2028 // Generic Timer registers 2029 case MISCREG_CNTHV_CTL_EL2: 2030 case MISCREG_CNTHV_CVAL_EL2: 2031 case MISCREG_CNTHV_TVAL_EL2: 2032 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 2033 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 2034 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 2035 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 2036 getGenericTimer(tc).setMiscReg(misc_reg, newVal); 2037 break; 2038 case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3: 2039 case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2: 2040 getGICv3CPUInterface(tc).setMiscReg(misc_reg, newVal); 2041 return; 2042 case MISCREG_ZCR_EL3: 2043 case MISCREG_ZCR_EL2: 2044 case MISCREG_ZCR_EL1: 2045 tc->getDecoderPtr()->setSveLen( 2046 (getCurSveVecLenInBits(tc) >> 7) - 1); 2047 break; 2048 } 2049 } 2050 setMiscRegNoEffect(misc_reg, newVal); 2051} 2052 2053BaseISADevice & 2054ISA::getGenericTimer(ThreadContext *tc) 2055{ 2056 // We only need to create an ISA interface the first time we try 2057 // to access the timer. 2058 if (timer) 2059 return *timer.get(); 2060 2061 assert(system); 2062 GenericTimer *generic_timer(system->getGenericTimer()); 2063 if (!generic_timer) { 2064 panic("Trying to get a generic timer from a system that hasn't " 2065 "been configured to use a generic timer.\n"); 2066 } 2067 2068 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 2069 timer->setThreadContext(tc); 2070 2071 return *timer.get(); 2072} 2073 2074BaseISADevice & 2075ISA::getGICv3CPUInterface(ThreadContext *tc) 2076{ 2077 panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!"); 2078 return *gicv3CpuInterface.get(); 2079} 2080 2081unsigned 2082ISA::getCurSveVecLenInBits(ThreadContext *tc) const 2083{ 2084 if (!FullSystem) { 2085 return sveVL * 128; 2086 } 2087 2088 panic_if(!tc, 2089 "A ThreadContext is needed to determine the SVE vector length " 2090 "in full-system mode"); 2091 2092 CPSR cpsr = miscRegs[MISCREG_CPSR]; 2093 ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el; 2094 2095 unsigned len = 0; 2096 2097 if (el == EL1 || (el == EL0 && !ELIsInHost(tc, el))) { 2098 len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL1]).len; 2099 } 2100 2101 if (el == EL2 || (el == EL0 && ELIsInHost(tc, el))) { 2102 len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL2]).len; 2103 } else if (haveVirtualization && !inSecureState(tc) && 2104 (el == EL0 || el == EL1)) { 2105 len = std::min( 2106 len, 2107 static_cast<unsigned>( 2108 static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL2]).len)); 2109 } 2110 2111 if (el == EL3) { 2112 len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL3]).len; 2113 } else if (haveSecurity) { 2114 len = std::min( 2115 len, 2116 static_cast<unsigned>( 2117 static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL3]).len)); 2118 } 2119 2120 len = std::min(len, sveVL - 1); 2121 2122 return (len + 1) * 128; 2123} 2124 2125void 2126ISA::zeroSveVecRegUpperPart(VecRegContainer &vc, unsigned eCount) 2127{ 2128 auto vv = vc.as<uint64_t>(); 2129 for (int i = 2; i < eCount; ++i) { 2130 vv[i] = 0; 2131 } 2132} 2133 2134} // namespace ArmISA 2135 2136ArmISA::ISA * 2137ArmISAParams::create() 2138{ 2139 return new ArmISA::ISA(this); 2140} 2141