isa.cc revision 13691
1/* 2 * Copyright (c) 2010-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 */ 40 41#include "arch/arm/isa.hh" 42#include "arch/arm/pmu.hh" 43#include "arch/arm/system.hh" 44#include "arch/arm/tlb.hh" 45#include "arch/arm/tlbi_op.hh" 46#include "cpu/base.hh" 47#include "cpu/checker/cpu.hh" 48#include "debug/Arm.hh" 49#include "debug/MiscRegs.hh" 50#include "dev/arm/generic_timer.hh" 51#include "dev/arm/gic_v3.hh" 52#include "dev/arm/gic_v3_cpu_interface.hh" 53#include "params/ArmISA.hh" 54#include "sim/faults.hh" 55#include "sim/stat_control.hh" 56#include "sim/system.hh" 57 58namespace ArmISA 59{ 60 61ISA::ISA(Params *p) 62 : SimObject(p), 63 system(NULL), 64 _decoderFlavour(p->decoderFlavour), 65 _vecRegRenameMode(Enums::Full), 66 pmu(p->pmu), 67 haveGICv3CPUInterface(false), 68 impdefAsNop(p->impdef_nop) 69{ 70 miscRegs[MISCREG_SCTLR_RST] = 0; 71 72 // Hook up a dummy device if we haven't been configured with a 73 // real PMU. By using a dummy device, we don't need to check that 74 // the PMU exist every time we try to access a PMU register. 75 if (!pmu) 76 pmu = &dummyDevice; 77 78 // Give all ISA devices a pointer to this ISA 79 pmu->setISA(this); 80 81 system = dynamic_cast<ArmSystem *>(p->system); 82 83 // Cache system-level properties 84 if (FullSystem && system) { 85 highestELIs64 = system->highestELIs64(); 86 haveSecurity = system->haveSecurity(); 87 haveLPAE = system->haveLPAE(); 88 haveCrypto = system->haveCrypto(); 89 haveVirtualization = system->haveVirtualization(); 90 haveLargeAsid64 = system->haveLargeAsid64(); 91 physAddrRange = system->physAddrRange(); 92 } else { 93 highestELIs64 = true; // ArmSystem::highestELIs64 does the same 94 haveSecurity = haveLPAE = haveVirtualization = false; 95 haveCrypto = true; 96 haveLargeAsid64 = false; 97 physAddrRange = 32; // dummy value 98 } 99 100 // Initial rename mode depends on highestEL 101 const_cast<Enums::VecRegRenameMode&>(_vecRegRenameMode) = 102 highestELIs64 ? Enums::Full : Enums::Elem; 103 104 initializeMiscRegMetadata(); 105 preUnflattenMiscReg(); 106 107 clear(); 108} 109 110std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS); 111 112const ArmISAParams * 113ISA::params() const 114{ 115 return dynamic_cast<const Params *>(_params); 116} 117 118void 119ISA::clear() 120{ 121 const Params *p(params()); 122 123 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 124 memset(miscRegs, 0, sizeof(miscRegs)); 125 126 initID32(p); 127 128 // We always initialize AArch64 ID registers even 129 // if we are in AArch32. This is done since if we 130 // are in SE mode we don't know if our ArmProcess is 131 // AArch32 or AArch64 132 initID64(p); 133 134 // Start with an event in the mailbox 135 miscRegs[MISCREG_SEV_MAILBOX] = 1; 136 137 // Separate Instruction and Data TLBs 138 miscRegs[MISCREG_TLBTR] = 1; 139 140 MVFR0 mvfr0 = 0; 141 mvfr0.advSimdRegisters = 2; 142 mvfr0.singlePrecision = 2; 143 mvfr0.doublePrecision = 2; 144 mvfr0.vfpExceptionTrapping = 0; 145 mvfr0.divide = 1; 146 mvfr0.squareRoot = 1; 147 mvfr0.shortVectors = 1; 148 mvfr0.roundingModes = 1; 149 miscRegs[MISCREG_MVFR0] = mvfr0; 150 151 MVFR1 mvfr1 = 0; 152 mvfr1.flushToZero = 1; 153 mvfr1.defaultNaN = 1; 154 mvfr1.advSimdLoadStore = 1; 155 mvfr1.advSimdInteger = 1; 156 mvfr1.advSimdSinglePrecision = 1; 157 mvfr1.advSimdHalfPrecision = 1; 158 mvfr1.vfpHalfPrecision = 1; 159 miscRegs[MISCREG_MVFR1] = mvfr1; 160 161 // Reset values of PRRR and NMRR are implementation dependent 162 163 // @todo: PRRR and NMRR in secure state? 164 miscRegs[MISCREG_PRRR_NS] = 165 (1 << 19) | // 19 166 (0 << 18) | // 18 167 (0 << 17) | // 17 168 (1 << 16) | // 16 169 (2 << 14) | // 15:14 170 (0 << 12) | // 13:12 171 (2 << 10) | // 11:10 172 (2 << 8) | // 9:8 173 (2 << 6) | // 7:6 174 (2 << 4) | // 5:4 175 (1 << 2) | // 3:2 176 0; // 1:0 177 178 miscRegs[MISCREG_NMRR_NS] = 179 (1 << 30) | // 31:30 180 (0 << 26) | // 27:26 181 (0 << 24) | // 25:24 182 (3 << 22) | // 23:22 183 (2 << 20) | // 21:20 184 (0 << 18) | // 19:18 185 (0 << 16) | // 17:16 186 (1 << 14) | // 15:14 187 (0 << 12) | // 13:12 188 (2 << 10) | // 11:10 189 (0 << 8) | // 9:8 190 (3 << 6) | // 7:6 191 (2 << 4) | // 5:4 192 (0 << 2) | // 3:2 193 0; // 1:0 194 195 if (FullSystem && system->highestELIs64()) { 196 // Initialize AArch64 state 197 clear64(p); 198 return; 199 } 200 201 // Initialize AArch32 state... 202 clear32(p, sctlr_rst); 203} 204 205void 206ISA::clear32(const ArmISAParams *p, const SCTLR &sctlr_rst) 207{ 208 CPSR cpsr = 0; 209 cpsr.mode = MODE_USER; 210 211 if (FullSystem) { 212 miscRegs[MISCREG_MVBAR] = system->resetAddr(); 213 } 214 215 miscRegs[MISCREG_CPSR] = cpsr; 216 updateRegMap(cpsr); 217 218 SCTLR sctlr = 0; 219 sctlr.te = (bool) sctlr_rst.te; 220 sctlr.nmfi = (bool) sctlr_rst.nmfi; 221 sctlr.v = (bool) sctlr_rst.v; 222 sctlr.u = 1; 223 sctlr.xp = 1; 224 sctlr.rao2 = 1; 225 sctlr.rao3 = 1; 226 sctlr.rao4 = 0xf; // SCTLR[6:3] 227 sctlr.uci = 1; 228 sctlr.dze = 1; 229 miscRegs[MISCREG_SCTLR_NS] = sctlr; 230 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 231 miscRegs[MISCREG_HCPTR] = 0; 232 233 miscRegs[MISCREG_CPACR] = 0; 234 235 miscRegs[MISCREG_FPSID] = p->fpsid; 236 237 if (haveLPAE) { 238 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 239 ttbcr.eae = 0; 240 miscRegs[MISCREG_TTBCR_NS] = ttbcr; 241 // Enforce consistency with system-level settings 242 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 243 } 244 245 if (haveSecurity) { 246 miscRegs[MISCREG_SCTLR_S] = sctlr; 247 miscRegs[MISCREG_SCR] = 0; 248 miscRegs[MISCREG_VBAR_S] = 0; 249 } else { 250 // we're always non-secure 251 miscRegs[MISCREG_SCR] = 1; 252 } 253 254 //XXX We need to initialize the rest of the state. 255} 256 257void 258ISA::clear64(const ArmISAParams *p) 259{ 260 CPSR cpsr = 0; 261 Addr rvbar = system->resetAddr(); 262 switch (system->highestEL()) { 263 // Set initial EL to highest implemented EL using associated stack 264 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 265 // value 266 case EL3: 267 cpsr.mode = MODE_EL3H; 268 miscRegs[MISCREG_RVBAR_EL3] = rvbar; 269 break; 270 case EL2: 271 cpsr.mode = MODE_EL2H; 272 miscRegs[MISCREG_RVBAR_EL2] = rvbar; 273 break; 274 case EL1: 275 cpsr.mode = MODE_EL1H; 276 miscRegs[MISCREG_RVBAR_EL1] = rvbar; 277 break; 278 default: 279 panic("Invalid highest implemented exception level"); 280 break; 281 } 282 283 // Initialize rest of CPSR 284 cpsr.daif = 0xf; // Mask all interrupts 285 cpsr.ss = 0; 286 cpsr.il = 0; 287 miscRegs[MISCREG_CPSR] = cpsr; 288 updateRegMap(cpsr); 289 290 // Initialize other control registers 291 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 292 if (haveSecurity) { 293 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830; 294 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 295 } else if (haveVirtualization) { 296 // also MISCREG_SCTLR_EL2 (by mapping) 297 miscRegs[MISCREG_HSCTLR] = 0x30c50830; 298 } else { 299 // also MISCREG_SCTLR_EL1 (by mapping) 300 miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init 301 // Always non-secure 302 miscRegs[MISCREG_SCR_EL3] = 1; 303 } 304} 305 306void 307ISA::initID32(const ArmISAParams *p) 308{ 309 // Initialize configurable default values 310 miscRegs[MISCREG_MIDR] = p->midr; 311 miscRegs[MISCREG_MIDR_EL1] = p->midr; 312 miscRegs[MISCREG_VPIDR] = p->midr; 313 314 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 315 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 316 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 317 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 318 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 319 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 320 321 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 322 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 323 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 324 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 325 326 miscRegs[MISCREG_ID_ISAR5] = insertBits( 327 miscRegs[MISCREG_ID_ISAR5], 19, 4, 328 haveCrypto ? 0x1112 : 0x0); 329} 330 331void 332ISA::initID64(const ArmISAParams *p) 333{ 334 // Initialize configurable id registers 335 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 336 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 337 miscRegs[MISCREG_ID_AA64DFR0_EL1] = 338 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 339 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 340 341 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 342 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 343 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 344 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 345 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 346 miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p->id_aa64mmfr2_el1; 347 348 miscRegs[MISCREG_ID_DFR0_EL1] = 349 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 350 351 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 352 353 // Enforce consistency with system-level settings... 354 355 // EL3 356 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 357 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 358 haveSecurity ? 0x2 : 0x0); 359 // EL2 360 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 361 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 362 haveVirtualization ? 0x2 : 0x0); 363 // Large ASID support 364 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 365 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 366 haveLargeAsid64 ? 0x2 : 0x0); 367 // Physical address size 368 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 369 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 370 encodePhysAddrRange64(physAddrRange)); 371 // Crypto 372 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits( 373 miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4, 374 haveCrypto ? 0x1112 : 0x0); 375} 376 377void 378ISA::startup(ThreadContext *tc) 379{ 380 pmu->setThreadContext(tc); 381 382 if (system) { 383 Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC()); 384 if (gicv3) { 385 haveGICv3CPUInterface = true; 386 gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId())); 387 gicv3CpuInterface->setISA(this); 388 } 389 } 390} 391 392 393RegVal 394ISA::readMiscRegNoEffect(int misc_reg) const 395{ 396 assert(misc_reg < NumMiscRegs); 397 398 const auto ® = lookUpMiscReg[misc_reg]; // bit masks 399 const auto &map = getMiscIndices(misc_reg); 400 int lower = map.first, upper = map.second; 401 // NB!: apply architectural masks according to desired register, 402 // despite possibly getting value from different (mapped) register. 403 auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32)) 404 |(miscRegs[upper] << 32)); 405 if (val & reg.res0()) { 406 DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n", 407 miscRegName[misc_reg], val & reg.res0()); 408 } 409 if ((val & reg.res1()) != reg.res1()) { 410 DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n", 411 miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1()); 412 } 413 return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao 414} 415 416 417RegVal 418ISA::readMiscReg(int misc_reg, ThreadContext *tc) 419{ 420 CPSR cpsr = 0; 421 PCState pc = 0; 422 SCR scr = 0; 423 424 if (misc_reg == MISCREG_CPSR) { 425 cpsr = miscRegs[misc_reg]; 426 pc = tc->pcState(); 427 cpsr.j = pc.jazelle() ? 1 : 0; 428 cpsr.t = pc.thumb() ? 1 : 0; 429 return cpsr; 430 } 431 432#ifndef NDEBUG 433 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 434 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 435 warn("Unimplemented system register %s read.\n", 436 miscRegName[misc_reg]); 437 else 438 panic("Unimplemented system register %s read.\n", 439 miscRegName[misc_reg]); 440 } 441#endif 442 443 switch (unflattenMiscReg(misc_reg)) { 444 case MISCREG_HCR: 445 { 446 if (!haveVirtualization) 447 return 0; 448 else 449 return readMiscRegNoEffect(MISCREG_HCR); 450 } 451 case MISCREG_CPACR: 452 { 453 const uint32_t ones = (uint32_t)(-1); 454 CPACR cpacrMask = 0; 455 // Only cp10, cp11, and ase are implemented, nothing else should 456 // be readable? (straight copy from the write code) 457 cpacrMask.cp10 = ones; 458 cpacrMask.cp11 = ones; 459 cpacrMask.asedis = ones; 460 461 // Security Extensions may limit the readability of CPACR 462 if (haveSecurity) { 463 scr = readMiscRegNoEffect(MISCREG_SCR); 464 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 465 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 466 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 467 // NB: Skipping the full loop, here 468 if (!nsacr.cp10) cpacrMask.cp10 = 0; 469 if (!nsacr.cp11) cpacrMask.cp11 = 0; 470 } 471 } 472 RegVal val = readMiscRegNoEffect(MISCREG_CPACR); 473 val &= cpacrMask; 474 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 475 miscRegName[misc_reg], val); 476 return val; 477 } 478 case MISCREG_MPIDR: 479 case MISCREG_MPIDR_EL1: 480 return readMPIDR(system, tc); 481 case MISCREG_VMPIDR: 482 case MISCREG_VMPIDR_EL2: 483 // top bit defined as RES1 484 return readMiscRegNoEffect(misc_reg) | 0x80000000; 485 case MISCREG_ID_AFR0: // not implemented, so alias MIDR 486 case MISCREG_REVIDR: // not implemented, so alias MIDR 487 case MISCREG_MIDR: 488 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 489 scr = readMiscRegNoEffect(MISCREG_SCR); 490 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 491 return readMiscRegNoEffect(misc_reg); 492 } else { 493 return readMiscRegNoEffect(MISCREG_VPIDR); 494 } 495 break; 496 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 497 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 498 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 499 case MISCREG_AIDR: // AUX ID set to 0 500 case MISCREG_TCMTR: // No TCM's 501 return 0; 502 503 case MISCREG_CLIDR: 504 warn_once("The clidr register always reports 0 caches.\n"); 505 warn_once("clidr LoUIS field of 0b001 to match current " 506 "ARM implementations.\n"); 507 return 0x00200000; 508 case MISCREG_CCSIDR: 509 warn_once("The ccsidr register isn't implemented and " 510 "always reads as 0.\n"); 511 break; 512 case MISCREG_CTR: // AArch32, ARMv7, top bit set 513 case MISCREG_CTR_EL0: // AArch64 514 { 515 //all caches have the same line size in gem5 516 //4 byte words in ARM 517 unsigned lineSizeWords = 518 tc->getSystemPtr()->cacheLineSize() / 4; 519 unsigned log2LineSizeWords = 0; 520 521 while (lineSizeWords >>= 1) { 522 ++log2LineSizeWords; 523 } 524 525 CTR ctr = 0; 526 //log2 of minimun i-cache line size (words) 527 ctr.iCacheLineSize = log2LineSizeWords; 528 //b11 - gem5 uses pipt 529 ctr.l1IndexPolicy = 0x3; 530 //log2 of minimum d-cache line size (words) 531 ctr.dCacheLineSize = log2LineSizeWords; 532 //log2 of max reservation size (words) 533 ctr.erg = log2LineSizeWords; 534 //log2 of max writeback size (words) 535 ctr.cwg = log2LineSizeWords; 536 //b100 - gem5 format is ARMv7 537 ctr.format = 0x4; 538 539 return ctr; 540 } 541 case MISCREG_ACTLR: 542 warn("Not doing anything for miscreg ACTLR\n"); 543 break; 544 545 case MISCREG_PMXEVTYPER_PMCCFILTR: 546 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 547 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 548 case MISCREG_PMCR ... MISCREG_PMOVSSET: 549 return pmu->readMiscReg(misc_reg); 550 551 case MISCREG_CPSR_Q: 552 panic("shouldn't be reading this register seperately\n"); 553 case MISCREG_FPSCR_QC: 554 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 555 case MISCREG_FPSCR_EXC: 556 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 557 case MISCREG_FPSR: 558 { 559 const uint32_t ones = (uint32_t)(-1); 560 FPSCR fpscrMask = 0; 561 fpscrMask.ioc = ones; 562 fpscrMask.dzc = ones; 563 fpscrMask.ofc = ones; 564 fpscrMask.ufc = ones; 565 fpscrMask.ixc = ones; 566 fpscrMask.idc = ones; 567 fpscrMask.qc = ones; 568 fpscrMask.v = ones; 569 fpscrMask.c = ones; 570 fpscrMask.z = ones; 571 fpscrMask.n = ones; 572 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 573 } 574 case MISCREG_FPCR: 575 { 576 const uint32_t ones = (uint32_t)(-1); 577 FPSCR fpscrMask = 0; 578 fpscrMask.len = ones; 579 fpscrMask.stride = ones; 580 fpscrMask.rMode = ones; 581 fpscrMask.fz = ones; 582 fpscrMask.dn = ones; 583 fpscrMask.ahp = ones; 584 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 585 } 586 case MISCREG_NZCV: 587 { 588 CPSR cpsr = 0; 589 cpsr.nz = tc->readCCReg(CCREG_NZ); 590 cpsr.c = tc->readCCReg(CCREG_C); 591 cpsr.v = tc->readCCReg(CCREG_V); 592 return cpsr; 593 } 594 case MISCREG_DAIF: 595 { 596 CPSR cpsr = 0; 597 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 598 return cpsr; 599 } 600 case MISCREG_SP_EL0: 601 { 602 return tc->readIntReg(INTREG_SP0); 603 } 604 case MISCREG_SP_EL1: 605 { 606 return tc->readIntReg(INTREG_SP1); 607 } 608 case MISCREG_SP_EL2: 609 { 610 return tc->readIntReg(INTREG_SP2); 611 } 612 case MISCREG_SPSEL: 613 { 614 return miscRegs[MISCREG_CPSR] & 0x1; 615 } 616 case MISCREG_CURRENTEL: 617 { 618 return miscRegs[MISCREG_CPSR] & 0xc; 619 } 620 case MISCREG_L2CTLR: 621 { 622 // mostly unimplemented, just set NumCPUs field from sim and return 623 L2CTLR l2ctlr = 0; 624 // b00:1CPU to b11:4CPUs 625 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 626 return l2ctlr; 627 } 628 case MISCREG_DBGDIDR: 629 /* For now just implement the version number. 630 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 631 */ 632 return 0x5 << 16; 633 case MISCREG_DBGDSCRint: 634 return 0; 635 case MISCREG_ISR: 636 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 637 readMiscRegNoEffect(MISCREG_HCR), 638 readMiscRegNoEffect(MISCREG_CPSR), 639 readMiscRegNoEffect(MISCREG_SCR)); 640 case MISCREG_ISR_EL1: 641 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 642 readMiscRegNoEffect(MISCREG_HCR_EL2), 643 readMiscRegNoEffect(MISCREG_CPSR), 644 readMiscRegNoEffect(MISCREG_SCR_EL3)); 645 case MISCREG_DCZID_EL0: 646 return 0x04; // DC ZVA clear 64-byte chunks 647 case MISCREG_HCPTR: 648 { 649 RegVal val = readMiscRegNoEffect(misc_reg); 650 // The trap bit associated with CP14 is defined as RAZ 651 val &= ~(1 << 14); 652 // If a CP bit in NSACR is 0 then the corresponding bit in 653 // HCPTR is RAO/WI 654 bool secure_lookup = haveSecurity && 655 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 656 readMiscRegNoEffect(MISCREG_CPSR)); 657 if (!secure_lookup) { 658 RegVal mask = readMiscRegNoEffect(MISCREG_NSACR); 659 val |= (mask ^ 0x7FFF) & 0xBFFF; 660 } 661 // Set the bits for unimplemented coprocessors to RAO/WI 662 val |= 0x33FF; 663 return (val); 664 } 665 case MISCREG_HDFAR: // alias for secure DFAR 666 return readMiscRegNoEffect(MISCREG_DFAR_S); 667 case MISCREG_HIFAR: // alias for secure IFAR 668 return readMiscRegNoEffect(MISCREG_IFAR_S); 669 670 case MISCREG_ID_PFR0: 671 // !ThumbEE | !Jazelle | Thumb | ARM 672 return 0x00000031; 673 case MISCREG_ID_PFR1: 674 { // Timer | Virti | !M Profile | TrustZone | ARMv4 675 bool haveTimer = (system->getGenericTimer() != NULL); 676 return 0x00000001 677 | (haveSecurity ? 0x00000010 : 0x0) 678 | (haveVirtualization ? 0x00001000 : 0x0) 679 | (haveTimer ? 0x00010000 : 0x0); 680 } 681 case MISCREG_ID_AA64PFR0_EL1: 682 return 0x0000000000000002 | // AArch{64,32} supported at EL0 683 0x0000000000000020 | // EL1 684 (haveVirtualization ? 0x0000000000000200 : 0) | // EL2 685 (haveSecurity ? 0x0000000000002000 : 0) | // EL3 686 (haveGICv3CPUInterface ? 0x0000000001000000 : 0); 687 case MISCREG_ID_AA64PFR1_EL1: 688 return 0; // bits [63:0] RES0 (reserved for future use) 689 690 // Generic Timer registers 691 case MISCREG_CNTHV_CTL_EL2: 692 case MISCREG_CNTHV_CVAL_EL2: 693 case MISCREG_CNTHV_TVAL_EL2: 694 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 695 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 696 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 697 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 698 return getGenericTimer(tc).readMiscReg(misc_reg); 699 700 case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3: 701 case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2: 702 return getGICv3CPUInterface(tc).readMiscReg(misc_reg); 703 704 default: 705 break; 706 707 } 708 return readMiscRegNoEffect(misc_reg); 709} 710 711void 712ISA::setMiscRegNoEffect(int misc_reg, RegVal val) 713{ 714 assert(misc_reg < NumMiscRegs); 715 716 const auto ® = lookUpMiscReg[misc_reg]; // bit masks 717 const auto &map = getMiscIndices(misc_reg); 718 int lower = map.first, upper = map.second; 719 720 auto v = (val & ~reg.wi()) | reg.rao(); 721 if (upper > 0) { 722 miscRegs[lower] = bits(v, 31, 0); 723 miscRegs[upper] = bits(v, 63, 32); 724 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 725 misc_reg, lower, upper, v); 726 } else { 727 miscRegs[lower] = v; 728 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 729 misc_reg, lower, v); 730 } 731} 732 733void 734ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) 735{ 736 737 RegVal newVal = val; 738 bool secure_lookup; 739 SCR scr; 740 741 if (misc_reg == MISCREG_CPSR) { 742 updateRegMap(val); 743 744 745 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 746 int old_mode = old_cpsr.mode; 747 CPSR cpsr = val; 748 if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) { 749 getITBPtr(tc)->invalidateMiscReg(); 750 getDTBPtr(tc)->invalidateMiscReg(); 751 } 752 753 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 754 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 755 PCState pc = tc->pcState(); 756 pc.nextThumb(cpsr.t); 757 pc.nextJazelle(cpsr.j); 758 pc.illegalExec(cpsr.il == 1); 759 760 // Follow slightly different semantics if a CheckerCPU object 761 // is connected 762 CheckerCPU *checker = tc->getCheckerCpuPtr(); 763 if (checker) { 764 tc->pcStateNoRecord(pc); 765 } else { 766 tc->pcState(pc); 767 } 768 } else { 769#ifndef NDEBUG 770 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 771 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 772 warn("Unimplemented system register %s write with %#x.\n", 773 miscRegName[misc_reg], val); 774 else 775 panic("Unimplemented system register %s write with %#x.\n", 776 miscRegName[misc_reg], val); 777 } 778#endif 779 switch (unflattenMiscReg(misc_reg)) { 780 case MISCREG_CPACR: 781 { 782 783 const uint32_t ones = (uint32_t)(-1); 784 CPACR cpacrMask = 0; 785 // Only cp10, cp11, and ase are implemented, nothing else should 786 // be writable 787 cpacrMask.cp10 = ones; 788 cpacrMask.cp11 = ones; 789 cpacrMask.asedis = ones; 790 791 // Security Extensions may limit the writability of CPACR 792 if (haveSecurity) { 793 scr = readMiscRegNoEffect(MISCREG_SCR); 794 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 795 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 796 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 797 // NB: Skipping the full loop, here 798 if (!nsacr.cp10) cpacrMask.cp10 = 0; 799 if (!nsacr.cp11) cpacrMask.cp11 = 0; 800 } 801 } 802 803 RegVal old_val = readMiscRegNoEffect(MISCREG_CPACR); 804 newVal &= cpacrMask; 805 newVal |= old_val & ~cpacrMask; 806 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 807 miscRegName[misc_reg], newVal); 808 } 809 break; 810 case MISCREG_CPTR_EL2: 811 { 812 const uint32_t ones = (uint32_t)(-1); 813 CPTR cptrMask = 0; 814 cptrMask.tcpac = ones; 815 cptrMask.tta = ones; 816 cptrMask.tfp = ones; 817 newVal &= cptrMask; 818 cptrMask = 0; 819 cptrMask.res1_13_12_el2 = ones; 820 cptrMask.res1_9_0_el2 = ones; 821 newVal |= cptrMask; 822 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 823 miscRegName[misc_reg], newVal); 824 } 825 break; 826 case MISCREG_CPTR_EL3: 827 { 828 const uint32_t ones = (uint32_t)(-1); 829 CPTR cptrMask = 0; 830 cptrMask.tcpac = ones; 831 cptrMask.tta = ones; 832 cptrMask.tfp = ones; 833 newVal &= cptrMask; 834 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 835 miscRegName[misc_reg], newVal); 836 } 837 break; 838 case MISCREG_CSSELR: 839 warn_once("The csselr register isn't implemented.\n"); 840 return; 841 842 case MISCREG_DC_ZVA_Xt: 843 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 844 return; 845 846 case MISCREG_FPSCR: 847 { 848 const uint32_t ones = (uint32_t)(-1); 849 FPSCR fpscrMask = 0; 850 fpscrMask.ioc = ones; 851 fpscrMask.dzc = ones; 852 fpscrMask.ofc = ones; 853 fpscrMask.ufc = ones; 854 fpscrMask.ixc = ones; 855 fpscrMask.idc = ones; 856 fpscrMask.ioe = ones; 857 fpscrMask.dze = ones; 858 fpscrMask.ofe = ones; 859 fpscrMask.ufe = ones; 860 fpscrMask.ixe = ones; 861 fpscrMask.ide = ones; 862 fpscrMask.len = ones; 863 fpscrMask.stride = ones; 864 fpscrMask.rMode = ones; 865 fpscrMask.fz = ones; 866 fpscrMask.dn = ones; 867 fpscrMask.ahp = ones; 868 fpscrMask.qc = ones; 869 fpscrMask.v = ones; 870 fpscrMask.c = ones; 871 fpscrMask.z = ones; 872 fpscrMask.n = ones; 873 newVal = (newVal & (uint32_t)fpscrMask) | 874 (readMiscRegNoEffect(MISCREG_FPSCR) & 875 ~(uint32_t)fpscrMask); 876 tc->getDecoderPtr()->setContext(newVal); 877 } 878 break; 879 case MISCREG_FPSR: 880 { 881 const uint32_t ones = (uint32_t)(-1); 882 FPSCR fpscrMask = 0; 883 fpscrMask.ioc = ones; 884 fpscrMask.dzc = ones; 885 fpscrMask.ofc = ones; 886 fpscrMask.ufc = ones; 887 fpscrMask.ixc = ones; 888 fpscrMask.idc = ones; 889 fpscrMask.qc = ones; 890 fpscrMask.v = ones; 891 fpscrMask.c = ones; 892 fpscrMask.z = ones; 893 fpscrMask.n = ones; 894 newVal = (newVal & (uint32_t)fpscrMask) | 895 (readMiscRegNoEffect(MISCREG_FPSCR) & 896 ~(uint32_t)fpscrMask); 897 misc_reg = MISCREG_FPSCR; 898 } 899 break; 900 case MISCREG_FPCR: 901 { 902 const uint32_t ones = (uint32_t)(-1); 903 FPSCR fpscrMask = 0; 904 fpscrMask.len = ones; 905 fpscrMask.stride = ones; 906 fpscrMask.rMode = ones; 907 fpscrMask.fz = ones; 908 fpscrMask.dn = ones; 909 fpscrMask.ahp = ones; 910 newVal = (newVal & (uint32_t)fpscrMask) | 911 (readMiscRegNoEffect(MISCREG_FPSCR) & 912 ~(uint32_t)fpscrMask); 913 misc_reg = MISCREG_FPSCR; 914 } 915 break; 916 case MISCREG_CPSR_Q: 917 { 918 assert(!(newVal & ~CpsrMaskQ)); 919 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 920 misc_reg = MISCREG_CPSR; 921 } 922 break; 923 case MISCREG_FPSCR_QC: 924 { 925 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 926 (newVal & FpscrQcMask); 927 misc_reg = MISCREG_FPSCR; 928 } 929 break; 930 case MISCREG_FPSCR_EXC: 931 { 932 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 933 (newVal & FpscrExcMask); 934 misc_reg = MISCREG_FPSCR; 935 } 936 break; 937 case MISCREG_FPEXC: 938 { 939 // vfpv3 architecture, section B.6.1 of DDI04068 940 // bit 29 - valid only if fpexc[31] is 0 941 const uint32_t fpexcMask = 0x60000000; 942 newVal = (newVal & fpexcMask) | 943 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 944 } 945 break; 946 case MISCREG_HCR: 947 { 948 if (!haveVirtualization) 949 return; 950 } 951 break; 952 case MISCREG_IFSR: 953 { 954 // ARM ARM (ARM DDI 0406C.b) B4.1.96 955 const uint32_t ifsrMask = 956 mask(31, 13) | mask(11, 11) | mask(8, 6); 957 newVal = newVal & ~ifsrMask; 958 } 959 break; 960 case MISCREG_DFSR: 961 { 962 // ARM ARM (ARM DDI 0406C.b) B4.1.52 963 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 964 newVal = newVal & ~dfsrMask; 965 } 966 break; 967 case MISCREG_AMAIR0: 968 case MISCREG_AMAIR1: 969 { 970 // ARM ARM (ARM DDI 0406C.b) B4.1.5 971 // Valid only with LPAE 972 if (!haveLPAE) 973 return; 974 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 975 } 976 break; 977 case MISCREG_SCR: 978 getITBPtr(tc)->invalidateMiscReg(); 979 getDTBPtr(tc)->invalidateMiscReg(); 980 break; 981 case MISCREG_SCTLR: 982 { 983 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 984 scr = readMiscRegNoEffect(MISCREG_SCR); 985 986 MiscRegIndex sctlr_idx; 987 if (haveSecurity && !highestELIs64 && !scr.ns) { 988 sctlr_idx = MISCREG_SCTLR_S; 989 } else { 990 sctlr_idx = MISCREG_SCTLR_NS; 991 } 992 993 SCTLR sctlr = miscRegs[sctlr_idx]; 994 SCTLR new_sctlr = newVal; 995 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 996 miscRegs[sctlr_idx] = (RegVal)new_sctlr; 997 getITBPtr(tc)->invalidateMiscReg(); 998 getDTBPtr(tc)->invalidateMiscReg(); 999 } 1000 case MISCREG_MIDR: 1001 case MISCREG_ID_PFR0: 1002 case MISCREG_ID_PFR1: 1003 case MISCREG_ID_DFR0: 1004 case MISCREG_ID_MMFR0: 1005 case MISCREG_ID_MMFR1: 1006 case MISCREG_ID_MMFR2: 1007 case MISCREG_ID_MMFR3: 1008 case MISCREG_ID_ISAR0: 1009 case MISCREG_ID_ISAR1: 1010 case MISCREG_ID_ISAR2: 1011 case MISCREG_ID_ISAR3: 1012 case MISCREG_ID_ISAR4: 1013 case MISCREG_ID_ISAR5: 1014 1015 case MISCREG_MPIDR: 1016 case MISCREG_FPSID: 1017 case MISCREG_TLBTR: 1018 case MISCREG_MVFR0: 1019 case MISCREG_MVFR1: 1020 1021 case MISCREG_ID_AA64AFR0_EL1: 1022 case MISCREG_ID_AA64AFR1_EL1: 1023 case MISCREG_ID_AA64DFR0_EL1: 1024 case MISCREG_ID_AA64DFR1_EL1: 1025 case MISCREG_ID_AA64ISAR0_EL1: 1026 case MISCREG_ID_AA64ISAR1_EL1: 1027 case MISCREG_ID_AA64MMFR0_EL1: 1028 case MISCREG_ID_AA64MMFR1_EL1: 1029 case MISCREG_ID_AA64MMFR2_EL1: 1030 case MISCREG_ID_AA64PFR0_EL1: 1031 case MISCREG_ID_AA64PFR1_EL1: 1032 // ID registers are constants. 1033 return; 1034 1035 // TLB Invalidate All 1036 case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 1037 { 1038 assert32(tc); 1039 scr = readMiscReg(MISCREG_SCR, tc); 1040 1041 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1042 tlbiOp(tc); 1043 return; 1044 } 1045 // TLB Invalidate All, Inner Shareable 1046 case MISCREG_TLBIALLIS: 1047 { 1048 assert32(tc); 1049 scr = readMiscReg(MISCREG_SCR, tc); 1050 1051 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1052 tlbiOp.broadcast(tc); 1053 return; 1054 } 1055 // Instruction TLB Invalidate All 1056 case MISCREG_ITLBIALL: 1057 { 1058 assert32(tc); 1059 scr = readMiscReg(MISCREG_SCR, tc); 1060 1061 ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1062 tlbiOp(tc); 1063 return; 1064 } 1065 // Data TLB Invalidate All 1066 case MISCREG_DTLBIALL: 1067 { 1068 assert32(tc); 1069 scr = readMiscReg(MISCREG_SCR, tc); 1070 1071 DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1072 tlbiOp(tc); 1073 return; 1074 } 1075 // TLB Invalidate by VA 1076 // mcr tlbimval(is) is invalidating all matching entries 1077 // regardless of the level of lookup, since in gem5 we cache 1078 // in the tlb the last level of lookup only. 1079 case MISCREG_TLBIMVA: 1080 case MISCREG_TLBIMVAL: 1081 { 1082 assert32(tc); 1083 scr = readMiscReg(MISCREG_SCR, tc); 1084 1085 TLBIMVA tlbiOp(EL1, 1086 haveSecurity && !scr.ns, 1087 mbits(newVal, 31, 12), 1088 bits(newVal, 7,0)); 1089 1090 tlbiOp(tc); 1091 return; 1092 } 1093 // TLB Invalidate by VA, Inner Shareable 1094 case MISCREG_TLBIMVAIS: 1095 case MISCREG_TLBIMVALIS: 1096 { 1097 assert32(tc); 1098 scr = readMiscReg(MISCREG_SCR, tc); 1099 1100 TLBIMVA tlbiOp(EL1, 1101 haveSecurity && !scr.ns, 1102 mbits(newVal, 31, 12), 1103 bits(newVal, 7,0)); 1104 1105 tlbiOp.broadcast(tc); 1106 return; 1107 } 1108 // TLB Invalidate by ASID match 1109 case MISCREG_TLBIASID: 1110 { 1111 assert32(tc); 1112 scr = readMiscReg(MISCREG_SCR, tc); 1113 1114 TLBIASID tlbiOp(EL1, 1115 haveSecurity && !scr.ns, 1116 bits(newVal, 7,0)); 1117 1118 tlbiOp(tc); 1119 return; 1120 } 1121 // TLB Invalidate by ASID match, Inner Shareable 1122 case MISCREG_TLBIASIDIS: 1123 { 1124 assert32(tc); 1125 scr = readMiscReg(MISCREG_SCR, tc); 1126 1127 TLBIASID tlbiOp(EL1, 1128 haveSecurity && !scr.ns, 1129 bits(newVal, 7,0)); 1130 1131 tlbiOp.broadcast(tc); 1132 return; 1133 } 1134 // mcr tlbimvaal(is) is invalidating all matching entries 1135 // regardless of the level of lookup, since in gem5 we cache 1136 // in the tlb the last level of lookup only. 1137 // TLB Invalidate by VA, All ASID 1138 case MISCREG_TLBIMVAA: 1139 case MISCREG_TLBIMVAAL: 1140 { 1141 assert32(tc); 1142 scr = readMiscReg(MISCREG_SCR, tc); 1143 1144 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1145 mbits(newVal, 31,12), false); 1146 1147 tlbiOp(tc); 1148 return; 1149 } 1150 // TLB Invalidate by VA, All ASID, Inner Shareable 1151 case MISCREG_TLBIMVAAIS: 1152 case MISCREG_TLBIMVAALIS: 1153 { 1154 assert32(tc); 1155 scr = readMiscReg(MISCREG_SCR, tc); 1156 1157 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1158 mbits(newVal, 31,12), false); 1159 1160 tlbiOp.broadcast(tc); 1161 return; 1162 } 1163 // mcr tlbimvalh(is) is invalidating all matching entries 1164 // regardless of the level of lookup, since in gem5 we cache 1165 // in the tlb the last level of lookup only. 1166 // TLB Invalidate by VA, Hyp mode 1167 case MISCREG_TLBIMVAH: 1168 case MISCREG_TLBIMVALH: 1169 { 1170 assert32(tc); 1171 scr = readMiscReg(MISCREG_SCR, tc); 1172 1173 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1174 mbits(newVal, 31,12), true); 1175 1176 tlbiOp(tc); 1177 return; 1178 } 1179 // TLB Invalidate by VA, Hyp mode, Inner Shareable 1180 case MISCREG_TLBIMVAHIS: 1181 case MISCREG_TLBIMVALHIS: 1182 { 1183 assert32(tc); 1184 scr = readMiscReg(MISCREG_SCR, tc); 1185 1186 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1187 mbits(newVal, 31,12), true); 1188 1189 tlbiOp.broadcast(tc); 1190 return; 1191 } 1192 // mcr tlbiipas2l(is) is invalidating all matching entries 1193 // regardless of the level of lookup, since in gem5 we cache 1194 // in the tlb the last level of lookup only. 1195 // TLB Invalidate by Intermediate Physical Address, Stage 2 1196 case MISCREG_TLBIIPAS2: 1197 case MISCREG_TLBIIPAS2L: 1198 { 1199 assert32(tc); 1200 scr = readMiscReg(MISCREG_SCR, tc); 1201 1202 TLBIIPA tlbiOp(EL1, 1203 haveSecurity && !scr.ns, 1204 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1205 1206 tlbiOp(tc); 1207 return; 1208 } 1209 // TLB Invalidate by Intermediate Physical Address, Stage 2, 1210 // Inner Shareable 1211 case MISCREG_TLBIIPAS2IS: 1212 case MISCREG_TLBIIPAS2LIS: 1213 { 1214 assert32(tc); 1215 scr = readMiscReg(MISCREG_SCR, tc); 1216 1217 TLBIIPA tlbiOp(EL1, 1218 haveSecurity && !scr.ns, 1219 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1220 1221 tlbiOp.broadcast(tc); 1222 return; 1223 } 1224 // Instruction TLB Invalidate by VA 1225 case MISCREG_ITLBIMVA: 1226 { 1227 assert32(tc); 1228 scr = readMiscReg(MISCREG_SCR, tc); 1229 1230 ITLBIMVA tlbiOp(EL1, 1231 haveSecurity && !scr.ns, 1232 mbits(newVal, 31, 12), 1233 bits(newVal, 7,0)); 1234 1235 tlbiOp(tc); 1236 return; 1237 } 1238 // Data TLB Invalidate by VA 1239 case MISCREG_DTLBIMVA: 1240 { 1241 assert32(tc); 1242 scr = readMiscReg(MISCREG_SCR, tc); 1243 1244 DTLBIMVA tlbiOp(EL1, 1245 haveSecurity && !scr.ns, 1246 mbits(newVal, 31, 12), 1247 bits(newVal, 7,0)); 1248 1249 tlbiOp(tc); 1250 return; 1251 } 1252 // Instruction TLB Invalidate by ASID match 1253 case MISCREG_ITLBIASID: 1254 { 1255 assert32(tc); 1256 scr = readMiscReg(MISCREG_SCR, tc); 1257 1258 ITLBIASID tlbiOp(EL1, 1259 haveSecurity && !scr.ns, 1260 bits(newVal, 7,0)); 1261 1262 tlbiOp(tc); 1263 return; 1264 } 1265 // Data TLB Invalidate by ASID match 1266 case MISCREG_DTLBIASID: 1267 { 1268 assert32(tc); 1269 scr = readMiscReg(MISCREG_SCR, tc); 1270 1271 DTLBIASID tlbiOp(EL1, 1272 haveSecurity && !scr.ns, 1273 bits(newVal, 7,0)); 1274 1275 tlbiOp(tc); 1276 return; 1277 } 1278 // TLB Invalidate All, Non-Secure Non-Hyp 1279 case MISCREG_TLBIALLNSNH: 1280 { 1281 assert32(tc); 1282 1283 TLBIALLN tlbiOp(EL1, false); 1284 tlbiOp(tc); 1285 return; 1286 } 1287 // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable 1288 case MISCREG_TLBIALLNSNHIS: 1289 { 1290 assert32(tc); 1291 1292 TLBIALLN tlbiOp(EL1, false); 1293 tlbiOp.broadcast(tc); 1294 return; 1295 } 1296 // TLB Invalidate All, Hyp mode 1297 case MISCREG_TLBIALLH: 1298 { 1299 assert32(tc); 1300 1301 TLBIALLN tlbiOp(EL1, true); 1302 tlbiOp(tc); 1303 return; 1304 } 1305 // TLB Invalidate All, Hyp mode, Inner Shareable 1306 case MISCREG_TLBIALLHIS: 1307 { 1308 assert32(tc); 1309 1310 TLBIALLN tlbiOp(EL1, true); 1311 tlbiOp.broadcast(tc); 1312 return; 1313 } 1314 // AArch64 TLB Invalidate All, EL3 1315 case MISCREG_TLBI_ALLE3: 1316 { 1317 assert64(tc); 1318 1319 TLBIALL tlbiOp(EL3, true); 1320 tlbiOp(tc); 1321 return; 1322 } 1323 // AArch64 TLB Invalidate All, EL3, Inner Shareable 1324 case MISCREG_TLBI_ALLE3IS: 1325 { 1326 assert64(tc); 1327 1328 TLBIALL tlbiOp(EL3, true); 1329 tlbiOp.broadcast(tc); 1330 return; 1331 } 1332 // AArch64 TLB Invalidate All, EL2, Inner Shareable 1333 case MISCREG_TLBI_ALLE2: 1334 case MISCREG_TLBI_ALLE2IS: 1335 { 1336 assert64(tc); 1337 scr = readMiscReg(MISCREG_SCR, tc); 1338 1339 TLBIALL tlbiOp(EL2, haveSecurity && !scr.ns); 1340 tlbiOp(tc); 1341 return; 1342 } 1343 // AArch64 TLB Invalidate All, EL1 1344 case MISCREG_TLBI_ALLE1: 1345 case MISCREG_TLBI_VMALLE1: 1346 case MISCREG_TLBI_VMALLS12E1: 1347 // @todo: handle VMID and stage 2 to enable Virtualization 1348 { 1349 assert64(tc); 1350 scr = readMiscReg(MISCREG_SCR, tc); 1351 1352 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1353 tlbiOp(tc); 1354 return; 1355 } 1356 // AArch64 TLB Invalidate All, EL1, Inner Shareable 1357 case MISCREG_TLBI_ALLE1IS: 1358 case MISCREG_TLBI_VMALLE1IS: 1359 case MISCREG_TLBI_VMALLS12E1IS: 1360 // @todo: handle VMID and stage 2 to enable Virtualization 1361 { 1362 assert64(tc); 1363 scr = readMiscReg(MISCREG_SCR, tc); 1364 1365 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1366 tlbiOp.broadcast(tc); 1367 return; 1368 } 1369 // VAEx(IS) and VALEx(IS) are the same because TLBs 1370 // only store entries 1371 // from the last level of translation table walks 1372 // @todo: handle VMID to enable Virtualization 1373 // AArch64 TLB Invalidate by VA, EL3 1374 case MISCREG_TLBI_VAE3_Xt: 1375 case MISCREG_TLBI_VALE3_Xt: 1376 { 1377 assert64(tc); 1378 1379 TLBIMVA tlbiOp(EL3, true, 1380 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1381 0xbeef); 1382 tlbiOp(tc); 1383 return; 1384 } 1385 // AArch64 TLB Invalidate by VA, EL3, Inner Shareable 1386 case MISCREG_TLBI_VAE3IS_Xt: 1387 case MISCREG_TLBI_VALE3IS_Xt: 1388 { 1389 assert64(tc); 1390 1391 TLBIMVA tlbiOp(EL3, true, 1392 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1393 0xbeef); 1394 1395 tlbiOp.broadcast(tc); 1396 return; 1397 } 1398 // AArch64 TLB Invalidate by VA, EL2 1399 case MISCREG_TLBI_VAE2_Xt: 1400 case MISCREG_TLBI_VALE2_Xt: 1401 { 1402 assert64(tc); 1403 scr = readMiscReg(MISCREG_SCR, tc); 1404 1405 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1406 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1407 0xbeef); 1408 tlbiOp(tc); 1409 return; 1410 } 1411 // AArch64 TLB Invalidate by VA, EL2, Inner Shareable 1412 case MISCREG_TLBI_VAE2IS_Xt: 1413 case MISCREG_TLBI_VALE2IS_Xt: 1414 { 1415 assert64(tc); 1416 scr = readMiscReg(MISCREG_SCR, tc); 1417 1418 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1419 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1420 0xbeef); 1421 1422 tlbiOp.broadcast(tc); 1423 return; 1424 } 1425 // AArch64 TLB Invalidate by VA, EL1 1426 case MISCREG_TLBI_VAE1_Xt: 1427 case MISCREG_TLBI_VALE1_Xt: 1428 { 1429 assert64(tc); 1430 scr = readMiscReg(MISCREG_SCR, tc); 1431 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1432 bits(newVal, 55, 48); 1433 1434 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1435 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1436 asid); 1437 1438 tlbiOp(tc); 1439 return; 1440 } 1441 // AArch64 TLB Invalidate by VA, EL1, Inner Shareable 1442 case MISCREG_TLBI_VAE1IS_Xt: 1443 case MISCREG_TLBI_VALE1IS_Xt: 1444 { 1445 assert64(tc); 1446 scr = readMiscReg(MISCREG_SCR, tc); 1447 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1448 bits(newVal, 55, 48); 1449 1450 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1451 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1452 asid); 1453 1454 tlbiOp.broadcast(tc); 1455 return; 1456 } 1457 // AArch64 TLB Invalidate by ASID, EL1 1458 // @todo: handle VMID to enable Virtualization 1459 case MISCREG_TLBI_ASIDE1_Xt: 1460 { 1461 assert64(tc); 1462 scr = readMiscReg(MISCREG_SCR, tc); 1463 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1464 bits(newVal, 55, 48); 1465 1466 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1467 tlbiOp(tc); 1468 return; 1469 } 1470 // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable 1471 case MISCREG_TLBI_ASIDE1IS_Xt: 1472 { 1473 assert64(tc); 1474 scr = readMiscReg(MISCREG_SCR, tc); 1475 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1476 bits(newVal, 55, 48); 1477 1478 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1479 tlbiOp.broadcast(tc); 1480 return; 1481 } 1482 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 1483 // entries from the last level of translation table walks 1484 // AArch64 TLB Invalidate by VA, All ASID, EL1 1485 case MISCREG_TLBI_VAAE1_Xt: 1486 case MISCREG_TLBI_VAALE1_Xt: 1487 { 1488 assert64(tc); 1489 scr = readMiscReg(MISCREG_SCR, tc); 1490 1491 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1492 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 1493 1494 tlbiOp(tc); 1495 return; 1496 } 1497 // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable 1498 case MISCREG_TLBI_VAAE1IS_Xt: 1499 case MISCREG_TLBI_VAALE1IS_Xt: 1500 { 1501 assert64(tc); 1502 scr = readMiscReg(MISCREG_SCR, tc); 1503 1504 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1505 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 1506 1507 tlbiOp.broadcast(tc); 1508 return; 1509 } 1510 // AArch64 TLB Invalidate by Intermediate Physical Address, 1511 // Stage 2, EL1 1512 case MISCREG_TLBI_IPAS2E1_Xt: 1513 case MISCREG_TLBI_IPAS2LE1_Xt: 1514 { 1515 assert64(tc); 1516 scr = readMiscReg(MISCREG_SCR, tc); 1517 1518 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1519 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1520 1521 tlbiOp(tc); 1522 return; 1523 } 1524 // AArch64 TLB Invalidate by Intermediate Physical Address, 1525 // Stage 2, EL1, Inner Shareable 1526 case MISCREG_TLBI_IPAS2E1IS_Xt: 1527 case MISCREG_TLBI_IPAS2LE1IS_Xt: 1528 { 1529 assert64(tc); 1530 scr = readMiscReg(MISCREG_SCR, tc); 1531 1532 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1533 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1534 1535 tlbiOp.broadcast(tc); 1536 return; 1537 } 1538 case MISCREG_ACTLR: 1539 warn("Not doing anything for write of miscreg ACTLR\n"); 1540 break; 1541 1542 case MISCREG_PMXEVTYPER_PMCCFILTR: 1543 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 1544 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 1545 case MISCREG_PMCR ... MISCREG_PMOVSSET: 1546 pmu->setMiscReg(misc_reg, newVal); 1547 break; 1548 1549 1550 case MISCREG_HSTR: // TJDBX, now redifined to be RES0 1551 { 1552 HSTR hstrMask = 0; 1553 hstrMask.tjdbx = 1; 1554 newVal &= ~((uint32_t) hstrMask); 1555 break; 1556 } 1557 case MISCREG_HCPTR: 1558 { 1559 // If a CP bit in NSACR is 0 then the corresponding bit in 1560 // HCPTR is RAO/WI. Same applies to NSASEDIS 1561 secure_lookup = haveSecurity && 1562 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 1563 readMiscRegNoEffect(MISCREG_CPSR)); 1564 if (!secure_lookup) { 1565 RegVal oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 1566 RegVal mask = 1567 (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 1568 newVal = (newVal & ~mask) | (oldValue & mask); 1569 } 1570 break; 1571 } 1572 case MISCREG_HDFAR: // alias for secure DFAR 1573 misc_reg = MISCREG_DFAR_S; 1574 break; 1575 case MISCREG_HIFAR: // alias for secure IFAR 1576 misc_reg = MISCREG_IFAR_S; 1577 break; 1578 case MISCREG_ATS1CPR: 1579 case MISCREG_ATS1CPW: 1580 case MISCREG_ATS1CUR: 1581 case MISCREG_ATS1CUW: 1582 case MISCREG_ATS12NSOPR: 1583 case MISCREG_ATS12NSOPW: 1584 case MISCREG_ATS12NSOUR: 1585 case MISCREG_ATS12NSOUW: 1586 case MISCREG_ATS1HR: 1587 case MISCREG_ATS1HW: 1588 { 1589 Request::Flags flags = 0; 1590 BaseTLB::Mode mode = BaseTLB::Read; 1591 TLB::ArmTranslationType tranType = TLB::NormalTran; 1592 Fault fault; 1593 switch(misc_reg) { 1594 case MISCREG_ATS1CPR: 1595 flags = TLB::MustBeOne; 1596 tranType = TLB::S1CTran; 1597 mode = BaseTLB::Read; 1598 break; 1599 case MISCREG_ATS1CPW: 1600 flags = TLB::MustBeOne; 1601 tranType = TLB::S1CTran; 1602 mode = BaseTLB::Write; 1603 break; 1604 case MISCREG_ATS1CUR: 1605 flags = TLB::MustBeOne | TLB::UserMode; 1606 tranType = TLB::S1CTran; 1607 mode = BaseTLB::Read; 1608 break; 1609 case MISCREG_ATS1CUW: 1610 flags = TLB::MustBeOne | TLB::UserMode; 1611 tranType = TLB::S1CTran; 1612 mode = BaseTLB::Write; 1613 break; 1614 case MISCREG_ATS12NSOPR: 1615 if (!haveSecurity) 1616 panic("Security Extensions required for ATS12NSOPR"); 1617 flags = TLB::MustBeOne; 1618 tranType = TLB::S1S2NsTran; 1619 mode = BaseTLB::Read; 1620 break; 1621 case MISCREG_ATS12NSOPW: 1622 if (!haveSecurity) 1623 panic("Security Extensions required for ATS12NSOPW"); 1624 flags = TLB::MustBeOne; 1625 tranType = TLB::S1S2NsTran; 1626 mode = BaseTLB::Write; 1627 break; 1628 case MISCREG_ATS12NSOUR: 1629 if (!haveSecurity) 1630 panic("Security Extensions required for ATS12NSOUR"); 1631 flags = TLB::MustBeOne | TLB::UserMode; 1632 tranType = TLB::S1S2NsTran; 1633 mode = BaseTLB::Read; 1634 break; 1635 case MISCREG_ATS12NSOUW: 1636 if (!haveSecurity) 1637 panic("Security Extensions required for ATS12NSOUW"); 1638 flags = TLB::MustBeOne | TLB::UserMode; 1639 tranType = TLB::S1S2NsTran; 1640 mode = BaseTLB::Write; 1641 break; 1642 case MISCREG_ATS1HR: // only really useful from secure mode. 1643 flags = TLB::MustBeOne; 1644 tranType = TLB::HypMode; 1645 mode = BaseTLB::Read; 1646 break; 1647 case MISCREG_ATS1HW: 1648 flags = TLB::MustBeOne; 1649 tranType = TLB::HypMode; 1650 mode = BaseTLB::Write; 1651 break; 1652 } 1653 // If we're in timing mode then doing the translation in 1654 // functional mode then we're slightly distorting performance 1655 // results obtained from simulations. The translation should be 1656 // done in the same mode the core is running in. NOTE: This 1657 // can't be an atomic translation because that causes problems 1658 // with unexpected atomic snoop requests. 1659 warn("Translating via %s in functional mode! Fix Me!\n", 1660 miscRegName[misc_reg]); 1661 1662 auto req = std::make_shared<Request>( 1663 0, val, 0, flags, Request::funcMasterId, 1664 tc->pcState().pc(), tc->contextId()); 1665 1666 fault = getDTBPtr(tc)->translateFunctional( 1667 req, tc, mode, tranType); 1668 1669 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1670 HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 1671 1672 RegVal newVal; 1673 if (fault == NoFault) { 1674 Addr paddr = req->getPaddr(); 1675 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 1676 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 1677 newVal = (paddr & mask(39, 12)) | 1678 (getDTBPtr(tc)->getAttr()); 1679 } else { 1680 newVal = (paddr & 0xfffff000) | 1681 (getDTBPtr(tc)->getAttr()); 1682 } 1683 DPRINTF(MiscRegs, 1684 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 1685 val, newVal); 1686 } else { 1687 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1688 armFault->update(tc); 1689 // Set fault bit and FSR 1690 FSR fsr = armFault->getFsr(tc); 1691 1692 newVal = ((fsr >> 9) & 1) << 11; 1693 if (newVal) { 1694 // LPAE - rearange fault status 1695 newVal |= ((fsr >> 0) & 0x3f) << 1; 1696 } else { 1697 // VMSA - rearange fault status 1698 newVal |= ((fsr >> 0) & 0xf) << 1; 1699 newVal |= ((fsr >> 10) & 0x1) << 5; 1700 newVal |= ((fsr >> 12) & 0x1) << 6; 1701 } 1702 newVal |= 0x1; // F bit 1703 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1704 newVal |= armFault->isStage2() ? 0x200 : 0; 1705 DPRINTF(MiscRegs, 1706 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 1707 val, fsr, newVal); 1708 } 1709 setMiscRegNoEffect(MISCREG_PAR, newVal); 1710 return; 1711 } 1712 case MISCREG_TTBCR: 1713 { 1714 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1715 const uint32_t ones = (uint32_t)(-1); 1716 TTBCR ttbcrMask = 0; 1717 TTBCR ttbcrNew = newVal; 1718 1719 // ARM DDI 0406C.b, ARMv7-32 1720 ttbcrMask.n = ones; // T0SZ 1721 if (haveSecurity) { 1722 ttbcrMask.pd0 = ones; 1723 ttbcrMask.pd1 = ones; 1724 } 1725 ttbcrMask.epd0 = ones; 1726 ttbcrMask.irgn0 = ones; 1727 ttbcrMask.orgn0 = ones; 1728 ttbcrMask.sh0 = ones; 1729 ttbcrMask.ps = ones; // T1SZ 1730 ttbcrMask.a1 = ones; 1731 ttbcrMask.epd1 = ones; 1732 ttbcrMask.irgn1 = ones; 1733 ttbcrMask.orgn1 = ones; 1734 ttbcrMask.sh1 = ones; 1735 if (haveLPAE) 1736 ttbcrMask.eae = ones; 1737 1738 if (haveLPAE && ttbcrNew.eae) { 1739 newVal = newVal & ttbcrMask; 1740 } else { 1741 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 1742 } 1743 // Invalidate TLB MiscReg 1744 getITBPtr(tc)->invalidateMiscReg(); 1745 getDTBPtr(tc)->invalidateMiscReg(); 1746 break; 1747 } 1748 case MISCREG_TTBR0: 1749 case MISCREG_TTBR1: 1750 { 1751 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1752 if (haveLPAE) { 1753 if (ttbcr.eae) { 1754 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 1755 // ARMv8 AArch32 bit 63-56 only 1756 uint64_t ttbrMask = mask(63,56) | mask(47,40); 1757 newVal = (newVal & (~ttbrMask)); 1758 } 1759 } 1760 // Invalidate TLB MiscReg 1761 getITBPtr(tc)->invalidateMiscReg(); 1762 getDTBPtr(tc)->invalidateMiscReg(); 1763 break; 1764 } 1765 case MISCREG_SCTLR_EL1: 1766 case MISCREG_CONTEXTIDR: 1767 case MISCREG_PRRR: 1768 case MISCREG_NMRR: 1769 case MISCREG_MAIR0: 1770 case MISCREG_MAIR1: 1771 case MISCREG_DACR: 1772 case MISCREG_VTTBR: 1773 case MISCREG_SCR_EL3: 1774 case MISCREG_HCR_EL2: 1775 case MISCREG_TCR_EL1: 1776 case MISCREG_TCR_EL2: 1777 case MISCREG_TCR_EL3: 1778 case MISCREG_SCTLR_EL2: 1779 case MISCREG_SCTLR_EL3: 1780 case MISCREG_HSCTLR: 1781 case MISCREG_TTBR0_EL1: 1782 case MISCREG_TTBR1_EL1: 1783 case MISCREG_TTBR0_EL2: 1784 case MISCREG_TTBR1_EL2: 1785 case MISCREG_TTBR0_EL3: 1786 getITBPtr(tc)->invalidateMiscReg(); 1787 getDTBPtr(tc)->invalidateMiscReg(); 1788 break; 1789 case MISCREG_NZCV: 1790 { 1791 CPSR cpsr = val; 1792 1793 tc->setCCReg(CCREG_NZ, cpsr.nz); 1794 tc->setCCReg(CCREG_C, cpsr.c); 1795 tc->setCCReg(CCREG_V, cpsr.v); 1796 } 1797 break; 1798 case MISCREG_DAIF: 1799 { 1800 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1801 cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 1802 newVal = cpsr; 1803 misc_reg = MISCREG_CPSR; 1804 } 1805 break; 1806 case MISCREG_SP_EL0: 1807 tc->setIntReg(INTREG_SP0, newVal); 1808 break; 1809 case MISCREG_SP_EL1: 1810 tc->setIntReg(INTREG_SP1, newVal); 1811 break; 1812 case MISCREG_SP_EL2: 1813 tc->setIntReg(INTREG_SP2, newVal); 1814 break; 1815 case MISCREG_SPSEL: 1816 { 1817 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1818 cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 1819 newVal = cpsr; 1820 misc_reg = MISCREG_CPSR; 1821 } 1822 break; 1823 case MISCREG_CURRENTEL: 1824 { 1825 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1826 cpsr.el = (uint8_t) ((CPSR) newVal).el; 1827 newVal = cpsr; 1828 misc_reg = MISCREG_CPSR; 1829 } 1830 break; 1831 case MISCREG_AT_S1E1R_Xt: 1832 case MISCREG_AT_S1E1W_Xt: 1833 case MISCREG_AT_S1E0R_Xt: 1834 case MISCREG_AT_S1E0W_Xt: 1835 case MISCREG_AT_S1E2R_Xt: 1836 case MISCREG_AT_S1E2W_Xt: 1837 case MISCREG_AT_S12E1R_Xt: 1838 case MISCREG_AT_S12E1W_Xt: 1839 case MISCREG_AT_S12E0R_Xt: 1840 case MISCREG_AT_S12E0W_Xt: 1841 case MISCREG_AT_S1E3R_Xt: 1842 case MISCREG_AT_S1E3W_Xt: 1843 { 1844 RequestPtr req = std::make_shared<Request>(); 1845 Request::Flags flags = 0; 1846 BaseTLB::Mode mode = BaseTLB::Read; 1847 TLB::ArmTranslationType tranType = TLB::NormalTran; 1848 Fault fault; 1849 switch(misc_reg) { 1850 case MISCREG_AT_S1E1R_Xt: 1851 flags = TLB::MustBeOne; 1852 tranType = TLB::S1E1Tran; 1853 mode = BaseTLB::Read; 1854 break; 1855 case MISCREG_AT_S1E1W_Xt: 1856 flags = TLB::MustBeOne; 1857 tranType = TLB::S1E1Tran; 1858 mode = BaseTLB::Write; 1859 break; 1860 case MISCREG_AT_S1E0R_Xt: 1861 flags = TLB::MustBeOne | TLB::UserMode; 1862 tranType = TLB::S1E0Tran; 1863 mode = BaseTLB::Read; 1864 break; 1865 case MISCREG_AT_S1E0W_Xt: 1866 flags = TLB::MustBeOne | TLB::UserMode; 1867 tranType = TLB::S1E0Tran; 1868 mode = BaseTLB::Write; 1869 break; 1870 case MISCREG_AT_S1E2R_Xt: 1871 flags = TLB::MustBeOne; 1872 tranType = TLB::S1E2Tran; 1873 mode = BaseTLB::Read; 1874 break; 1875 case MISCREG_AT_S1E2W_Xt: 1876 flags = TLB::MustBeOne; 1877 tranType = TLB::S1E2Tran; 1878 mode = BaseTLB::Write; 1879 break; 1880 case MISCREG_AT_S12E0R_Xt: 1881 flags = TLB::MustBeOne | TLB::UserMode; 1882 tranType = TLB::S12E0Tran; 1883 mode = BaseTLB::Read; 1884 break; 1885 case MISCREG_AT_S12E0W_Xt: 1886 flags = TLB::MustBeOne | TLB::UserMode; 1887 tranType = TLB::S12E0Tran; 1888 mode = BaseTLB::Write; 1889 break; 1890 case MISCREG_AT_S12E1R_Xt: 1891 flags = TLB::MustBeOne; 1892 tranType = TLB::S12E1Tran; 1893 mode = BaseTLB::Read; 1894 break; 1895 case MISCREG_AT_S12E1W_Xt: 1896 flags = TLB::MustBeOne; 1897 tranType = TLB::S12E1Tran; 1898 mode = BaseTLB::Write; 1899 break; 1900 case MISCREG_AT_S1E3R_Xt: 1901 flags = TLB::MustBeOne; 1902 tranType = TLB::S1E3Tran; 1903 mode = BaseTLB::Read; 1904 break; 1905 case MISCREG_AT_S1E3W_Xt: 1906 flags = TLB::MustBeOne; 1907 tranType = TLB::S1E3Tran; 1908 mode = BaseTLB::Write; 1909 break; 1910 } 1911 // If we're in timing mode then doing the translation in 1912 // functional mode then we're slightly distorting performance 1913 // results obtained from simulations. The translation should be 1914 // done in the same mode the core is running in. NOTE: This 1915 // can't be an atomic translation because that causes problems 1916 // with unexpected atomic snoop requests. 1917 warn("Translating via %s in functional mode! Fix Me!\n", 1918 miscRegName[misc_reg]); 1919 1920 req->setVirt(0, val, 0, flags, Request::funcMasterId, 1921 tc->pcState().pc()); 1922 req->setContext(tc->contextId()); 1923 fault = getDTBPtr(tc)->translateFunctional(req, tc, mode, 1924 tranType); 1925 1926 RegVal newVal; 1927 if (fault == NoFault) { 1928 Addr paddr = req->getPaddr(); 1929 uint64_t attr = getDTBPtr(tc)->getAttr(); 1930 uint64_t attr1 = attr >> 56; 1931 if (!attr1 || attr1 ==0x44) { 1932 attr |= 0x100; 1933 attr &= ~ uint64_t(0x80); 1934 } 1935 newVal = (paddr & mask(47, 12)) | attr; 1936 DPRINTF(MiscRegs, 1937 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 1938 val, newVal); 1939 } else { 1940 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1941 armFault->update(tc); 1942 // Set fault bit and FSR 1943 FSR fsr = armFault->getFsr(tc); 1944 1945 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1946 if (cpsr.width) { // AArch32 1947 newVal = ((fsr >> 9) & 1) << 11; 1948 // rearrange fault status 1949 newVal |= ((fsr >> 0) & 0x3f) << 1; 1950 newVal |= 0x1; // F bit 1951 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1952 newVal |= armFault->isStage2() ? 0x200 : 0; 1953 } else { // AArch64 1954 newVal = 1; // F bit 1955 newVal |= fsr << 1; // FST 1956 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit. 1957 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 1958 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 1959 newVal |= 1 << 11; // RES1 1960 } 1961 DPRINTF(MiscRegs, 1962 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 1963 val, fsr, newVal); 1964 } 1965 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 1966 return; 1967 } 1968 case MISCREG_SPSR_EL3: 1969 case MISCREG_SPSR_EL2: 1970 case MISCREG_SPSR_EL1: 1971 // Force bits 23:21 to 0 1972 newVal = val & ~(0x7 << 21); 1973 break; 1974 case MISCREG_L2CTLR: 1975 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 1976 miscRegName[misc_reg], uint32_t(val)); 1977 break; 1978 1979 // Generic Timer registers 1980 case MISCREG_CNTHV_CTL_EL2: 1981 case MISCREG_CNTHV_CVAL_EL2: 1982 case MISCREG_CNTHV_TVAL_EL2: 1983 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 1984 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 1985 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 1986 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 1987 getGenericTimer(tc).setMiscReg(misc_reg, newVal); 1988 break; 1989 1990 case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3: 1991 case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2: 1992 getGICv3CPUInterface(tc).setMiscReg(misc_reg, newVal); 1993 return; 1994 } 1995 } 1996 setMiscRegNoEffect(misc_reg, newVal); 1997} 1998 1999BaseISADevice & 2000ISA::getGenericTimer(ThreadContext *tc) 2001{ 2002 // We only need to create an ISA interface the first time we try 2003 // to access the timer. 2004 if (timer) 2005 return *timer.get(); 2006 2007 assert(system); 2008 GenericTimer *generic_timer(system->getGenericTimer()); 2009 if (!generic_timer) { 2010 panic("Trying to get a generic timer from a system that hasn't " 2011 "been configured to use a generic timer.\n"); 2012 } 2013 2014 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 2015 timer->setThreadContext(tc); 2016 2017 return *timer.get(); 2018} 2019 2020BaseISADevice & 2021ISA::getGICv3CPUInterface(ThreadContext *tc) 2022{ 2023 panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!"); 2024 return *gicv3CpuInterface.get(); 2025} 2026 2027} 2028 2029ArmISA::ISA * 2030ArmISAParams::create() 2031{ 2032 return new ArmISA::ISA(this); 2033} 2034