isa.cc revision 13599:05e9234fef20
1/* 2 * Copyright (c) 2010-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 */ 40 41#include "arch/arm/isa.hh" 42#include "arch/arm/pmu.hh" 43#include "arch/arm/system.hh" 44#include "arch/arm/tlb.hh" 45#include "arch/arm/tlbi_op.hh" 46#include "cpu/base.hh" 47#include "cpu/checker/cpu.hh" 48#include "debug/Arm.hh" 49#include "debug/MiscRegs.hh" 50#include "dev/arm/generic_timer.hh" 51#include "dev/arm/gic_v3.hh" 52#include "dev/arm/gic_v3_cpu_interface.hh" 53#include "params/ArmISA.hh" 54#include "sim/faults.hh" 55#include "sim/stat_control.hh" 56#include "sim/system.hh" 57 58namespace ArmISA 59{ 60 61ISA::ISA(Params *p) 62 : SimObject(p), 63 system(NULL), 64 _decoderFlavour(p->decoderFlavour), 65 _vecRegRenameMode(Enums::Full), 66 pmu(p->pmu), 67 impdefAsNop(p->impdef_nop) 68{ 69 miscRegs[MISCREG_SCTLR_RST] = 0; 70 71 // Hook up a dummy device if we haven't been configured with a 72 // real PMU. By using a dummy device, we don't need to check that 73 // the PMU exist every time we try to access a PMU register. 74 if (!pmu) 75 pmu = &dummyDevice; 76 77 // Give all ISA devices a pointer to this ISA 78 pmu->setISA(this); 79 80 system = dynamic_cast<ArmSystem *>(p->system); 81 82 // Cache system-level properties 83 if (FullSystem && system) { 84 highestELIs64 = system->highestELIs64(); 85 haveSecurity = system->haveSecurity(); 86 haveLPAE = system->haveLPAE(); 87 haveCrypto = system->haveCrypto(); 88 haveVirtualization = system->haveVirtualization(); 89 haveLargeAsid64 = system->haveLargeAsid64(); 90 physAddrRange = system->physAddrRange(); 91 } else { 92 highestELIs64 = true; // ArmSystem::highestELIs64 does the same 93 haveSecurity = haveLPAE = haveVirtualization = false; 94 haveCrypto = true; 95 haveLargeAsid64 = false; 96 physAddrRange = 32; // dummy value 97 } 98 99 // GICv3 CPU interface system registers are supported 100 haveGICv3CPUInterface = false; 101 102 if (system && dynamic_cast<Gicv3 *>(system->getGIC())) { 103 haveGICv3CPUInterface = true; 104 } 105 106 // Initial rename mode depends on highestEL 107 const_cast<Enums::VecRegRenameMode&>(_vecRegRenameMode) = 108 highestELIs64 ? Enums::Full : Enums::Elem; 109 110 initializeMiscRegMetadata(); 111 preUnflattenMiscReg(); 112 113 clear(); 114} 115 116std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS); 117 118const ArmISAParams * 119ISA::params() const 120{ 121 return dynamic_cast<const Params *>(_params); 122} 123 124void 125ISA::clear() 126{ 127 const Params *p(params()); 128 129 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 130 memset(miscRegs, 0, sizeof(miscRegs)); 131 132 initID32(p); 133 134 // We always initialize AArch64 ID registers even 135 // if we are in AArch32. This is done since if we 136 // are in SE mode we don't know if our ArmProcess is 137 // AArch32 or AArch64 138 initID64(p); 139 140 // Start with an event in the mailbox 141 miscRegs[MISCREG_SEV_MAILBOX] = 1; 142 143 // Separate Instruction and Data TLBs 144 miscRegs[MISCREG_TLBTR] = 1; 145 146 MVFR0 mvfr0 = 0; 147 mvfr0.advSimdRegisters = 2; 148 mvfr0.singlePrecision = 2; 149 mvfr0.doublePrecision = 2; 150 mvfr0.vfpExceptionTrapping = 0; 151 mvfr0.divide = 1; 152 mvfr0.squareRoot = 1; 153 mvfr0.shortVectors = 1; 154 mvfr0.roundingModes = 1; 155 miscRegs[MISCREG_MVFR0] = mvfr0; 156 157 MVFR1 mvfr1 = 0; 158 mvfr1.flushToZero = 1; 159 mvfr1.defaultNaN = 1; 160 mvfr1.advSimdLoadStore = 1; 161 mvfr1.advSimdInteger = 1; 162 mvfr1.advSimdSinglePrecision = 1; 163 mvfr1.advSimdHalfPrecision = 1; 164 mvfr1.vfpHalfPrecision = 1; 165 miscRegs[MISCREG_MVFR1] = mvfr1; 166 167 // Reset values of PRRR and NMRR are implementation dependent 168 169 // @todo: PRRR and NMRR in secure state? 170 miscRegs[MISCREG_PRRR_NS] = 171 (1 << 19) | // 19 172 (0 << 18) | // 18 173 (0 << 17) | // 17 174 (1 << 16) | // 16 175 (2 << 14) | // 15:14 176 (0 << 12) | // 13:12 177 (2 << 10) | // 11:10 178 (2 << 8) | // 9:8 179 (2 << 6) | // 7:6 180 (2 << 4) | // 5:4 181 (1 << 2) | // 3:2 182 0; // 1:0 183 184 miscRegs[MISCREG_NMRR_NS] = 185 (1 << 30) | // 31:30 186 (0 << 26) | // 27:26 187 (0 << 24) | // 25:24 188 (3 << 22) | // 23:22 189 (2 << 20) | // 21:20 190 (0 << 18) | // 19:18 191 (0 << 16) | // 17:16 192 (1 << 14) | // 15:14 193 (0 << 12) | // 13:12 194 (2 << 10) | // 11:10 195 (0 << 8) | // 9:8 196 (3 << 6) | // 7:6 197 (2 << 4) | // 5:4 198 (0 << 2) | // 3:2 199 0; // 1:0 200 201 if (FullSystem && system->highestELIs64()) { 202 // Initialize AArch64 state 203 clear64(p); 204 return; 205 } 206 207 // Initialize AArch32 state... 208 clear32(p, sctlr_rst); 209} 210 211void 212ISA::clear32(const ArmISAParams *p, const SCTLR &sctlr_rst) 213{ 214 CPSR cpsr = 0; 215 cpsr.mode = MODE_USER; 216 217 if (FullSystem) { 218 miscRegs[MISCREG_MVBAR] = system->resetAddr(); 219 } 220 221 miscRegs[MISCREG_CPSR] = cpsr; 222 updateRegMap(cpsr); 223 224 SCTLR sctlr = 0; 225 sctlr.te = (bool) sctlr_rst.te; 226 sctlr.nmfi = (bool) sctlr_rst.nmfi; 227 sctlr.v = (bool) sctlr_rst.v; 228 sctlr.u = 1; 229 sctlr.xp = 1; 230 sctlr.rao2 = 1; 231 sctlr.rao3 = 1; 232 sctlr.rao4 = 0xf; // SCTLR[6:3] 233 sctlr.uci = 1; 234 sctlr.dze = 1; 235 miscRegs[MISCREG_SCTLR_NS] = sctlr; 236 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 237 miscRegs[MISCREG_HCPTR] = 0; 238 239 miscRegs[MISCREG_CPACR] = 0; 240 241 miscRegs[MISCREG_FPSID] = p->fpsid; 242 243 if (haveLPAE) { 244 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 245 ttbcr.eae = 0; 246 miscRegs[MISCREG_TTBCR_NS] = ttbcr; 247 // Enforce consistency with system-level settings 248 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 249 } 250 251 if (haveSecurity) { 252 miscRegs[MISCREG_SCTLR_S] = sctlr; 253 miscRegs[MISCREG_SCR] = 0; 254 miscRegs[MISCREG_VBAR_S] = 0; 255 } else { 256 // we're always non-secure 257 miscRegs[MISCREG_SCR] = 1; 258 } 259 260 //XXX We need to initialize the rest of the state. 261} 262 263void 264ISA::clear64(const ArmISAParams *p) 265{ 266 CPSR cpsr = 0; 267 Addr rvbar = system->resetAddr(); 268 switch (system->highestEL()) { 269 // Set initial EL to highest implemented EL using associated stack 270 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 271 // value 272 case EL3: 273 cpsr.mode = MODE_EL3H; 274 miscRegs[MISCREG_RVBAR_EL3] = rvbar; 275 break; 276 case EL2: 277 cpsr.mode = MODE_EL2H; 278 miscRegs[MISCREG_RVBAR_EL2] = rvbar; 279 break; 280 case EL1: 281 cpsr.mode = MODE_EL1H; 282 miscRegs[MISCREG_RVBAR_EL1] = rvbar; 283 break; 284 default: 285 panic("Invalid highest implemented exception level"); 286 break; 287 } 288 289 // Initialize rest of CPSR 290 cpsr.daif = 0xf; // Mask all interrupts 291 cpsr.ss = 0; 292 cpsr.il = 0; 293 miscRegs[MISCREG_CPSR] = cpsr; 294 updateRegMap(cpsr); 295 296 // Initialize other control registers 297 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 298 if (haveSecurity) { 299 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830; 300 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 301 } else if (haveVirtualization) { 302 // also MISCREG_SCTLR_EL2 (by mapping) 303 miscRegs[MISCREG_HSCTLR] = 0x30c50830; 304 } else { 305 // also MISCREG_SCTLR_EL1 (by mapping) 306 miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init 307 // Always non-secure 308 miscRegs[MISCREG_SCR_EL3] = 1; 309 } 310} 311 312void 313ISA::initID32(const ArmISAParams *p) 314{ 315 // Initialize configurable default values 316 miscRegs[MISCREG_MIDR] = p->midr; 317 miscRegs[MISCREG_MIDR_EL1] = p->midr; 318 miscRegs[MISCREG_VPIDR] = p->midr; 319 320 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 321 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 322 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 323 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 324 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 325 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 326 327 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 328 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 329 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 330 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 331 332 miscRegs[MISCREG_ID_ISAR5] = insertBits( 333 miscRegs[MISCREG_ID_ISAR5], 19, 4, 334 haveCrypto ? 0x1112 : 0x0); 335} 336 337void 338ISA::initID64(const ArmISAParams *p) 339{ 340 // Initialize configurable id registers 341 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 342 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 343 miscRegs[MISCREG_ID_AA64DFR0_EL1] = 344 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 345 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 346 347 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 348 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 349 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 350 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 351 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 352 miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p->id_aa64mmfr2_el1; 353 354 miscRegs[MISCREG_ID_DFR0_EL1] = 355 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 356 357 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 358 359 // Enforce consistency with system-level settings... 360 361 // EL3 362 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 363 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 364 haveSecurity ? 0x2 : 0x0); 365 // EL2 366 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 367 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 368 haveVirtualization ? 0x2 : 0x0); 369 // Large ASID support 370 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 371 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 372 haveLargeAsid64 ? 0x2 : 0x0); 373 // Physical address size 374 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 375 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 376 encodePhysAddrRange64(physAddrRange)); 377 // Crypto 378 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits( 379 miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4, 380 haveCrypto ? 0x1112 : 0x0); 381} 382 383void 384ISA::startup(ThreadContext *tc) 385{ 386 pmu->setThreadContext(tc); 387 388 if (system) { 389 Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC()); 390 if (gicv3) { 391 gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId())); 392 gicv3CpuInterface->setISA(this); 393 } 394 } 395} 396 397 398RegVal 399ISA::readMiscRegNoEffect(int misc_reg) const 400{ 401 assert(misc_reg < NumMiscRegs); 402 403 const auto ® = lookUpMiscReg[misc_reg]; // bit masks 404 const auto &map = getMiscIndices(misc_reg); 405 int lower = map.first, upper = map.second; 406 // NB!: apply architectural masks according to desired register, 407 // despite possibly getting value from different (mapped) register. 408 auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32)) 409 |(miscRegs[upper] << 32)); 410 if (val & reg.res0()) { 411 DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n", 412 miscRegName[misc_reg], val & reg.res0()); 413 } 414 if ((val & reg.res1()) != reg.res1()) { 415 DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n", 416 miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1()); 417 } 418 return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao 419} 420 421 422RegVal 423ISA::readMiscReg(int misc_reg, ThreadContext *tc) 424{ 425 CPSR cpsr = 0; 426 PCState pc = 0; 427 SCR scr = 0; 428 429 if (misc_reg == MISCREG_CPSR) { 430 cpsr = miscRegs[misc_reg]; 431 pc = tc->pcState(); 432 cpsr.j = pc.jazelle() ? 1 : 0; 433 cpsr.t = pc.thumb() ? 1 : 0; 434 return cpsr; 435 } 436 437#ifndef NDEBUG 438 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 439 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 440 warn("Unimplemented system register %s read.\n", 441 miscRegName[misc_reg]); 442 else 443 panic("Unimplemented system register %s read.\n", 444 miscRegName[misc_reg]); 445 } 446#endif 447 448 switch (unflattenMiscReg(misc_reg)) { 449 case MISCREG_HCR: 450 { 451 if (!haveVirtualization) 452 return 0; 453 else 454 return readMiscRegNoEffect(MISCREG_HCR); 455 } 456 case MISCREG_CPACR: 457 { 458 const uint32_t ones = (uint32_t)(-1); 459 CPACR cpacrMask = 0; 460 // Only cp10, cp11, and ase are implemented, nothing else should 461 // be readable? (straight copy from the write code) 462 cpacrMask.cp10 = ones; 463 cpacrMask.cp11 = ones; 464 cpacrMask.asedis = ones; 465 466 // Security Extensions may limit the readability of CPACR 467 if (haveSecurity) { 468 scr = readMiscRegNoEffect(MISCREG_SCR); 469 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 470 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 471 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 472 // NB: Skipping the full loop, here 473 if (!nsacr.cp10) cpacrMask.cp10 = 0; 474 if (!nsacr.cp11) cpacrMask.cp11 = 0; 475 } 476 } 477 RegVal val = readMiscRegNoEffect(MISCREG_CPACR); 478 val &= cpacrMask; 479 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 480 miscRegName[misc_reg], val); 481 return val; 482 } 483 case MISCREG_MPIDR: 484 case MISCREG_MPIDR_EL1: 485 return readMPIDR(system, tc); 486 case MISCREG_VMPIDR: 487 case MISCREG_VMPIDR_EL2: 488 // top bit defined as RES1 489 return readMiscRegNoEffect(misc_reg) | 0x80000000; 490 case MISCREG_ID_AFR0: // not implemented, so alias MIDR 491 case MISCREG_REVIDR: // not implemented, so alias MIDR 492 case MISCREG_MIDR: 493 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 494 scr = readMiscRegNoEffect(MISCREG_SCR); 495 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 496 return readMiscRegNoEffect(misc_reg); 497 } else { 498 return readMiscRegNoEffect(MISCREG_VPIDR); 499 } 500 break; 501 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 502 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 503 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 504 case MISCREG_AIDR: // AUX ID set to 0 505 case MISCREG_TCMTR: // No TCM's 506 return 0; 507 508 case MISCREG_CLIDR: 509 warn_once("The clidr register always reports 0 caches.\n"); 510 warn_once("clidr LoUIS field of 0b001 to match current " 511 "ARM implementations.\n"); 512 return 0x00200000; 513 case MISCREG_CCSIDR: 514 warn_once("The ccsidr register isn't implemented and " 515 "always reads as 0.\n"); 516 break; 517 case MISCREG_CTR: // AArch32, ARMv7, top bit set 518 case MISCREG_CTR_EL0: // AArch64 519 { 520 //all caches have the same line size in gem5 521 //4 byte words in ARM 522 unsigned lineSizeWords = 523 tc->getSystemPtr()->cacheLineSize() / 4; 524 unsigned log2LineSizeWords = 0; 525 526 while (lineSizeWords >>= 1) { 527 ++log2LineSizeWords; 528 } 529 530 CTR ctr = 0; 531 //log2 of minimun i-cache line size (words) 532 ctr.iCacheLineSize = log2LineSizeWords; 533 //b11 - gem5 uses pipt 534 ctr.l1IndexPolicy = 0x3; 535 //log2 of minimum d-cache line size (words) 536 ctr.dCacheLineSize = log2LineSizeWords; 537 //log2 of max reservation size (words) 538 ctr.erg = log2LineSizeWords; 539 //log2 of max writeback size (words) 540 ctr.cwg = log2LineSizeWords; 541 //b100 - gem5 format is ARMv7 542 ctr.format = 0x4; 543 544 return ctr; 545 } 546 case MISCREG_ACTLR: 547 warn("Not doing anything for miscreg ACTLR\n"); 548 break; 549 550 case MISCREG_PMXEVTYPER_PMCCFILTR: 551 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 552 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 553 case MISCREG_PMCR ... MISCREG_PMOVSSET: 554 return pmu->readMiscReg(misc_reg); 555 556 case MISCREG_CPSR_Q: 557 panic("shouldn't be reading this register seperately\n"); 558 case MISCREG_FPSCR_QC: 559 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 560 case MISCREG_FPSCR_EXC: 561 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 562 case MISCREG_FPSR: 563 { 564 const uint32_t ones = (uint32_t)(-1); 565 FPSCR fpscrMask = 0; 566 fpscrMask.ioc = ones; 567 fpscrMask.dzc = ones; 568 fpscrMask.ofc = ones; 569 fpscrMask.ufc = ones; 570 fpscrMask.ixc = ones; 571 fpscrMask.idc = ones; 572 fpscrMask.qc = ones; 573 fpscrMask.v = ones; 574 fpscrMask.c = ones; 575 fpscrMask.z = ones; 576 fpscrMask.n = ones; 577 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 578 } 579 case MISCREG_FPCR: 580 { 581 const uint32_t ones = (uint32_t)(-1); 582 FPSCR fpscrMask = 0; 583 fpscrMask.len = ones; 584 fpscrMask.stride = ones; 585 fpscrMask.rMode = ones; 586 fpscrMask.fz = ones; 587 fpscrMask.dn = ones; 588 fpscrMask.ahp = ones; 589 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 590 } 591 case MISCREG_NZCV: 592 { 593 CPSR cpsr = 0; 594 cpsr.nz = tc->readCCReg(CCREG_NZ); 595 cpsr.c = tc->readCCReg(CCREG_C); 596 cpsr.v = tc->readCCReg(CCREG_V); 597 return cpsr; 598 } 599 case MISCREG_DAIF: 600 { 601 CPSR cpsr = 0; 602 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 603 return cpsr; 604 } 605 case MISCREG_SP_EL0: 606 { 607 return tc->readIntReg(INTREG_SP0); 608 } 609 case MISCREG_SP_EL1: 610 { 611 return tc->readIntReg(INTREG_SP1); 612 } 613 case MISCREG_SP_EL2: 614 { 615 return tc->readIntReg(INTREG_SP2); 616 } 617 case MISCREG_SPSEL: 618 { 619 return miscRegs[MISCREG_CPSR] & 0x1; 620 } 621 case MISCREG_CURRENTEL: 622 { 623 return miscRegs[MISCREG_CPSR] & 0xc; 624 } 625 case MISCREG_L2CTLR: 626 { 627 // mostly unimplemented, just set NumCPUs field from sim and return 628 L2CTLR l2ctlr = 0; 629 // b00:1CPU to b11:4CPUs 630 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 631 return l2ctlr; 632 } 633 case MISCREG_DBGDIDR: 634 /* For now just implement the version number. 635 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 636 */ 637 return 0x5 << 16; 638 case MISCREG_DBGDSCRint: 639 return 0; 640 case MISCREG_ISR: 641 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 642 readMiscRegNoEffect(MISCREG_HCR), 643 readMiscRegNoEffect(MISCREG_CPSR), 644 readMiscRegNoEffect(MISCREG_SCR)); 645 case MISCREG_ISR_EL1: 646 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 647 readMiscRegNoEffect(MISCREG_HCR_EL2), 648 readMiscRegNoEffect(MISCREG_CPSR), 649 readMiscRegNoEffect(MISCREG_SCR_EL3)); 650 case MISCREG_DCZID_EL0: 651 return 0x04; // DC ZVA clear 64-byte chunks 652 case MISCREG_HCPTR: 653 { 654 RegVal val = readMiscRegNoEffect(misc_reg); 655 // The trap bit associated with CP14 is defined as RAZ 656 val &= ~(1 << 14); 657 // If a CP bit in NSACR is 0 then the corresponding bit in 658 // HCPTR is RAO/WI 659 bool secure_lookup = haveSecurity && 660 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 661 readMiscRegNoEffect(MISCREG_CPSR)); 662 if (!secure_lookup) { 663 RegVal mask = readMiscRegNoEffect(MISCREG_NSACR); 664 val |= (mask ^ 0x7FFF) & 0xBFFF; 665 } 666 // Set the bits for unimplemented coprocessors to RAO/WI 667 val |= 0x33FF; 668 return (val); 669 } 670 case MISCREG_HDFAR: // alias for secure DFAR 671 return readMiscRegNoEffect(MISCREG_DFAR_S); 672 case MISCREG_HIFAR: // alias for secure IFAR 673 return readMiscRegNoEffect(MISCREG_IFAR_S); 674 675 case MISCREG_ID_PFR0: 676 // !ThumbEE | !Jazelle | Thumb | ARM 677 return 0x00000031; 678 case MISCREG_ID_PFR1: 679 { // Timer | Virti | !M Profile | TrustZone | ARMv4 680 bool haveTimer = (system->getGenericTimer() != NULL); 681 return 0x00000001 682 | (haveSecurity ? 0x00000010 : 0x0) 683 | (haveVirtualization ? 0x00001000 : 0x0) 684 | (haveTimer ? 0x00010000 : 0x0); 685 } 686 case MISCREG_ID_AA64PFR0_EL1: 687 return 0x0000000000000002 | // AArch{64,32} supported at EL0 688 0x0000000000000020 | // EL1 689 (haveVirtualization ? 0x0000000000000200 : 0) | // EL2 690 (haveSecurity ? 0x0000000000002000 : 0) | // EL3 691 (haveGICv3CPUInterface ? 0x0000000001000000 : 0); 692 case MISCREG_ID_AA64PFR1_EL1: 693 return 0; // bits [63:0] RES0 (reserved for future use) 694 695 // Generic Timer registers 696 case MISCREG_CNTHV_CTL_EL2: 697 case MISCREG_CNTHV_CVAL_EL2: 698 case MISCREG_CNTHV_TVAL_EL2: 699 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 700 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 701 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 702 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 703 return getGenericTimer(tc).readMiscReg(misc_reg); 704 705 case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3: 706 case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2: 707 return getGICv3CPUInterface(tc).readMiscReg(misc_reg); 708 709 default: 710 break; 711 712 } 713 return readMiscRegNoEffect(misc_reg); 714} 715 716void 717ISA::setMiscRegNoEffect(int misc_reg, RegVal val) 718{ 719 assert(misc_reg < NumMiscRegs); 720 721 const auto ® = lookUpMiscReg[misc_reg]; // bit masks 722 const auto &map = getMiscIndices(misc_reg); 723 int lower = map.first, upper = map.second; 724 725 auto v = (val & ~reg.wi()) | reg.rao(); 726 if (upper > 0) { 727 miscRegs[lower] = bits(v, 31, 0); 728 miscRegs[upper] = bits(v, 63, 32); 729 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 730 misc_reg, lower, upper, v); 731 } else { 732 miscRegs[lower] = v; 733 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 734 misc_reg, lower, v); 735 } 736} 737 738void 739ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) 740{ 741 742 RegVal newVal = val; 743 bool secure_lookup; 744 SCR scr; 745 746 if (misc_reg == MISCREG_CPSR) { 747 updateRegMap(val); 748 749 750 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 751 int old_mode = old_cpsr.mode; 752 CPSR cpsr = val; 753 if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) { 754 getITBPtr(tc)->invalidateMiscReg(); 755 getDTBPtr(tc)->invalidateMiscReg(); 756 } 757 758 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 759 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 760 PCState pc = tc->pcState(); 761 pc.nextThumb(cpsr.t); 762 pc.nextJazelle(cpsr.j); 763 pc.illegalExec(cpsr.il == 1); 764 765 // Follow slightly different semantics if a CheckerCPU object 766 // is connected 767 CheckerCPU *checker = tc->getCheckerCpuPtr(); 768 if (checker) { 769 tc->pcStateNoRecord(pc); 770 } else { 771 tc->pcState(pc); 772 } 773 } else { 774#ifndef NDEBUG 775 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 776 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 777 warn("Unimplemented system register %s write with %#x.\n", 778 miscRegName[misc_reg], val); 779 else 780 panic("Unimplemented system register %s write with %#x.\n", 781 miscRegName[misc_reg], val); 782 } 783#endif 784 switch (unflattenMiscReg(misc_reg)) { 785 case MISCREG_CPACR: 786 { 787 788 const uint32_t ones = (uint32_t)(-1); 789 CPACR cpacrMask = 0; 790 // Only cp10, cp11, and ase are implemented, nothing else should 791 // be writable 792 cpacrMask.cp10 = ones; 793 cpacrMask.cp11 = ones; 794 cpacrMask.asedis = ones; 795 796 // Security Extensions may limit the writability of CPACR 797 if (haveSecurity) { 798 scr = readMiscRegNoEffect(MISCREG_SCR); 799 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 800 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 801 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 802 // NB: Skipping the full loop, here 803 if (!nsacr.cp10) cpacrMask.cp10 = 0; 804 if (!nsacr.cp11) cpacrMask.cp11 = 0; 805 } 806 } 807 808 RegVal old_val = readMiscRegNoEffect(MISCREG_CPACR); 809 newVal &= cpacrMask; 810 newVal |= old_val & ~cpacrMask; 811 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 812 miscRegName[misc_reg], newVal); 813 } 814 break; 815 case MISCREG_CPTR_EL2: 816 { 817 const uint32_t ones = (uint32_t)(-1); 818 CPTR cptrMask = 0; 819 cptrMask.tcpac = ones; 820 cptrMask.tta = ones; 821 cptrMask.tfp = ones; 822 newVal &= cptrMask; 823 cptrMask = 0; 824 cptrMask.res1_13_12_el2 = ones; 825 cptrMask.res1_9_0_el2 = ones; 826 newVal |= cptrMask; 827 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 828 miscRegName[misc_reg], newVal); 829 } 830 break; 831 case MISCREG_CPTR_EL3: 832 { 833 const uint32_t ones = (uint32_t)(-1); 834 CPTR cptrMask = 0; 835 cptrMask.tcpac = ones; 836 cptrMask.tta = ones; 837 cptrMask.tfp = ones; 838 newVal &= cptrMask; 839 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 840 miscRegName[misc_reg], newVal); 841 } 842 break; 843 case MISCREG_CSSELR: 844 warn_once("The csselr register isn't implemented.\n"); 845 return; 846 847 case MISCREG_DC_ZVA_Xt: 848 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 849 return; 850 851 case MISCREG_FPSCR: 852 { 853 const uint32_t ones = (uint32_t)(-1); 854 FPSCR fpscrMask = 0; 855 fpscrMask.ioc = ones; 856 fpscrMask.dzc = ones; 857 fpscrMask.ofc = ones; 858 fpscrMask.ufc = ones; 859 fpscrMask.ixc = ones; 860 fpscrMask.idc = ones; 861 fpscrMask.ioe = ones; 862 fpscrMask.dze = ones; 863 fpscrMask.ofe = ones; 864 fpscrMask.ufe = ones; 865 fpscrMask.ixe = ones; 866 fpscrMask.ide = ones; 867 fpscrMask.len = ones; 868 fpscrMask.stride = ones; 869 fpscrMask.rMode = ones; 870 fpscrMask.fz = ones; 871 fpscrMask.dn = ones; 872 fpscrMask.ahp = ones; 873 fpscrMask.qc = ones; 874 fpscrMask.v = ones; 875 fpscrMask.c = ones; 876 fpscrMask.z = ones; 877 fpscrMask.n = ones; 878 newVal = (newVal & (uint32_t)fpscrMask) | 879 (readMiscRegNoEffect(MISCREG_FPSCR) & 880 ~(uint32_t)fpscrMask); 881 tc->getDecoderPtr()->setContext(newVal); 882 } 883 break; 884 case MISCREG_FPSR: 885 { 886 const uint32_t ones = (uint32_t)(-1); 887 FPSCR fpscrMask = 0; 888 fpscrMask.ioc = ones; 889 fpscrMask.dzc = ones; 890 fpscrMask.ofc = ones; 891 fpscrMask.ufc = ones; 892 fpscrMask.ixc = ones; 893 fpscrMask.idc = ones; 894 fpscrMask.qc = ones; 895 fpscrMask.v = ones; 896 fpscrMask.c = ones; 897 fpscrMask.z = ones; 898 fpscrMask.n = ones; 899 newVal = (newVal & (uint32_t)fpscrMask) | 900 (readMiscRegNoEffect(MISCREG_FPSCR) & 901 ~(uint32_t)fpscrMask); 902 misc_reg = MISCREG_FPSCR; 903 } 904 break; 905 case MISCREG_FPCR: 906 { 907 const uint32_t ones = (uint32_t)(-1); 908 FPSCR fpscrMask = 0; 909 fpscrMask.len = ones; 910 fpscrMask.stride = ones; 911 fpscrMask.rMode = ones; 912 fpscrMask.fz = ones; 913 fpscrMask.dn = ones; 914 fpscrMask.ahp = ones; 915 newVal = (newVal & (uint32_t)fpscrMask) | 916 (readMiscRegNoEffect(MISCREG_FPSCR) & 917 ~(uint32_t)fpscrMask); 918 misc_reg = MISCREG_FPSCR; 919 } 920 break; 921 case MISCREG_CPSR_Q: 922 { 923 assert(!(newVal & ~CpsrMaskQ)); 924 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 925 misc_reg = MISCREG_CPSR; 926 } 927 break; 928 case MISCREG_FPSCR_QC: 929 { 930 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 931 (newVal & FpscrQcMask); 932 misc_reg = MISCREG_FPSCR; 933 } 934 break; 935 case MISCREG_FPSCR_EXC: 936 { 937 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 938 (newVal & FpscrExcMask); 939 misc_reg = MISCREG_FPSCR; 940 } 941 break; 942 case MISCREG_FPEXC: 943 { 944 // vfpv3 architecture, section B.6.1 of DDI04068 945 // bit 29 - valid only if fpexc[31] is 0 946 const uint32_t fpexcMask = 0x60000000; 947 newVal = (newVal & fpexcMask) | 948 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 949 } 950 break; 951 case MISCREG_HCR: 952 { 953 if (!haveVirtualization) 954 return; 955 } 956 break; 957 case MISCREG_IFSR: 958 { 959 // ARM ARM (ARM DDI 0406C.b) B4.1.96 960 const uint32_t ifsrMask = 961 mask(31, 13) | mask(11, 11) | mask(8, 6); 962 newVal = newVal & ~ifsrMask; 963 } 964 break; 965 case MISCREG_DFSR: 966 { 967 // ARM ARM (ARM DDI 0406C.b) B4.1.52 968 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 969 newVal = newVal & ~dfsrMask; 970 } 971 break; 972 case MISCREG_AMAIR0: 973 case MISCREG_AMAIR1: 974 { 975 // ARM ARM (ARM DDI 0406C.b) B4.1.5 976 // Valid only with LPAE 977 if (!haveLPAE) 978 return; 979 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 980 } 981 break; 982 case MISCREG_SCR: 983 getITBPtr(tc)->invalidateMiscReg(); 984 getDTBPtr(tc)->invalidateMiscReg(); 985 break; 986 case MISCREG_SCTLR: 987 { 988 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 989 scr = readMiscRegNoEffect(MISCREG_SCR); 990 991 MiscRegIndex sctlr_idx; 992 if (haveSecurity && !highestELIs64 && !scr.ns) { 993 sctlr_idx = MISCREG_SCTLR_S; 994 } else { 995 sctlr_idx = MISCREG_SCTLR_NS; 996 } 997 998 SCTLR sctlr = miscRegs[sctlr_idx]; 999 SCTLR new_sctlr = newVal; 1000 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 1001 miscRegs[sctlr_idx] = (RegVal)new_sctlr; 1002 getITBPtr(tc)->invalidateMiscReg(); 1003 getDTBPtr(tc)->invalidateMiscReg(); 1004 } 1005 case MISCREG_MIDR: 1006 case MISCREG_ID_PFR0: 1007 case MISCREG_ID_PFR1: 1008 case MISCREG_ID_DFR0: 1009 case MISCREG_ID_MMFR0: 1010 case MISCREG_ID_MMFR1: 1011 case MISCREG_ID_MMFR2: 1012 case MISCREG_ID_MMFR3: 1013 case MISCREG_ID_ISAR0: 1014 case MISCREG_ID_ISAR1: 1015 case MISCREG_ID_ISAR2: 1016 case MISCREG_ID_ISAR3: 1017 case MISCREG_ID_ISAR4: 1018 case MISCREG_ID_ISAR5: 1019 1020 case MISCREG_MPIDR: 1021 case MISCREG_FPSID: 1022 case MISCREG_TLBTR: 1023 case MISCREG_MVFR0: 1024 case MISCREG_MVFR1: 1025 1026 case MISCREG_ID_AA64AFR0_EL1: 1027 case MISCREG_ID_AA64AFR1_EL1: 1028 case MISCREG_ID_AA64DFR0_EL1: 1029 case MISCREG_ID_AA64DFR1_EL1: 1030 case MISCREG_ID_AA64ISAR0_EL1: 1031 case MISCREG_ID_AA64ISAR1_EL1: 1032 case MISCREG_ID_AA64MMFR0_EL1: 1033 case MISCREG_ID_AA64MMFR1_EL1: 1034 case MISCREG_ID_AA64MMFR2_EL1: 1035 case MISCREG_ID_AA64PFR0_EL1: 1036 case MISCREG_ID_AA64PFR1_EL1: 1037 // ID registers are constants. 1038 return; 1039 1040 // TLB Invalidate All 1041 case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 1042 { 1043 assert32(tc); 1044 scr = readMiscReg(MISCREG_SCR, tc); 1045 1046 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1047 tlbiOp(tc); 1048 return; 1049 } 1050 // TLB Invalidate All, Inner Shareable 1051 case MISCREG_TLBIALLIS: 1052 { 1053 assert32(tc); 1054 scr = readMiscReg(MISCREG_SCR, tc); 1055 1056 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1057 tlbiOp.broadcast(tc); 1058 return; 1059 } 1060 // Instruction TLB Invalidate All 1061 case MISCREG_ITLBIALL: 1062 { 1063 assert32(tc); 1064 scr = readMiscReg(MISCREG_SCR, tc); 1065 1066 ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1067 tlbiOp(tc); 1068 return; 1069 } 1070 // Data TLB Invalidate All 1071 case MISCREG_DTLBIALL: 1072 { 1073 assert32(tc); 1074 scr = readMiscReg(MISCREG_SCR, tc); 1075 1076 DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1077 tlbiOp(tc); 1078 return; 1079 } 1080 // TLB Invalidate by VA 1081 // mcr tlbimval(is) is invalidating all matching entries 1082 // regardless of the level of lookup, since in gem5 we cache 1083 // in the tlb the last level of lookup only. 1084 case MISCREG_TLBIMVA: 1085 case MISCREG_TLBIMVAL: 1086 { 1087 assert32(tc); 1088 scr = readMiscReg(MISCREG_SCR, tc); 1089 1090 TLBIMVA tlbiOp(EL1, 1091 haveSecurity && !scr.ns, 1092 mbits(newVal, 31, 12), 1093 bits(newVal, 7,0)); 1094 1095 tlbiOp(tc); 1096 return; 1097 } 1098 // TLB Invalidate by VA, Inner Shareable 1099 case MISCREG_TLBIMVAIS: 1100 case MISCREG_TLBIMVALIS: 1101 { 1102 assert32(tc); 1103 scr = readMiscReg(MISCREG_SCR, tc); 1104 1105 TLBIMVA tlbiOp(EL1, 1106 haveSecurity && !scr.ns, 1107 mbits(newVal, 31, 12), 1108 bits(newVal, 7,0)); 1109 1110 tlbiOp.broadcast(tc); 1111 return; 1112 } 1113 // TLB Invalidate by ASID match 1114 case MISCREG_TLBIASID: 1115 { 1116 assert32(tc); 1117 scr = readMiscReg(MISCREG_SCR, tc); 1118 1119 TLBIASID tlbiOp(EL1, 1120 haveSecurity && !scr.ns, 1121 bits(newVal, 7,0)); 1122 1123 tlbiOp(tc); 1124 return; 1125 } 1126 // TLB Invalidate by ASID match, Inner Shareable 1127 case MISCREG_TLBIASIDIS: 1128 { 1129 assert32(tc); 1130 scr = readMiscReg(MISCREG_SCR, tc); 1131 1132 TLBIASID tlbiOp(EL1, 1133 haveSecurity && !scr.ns, 1134 bits(newVal, 7,0)); 1135 1136 tlbiOp.broadcast(tc); 1137 return; 1138 } 1139 // mcr tlbimvaal(is) is invalidating all matching entries 1140 // regardless of the level of lookup, since in gem5 we cache 1141 // in the tlb the last level of lookup only. 1142 // TLB Invalidate by VA, All ASID 1143 case MISCREG_TLBIMVAA: 1144 case MISCREG_TLBIMVAAL: 1145 { 1146 assert32(tc); 1147 scr = readMiscReg(MISCREG_SCR, tc); 1148 1149 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1150 mbits(newVal, 31,12), false); 1151 1152 tlbiOp(tc); 1153 return; 1154 } 1155 // TLB Invalidate by VA, All ASID, Inner Shareable 1156 case MISCREG_TLBIMVAAIS: 1157 case MISCREG_TLBIMVAALIS: 1158 { 1159 assert32(tc); 1160 scr = readMiscReg(MISCREG_SCR, tc); 1161 1162 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1163 mbits(newVal, 31,12), false); 1164 1165 tlbiOp.broadcast(tc); 1166 return; 1167 } 1168 // mcr tlbimvalh(is) is invalidating all matching entries 1169 // regardless of the level of lookup, since in gem5 we cache 1170 // in the tlb the last level of lookup only. 1171 // TLB Invalidate by VA, Hyp mode 1172 case MISCREG_TLBIMVAH: 1173 case MISCREG_TLBIMVALH: 1174 { 1175 assert32(tc); 1176 scr = readMiscReg(MISCREG_SCR, tc); 1177 1178 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1179 mbits(newVal, 31,12), true); 1180 1181 tlbiOp(tc); 1182 return; 1183 } 1184 // TLB Invalidate by VA, Hyp mode, Inner Shareable 1185 case MISCREG_TLBIMVAHIS: 1186 case MISCREG_TLBIMVALHIS: 1187 { 1188 assert32(tc); 1189 scr = readMiscReg(MISCREG_SCR, tc); 1190 1191 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1192 mbits(newVal, 31,12), true); 1193 1194 tlbiOp.broadcast(tc); 1195 return; 1196 } 1197 // mcr tlbiipas2l(is) is invalidating all matching entries 1198 // regardless of the level of lookup, since in gem5 we cache 1199 // in the tlb the last level of lookup only. 1200 // TLB Invalidate by Intermediate Physical Address, Stage 2 1201 case MISCREG_TLBIIPAS2: 1202 case MISCREG_TLBIIPAS2L: 1203 { 1204 assert32(tc); 1205 scr = readMiscReg(MISCREG_SCR, tc); 1206 1207 TLBIIPA tlbiOp(EL1, 1208 haveSecurity && !scr.ns, 1209 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1210 1211 tlbiOp(tc); 1212 return; 1213 } 1214 // TLB Invalidate by Intermediate Physical Address, Stage 2, 1215 // Inner Shareable 1216 case MISCREG_TLBIIPAS2IS: 1217 case MISCREG_TLBIIPAS2LIS: 1218 { 1219 assert32(tc); 1220 scr = readMiscReg(MISCREG_SCR, tc); 1221 1222 TLBIIPA tlbiOp(EL1, 1223 haveSecurity && !scr.ns, 1224 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1225 1226 tlbiOp.broadcast(tc); 1227 return; 1228 } 1229 // Instruction TLB Invalidate by VA 1230 case MISCREG_ITLBIMVA: 1231 { 1232 assert32(tc); 1233 scr = readMiscReg(MISCREG_SCR, tc); 1234 1235 ITLBIMVA tlbiOp(EL1, 1236 haveSecurity && !scr.ns, 1237 mbits(newVal, 31, 12), 1238 bits(newVal, 7,0)); 1239 1240 tlbiOp(tc); 1241 return; 1242 } 1243 // Data TLB Invalidate by VA 1244 case MISCREG_DTLBIMVA: 1245 { 1246 assert32(tc); 1247 scr = readMiscReg(MISCREG_SCR, tc); 1248 1249 DTLBIMVA tlbiOp(EL1, 1250 haveSecurity && !scr.ns, 1251 mbits(newVal, 31, 12), 1252 bits(newVal, 7,0)); 1253 1254 tlbiOp(tc); 1255 return; 1256 } 1257 // Instruction TLB Invalidate by ASID match 1258 case MISCREG_ITLBIASID: 1259 { 1260 assert32(tc); 1261 scr = readMiscReg(MISCREG_SCR, tc); 1262 1263 ITLBIASID tlbiOp(EL1, 1264 haveSecurity && !scr.ns, 1265 bits(newVal, 7,0)); 1266 1267 tlbiOp(tc); 1268 return; 1269 } 1270 // Data TLB Invalidate by ASID match 1271 case MISCREG_DTLBIASID: 1272 { 1273 assert32(tc); 1274 scr = readMiscReg(MISCREG_SCR, tc); 1275 1276 DTLBIASID tlbiOp(EL1, 1277 haveSecurity && !scr.ns, 1278 bits(newVal, 7,0)); 1279 1280 tlbiOp(tc); 1281 return; 1282 } 1283 // TLB Invalidate All, Non-Secure Non-Hyp 1284 case MISCREG_TLBIALLNSNH: 1285 { 1286 assert32(tc); 1287 1288 TLBIALLN tlbiOp(EL1, false); 1289 tlbiOp(tc); 1290 return; 1291 } 1292 // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable 1293 case MISCREG_TLBIALLNSNHIS: 1294 { 1295 assert32(tc); 1296 1297 TLBIALLN tlbiOp(EL1, false); 1298 tlbiOp.broadcast(tc); 1299 return; 1300 } 1301 // TLB Invalidate All, Hyp mode 1302 case MISCREG_TLBIALLH: 1303 { 1304 assert32(tc); 1305 1306 TLBIALLN tlbiOp(EL1, true); 1307 tlbiOp(tc); 1308 return; 1309 } 1310 // TLB Invalidate All, Hyp mode, Inner Shareable 1311 case MISCREG_TLBIALLHIS: 1312 { 1313 assert32(tc); 1314 1315 TLBIALLN tlbiOp(EL1, true); 1316 tlbiOp.broadcast(tc); 1317 return; 1318 } 1319 // AArch64 TLB Invalidate All, EL3 1320 case MISCREG_TLBI_ALLE3: 1321 { 1322 assert64(tc); 1323 1324 TLBIALL tlbiOp(EL3, true); 1325 tlbiOp(tc); 1326 return; 1327 } 1328 // AArch64 TLB Invalidate All, EL3, Inner Shareable 1329 case MISCREG_TLBI_ALLE3IS: 1330 { 1331 assert64(tc); 1332 1333 TLBIALL tlbiOp(EL3, true); 1334 tlbiOp.broadcast(tc); 1335 return; 1336 } 1337 // AArch64 TLB Invalidate All, EL2, Inner Shareable 1338 case MISCREG_TLBI_ALLE2: 1339 case MISCREG_TLBI_ALLE2IS: 1340 { 1341 assert64(tc); 1342 scr = readMiscReg(MISCREG_SCR, tc); 1343 1344 TLBIALL tlbiOp(EL2, haveSecurity && !scr.ns); 1345 tlbiOp(tc); 1346 return; 1347 } 1348 // AArch64 TLB Invalidate All, EL1 1349 case MISCREG_TLBI_ALLE1: 1350 case MISCREG_TLBI_VMALLE1: 1351 case MISCREG_TLBI_VMALLS12E1: 1352 // @todo: handle VMID and stage 2 to enable Virtualization 1353 { 1354 assert64(tc); 1355 scr = readMiscReg(MISCREG_SCR, tc); 1356 1357 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1358 tlbiOp(tc); 1359 return; 1360 } 1361 // AArch64 TLB Invalidate All, EL1, Inner Shareable 1362 case MISCREG_TLBI_ALLE1IS: 1363 case MISCREG_TLBI_VMALLE1IS: 1364 case MISCREG_TLBI_VMALLS12E1IS: 1365 // @todo: handle VMID and stage 2 to enable Virtualization 1366 { 1367 assert64(tc); 1368 scr = readMiscReg(MISCREG_SCR, tc); 1369 1370 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1371 tlbiOp.broadcast(tc); 1372 return; 1373 } 1374 // VAEx(IS) and VALEx(IS) are the same because TLBs 1375 // only store entries 1376 // from the last level of translation table walks 1377 // @todo: handle VMID to enable Virtualization 1378 // AArch64 TLB Invalidate by VA, EL3 1379 case MISCREG_TLBI_VAE3_Xt: 1380 case MISCREG_TLBI_VALE3_Xt: 1381 { 1382 assert64(tc); 1383 1384 TLBIMVA tlbiOp(EL3, true, 1385 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1386 0xbeef); 1387 tlbiOp(tc); 1388 return; 1389 } 1390 // AArch64 TLB Invalidate by VA, EL3, Inner Shareable 1391 case MISCREG_TLBI_VAE3IS_Xt: 1392 case MISCREG_TLBI_VALE3IS_Xt: 1393 { 1394 assert64(tc); 1395 1396 TLBIMVA tlbiOp(EL3, true, 1397 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1398 0xbeef); 1399 1400 tlbiOp.broadcast(tc); 1401 return; 1402 } 1403 // AArch64 TLB Invalidate by VA, EL2 1404 case MISCREG_TLBI_VAE2_Xt: 1405 case MISCREG_TLBI_VALE2_Xt: 1406 { 1407 assert64(tc); 1408 scr = readMiscReg(MISCREG_SCR, tc); 1409 1410 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1411 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1412 0xbeef); 1413 tlbiOp(tc); 1414 return; 1415 } 1416 // AArch64 TLB Invalidate by VA, EL2, Inner Shareable 1417 case MISCREG_TLBI_VAE2IS_Xt: 1418 case MISCREG_TLBI_VALE2IS_Xt: 1419 { 1420 assert64(tc); 1421 scr = readMiscReg(MISCREG_SCR, tc); 1422 1423 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1424 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1425 0xbeef); 1426 1427 tlbiOp.broadcast(tc); 1428 return; 1429 } 1430 // AArch64 TLB Invalidate by VA, EL1 1431 case MISCREG_TLBI_VAE1_Xt: 1432 case MISCREG_TLBI_VALE1_Xt: 1433 { 1434 assert64(tc); 1435 scr = readMiscReg(MISCREG_SCR, tc); 1436 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1437 bits(newVal, 55, 48); 1438 1439 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1440 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1441 asid); 1442 1443 tlbiOp(tc); 1444 return; 1445 } 1446 // AArch64 TLB Invalidate by VA, EL1, Inner Shareable 1447 case MISCREG_TLBI_VAE1IS_Xt: 1448 case MISCREG_TLBI_VALE1IS_Xt: 1449 { 1450 assert64(tc); 1451 scr = readMiscReg(MISCREG_SCR, tc); 1452 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1453 bits(newVal, 55, 48); 1454 1455 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1456 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1457 asid); 1458 1459 tlbiOp.broadcast(tc); 1460 return; 1461 } 1462 // AArch64 TLB Invalidate by ASID, EL1 1463 // @todo: handle VMID to enable Virtualization 1464 case MISCREG_TLBI_ASIDE1_Xt: 1465 { 1466 assert64(tc); 1467 scr = readMiscReg(MISCREG_SCR, tc); 1468 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1469 bits(newVal, 55, 48); 1470 1471 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1472 tlbiOp(tc); 1473 return; 1474 } 1475 // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable 1476 case MISCREG_TLBI_ASIDE1IS_Xt: 1477 { 1478 assert64(tc); 1479 scr = readMiscReg(MISCREG_SCR, tc); 1480 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1481 bits(newVal, 55, 48); 1482 1483 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1484 tlbiOp.broadcast(tc); 1485 return; 1486 } 1487 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 1488 // entries from the last level of translation table walks 1489 // AArch64 TLB Invalidate by VA, All ASID, EL1 1490 case MISCREG_TLBI_VAAE1_Xt: 1491 case MISCREG_TLBI_VAALE1_Xt: 1492 { 1493 assert64(tc); 1494 scr = readMiscReg(MISCREG_SCR, tc); 1495 1496 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1497 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 1498 1499 tlbiOp(tc); 1500 return; 1501 } 1502 // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable 1503 case MISCREG_TLBI_VAAE1IS_Xt: 1504 case MISCREG_TLBI_VAALE1IS_Xt: 1505 { 1506 assert64(tc); 1507 scr = readMiscReg(MISCREG_SCR, tc); 1508 1509 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1510 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 1511 1512 tlbiOp.broadcast(tc); 1513 return; 1514 } 1515 // AArch64 TLB Invalidate by Intermediate Physical Address, 1516 // Stage 2, EL1 1517 case MISCREG_TLBI_IPAS2E1_Xt: 1518 case MISCREG_TLBI_IPAS2LE1_Xt: 1519 { 1520 assert64(tc); 1521 scr = readMiscReg(MISCREG_SCR, tc); 1522 1523 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1524 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1525 1526 tlbiOp(tc); 1527 return; 1528 } 1529 // AArch64 TLB Invalidate by Intermediate Physical Address, 1530 // Stage 2, EL1, Inner Shareable 1531 case MISCREG_TLBI_IPAS2E1IS_Xt: 1532 case MISCREG_TLBI_IPAS2LE1IS_Xt: 1533 { 1534 assert64(tc); 1535 scr = readMiscReg(MISCREG_SCR, tc); 1536 1537 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1538 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1539 1540 tlbiOp.broadcast(tc); 1541 return; 1542 } 1543 case MISCREG_ACTLR: 1544 warn("Not doing anything for write of miscreg ACTLR\n"); 1545 break; 1546 1547 case MISCREG_PMXEVTYPER_PMCCFILTR: 1548 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 1549 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 1550 case MISCREG_PMCR ... MISCREG_PMOVSSET: 1551 pmu->setMiscReg(misc_reg, newVal); 1552 break; 1553 1554 1555 case MISCREG_HSTR: // TJDBX, now redifined to be RES0 1556 { 1557 HSTR hstrMask = 0; 1558 hstrMask.tjdbx = 1; 1559 newVal &= ~((uint32_t) hstrMask); 1560 break; 1561 } 1562 case MISCREG_HCPTR: 1563 { 1564 // If a CP bit in NSACR is 0 then the corresponding bit in 1565 // HCPTR is RAO/WI. Same applies to NSASEDIS 1566 secure_lookup = haveSecurity && 1567 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 1568 readMiscRegNoEffect(MISCREG_CPSR)); 1569 if (!secure_lookup) { 1570 RegVal oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 1571 RegVal mask = 1572 (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 1573 newVal = (newVal & ~mask) | (oldValue & mask); 1574 } 1575 break; 1576 } 1577 case MISCREG_HDFAR: // alias for secure DFAR 1578 misc_reg = MISCREG_DFAR_S; 1579 break; 1580 case MISCREG_HIFAR: // alias for secure IFAR 1581 misc_reg = MISCREG_IFAR_S; 1582 break; 1583 case MISCREG_ATS1CPR: 1584 case MISCREG_ATS1CPW: 1585 case MISCREG_ATS1CUR: 1586 case MISCREG_ATS1CUW: 1587 case MISCREG_ATS12NSOPR: 1588 case MISCREG_ATS12NSOPW: 1589 case MISCREG_ATS12NSOUR: 1590 case MISCREG_ATS12NSOUW: 1591 case MISCREG_ATS1HR: 1592 case MISCREG_ATS1HW: 1593 { 1594 Request::Flags flags = 0; 1595 BaseTLB::Mode mode = BaseTLB::Read; 1596 TLB::ArmTranslationType tranType = TLB::NormalTran; 1597 Fault fault; 1598 switch(misc_reg) { 1599 case MISCREG_ATS1CPR: 1600 flags = TLB::MustBeOne; 1601 tranType = TLB::S1CTran; 1602 mode = BaseTLB::Read; 1603 break; 1604 case MISCREG_ATS1CPW: 1605 flags = TLB::MustBeOne; 1606 tranType = TLB::S1CTran; 1607 mode = BaseTLB::Write; 1608 break; 1609 case MISCREG_ATS1CUR: 1610 flags = TLB::MustBeOne | TLB::UserMode; 1611 tranType = TLB::S1CTran; 1612 mode = BaseTLB::Read; 1613 break; 1614 case MISCREG_ATS1CUW: 1615 flags = TLB::MustBeOne | TLB::UserMode; 1616 tranType = TLB::S1CTran; 1617 mode = BaseTLB::Write; 1618 break; 1619 case MISCREG_ATS12NSOPR: 1620 if (!haveSecurity) 1621 panic("Security Extensions required for ATS12NSOPR"); 1622 flags = TLB::MustBeOne; 1623 tranType = TLB::S1S2NsTran; 1624 mode = BaseTLB::Read; 1625 break; 1626 case MISCREG_ATS12NSOPW: 1627 if (!haveSecurity) 1628 panic("Security Extensions required for ATS12NSOPW"); 1629 flags = TLB::MustBeOne; 1630 tranType = TLB::S1S2NsTran; 1631 mode = BaseTLB::Write; 1632 break; 1633 case MISCREG_ATS12NSOUR: 1634 if (!haveSecurity) 1635 panic("Security Extensions required for ATS12NSOUR"); 1636 flags = TLB::MustBeOne | TLB::UserMode; 1637 tranType = TLB::S1S2NsTran; 1638 mode = BaseTLB::Read; 1639 break; 1640 case MISCREG_ATS12NSOUW: 1641 if (!haveSecurity) 1642 panic("Security Extensions required for ATS12NSOUW"); 1643 flags = TLB::MustBeOne | TLB::UserMode; 1644 tranType = TLB::S1S2NsTran; 1645 mode = BaseTLB::Write; 1646 break; 1647 case MISCREG_ATS1HR: // only really useful from secure mode. 1648 flags = TLB::MustBeOne; 1649 tranType = TLB::HypMode; 1650 mode = BaseTLB::Read; 1651 break; 1652 case MISCREG_ATS1HW: 1653 flags = TLB::MustBeOne; 1654 tranType = TLB::HypMode; 1655 mode = BaseTLB::Write; 1656 break; 1657 } 1658 // If we're in timing mode then doing the translation in 1659 // functional mode then we're slightly distorting performance 1660 // results obtained from simulations. The translation should be 1661 // done in the same mode the core is running in. NOTE: This 1662 // can't be an atomic translation because that causes problems 1663 // with unexpected atomic snoop requests. 1664 warn("Translating via %s in functional mode! Fix Me!\n", 1665 miscRegName[misc_reg]); 1666 1667 auto req = std::make_shared<Request>( 1668 0, val, 0, flags, Request::funcMasterId, 1669 tc->pcState().pc(), tc->contextId()); 1670 1671 fault = getDTBPtr(tc)->translateFunctional( 1672 req, tc, mode, tranType); 1673 1674 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1675 HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 1676 1677 RegVal newVal; 1678 if (fault == NoFault) { 1679 Addr paddr = req->getPaddr(); 1680 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 1681 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 1682 newVal = (paddr & mask(39, 12)) | 1683 (getDTBPtr(tc)->getAttr()); 1684 } else { 1685 newVal = (paddr & 0xfffff000) | 1686 (getDTBPtr(tc)->getAttr()); 1687 } 1688 DPRINTF(MiscRegs, 1689 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 1690 val, newVal); 1691 } else { 1692 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1693 armFault->update(tc); 1694 // Set fault bit and FSR 1695 FSR fsr = armFault->getFsr(tc); 1696 1697 newVal = ((fsr >> 9) & 1) << 11; 1698 if (newVal) { 1699 // LPAE - rearange fault status 1700 newVal |= ((fsr >> 0) & 0x3f) << 1; 1701 } else { 1702 // VMSA - rearange fault status 1703 newVal |= ((fsr >> 0) & 0xf) << 1; 1704 newVal |= ((fsr >> 10) & 0x1) << 5; 1705 newVal |= ((fsr >> 12) & 0x1) << 6; 1706 } 1707 newVal |= 0x1; // F bit 1708 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1709 newVal |= armFault->isStage2() ? 0x200 : 0; 1710 DPRINTF(MiscRegs, 1711 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 1712 val, fsr, newVal); 1713 } 1714 setMiscRegNoEffect(MISCREG_PAR, newVal); 1715 return; 1716 } 1717 case MISCREG_TTBCR: 1718 { 1719 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1720 const uint32_t ones = (uint32_t)(-1); 1721 TTBCR ttbcrMask = 0; 1722 TTBCR ttbcrNew = newVal; 1723 1724 // ARM DDI 0406C.b, ARMv7-32 1725 ttbcrMask.n = ones; // T0SZ 1726 if (haveSecurity) { 1727 ttbcrMask.pd0 = ones; 1728 ttbcrMask.pd1 = ones; 1729 } 1730 ttbcrMask.epd0 = ones; 1731 ttbcrMask.irgn0 = ones; 1732 ttbcrMask.orgn0 = ones; 1733 ttbcrMask.sh0 = ones; 1734 ttbcrMask.ps = ones; // T1SZ 1735 ttbcrMask.a1 = ones; 1736 ttbcrMask.epd1 = ones; 1737 ttbcrMask.irgn1 = ones; 1738 ttbcrMask.orgn1 = ones; 1739 ttbcrMask.sh1 = ones; 1740 if (haveLPAE) 1741 ttbcrMask.eae = ones; 1742 1743 if (haveLPAE && ttbcrNew.eae) { 1744 newVal = newVal & ttbcrMask; 1745 } else { 1746 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 1747 } 1748 // Invalidate TLB MiscReg 1749 getITBPtr(tc)->invalidateMiscReg(); 1750 getDTBPtr(tc)->invalidateMiscReg(); 1751 break; 1752 } 1753 case MISCREG_TTBR0: 1754 case MISCREG_TTBR1: 1755 { 1756 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1757 if (haveLPAE) { 1758 if (ttbcr.eae) { 1759 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 1760 // ARMv8 AArch32 bit 63-56 only 1761 uint64_t ttbrMask = mask(63,56) | mask(47,40); 1762 newVal = (newVal & (~ttbrMask)); 1763 } 1764 } 1765 // Invalidate TLB MiscReg 1766 getITBPtr(tc)->invalidateMiscReg(); 1767 getDTBPtr(tc)->invalidateMiscReg(); 1768 break; 1769 } 1770 case MISCREG_SCTLR_EL1: 1771 case MISCREG_CONTEXTIDR: 1772 case MISCREG_PRRR: 1773 case MISCREG_NMRR: 1774 case MISCREG_MAIR0: 1775 case MISCREG_MAIR1: 1776 case MISCREG_DACR: 1777 case MISCREG_VTTBR: 1778 case MISCREG_SCR_EL3: 1779 case MISCREG_HCR_EL2: 1780 case MISCREG_TCR_EL1: 1781 case MISCREG_TCR_EL2: 1782 case MISCREG_TCR_EL3: 1783 case MISCREG_SCTLR_EL2: 1784 case MISCREG_SCTLR_EL3: 1785 case MISCREG_HSCTLR: 1786 case MISCREG_TTBR0_EL1: 1787 case MISCREG_TTBR1_EL1: 1788 case MISCREG_TTBR0_EL2: 1789 case MISCREG_TTBR1_EL2: 1790 case MISCREG_TTBR0_EL3: 1791 getITBPtr(tc)->invalidateMiscReg(); 1792 getDTBPtr(tc)->invalidateMiscReg(); 1793 break; 1794 case MISCREG_NZCV: 1795 { 1796 CPSR cpsr = val; 1797 1798 tc->setCCReg(CCREG_NZ, cpsr.nz); 1799 tc->setCCReg(CCREG_C, cpsr.c); 1800 tc->setCCReg(CCREG_V, cpsr.v); 1801 } 1802 break; 1803 case MISCREG_DAIF: 1804 { 1805 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1806 cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 1807 newVal = cpsr; 1808 misc_reg = MISCREG_CPSR; 1809 } 1810 break; 1811 case MISCREG_SP_EL0: 1812 tc->setIntReg(INTREG_SP0, newVal); 1813 break; 1814 case MISCREG_SP_EL1: 1815 tc->setIntReg(INTREG_SP1, newVal); 1816 break; 1817 case MISCREG_SP_EL2: 1818 tc->setIntReg(INTREG_SP2, newVal); 1819 break; 1820 case MISCREG_SPSEL: 1821 { 1822 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1823 cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 1824 newVal = cpsr; 1825 misc_reg = MISCREG_CPSR; 1826 } 1827 break; 1828 case MISCREG_CURRENTEL: 1829 { 1830 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1831 cpsr.el = (uint8_t) ((CPSR) newVal).el; 1832 newVal = cpsr; 1833 misc_reg = MISCREG_CPSR; 1834 } 1835 break; 1836 case MISCREG_AT_S1E1R_Xt: 1837 case MISCREG_AT_S1E1W_Xt: 1838 case MISCREG_AT_S1E0R_Xt: 1839 case MISCREG_AT_S1E0W_Xt: 1840 case MISCREG_AT_S1E2R_Xt: 1841 case MISCREG_AT_S1E2W_Xt: 1842 case MISCREG_AT_S12E1R_Xt: 1843 case MISCREG_AT_S12E1W_Xt: 1844 case MISCREG_AT_S12E0R_Xt: 1845 case MISCREG_AT_S12E0W_Xt: 1846 case MISCREG_AT_S1E3R_Xt: 1847 case MISCREG_AT_S1E3W_Xt: 1848 { 1849 RequestPtr req = std::make_shared<Request>(); 1850 Request::Flags flags = 0; 1851 BaseTLB::Mode mode = BaseTLB::Read; 1852 TLB::ArmTranslationType tranType = TLB::NormalTran; 1853 Fault fault; 1854 switch(misc_reg) { 1855 case MISCREG_AT_S1E1R_Xt: 1856 flags = TLB::MustBeOne; 1857 tranType = TLB::S1E1Tran; 1858 mode = BaseTLB::Read; 1859 break; 1860 case MISCREG_AT_S1E1W_Xt: 1861 flags = TLB::MustBeOne; 1862 tranType = TLB::S1E1Tran; 1863 mode = BaseTLB::Write; 1864 break; 1865 case MISCREG_AT_S1E0R_Xt: 1866 flags = TLB::MustBeOne | TLB::UserMode; 1867 tranType = TLB::S1E0Tran; 1868 mode = BaseTLB::Read; 1869 break; 1870 case MISCREG_AT_S1E0W_Xt: 1871 flags = TLB::MustBeOne | TLB::UserMode; 1872 tranType = TLB::S1E0Tran; 1873 mode = BaseTLB::Write; 1874 break; 1875 case MISCREG_AT_S1E2R_Xt: 1876 flags = TLB::MustBeOne; 1877 tranType = TLB::S1E2Tran; 1878 mode = BaseTLB::Read; 1879 break; 1880 case MISCREG_AT_S1E2W_Xt: 1881 flags = TLB::MustBeOne; 1882 tranType = TLB::S1E2Tran; 1883 mode = BaseTLB::Write; 1884 break; 1885 case MISCREG_AT_S12E0R_Xt: 1886 flags = TLB::MustBeOne | TLB::UserMode; 1887 tranType = TLB::S12E0Tran; 1888 mode = BaseTLB::Read; 1889 break; 1890 case MISCREG_AT_S12E0W_Xt: 1891 flags = TLB::MustBeOne | TLB::UserMode; 1892 tranType = TLB::S12E0Tran; 1893 mode = BaseTLB::Write; 1894 break; 1895 case MISCREG_AT_S12E1R_Xt: 1896 flags = TLB::MustBeOne; 1897 tranType = TLB::S12E1Tran; 1898 mode = BaseTLB::Read; 1899 break; 1900 case MISCREG_AT_S12E1W_Xt: 1901 flags = TLB::MustBeOne; 1902 tranType = TLB::S12E1Tran; 1903 mode = BaseTLB::Write; 1904 break; 1905 case MISCREG_AT_S1E3R_Xt: 1906 flags = TLB::MustBeOne; 1907 tranType = TLB::S1E3Tran; 1908 mode = BaseTLB::Read; 1909 break; 1910 case MISCREG_AT_S1E3W_Xt: 1911 flags = TLB::MustBeOne; 1912 tranType = TLB::S1E3Tran; 1913 mode = BaseTLB::Write; 1914 break; 1915 } 1916 // If we're in timing mode then doing the translation in 1917 // functional mode then we're slightly distorting performance 1918 // results obtained from simulations. The translation should be 1919 // done in the same mode the core is running in. NOTE: This 1920 // can't be an atomic translation because that causes problems 1921 // with unexpected atomic snoop requests. 1922 warn("Translating via %s in functional mode! Fix Me!\n", 1923 miscRegName[misc_reg]); 1924 1925 req->setVirt(0, val, 0, flags, Request::funcMasterId, 1926 tc->pcState().pc()); 1927 req->setContext(tc->contextId()); 1928 fault = getDTBPtr(tc)->translateFunctional(req, tc, mode, 1929 tranType); 1930 1931 RegVal newVal; 1932 if (fault == NoFault) { 1933 Addr paddr = req->getPaddr(); 1934 uint64_t attr = getDTBPtr(tc)->getAttr(); 1935 uint64_t attr1 = attr >> 56; 1936 if (!attr1 || attr1 ==0x44) { 1937 attr |= 0x100; 1938 attr &= ~ uint64_t(0x80); 1939 } 1940 newVal = (paddr & mask(47, 12)) | attr; 1941 DPRINTF(MiscRegs, 1942 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 1943 val, newVal); 1944 } else { 1945 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1946 armFault->update(tc); 1947 // Set fault bit and FSR 1948 FSR fsr = armFault->getFsr(tc); 1949 1950 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1951 if (cpsr.width) { // AArch32 1952 newVal = ((fsr >> 9) & 1) << 11; 1953 // rearrange fault status 1954 newVal |= ((fsr >> 0) & 0x3f) << 1; 1955 newVal |= 0x1; // F bit 1956 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1957 newVal |= armFault->isStage2() ? 0x200 : 0; 1958 } else { // AArch64 1959 newVal = 1; // F bit 1960 newVal |= fsr << 1; // FST 1961 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit. 1962 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 1963 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 1964 newVal |= 1 << 11; // RES1 1965 } 1966 DPRINTF(MiscRegs, 1967 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 1968 val, fsr, newVal); 1969 } 1970 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 1971 return; 1972 } 1973 case MISCREG_SPSR_EL3: 1974 case MISCREG_SPSR_EL2: 1975 case MISCREG_SPSR_EL1: 1976 // Force bits 23:21 to 0 1977 newVal = val & ~(0x7 << 21); 1978 break; 1979 case MISCREG_L2CTLR: 1980 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 1981 miscRegName[misc_reg], uint32_t(val)); 1982 break; 1983 1984 // Generic Timer registers 1985 case MISCREG_CNTHV_CTL_EL2: 1986 case MISCREG_CNTHV_CVAL_EL2: 1987 case MISCREG_CNTHV_TVAL_EL2: 1988 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 1989 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 1990 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 1991 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 1992 getGenericTimer(tc).setMiscReg(misc_reg, newVal); 1993 break; 1994 1995 case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3: 1996 case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2: 1997 getGICv3CPUInterface(tc).setMiscReg(misc_reg, newVal); 1998 return; 1999 } 2000 } 2001 setMiscRegNoEffect(misc_reg, newVal); 2002} 2003 2004BaseISADevice & 2005ISA::getGenericTimer(ThreadContext *tc) 2006{ 2007 // We only need to create an ISA interface the first time we try 2008 // to access the timer. 2009 if (timer) 2010 return *timer.get(); 2011 2012 assert(system); 2013 GenericTimer *generic_timer(system->getGenericTimer()); 2014 if (!generic_timer) { 2015 panic("Trying to get a generic timer from a system that hasn't " 2016 "been configured to use a generic timer.\n"); 2017 } 2018 2019 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 2020 timer->setThreadContext(tc); 2021 2022 return *timer.get(); 2023} 2024 2025BaseISADevice & 2026ISA::getGICv3CPUInterface(ThreadContext *tc) 2027{ 2028 panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!"); 2029 return *gicv3CpuInterface.get(); 2030} 2031 2032} 2033 2034ArmISA::ISA * 2035ArmISAParams::create() 2036{ 2037 return new ArmISA::ISA(this); 2038} 2039