isa.cc revision 13549:307ffddbd819
1/* 2 * Copyright (c) 2010-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 */ 40 41#include "arch/arm/isa.hh" 42#include "arch/arm/pmu.hh" 43#include "arch/arm/system.hh" 44#include "arch/arm/tlb.hh" 45#include "arch/arm/tlbi_op.hh" 46#include "cpu/base.hh" 47#include "cpu/checker/cpu.hh" 48#include "debug/Arm.hh" 49#include "debug/MiscRegs.hh" 50#include "dev/arm/generic_timer.hh" 51#include "dev/arm/gic_v3.hh" 52#include "dev/arm/gic_v3_cpu_interface.hh" 53#include "params/ArmISA.hh" 54#include "sim/faults.hh" 55#include "sim/stat_control.hh" 56#include "sim/system.hh" 57 58namespace ArmISA 59{ 60 61ISA::ISA(Params *p) 62 : SimObject(p), 63 system(NULL), 64 _decoderFlavour(p->decoderFlavour), 65 _vecRegRenameMode(p->vecRegRenameMode), 66 pmu(p->pmu), 67 impdefAsNop(p->impdef_nop) 68{ 69 miscRegs[MISCREG_SCTLR_RST] = 0; 70 71 // Hook up a dummy device if we haven't been configured with a 72 // real PMU. By using a dummy device, we don't need to check that 73 // the PMU exist every time we try to access a PMU register. 74 if (!pmu) 75 pmu = &dummyDevice; 76 77 // Give all ISA devices a pointer to this ISA 78 pmu->setISA(this); 79 80 system = dynamic_cast<ArmSystem *>(p->system); 81 82 // Cache system-level properties 83 if (FullSystem && system) { 84 highestELIs64 = system->highestELIs64(); 85 haveSecurity = system->haveSecurity(); 86 haveLPAE = system->haveLPAE(); 87 haveCrypto = system->haveCrypto(); 88 haveVirtualization = system->haveVirtualization(); 89 haveLargeAsid64 = system->haveLargeAsid64(); 90 physAddrRange = system->physAddrRange(); 91 } else { 92 highestELIs64 = true; // ArmSystem::highestELIs64 does the same 93 haveSecurity = haveLPAE = haveVirtualization = false; 94 haveCrypto = true; 95 haveLargeAsid64 = false; 96 physAddrRange = 32; // dummy value 97 } 98 99 // GICv3 CPU interface system registers are supported 100 haveGICv3CPUInterface = false; 101 102 if (system && dynamic_cast<Gicv3 *>(system->getGIC())) { 103 haveGICv3CPUInterface = true; 104 } 105 106 initializeMiscRegMetadata(); 107 preUnflattenMiscReg(); 108 109 clear(); 110} 111 112std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS); 113 114const ArmISAParams * 115ISA::params() const 116{ 117 return dynamic_cast<const Params *>(_params); 118} 119 120void 121ISA::clear() 122{ 123 const Params *p(params()); 124 125 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 126 memset(miscRegs, 0, sizeof(miscRegs)); 127 128 initID32(p); 129 130 // We always initialize AArch64 ID registers even 131 // if we are in AArch32. This is done since if we 132 // are in SE mode we don't know if our ArmProcess is 133 // AArch32 or AArch64 134 initID64(p); 135 136 // Start with an event in the mailbox 137 miscRegs[MISCREG_SEV_MAILBOX] = 1; 138 139 // Separate Instruction and Data TLBs 140 miscRegs[MISCREG_TLBTR] = 1; 141 142 MVFR0 mvfr0 = 0; 143 mvfr0.advSimdRegisters = 2; 144 mvfr0.singlePrecision = 2; 145 mvfr0.doublePrecision = 2; 146 mvfr0.vfpExceptionTrapping = 0; 147 mvfr0.divide = 1; 148 mvfr0.squareRoot = 1; 149 mvfr0.shortVectors = 1; 150 mvfr0.roundingModes = 1; 151 miscRegs[MISCREG_MVFR0] = mvfr0; 152 153 MVFR1 mvfr1 = 0; 154 mvfr1.flushToZero = 1; 155 mvfr1.defaultNaN = 1; 156 mvfr1.advSimdLoadStore = 1; 157 mvfr1.advSimdInteger = 1; 158 mvfr1.advSimdSinglePrecision = 1; 159 mvfr1.advSimdHalfPrecision = 1; 160 mvfr1.vfpHalfPrecision = 1; 161 miscRegs[MISCREG_MVFR1] = mvfr1; 162 163 // Reset values of PRRR and NMRR are implementation dependent 164 165 // @todo: PRRR and NMRR in secure state? 166 miscRegs[MISCREG_PRRR_NS] = 167 (1 << 19) | // 19 168 (0 << 18) | // 18 169 (0 << 17) | // 17 170 (1 << 16) | // 16 171 (2 << 14) | // 15:14 172 (0 << 12) | // 13:12 173 (2 << 10) | // 11:10 174 (2 << 8) | // 9:8 175 (2 << 6) | // 7:6 176 (2 << 4) | // 5:4 177 (1 << 2) | // 3:2 178 0; // 1:0 179 180 miscRegs[MISCREG_NMRR_NS] = 181 (1 << 30) | // 31:30 182 (0 << 26) | // 27:26 183 (0 << 24) | // 25:24 184 (3 << 22) | // 23:22 185 (2 << 20) | // 21:20 186 (0 << 18) | // 19:18 187 (0 << 16) | // 17:16 188 (1 << 14) | // 15:14 189 (0 << 12) | // 13:12 190 (2 << 10) | // 11:10 191 (0 << 8) | // 9:8 192 (3 << 6) | // 7:6 193 (2 << 4) | // 5:4 194 (0 << 2) | // 3:2 195 0; // 1:0 196 197 if (FullSystem && system->highestELIs64()) { 198 // Initialize AArch64 state 199 clear64(p); 200 return; 201 } 202 203 // Initialize AArch32 state... 204 clear32(p, sctlr_rst); 205} 206 207void 208ISA::clear32(const ArmISAParams *p, const SCTLR &sctlr_rst) 209{ 210 CPSR cpsr = 0; 211 cpsr.mode = MODE_USER; 212 213 if (FullSystem) { 214 miscRegs[MISCREG_MVBAR] = system->resetAddr(); 215 } 216 217 miscRegs[MISCREG_CPSR] = cpsr; 218 updateRegMap(cpsr); 219 220 SCTLR sctlr = 0; 221 sctlr.te = (bool) sctlr_rst.te; 222 sctlr.nmfi = (bool) sctlr_rst.nmfi; 223 sctlr.v = (bool) sctlr_rst.v; 224 sctlr.u = 1; 225 sctlr.xp = 1; 226 sctlr.rao2 = 1; 227 sctlr.rao3 = 1; 228 sctlr.rao4 = 0xf; // SCTLR[6:3] 229 sctlr.uci = 1; 230 sctlr.dze = 1; 231 miscRegs[MISCREG_SCTLR_NS] = sctlr; 232 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 233 miscRegs[MISCREG_HCPTR] = 0; 234 235 miscRegs[MISCREG_CPACR] = 0; 236 237 miscRegs[MISCREG_FPSID] = p->fpsid; 238 239 if (haveLPAE) { 240 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 241 ttbcr.eae = 0; 242 miscRegs[MISCREG_TTBCR_NS] = ttbcr; 243 // Enforce consistency with system-level settings 244 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 245 } 246 247 if (haveSecurity) { 248 miscRegs[MISCREG_SCTLR_S] = sctlr; 249 miscRegs[MISCREG_SCR] = 0; 250 miscRegs[MISCREG_VBAR_S] = 0; 251 } else { 252 // we're always non-secure 253 miscRegs[MISCREG_SCR] = 1; 254 } 255 256 //XXX We need to initialize the rest of the state. 257} 258 259void 260ISA::clear64(const ArmISAParams *p) 261{ 262 CPSR cpsr = 0; 263 Addr rvbar = system->resetAddr(); 264 switch (system->highestEL()) { 265 // Set initial EL to highest implemented EL using associated stack 266 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 267 // value 268 case EL3: 269 cpsr.mode = MODE_EL3H; 270 miscRegs[MISCREG_RVBAR_EL3] = rvbar; 271 break; 272 case EL2: 273 cpsr.mode = MODE_EL2H; 274 miscRegs[MISCREG_RVBAR_EL2] = rvbar; 275 break; 276 case EL1: 277 cpsr.mode = MODE_EL1H; 278 miscRegs[MISCREG_RVBAR_EL1] = rvbar; 279 break; 280 default: 281 panic("Invalid highest implemented exception level"); 282 break; 283 } 284 285 // Initialize rest of CPSR 286 cpsr.daif = 0xf; // Mask all interrupts 287 cpsr.ss = 0; 288 cpsr.il = 0; 289 miscRegs[MISCREG_CPSR] = cpsr; 290 updateRegMap(cpsr); 291 292 // Initialize other control registers 293 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 294 if (haveSecurity) { 295 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830; 296 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 297 } else if (haveVirtualization) { 298 // also MISCREG_SCTLR_EL2 (by mapping) 299 miscRegs[MISCREG_HSCTLR] = 0x30c50830; 300 } else { 301 // also MISCREG_SCTLR_EL1 (by mapping) 302 miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init 303 // Always non-secure 304 miscRegs[MISCREG_SCR_EL3] = 1; 305 } 306} 307 308void 309ISA::initID32(const ArmISAParams *p) 310{ 311 // Initialize configurable default values 312 miscRegs[MISCREG_MIDR] = p->midr; 313 miscRegs[MISCREG_MIDR_EL1] = p->midr; 314 miscRegs[MISCREG_VPIDR] = p->midr; 315 316 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 317 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 318 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 319 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 320 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 321 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 322 323 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 324 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 325 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 326 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 327 328 miscRegs[MISCREG_ID_ISAR5] = insertBits( 329 miscRegs[MISCREG_ID_ISAR5], 19, 4, 330 haveCrypto ? 0x1112 : 0x0); 331} 332 333void 334ISA::initID64(const ArmISAParams *p) 335{ 336 // Initialize configurable id registers 337 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 338 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 339 miscRegs[MISCREG_ID_AA64DFR0_EL1] = 340 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 341 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 342 343 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 344 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 345 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 346 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 347 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 348 miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p->id_aa64mmfr2_el1; 349 350 miscRegs[MISCREG_ID_DFR0_EL1] = 351 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 352 353 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 354 355 // Enforce consistency with system-level settings... 356 357 // EL3 358 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 359 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 360 haveSecurity ? 0x2 : 0x0); 361 // EL2 362 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 363 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 364 haveVirtualization ? 0x2 : 0x0); 365 // Large ASID support 366 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 367 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 368 haveLargeAsid64 ? 0x2 : 0x0); 369 // Physical address size 370 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 371 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 372 encodePhysAddrRange64(physAddrRange)); 373 // Crypto 374 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits( 375 miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4, 376 haveCrypto ? 0x1112 : 0x0); 377} 378 379void 380ISA::startup(ThreadContext *tc) 381{ 382 pmu->setThreadContext(tc); 383 384 if (system) { 385 Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC()); 386 if (gicv3) { 387 gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId())); 388 gicv3CpuInterface->setISA(this); 389 } 390 } 391} 392 393 394MiscReg 395ISA::readMiscRegNoEffect(int misc_reg) const 396{ 397 assert(misc_reg < NumMiscRegs); 398 399 const auto ® = lookUpMiscReg[misc_reg]; // bit masks 400 const auto &map = getMiscIndices(misc_reg); 401 int lower = map.first, upper = map.second; 402 // NB!: apply architectural masks according to desired register, 403 // despite possibly getting value from different (mapped) register. 404 auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32)) 405 |(miscRegs[upper] << 32)); 406 if (val & reg.res0()) { 407 DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n", 408 miscRegName[misc_reg], val & reg.res0()); 409 } 410 if ((val & reg.res1()) != reg.res1()) { 411 DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n", 412 miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1()); 413 } 414 return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao 415} 416 417 418MiscReg 419ISA::readMiscReg(int misc_reg, ThreadContext *tc) 420{ 421 CPSR cpsr = 0; 422 PCState pc = 0; 423 SCR scr = 0; 424 425 if (misc_reg == MISCREG_CPSR) { 426 cpsr = miscRegs[misc_reg]; 427 pc = tc->pcState(); 428 cpsr.j = pc.jazelle() ? 1 : 0; 429 cpsr.t = pc.thumb() ? 1 : 0; 430 return cpsr; 431 } 432 433#ifndef NDEBUG 434 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 435 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 436 warn("Unimplemented system register %s read.\n", 437 miscRegName[misc_reg]); 438 else 439 panic("Unimplemented system register %s read.\n", 440 miscRegName[misc_reg]); 441 } 442#endif 443 444 switch (unflattenMiscReg(misc_reg)) { 445 case MISCREG_HCR: 446 { 447 if (!haveVirtualization) 448 return 0; 449 else 450 return readMiscRegNoEffect(MISCREG_HCR); 451 } 452 case MISCREG_CPACR: 453 { 454 const uint32_t ones = (uint32_t)(-1); 455 CPACR cpacrMask = 0; 456 // Only cp10, cp11, and ase are implemented, nothing else should 457 // be readable? (straight copy from the write code) 458 cpacrMask.cp10 = ones; 459 cpacrMask.cp11 = ones; 460 cpacrMask.asedis = ones; 461 462 // Security Extensions may limit the readability of CPACR 463 if (haveSecurity) { 464 scr = readMiscRegNoEffect(MISCREG_SCR); 465 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 466 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 467 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 468 // NB: Skipping the full loop, here 469 if (!nsacr.cp10) cpacrMask.cp10 = 0; 470 if (!nsacr.cp11) cpacrMask.cp11 = 0; 471 } 472 } 473 MiscReg val = readMiscRegNoEffect(MISCREG_CPACR); 474 val &= cpacrMask; 475 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 476 miscRegName[misc_reg], val); 477 return val; 478 } 479 case MISCREG_MPIDR: 480 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 481 scr = readMiscRegNoEffect(MISCREG_SCR); 482 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 483 return getMPIDR(system, tc); 484 } else { 485 return readMiscReg(MISCREG_VMPIDR, tc); 486 } 487 break; 488 case MISCREG_MPIDR_EL1: 489 // @todo in the absence of v8 virtualization support just return MPIDR_EL1 490 return getMPIDR(system, tc) & 0xffffffff; 491 case MISCREG_VMPIDR: 492 // top bit defined as RES1 493 return readMiscRegNoEffect(misc_reg) | 0x80000000; 494 case MISCREG_ID_AFR0: // not implemented, so alias MIDR 495 case MISCREG_REVIDR: // not implemented, so alias MIDR 496 case MISCREG_MIDR: 497 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 498 scr = readMiscRegNoEffect(MISCREG_SCR); 499 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 500 return readMiscRegNoEffect(misc_reg); 501 } else { 502 return readMiscRegNoEffect(MISCREG_VPIDR); 503 } 504 break; 505 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 506 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 507 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 508 case MISCREG_AIDR: // AUX ID set to 0 509 case MISCREG_TCMTR: // No TCM's 510 return 0; 511 512 case MISCREG_CLIDR: 513 warn_once("The clidr register always reports 0 caches.\n"); 514 warn_once("clidr LoUIS field of 0b001 to match current " 515 "ARM implementations.\n"); 516 return 0x00200000; 517 case MISCREG_CCSIDR: 518 warn_once("The ccsidr register isn't implemented and " 519 "always reads as 0.\n"); 520 break; 521 case MISCREG_CTR: // AArch32, ARMv7, top bit set 522 case MISCREG_CTR_EL0: // AArch64 523 { 524 //all caches have the same line size in gem5 525 //4 byte words in ARM 526 unsigned lineSizeWords = 527 tc->getSystemPtr()->cacheLineSize() / 4; 528 unsigned log2LineSizeWords = 0; 529 530 while (lineSizeWords >>= 1) { 531 ++log2LineSizeWords; 532 } 533 534 CTR ctr = 0; 535 //log2 of minimun i-cache line size (words) 536 ctr.iCacheLineSize = log2LineSizeWords; 537 //b11 - gem5 uses pipt 538 ctr.l1IndexPolicy = 0x3; 539 //log2 of minimum d-cache line size (words) 540 ctr.dCacheLineSize = log2LineSizeWords; 541 //log2 of max reservation size (words) 542 ctr.erg = log2LineSizeWords; 543 //log2 of max writeback size (words) 544 ctr.cwg = log2LineSizeWords; 545 //b100 - gem5 format is ARMv7 546 ctr.format = 0x4; 547 548 return ctr; 549 } 550 case MISCREG_ACTLR: 551 warn("Not doing anything for miscreg ACTLR\n"); 552 break; 553 554 case MISCREG_PMXEVTYPER_PMCCFILTR: 555 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 556 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 557 case MISCREG_PMCR ... MISCREG_PMOVSSET: 558 return pmu->readMiscReg(misc_reg); 559 560 case MISCREG_CPSR_Q: 561 panic("shouldn't be reading this register seperately\n"); 562 case MISCREG_FPSCR_QC: 563 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 564 case MISCREG_FPSCR_EXC: 565 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 566 case MISCREG_FPSR: 567 { 568 const uint32_t ones = (uint32_t)(-1); 569 FPSCR fpscrMask = 0; 570 fpscrMask.ioc = ones; 571 fpscrMask.dzc = ones; 572 fpscrMask.ofc = ones; 573 fpscrMask.ufc = ones; 574 fpscrMask.ixc = ones; 575 fpscrMask.idc = ones; 576 fpscrMask.qc = ones; 577 fpscrMask.v = ones; 578 fpscrMask.c = ones; 579 fpscrMask.z = ones; 580 fpscrMask.n = ones; 581 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 582 } 583 case MISCREG_FPCR: 584 { 585 const uint32_t ones = (uint32_t)(-1); 586 FPSCR fpscrMask = 0; 587 fpscrMask.len = ones; 588 fpscrMask.stride = ones; 589 fpscrMask.rMode = ones; 590 fpscrMask.fz = ones; 591 fpscrMask.dn = ones; 592 fpscrMask.ahp = ones; 593 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 594 } 595 case MISCREG_NZCV: 596 { 597 CPSR cpsr = 0; 598 cpsr.nz = tc->readCCReg(CCREG_NZ); 599 cpsr.c = tc->readCCReg(CCREG_C); 600 cpsr.v = tc->readCCReg(CCREG_V); 601 return cpsr; 602 } 603 case MISCREG_DAIF: 604 { 605 CPSR cpsr = 0; 606 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 607 return cpsr; 608 } 609 case MISCREG_SP_EL0: 610 { 611 return tc->readIntReg(INTREG_SP0); 612 } 613 case MISCREG_SP_EL1: 614 { 615 return tc->readIntReg(INTREG_SP1); 616 } 617 case MISCREG_SP_EL2: 618 { 619 return tc->readIntReg(INTREG_SP2); 620 } 621 case MISCREG_SPSEL: 622 { 623 return miscRegs[MISCREG_CPSR] & 0x1; 624 } 625 case MISCREG_CURRENTEL: 626 { 627 return miscRegs[MISCREG_CPSR] & 0xc; 628 } 629 case MISCREG_L2CTLR: 630 { 631 // mostly unimplemented, just set NumCPUs field from sim and return 632 L2CTLR l2ctlr = 0; 633 // b00:1CPU to b11:4CPUs 634 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 635 return l2ctlr; 636 } 637 case MISCREG_DBGDIDR: 638 /* For now just implement the version number. 639 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 640 */ 641 return 0x5 << 16; 642 case MISCREG_DBGDSCRint: 643 return 0; 644 case MISCREG_ISR: 645 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 646 readMiscRegNoEffect(MISCREG_HCR), 647 readMiscRegNoEffect(MISCREG_CPSR), 648 readMiscRegNoEffect(MISCREG_SCR)); 649 case MISCREG_ISR_EL1: 650 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 651 readMiscRegNoEffect(MISCREG_HCR_EL2), 652 readMiscRegNoEffect(MISCREG_CPSR), 653 readMiscRegNoEffect(MISCREG_SCR_EL3)); 654 case MISCREG_DCZID_EL0: 655 return 0x04; // DC ZVA clear 64-byte chunks 656 case MISCREG_HCPTR: 657 { 658 MiscReg val = readMiscRegNoEffect(misc_reg); 659 // The trap bit associated with CP14 is defined as RAZ 660 val &= ~(1 << 14); 661 // If a CP bit in NSACR is 0 then the corresponding bit in 662 // HCPTR is RAO/WI 663 bool secure_lookup = haveSecurity && 664 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 665 readMiscRegNoEffect(MISCREG_CPSR)); 666 if (!secure_lookup) { 667 MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR); 668 val |= (mask ^ 0x7FFF) & 0xBFFF; 669 } 670 // Set the bits for unimplemented coprocessors to RAO/WI 671 val |= 0x33FF; 672 return (val); 673 } 674 case MISCREG_HDFAR: // alias for secure DFAR 675 return readMiscRegNoEffect(MISCREG_DFAR_S); 676 case MISCREG_HIFAR: // alias for secure IFAR 677 return readMiscRegNoEffect(MISCREG_IFAR_S); 678 679 case MISCREG_ID_PFR0: 680 // !ThumbEE | !Jazelle | Thumb | ARM 681 return 0x00000031; 682 case MISCREG_ID_PFR1: 683 { // Timer | Virti | !M Profile | TrustZone | ARMv4 684 bool haveTimer = (system->getGenericTimer() != NULL); 685 return 0x00000001 686 | (haveSecurity ? 0x00000010 : 0x0) 687 | (haveVirtualization ? 0x00001000 : 0x0) 688 | (haveTimer ? 0x00010000 : 0x0); 689 } 690 case MISCREG_ID_AA64PFR0_EL1: 691 return 0x0000000000000002 | // AArch{64,32} supported at EL0 692 0x0000000000000020 | // EL1 693 (haveVirtualization ? 0x0000000000000200 : 0) | // EL2 694 (haveSecurity ? 0x0000000000002000 : 0) | // EL3 695 (haveGICv3CPUInterface ? 0x0000000001000000 : 0); 696 case MISCREG_ID_AA64PFR1_EL1: 697 return 0; // bits [63:0] RES0 (reserved for future use) 698 699 // Generic Timer registers 700 case MISCREG_CNTHV_CTL_EL2: 701 case MISCREG_CNTHV_CVAL_EL2: 702 case MISCREG_CNTHV_TVAL_EL2: 703 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 704 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 705 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 706 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 707 return getGenericTimer(tc).readMiscReg(misc_reg); 708 709 case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3: 710 case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2: 711 return getGICv3CPUInterface(tc).readMiscReg(misc_reg); 712 713 default: 714 break; 715 716 } 717 return readMiscRegNoEffect(misc_reg); 718} 719 720void 721ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 722{ 723 assert(misc_reg < NumMiscRegs); 724 725 const auto ® = lookUpMiscReg[misc_reg]; // bit masks 726 const auto &map = getMiscIndices(misc_reg); 727 int lower = map.first, upper = map.second; 728 729 auto v = (val & ~reg.wi()) | reg.rao(); 730 if (upper > 0) { 731 miscRegs[lower] = bits(v, 31, 0); 732 miscRegs[upper] = bits(v, 63, 32); 733 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 734 misc_reg, lower, upper, v); 735 } else { 736 miscRegs[lower] = v; 737 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 738 misc_reg, lower, v); 739 } 740} 741 742void 743ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 744{ 745 746 MiscReg newVal = val; 747 bool secure_lookup; 748 SCR scr; 749 750 if (misc_reg == MISCREG_CPSR) { 751 updateRegMap(val); 752 753 754 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 755 int old_mode = old_cpsr.mode; 756 CPSR cpsr = val; 757 if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) { 758 getITBPtr(tc)->invalidateMiscReg(); 759 getDTBPtr(tc)->invalidateMiscReg(); 760 } 761 762 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 763 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 764 PCState pc = tc->pcState(); 765 pc.nextThumb(cpsr.t); 766 pc.nextJazelle(cpsr.j); 767 pc.illegalExec(cpsr.il == 1); 768 769 // Follow slightly different semantics if a CheckerCPU object 770 // is connected 771 CheckerCPU *checker = tc->getCheckerCpuPtr(); 772 if (checker) { 773 tc->pcStateNoRecord(pc); 774 } else { 775 tc->pcState(pc); 776 } 777 } else { 778#ifndef NDEBUG 779 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 780 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 781 warn("Unimplemented system register %s write with %#x.\n", 782 miscRegName[misc_reg], val); 783 else 784 panic("Unimplemented system register %s write with %#x.\n", 785 miscRegName[misc_reg], val); 786 } 787#endif 788 switch (unflattenMiscReg(misc_reg)) { 789 case MISCREG_CPACR: 790 { 791 792 const uint32_t ones = (uint32_t)(-1); 793 CPACR cpacrMask = 0; 794 // Only cp10, cp11, and ase are implemented, nothing else should 795 // be writable 796 cpacrMask.cp10 = ones; 797 cpacrMask.cp11 = ones; 798 cpacrMask.asedis = ones; 799 800 // Security Extensions may limit the writability of CPACR 801 if (haveSecurity) { 802 scr = readMiscRegNoEffect(MISCREG_SCR); 803 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 804 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 805 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 806 // NB: Skipping the full loop, here 807 if (!nsacr.cp10) cpacrMask.cp10 = 0; 808 if (!nsacr.cp11) cpacrMask.cp11 = 0; 809 } 810 } 811 812 MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR); 813 newVal &= cpacrMask; 814 newVal |= old_val & ~cpacrMask; 815 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 816 miscRegName[misc_reg], newVal); 817 } 818 break; 819 case MISCREG_CPTR_EL2: 820 { 821 const uint32_t ones = (uint32_t)(-1); 822 CPTR cptrMask = 0; 823 cptrMask.tcpac = ones; 824 cptrMask.tta = ones; 825 cptrMask.tfp = ones; 826 newVal &= cptrMask; 827 cptrMask = 0; 828 cptrMask.res1_13_12_el2 = ones; 829 cptrMask.res1_9_0_el2 = ones; 830 newVal |= cptrMask; 831 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 832 miscRegName[misc_reg], newVal); 833 } 834 break; 835 case MISCREG_CPTR_EL3: 836 { 837 const uint32_t ones = (uint32_t)(-1); 838 CPTR cptrMask = 0; 839 cptrMask.tcpac = ones; 840 cptrMask.tta = ones; 841 cptrMask.tfp = ones; 842 newVal &= cptrMask; 843 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 844 miscRegName[misc_reg], newVal); 845 } 846 break; 847 case MISCREG_CSSELR: 848 warn_once("The csselr register isn't implemented.\n"); 849 return; 850 851 case MISCREG_DC_ZVA_Xt: 852 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 853 return; 854 855 case MISCREG_FPSCR: 856 { 857 const uint32_t ones = (uint32_t)(-1); 858 FPSCR fpscrMask = 0; 859 fpscrMask.ioc = ones; 860 fpscrMask.dzc = ones; 861 fpscrMask.ofc = ones; 862 fpscrMask.ufc = ones; 863 fpscrMask.ixc = ones; 864 fpscrMask.idc = ones; 865 fpscrMask.ioe = ones; 866 fpscrMask.dze = ones; 867 fpscrMask.ofe = ones; 868 fpscrMask.ufe = ones; 869 fpscrMask.ixe = ones; 870 fpscrMask.ide = ones; 871 fpscrMask.len = ones; 872 fpscrMask.stride = ones; 873 fpscrMask.rMode = ones; 874 fpscrMask.fz = ones; 875 fpscrMask.dn = ones; 876 fpscrMask.ahp = ones; 877 fpscrMask.qc = ones; 878 fpscrMask.v = ones; 879 fpscrMask.c = ones; 880 fpscrMask.z = ones; 881 fpscrMask.n = ones; 882 newVal = (newVal & (uint32_t)fpscrMask) | 883 (readMiscRegNoEffect(MISCREG_FPSCR) & 884 ~(uint32_t)fpscrMask); 885 tc->getDecoderPtr()->setContext(newVal); 886 } 887 break; 888 case MISCREG_FPSR: 889 { 890 const uint32_t ones = (uint32_t)(-1); 891 FPSCR fpscrMask = 0; 892 fpscrMask.ioc = ones; 893 fpscrMask.dzc = ones; 894 fpscrMask.ofc = ones; 895 fpscrMask.ufc = ones; 896 fpscrMask.ixc = ones; 897 fpscrMask.idc = ones; 898 fpscrMask.qc = ones; 899 fpscrMask.v = ones; 900 fpscrMask.c = ones; 901 fpscrMask.z = ones; 902 fpscrMask.n = ones; 903 newVal = (newVal & (uint32_t)fpscrMask) | 904 (readMiscRegNoEffect(MISCREG_FPSCR) & 905 ~(uint32_t)fpscrMask); 906 misc_reg = MISCREG_FPSCR; 907 } 908 break; 909 case MISCREG_FPCR: 910 { 911 const uint32_t ones = (uint32_t)(-1); 912 FPSCR fpscrMask = 0; 913 fpscrMask.len = ones; 914 fpscrMask.stride = ones; 915 fpscrMask.rMode = ones; 916 fpscrMask.fz = ones; 917 fpscrMask.dn = ones; 918 fpscrMask.ahp = ones; 919 newVal = (newVal & (uint32_t)fpscrMask) | 920 (readMiscRegNoEffect(MISCREG_FPSCR) & 921 ~(uint32_t)fpscrMask); 922 misc_reg = MISCREG_FPSCR; 923 } 924 break; 925 case MISCREG_CPSR_Q: 926 { 927 assert(!(newVal & ~CpsrMaskQ)); 928 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 929 misc_reg = MISCREG_CPSR; 930 } 931 break; 932 case MISCREG_FPSCR_QC: 933 { 934 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 935 (newVal & FpscrQcMask); 936 misc_reg = MISCREG_FPSCR; 937 } 938 break; 939 case MISCREG_FPSCR_EXC: 940 { 941 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 942 (newVal & FpscrExcMask); 943 misc_reg = MISCREG_FPSCR; 944 } 945 break; 946 case MISCREG_FPEXC: 947 { 948 // vfpv3 architecture, section B.6.1 of DDI04068 949 // bit 29 - valid only if fpexc[31] is 0 950 const uint32_t fpexcMask = 0x60000000; 951 newVal = (newVal & fpexcMask) | 952 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 953 } 954 break; 955 case MISCREG_HCR: 956 { 957 if (!haveVirtualization) 958 return; 959 } 960 break; 961 case MISCREG_IFSR: 962 { 963 // ARM ARM (ARM DDI 0406C.b) B4.1.96 964 const uint32_t ifsrMask = 965 mask(31, 13) | mask(11, 11) | mask(8, 6); 966 newVal = newVal & ~ifsrMask; 967 } 968 break; 969 case MISCREG_DFSR: 970 { 971 // ARM ARM (ARM DDI 0406C.b) B4.1.52 972 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 973 newVal = newVal & ~dfsrMask; 974 } 975 break; 976 case MISCREG_AMAIR0: 977 case MISCREG_AMAIR1: 978 { 979 // ARM ARM (ARM DDI 0406C.b) B4.1.5 980 // Valid only with LPAE 981 if (!haveLPAE) 982 return; 983 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 984 } 985 break; 986 case MISCREG_SCR: 987 getITBPtr(tc)->invalidateMiscReg(); 988 getDTBPtr(tc)->invalidateMiscReg(); 989 break; 990 case MISCREG_SCTLR: 991 { 992 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 993 scr = readMiscRegNoEffect(MISCREG_SCR); 994 995 MiscRegIndex sctlr_idx; 996 if (haveSecurity && !highestELIs64 && !scr.ns) { 997 sctlr_idx = MISCREG_SCTLR_S; 998 } else { 999 sctlr_idx = MISCREG_SCTLR_NS; 1000 } 1001 1002 SCTLR sctlr = miscRegs[sctlr_idx]; 1003 SCTLR new_sctlr = newVal; 1004 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 1005 miscRegs[sctlr_idx] = (MiscReg)new_sctlr; 1006 getITBPtr(tc)->invalidateMiscReg(); 1007 getDTBPtr(tc)->invalidateMiscReg(); 1008 } 1009 case MISCREG_MIDR: 1010 case MISCREG_ID_PFR0: 1011 case MISCREG_ID_PFR1: 1012 case MISCREG_ID_DFR0: 1013 case MISCREG_ID_MMFR0: 1014 case MISCREG_ID_MMFR1: 1015 case MISCREG_ID_MMFR2: 1016 case MISCREG_ID_MMFR3: 1017 case MISCREG_ID_ISAR0: 1018 case MISCREG_ID_ISAR1: 1019 case MISCREG_ID_ISAR2: 1020 case MISCREG_ID_ISAR3: 1021 case MISCREG_ID_ISAR4: 1022 case MISCREG_ID_ISAR5: 1023 1024 case MISCREG_MPIDR: 1025 case MISCREG_FPSID: 1026 case MISCREG_TLBTR: 1027 case MISCREG_MVFR0: 1028 case MISCREG_MVFR1: 1029 1030 case MISCREG_ID_AA64AFR0_EL1: 1031 case MISCREG_ID_AA64AFR1_EL1: 1032 case MISCREG_ID_AA64DFR0_EL1: 1033 case MISCREG_ID_AA64DFR1_EL1: 1034 case MISCREG_ID_AA64ISAR0_EL1: 1035 case MISCREG_ID_AA64ISAR1_EL1: 1036 case MISCREG_ID_AA64MMFR0_EL1: 1037 case MISCREG_ID_AA64MMFR1_EL1: 1038 case MISCREG_ID_AA64MMFR2_EL1: 1039 case MISCREG_ID_AA64PFR0_EL1: 1040 case MISCREG_ID_AA64PFR1_EL1: 1041 // ID registers are constants. 1042 return; 1043 1044 // TLB Invalidate All 1045 case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 1046 { 1047 assert32(tc); 1048 scr = readMiscReg(MISCREG_SCR, tc); 1049 1050 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1051 tlbiOp(tc); 1052 return; 1053 } 1054 // TLB Invalidate All, Inner Shareable 1055 case MISCREG_TLBIALLIS: 1056 { 1057 assert32(tc); 1058 scr = readMiscReg(MISCREG_SCR, tc); 1059 1060 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1061 tlbiOp.broadcast(tc); 1062 return; 1063 } 1064 // Instruction TLB Invalidate All 1065 case MISCREG_ITLBIALL: 1066 { 1067 assert32(tc); 1068 scr = readMiscReg(MISCREG_SCR, tc); 1069 1070 ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1071 tlbiOp(tc); 1072 return; 1073 } 1074 // Data TLB Invalidate All 1075 case MISCREG_DTLBIALL: 1076 { 1077 assert32(tc); 1078 scr = readMiscReg(MISCREG_SCR, tc); 1079 1080 DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1081 tlbiOp(tc); 1082 return; 1083 } 1084 // TLB Invalidate by VA 1085 // mcr tlbimval(is) is invalidating all matching entries 1086 // regardless of the level of lookup, since in gem5 we cache 1087 // in the tlb the last level of lookup only. 1088 case MISCREG_TLBIMVA: 1089 case MISCREG_TLBIMVAL: 1090 { 1091 assert32(tc); 1092 scr = readMiscReg(MISCREG_SCR, tc); 1093 1094 TLBIMVA tlbiOp(EL1, 1095 haveSecurity && !scr.ns, 1096 mbits(newVal, 31, 12), 1097 bits(newVal, 7,0)); 1098 1099 tlbiOp(tc); 1100 return; 1101 } 1102 // TLB Invalidate by VA, Inner Shareable 1103 case MISCREG_TLBIMVAIS: 1104 case MISCREG_TLBIMVALIS: 1105 { 1106 assert32(tc); 1107 scr = readMiscReg(MISCREG_SCR, tc); 1108 1109 TLBIMVA tlbiOp(EL1, 1110 haveSecurity && !scr.ns, 1111 mbits(newVal, 31, 12), 1112 bits(newVal, 7,0)); 1113 1114 tlbiOp.broadcast(tc); 1115 return; 1116 } 1117 // TLB Invalidate by ASID match 1118 case MISCREG_TLBIASID: 1119 { 1120 assert32(tc); 1121 scr = readMiscReg(MISCREG_SCR, tc); 1122 1123 TLBIASID tlbiOp(EL1, 1124 haveSecurity && !scr.ns, 1125 bits(newVal, 7,0)); 1126 1127 tlbiOp(tc); 1128 return; 1129 } 1130 // TLB Invalidate by ASID match, Inner Shareable 1131 case MISCREG_TLBIASIDIS: 1132 { 1133 assert32(tc); 1134 scr = readMiscReg(MISCREG_SCR, tc); 1135 1136 TLBIASID tlbiOp(EL1, 1137 haveSecurity && !scr.ns, 1138 bits(newVal, 7,0)); 1139 1140 tlbiOp.broadcast(tc); 1141 return; 1142 } 1143 // mcr tlbimvaal(is) is invalidating all matching entries 1144 // regardless of the level of lookup, since in gem5 we cache 1145 // in the tlb the last level of lookup only. 1146 // TLB Invalidate by VA, All ASID 1147 case MISCREG_TLBIMVAA: 1148 case MISCREG_TLBIMVAAL: 1149 { 1150 assert32(tc); 1151 scr = readMiscReg(MISCREG_SCR, tc); 1152 1153 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1154 mbits(newVal, 31,12), false); 1155 1156 tlbiOp(tc); 1157 return; 1158 } 1159 // TLB Invalidate by VA, All ASID, Inner Shareable 1160 case MISCREG_TLBIMVAAIS: 1161 case MISCREG_TLBIMVAALIS: 1162 { 1163 assert32(tc); 1164 scr = readMiscReg(MISCREG_SCR, tc); 1165 1166 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1167 mbits(newVal, 31,12), false); 1168 1169 tlbiOp.broadcast(tc); 1170 return; 1171 } 1172 // mcr tlbimvalh(is) is invalidating all matching entries 1173 // regardless of the level of lookup, since in gem5 we cache 1174 // in the tlb the last level of lookup only. 1175 // TLB Invalidate by VA, Hyp mode 1176 case MISCREG_TLBIMVAH: 1177 case MISCREG_TLBIMVALH: 1178 { 1179 assert32(tc); 1180 scr = readMiscReg(MISCREG_SCR, tc); 1181 1182 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1183 mbits(newVal, 31,12), true); 1184 1185 tlbiOp(tc); 1186 return; 1187 } 1188 // TLB Invalidate by VA, Hyp mode, Inner Shareable 1189 case MISCREG_TLBIMVAHIS: 1190 case MISCREG_TLBIMVALHIS: 1191 { 1192 assert32(tc); 1193 scr = readMiscReg(MISCREG_SCR, tc); 1194 1195 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1196 mbits(newVal, 31,12), true); 1197 1198 tlbiOp.broadcast(tc); 1199 return; 1200 } 1201 // mcr tlbiipas2l(is) is invalidating all matching entries 1202 // regardless of the level of lookup, since in gem5 we cache 1203 // in the tlb the last level of lookup only. 1204 // TLB Invalidate by Intermediate Physical Address, Stage 2 1205 case MISCREG_TLBIIPAS2: 1206 case MISCREG_TLBIIPAS2L: 1207 { 1208 assert32(tc); 1209 scr = readMiscReg(MISCREG_SCR, tc); 1210 1211 TLBIIPA tlbiOp(EL1, 1212 haveSecurity && !scr.ns, 1213 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1214 1215 tlbiOp(tc); 1216 return; 1217 } 1218 // TLB Invalidate by Intermediate Physical Address, Stage 2, 1219 // Inner Shareable 1220 case MISCREG_TLBIIPAS2IS: 1221 case MISCREG_TLBIIPAS2LIS: 1222 { 1223 assert32(tc); 1224 scr = readMiscReg(MISCREG_SCR, tc); 1225 1226 TLBIIPA tlbiOp(EL1, 1227 haveSecurity && !scr.ns, 1228 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1229 1230 tlbiOp.broadcast(tc); 1231 return; 1232 } 1233 // Instruction TLB Invalidate by VA 1234 case MISCREG_ITLBIMVA: 1235 { 1236 assert32(tc); 1237 scr = readMiscReg(MISCREG_SCR, tc); 1238 1239 ITLBIMVA tlbiOp(EL1, 1240 haveSecurity && !scr.ns, 1241 mbits(newVal, 31, 12), 1242 bits(newVal, 7,0)); 1243 1244 tlbiOp(tc); 1245 return; 1246 } 1247 // Data TLB Invalidate by VA 1248 case MISCREG_DTLBIMVA: 1249 { 1250 assert32(tc); 1251 scr = readMiscReg(MISCREG_SCR, tc); 1252 1253 DTLBIMVA tlbiOp(EL1, 1254 haveSecurity && !scr.ns, 1255 mbits(newVal, 31, 12), 1256 bits(newVal, 7,0)); 1257 1258 tlbiOp(tc); 1259 return; 1260 } 1261 // Instruction TLB Invalidate by ASID match 1262 case MISCREG_ITLBIASID: 1263 { 1264 assert32(tc); 1265 scr = readMiscReg(MISCREG_SCR, tc); 1266 1267 ITLBIASID tlbiOp(EL1, 1268 haveSecurity && !scr.ns, 1269 bits(newVal, 7,0)); 1270 1271 tlbiOp(tc); 1272 return; 1273 } 1274 // Data TLB Invalidate by ASID match 1275 case MISCREG_DTLBIASID: 1276 { 1277 assert32(tc); 1278 scr = readMiscReg(MISCREG_SCR, tc); 1279 1280 DTLBIASID tlbiOp(EL1, 1281 haveSecurity && !scr.ns, 1282 bits(newVal, 7,0)); 1283 1284 tlbiOp(tc); 1285 return; 1286 } 1287 // TLB Invalidate All, Non-Secure Non-Hyp 1288 case MISCREG_TLBIALLNSNH: 1289 { 1290 assert32(tc); 1291 1292 TLBIALLN tlbiOp(EL1, false); 1293 tlbiOp(tc); 1294 return; 1295 } 1296 // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable 1297 case MISCREG_TLBIALLNSNHIS: 1298 { 1299 assert32(tc); 1300 1301 TLBIALLN tlbiOp(EL1, false); 1302 tlbiOp.broadcast(tc); 1303 return; 1304 } 1305 // TLB Invalidate All, Hyp mode 1306 case MISCREG_TLBIALLH: 1307 { 1308 assert32(tc); 1309 1310 TLBIALLN tlbiOp(EL1, true); 1311 tlbiOp(tc); 1312 return; 1313 } 1314 // TLB Invalidate All, Hyp mode, Inner Shareable 1315 case MISCREG_TLBIALLHIS: 1316 { 1317 assert32(tc); 1318 1319 TLBIALLN tlbiOp(EL1, true); 1320 tlbiOp.broadcast(tc); 1321 return; 1322 } 1323 // AArch64 TLB Invalidate All, EL3 1324 case MISCREG_TLBI_ALLE3: 1325 { 1326 assert64(tc); 1327 1328 TLBIALL tlbiOp(EL3, true); 1329 tlbiOp(tc); 1330 return; 1331 } 1332 // AArch64 TLB Invalidate All, EL3, Inner Shareable 1333 case MISCREG_TLBI_ALLE3IS: 1334 { 1335 assert64(tc); 1336 1337 TLBIALL tlbiOp(EL3, true); 1338 tlbiOp.broadcast(tc); 1339 return; 1340 } 1341 // AArch64 TLB Invalidate All, EL2, Inner Shareable 1342 case MISCREG_TLBI_ALLE2: 1343 case MISCREG_TLBI_ALLE2IS: 1344 { 1345 assert64(tc); 1346 scr = readMiscReg(MISCREG_SCR, tc); 1347 1348 TLBIALL tlbiOp(EL2, haveSecurity && !scr.ns); 1349 tlbiOp(tc); 1350 return; 1351 } 1352 // AArch64 TLB Invalidate All, EL1 1353 case MISCREG_TLBI_ALLE1: 1354 case MISCREG_TLBI_VMALLE1: 1355 case MISCREG_TLBI_VMALLS12E1: 1356 // @todo: handle VMID and stage 2 to enable Virtualization 1357 { 1358 assert64(tc); 1359 scr = readMiscReg(MISCREG_SCR, tc); 1360 1361 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1362 tlbiOp(tc); 1363 return; 1364 } 1365 // AArch64 TLB Invalidate All, EL1, Inner Shareable 1366 case MISCREG_TLBI_ALLE1IS: 1367 case MISCREG_TLBI_VMALLE1IS: 1368 case MISCREG_TLBI_VMALLS12E1IS: 1369 // @todo: handle VMID and stage 2 to enable Virtualization 1370 { 1371 assert64(tc); 1372 scr = readMiscReg(MISCREG_SCR, tc); 1373 1374 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1375 tlbiOp.broadcast(tc); 1376 return; 1377 } 1378 // VAEx(IS) and VALEx(IS) are the same because TLBs 1379 // only store entries 1380 // from the last level of translation table walks 1381 // @todo: handle VMID to enable Virtualization 1382 // AArch64 TLB Invalidate by VA, EL3 1383 case MISCREG_TLBI_VAE3_Xt: 1384 case MISCREG_TLBI_VALE3_Xt: 1385 { 1386 assert64(tc); 1387 1388 TLBIMVA tlbiOp(EL3, true, 1389 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1390 0xbeef); 1391 tlbiOp(tc); 1392 return; 1393 } 1394 // AArch64 TLB Invalidate by VA, EL3, Inner Shareable 1395 case MISCREG_TLBI_VAE3IS_Xt: 1396 case MISCREG_TLBI_VALE3IS_Xt: 1397 { 1398 assert64(tc); 1399 1400 TLBIMVA tlbiOp(EL3, true, 1401 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1402 0xbeef); 1403 1404 tlbiOp.broadcast(tc); 1405 return; 1406 } 1407 // AArch64 TLB Invalidate by VA, EL2 1408 case MISCREG_TLBI_VAE2_Xt: 1409 case MISCREG_TLBI_VALE2_Xt: 1410 { 1411 assert64(tc); 1412 scr = readMiscReg(MISCREG_SCR, tc); 1413 1414 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1415 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1416 0xbeef); 1417 tlbiOp(tc); 1418 return; 1419 } 1420 // AArch64 TLB Invalidate by VA, EL2, Inner Shareable 1421 case MISCREG_TLBI_VAE2IS_Xt: 1422 case MISCREG_TLBI_VALE2IS_Xt: 1423 { 1424 assert64(tc); 1425 scr = readMiscReg(MISCREG_SCR, tc); 1426 1427 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1428 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1429 0xbeef); 1430 1431 tlbiOp.broadcast(tc); 1432 return; 1433 } 1434 // AArch64 TLB Invalidate by VA, EL1 1435 case MISCREG_TLBI_VAE1_Xt: 1436 case MISCREG_TLBI_VALE1_Xt: 1437 { 1438 assert64(tc); 1439 scr = readMiscReg(MISCREG_SCR, tc); 1440 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1441 bits(newVal, 55, 48); 1442 1443 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1444 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1445 asid); 1446 1447 tlbiOp(tc); 1448 return; 1449 } 1450 // AArch64 TLB Invalidate by VA, EL1, Inner Shareable 1451 case MISCREG_TLBI_VAE1IS_Xt: 1452 case MISCREG_TLBI_VALE1IS_Xt: 1453 { 1454 assert64(tc); 1455 scr = readMiscReg(MISCREG_SCR, tc); 1456 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1457 bits(newVal, 55, 48); 1458 1459 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1460 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1461 asid); 1462 1463 tlbiOp.broadcast(tc); 1464 return; 1465 } 1466 // AArch64 TLB Invalidate by ASID, EL1 1467 // @todo: handle VMID to enable Virtualization 1468 case MISCREG_TLBI_ASIDE1_Xt: 1469 { 1470 assert64(tc); 1471 scr = readMiscReg(MISCREG_SCR, tc); 1472 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1473 bits(newVal, 55, 48); 1474 1475 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1476 tlbiOp(tc); 1477 return; 1478 } 1479 // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable 1480 case MISCREG_TLBI_ASIDE1IS_Xt: 1481 { 1482 assert64(tc); 1483 scr = readMiscReg(MISCREG_SCR, tc); 1484 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1485 bits(newVal, 55, 48); 1486 1487 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1488 tlbiOp.broadcast(tc); 1489 return; 1490 } 1491 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 1492 // entries from the last level of translation table walks 1493 // AArch64 TLB Invalidate by VA, All ASID, EL1 1494 case MISCREG_TLBI_VAAE1_Xt: 1495 case MISCREG_TLBI_VAALE1_Xt: 1496 { 1497 assert64(tc); 1498 scr = readMiscReg(MISCREG_SCR, tc); 1499 1500 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1501 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 1502 1503 tlbiOp(tc); 1504 return; 1505 } 1506 // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable 1507 case MISCREG_TLBI_VAAE1IS_Xt: 1508 case MISCREG_TLBI_VAALE1IS_Xt: 1509 { 1510 assert64(tc); 1511 scr = readMiscReg(MISCREG_SCR, tc); 1512 1513 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1514 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 1515 1516 tlbiOp.broadcast(tc); 1517 return; 1518 } 1519 // AArch64 TLB Invalidate by Intermediate Physical Address, 1520 // Stage 2, EL1 1521 case MISCREG_TLBI_IPAS2E1_Xt: 1522 case MISCREG_TLBI_IPAS2LE1_Xt: 1523 { 1524 assert64(tc); 1525 scr = readMiscReg(MISCREG_SCR, tc); 1526 1527 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1528 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1529 1530 tlbiOp(tc); 1531 return; 1532 } 1533 // AArch64 TLB Invalidate by Intermediate Physical Address, 1534 // Stage 2, EL1, Inner Shareable 1535 case MISCREG_TLBI_IPAS2E1IS_Xt: 1536 case MISCREG_TLBI_IPAS2LE1IS_Xt: 1537 { 1538 assert64(tc); 1539 scr = readMiscReg(MISCREG_SCR, tc); 1540 1541 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1542 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1543 1544 tlbiOp.broadcast(tc); 1545 return; 1546 } 1547 case MISCREG_ACTLR: 1548 warn("Not doing anything for write of miscreg ACTLR\n"); 1549 break; 1550 1551 case MISCREG_PMXEVTYPER_PMCCFILTR: 1552 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 1553 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 1554 case MISCREG_PMCR ... MISCREG_PMOVSSET: 1555 pmu->setMiscReg(misc_reg, newVal); 1556 break; 1557 1558 1559 case MISCREG_HSTR: // TJDBX, now redifined to be RES0 1560 { 1561 HSTR hstrMask = 0; 1562 hstrMask.tjdbx = 1; 1563 newVal &= ~((uint32_t) hstrMask); 1564 break; 1565 } 1566 case MISCREG_HCPTR: 1567 { 1568 // If a CP bit in NSACR is 0 then the corresponding bit in 1569 // HCPTR is RAO/WI. Same applies to NSASEDIS 1570 secure_lookup = haveSecurity && 1571 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 1572 readMiscRegNoEffect(MISCREG_CPSR)); 1573 if (!secure_lookup) { 1574 MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 1575 MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 1576 newVal = (newVal & ~mask) | (oldValue & mask); 1577 } 1578 break; 1579 } 1580 case MISCREG_HDFAR: // alias for secure DFAR 1581 misc_reg = MISCREG_DFAR_S; 1582 break; 1583 case MISCREG_HIFAR: // alias for secure IFAR 1584 misc_reg = MISCREG_IFAR_S; 1585 break; 1586 case MISCREG_ATS1CPR: 1587 case MISCREG_ATS1CPW: 1588 case MISCREG_ATS1CUR: 1589 case MISCREG_ATS1CUW: 1590 case MISCREG_ATS12NSOPR: 1591 case MISCREG_ATS12NSOPW: 1592 case MISCREG_ATS12NSOUR: 1593 case MISCREG_ATS12NSOUW: 1594 case MISCREG_ATS1HR: 1595 case MISCREG_ATS1HW: 1596 { 1597 Request::Flags flags = 0; 1598 BaseTLB::Mode mode = BaseTLB::Read; 1599 TLB::ArmTranslationType tranType = TLB::NormalTran; 1600 Fault fault; 1601 switch(misc_reg) { 1602 case MISCREG_ATS1CPR: 1603 flags = TLB::MustBeOne; 1604 tranType = TLB::S1CTran; 1605 mode = BaseTLB::Read; 1606 break; 1607 case MISCREG_ATS1CPW: 1608 flags = TLB::MustBeOne; 1609 tranType = TLB::S1CTran; 1610 mode = BaseTLB::Write; 1611 break; 1612 case MISCREG_ATS1CUR: 1613 flags = TLB::MustBeOne | TLB::UserMode; 1614 tranType = TLB::S1CTran; 1615 mode = BaseTLB::Read; 1616 break; 1617 case MISCREG_ATS1CUW: 1618 flags = TLB::MustBeOne | TLB::UserMode; 1619 tranType = TLB::S1CTran; 1620 mode = BaseTLB::Write; 1621 break; 1622 case MISCREG_ATS12NSOPR: 1623 if (!haveSecurity) 1624 panic("Security Extensions required for ATS12NSOPR"); 1625 flags = TLB::MustBeOne; 1626 tranType = TLB::S1S2NsTran; 1627 mode = BaseTLB::Read; 1628 break; 1629 case MISCREG_ATS12NSOPW: 1630 if (!haveSecurity) 1631 panic("Security Extensions required for ATS12NSOPW"); 1632 flags = TLB::MustBeOne; 1633 tranType = TLB::S1S2NsTran; 1634 mode = BaseTLB::Write; 1635 break; 1636 case MISCREG_ATS12NSOUR: 1637 if (!haveSecurity) 1638 panic("Security Extensions required for ATS12NSOUR"); 1639 flags = TLB::MustBeOne | TLB::UserMode; 1640 tranType = TLB::S1S2NsTran; 1641 mode = BaseTLB::Read; 1642 break; 1643 case MISCREG_ATS12NSOUW: 1644 if (!haveSecurity) 1645 panic("Security Extensions required for ATS12NSOUW"); 1646 flags = TLB::MustBeOne | TLB::UserMode; 1647 tranType = TLB::S1S2NsTran; 1648 mode = BaseTLB::Write; 1649 break; 1650 case MISCREG_ATS1HR: // only really useful from secure mode. 1651 flags = TLB::MustBeOne; 1652 tranType = TLB::HypMode; 1653 mode = BaseTLB::Read; 1654 break; 1655 case MISCREG_ATS1HW: 1656 flags = TLB::MustBeOne; 1657 tranType = TLB::HypMode; 1658 mode = BaseTLB::Write; 1659 break; 1660 } 1661 // If we're in timing mode then doing the translation in 1662 // functional mode then we're slightly distorting performance 1663 // results obtained from simulations. The translation should be 1664 // done in the same mode the core is running in. NOTE: This 1665 // can't be an atomic translation because that causes problems 1666 // with unexpected atomic snoop requests. 1667 warn("Translating via %s in functional mode! Fix Me!\n", 1668 miscRegName[misc_reg]); 1669 1670 auto req = std::make_shared<Request>( 1671 0, val, 0, flags, Request::funcMasterId, 1672 tc->pcState().pc(), tc->contextId()); 1673 1674 fault = getDTBPtr(tc)->translateFunctional( 1675 req, tc, mode, tranType); 1676 1677 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1678 HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 1679 1680 MiscReg newVal; 1681 if (fault == NoFault) { 1682 Addr paddr = req->getPaddr(); 1683 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 1684 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 1685 newVal = (paddr & mask(39, 12)) | 1686 (getDTBPtr(tc)->getAttr()); 1687 } else { 1688 newVal = (paddr & 0xfffff000) | 1689 (getDTBPtr(tc)->getAttr()); 1690 } 1691 DPRINTF(MiscRegs, 1692 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 1693 val, newVal); 1694 } else { 1695 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1696 armFault->update(tc); 1697 // Set fault bit and FSR 1698 FSR fsr = armFault->getFsr(tc); 1699 1700 newVal = ((fsr >> 9) & 1) << 11; 1701 if (newVal) { 1702 // LPAE - rearange fault status 1703 newVal |= ((fsr >> 0) & 0x3f) << 1; 1704 } else { 1705 // VMSA - rearange fault status 1706 newVal |= ((fsr >> 0) & 0xf) << 1; 1707 newVal |= ((fsr >> 10) & 0x1) << 5; 1708 newVal |= ((fsr >> 12) & 0x1) << 6; 1709 } 1710 newVal |= 0x1; // F bit 1711 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1712 newVal |= armFault->isStage2() ? 0x200 : 0; 1713 DPRINTF(MiscRegs, 1714 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 1715 val, fsr, newVal); 1716 } 1717 setMiscRegNoEffect(MISCREG_PAR, newVal); 1718 return; 1719 } 1720 case MISCREG_TTBCR: 1721 { 1722 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1723 const uint32_t ones = (uint32_t)(-1); 1724 TTBCR ttbcrMask = 0; 1725 TTBCR ttbcrNew = newVal; 1726 1727 // ARM DDI 0406C.b, ARMv7-32 1728 ttbcrMask.n = ones; // T0SZ 1729 if (haveSecurity) { 1730 ttbcrMask.pd0 = ones; 1731 ttbcrMask.pd1 = ones; 1732 } 1733 ttbcrMask.epd0 = ones; 1734 ttbcrMask.irgn0 = ones; 1735 ttbcrMask.orgn0 = ones; 1736 ttbcrMask.sh0 = ones; 1737 ttbcrMask.ps = ones; // T1SZ 1738 ttbcrMask.a1 = ones; 1739 ttbcrMask.epd1 = ones; 1740 ttbcrMask.irgn1 = ones; 1741 ttbcrMask.orgn1 = ones; 1742 ttbcrMask.sh1 = ones; 1743 if (haveLPAE) 1744 ttbcrMask.eae = ones; 1745 1746 if (haveLPAE && ttbcrNew.eae) { 1747 newVal = newVal & ttbcrMask; 1748 } else { 1749 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 1750 } 1751 // Invalidate TLB MiscReg 1752 getITBPtr(tc)->invalidateMiscReg(); 1753 getDTBPtr(tc)->invalidateMiscReg(); 1754 break; 1755 } 1756 case MISCREG_TTBR0: 1757 case MISCREG_TTBR1: 1758 { 1759 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1760 if (haveLPAE) { 1761 if (ttbcr.eae) { 1762 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 1763 // ARMv8 AArch32 bit 63-56 only 1764 uint64_t ttbrMask = mask(63,56) | mask(47,40); 1765 newVal = (newVal & (~ttbrMask)); 1766 } 1767 } 1768 // Invalidate TLB MiscReg 1769 getITBPtr(tc)->invalidateMiscReg(); 1770 getDTBPtr(tc)->invalidateMiscReg(); 1771 break; 1772 } 1773 case MISCREG_SCTLR_EL1: 1774 case MISCREG_CONTEXTIDR: 1775 case MISCREG_PRRR: 1776 case MISCREG_NMRR: 1777 case MISCREG_MAIR0: 1778 case MISCREG_MAIR1: 1779 case MISCREG_DACR: 1780 case MISCREG_VTTBR: 1781 case MISCREG_SCR_EL3: 1782 case MISCREG_HCR_EL2: 1783 case MISCREG_TCR_EL1: 1784 case MISCREG_TCR_EL2: 1785 case MISCREG_TCR_EL3: 1786 case MISCREG_SCTLR_EL2: 1787 case MISCREG_SCTLR_EL3: 1788 case MISCREG_HSCTLR: 1789 case MISCREG_TTBR0_EL1: 1790 case MISCREG_TTBR1_EL1: 1791 case MISCREG_TTBR0_EL2: 1792 case MISCREG_TTBR1_EL2: 1793 case MISCREG_TTBR0_EL3: 1794 getITBPtr(tc)->invalidateMiscReg(); 1795 getDTBPtr(tc)->invalidateMiscReg(); 1796 break; 1797 case MISCREG_NZCV: 1798 { 1799 CPSR cpsr = val; 1800 1801 tc->setCCReg(CCREG_NZ, cpsr.nz); 1802 tc->setCCReg(CCREG_C, cpsr.c); 1803 tc->setCCReg(CCREG_V, cpsr.v); 1804 } 1805 break; 1806 case MISCREG_DAIF: 1807 { 1808 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1809 cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 1810 newVal = cpsr; 1811 misc_reg = MISCREG_CPSR; 1812 } 1813 break; 1814 case MISCREG_SP_EL0: 1815 tc->setIntReg(INTREG_SP0, newVal); 1816 break; 1817 case MISCREG_SP_EL1: 1818 tc->setIntReg(INTREG_SP1, newVal); 1819 break; 1820 case MISCREG_SP_EL2: 1821 tc->setIntReg(INTREG_SP2, newVal); 1822 break; 1823 case MISCREG_SPSEL: 1824 { 1825 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1826 cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 1827 newVal = cpsr; 1828 misc_reg = MISCREG_CPSR; 1829 } 1830 break; 1831 case MISCREG_CURRENTEL: 1832 { 1833 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1834 cpsr.el = (uint8_t) ((CPSR) newVal).el; 1835 newVal = cpsr; 1836 misc_reg = MISCREG_CPSR; 1837 } 1838 break; 1839 case MISCREG_AT_S1E1R_Xt: 1840 case MISCREG_AT_S1E1W_Xt: 1841 case MISCREG_AT_S1E0R_Xt: 1842 case MISCREG_AT_S1E0W_Xt: 1843 case MISCREG_AT_S1E2R_Xt: 1844 case MISCREG_AT_S1E2W_Xt: 1845 case MISCREG_AT_S12E1R_Xt: 1846 case MISCREG_AT_S12E1W_Xt: 1847 case MISCREG_AT_S12E0R_Xt: 1848 case MISCREG_AT_S12E0W_Xt: 1849 case MISCREG_AT_S1E3R_Xt: 1850 case MISCREG_AT_S1E3W_Xt: 1851 { 1852 RequestPtr req = std::make_shared<Request>(); 1853 Request::Flags flags = 0; 1854 BaseTLB::Mode mode = BaseTLB::Read; 1855 TLB::ArmTranslationType tranType = TLB::NormalTran; 1856 Fault fault; 1857 switch(misc_reg) { 1858 case MISCREG_AT_S1E1R_Xt: 1859 flags = TLB::MustBeOne; 1860 tranType = TLB::S1E1Tran; 1861 mode = BaseTLB::Read; 1862 break; 1863 case MISCREG_AT_S1E1W_Xt: 1864 flags = TLB::MustBeOne; 1865 tranType = TLB::S1E1Tran; 1866 mode = BaseTLB::Write; 1867 break; 1868 case MISCREG_AT_S1E0R_Xt: 1869 flags = TLB::MustBeOne | TLB::UserMode; 1870 tranType = TLB::S1E0Tran; 1871 mode = BaseTLB::Read; 1872 break; 1873 case MISCREG_AT_S1E0W_Xt: 1874 flags = TLB::MustBeOne | TLB::UserMode; 1875 tranType = TLB::S1E0Tran; 1876 mode = BaseTLB::Write; 1877 break; 1878 case MISCREG_AT_S1E2R_Xt: 1879 flags = TLB::MustBeOne; 1880 tranType = TLB::S1E2Tran; 1881 mode = BaseTLB::Read; 1882 break; 1883 case MISCREG_AT_S1E2W_Xt: 1884 flags = TLB::MustBeOne; 1885 tranType = TLB::S1E2Tran; 1886 mode = BaseTLB::Write; 1887 break; 1888 case MISCREG_AT_S12E0R_Xt: 1889 flags = TLB::MustBeOne | TLB::UserMode; 1890 tranType = TLB::S12E0Tran; 1891 mode = BaseTLB::Read; 1892 break; 1893 case MISCREG_AT_S12E0W_Xt: 1894 flags = TLB::MustBeOne | TLB::UserMode; 1895 tranType = TLB::S12E0Tran; 1896 mode = BaseTLB::Write; 1897 break; 1898 case MISCREG_AT_S12E1R_Xt: 1899 flags = TLB::MustBeOne; 1900 tranType = TLB::S12E1Tran; 1901 mode = BaseTLB::Read; 1902 break; 1903 case MISCREG_AT_S12E1W_Xt: 1904 flags = TLB::MustBeOne; 1905 tranType = TLB::S12E1Tran; 1906 mode = BaseTLB::Write; 1907 break; 1908 case MISCREG_AT_S1E3R_Xt: 1909 flags = TLB::MustBeOne; 1910 tranType = TLB::S1E3Tran; 1911 mode = BaseTLB::Read; 1912 break; 1913 case MISCREG_AT_S1E3W_Xt: 1914 flags = TLB::MustBeOne; 1915 tranType = TLB::S1E3Tran; 1916 mode = BaseTLB::Write; 1917 break; 1918 } 1919 // If we're in timing mode then doing the translation in 1920 // functional mode then we're slightly distorting performance 1921 // results obtained from simulations. The translation should be 1922 // done in the same mode the core is running in. NOTE: This 1923 // can't be an atomic translation because that causes problems 1924 // with unexpected atomic snoop requests. 1925 warn("Translating via %s in functional mode! Fix Me!\n", 1926 miscRegName[misc_reg]); 1927 1928 req->setVirt(0, val, 0, flags, Request::funcMasterId, 1929 tc->pcState().pc()); 1930 req->setContext(tc->contextId()); 1931 fault = getDTBPtr(tc)->translateFunctional(req, tc, mode, 1932 tranType); 1933 1934 MiscReg newVal; 1935 if (fault == NoFault) { 1936 Addr paddr = req->getPaddr(); 1937 uint64_t attr = getDTBPtr(tc)->getAttr(); 1938 uint64_t attr1 = attr >> 56; 1939 if (!attr1 || attr1 ==0x44) { 1940 attr |= 0x100; 1941 attr &= ~ uint64_t(0x80); 1942 } 1943 newVal = (paddr & mask(47, 12)) | attr; 1944 DPRINTF(MiscRegs, 1945 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 1946 val, newVal); 1947 } else { 1948 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1949 armFault->update(tc); 1950 // Set fault bit and FSR 1951 FSR fsr = armFault->getFsr(tc); 1952 1953 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1954 if (cpsr.width) { // AArch32 1955 newVal = ((fsr >> 9) & 1) << 11; 1956 // rearrange fault status 1957 newVal |= ((fsr >> 0) & 0x3f) << 1; 1958 newVal |= 0x1; // F bit 1959 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1960 newVal |= armFault->isStage2() ? 0x200 : 0; 1961 } else { // AArch64 1962 newVal = 1; // F bit 1963 newVal |= fsr << 1; // FST 1964 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit. 1965 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 1966 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 1967 newVal |= 1 << 11; // RES1 1968 } 1969 DPRINTF(MiscRegs, 1970 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 1971 val, fsr, newVal); 1972 } 1973 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 1974 return; 1975 } 1976 case MISCREG_SPSR_EL3: 1977 case MISCREG_SPSR_EL2: 1978 case MISCREG_SPSR_EL1: 1979 // Force bits 23:21 to 0 1980 newVal = val & ~(0x7 << 21); 1981 break; 1982 case MISCREG_L2CTLR: 1983 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 1984 miscRegName[misc_reg], uint32_t(val)); 1985 break; 1986 1987 // Generic Timer registers 1988 case MISCREG_CNTHV_CTL_EL2: 1989 case MISCREG_CNTHV_CVAL_EL2: 1990 case MISCREG_CNTHV_TVAL_EL2: 1991 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 1992 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 1993 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 1994 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 1995 getGenericTimer(tc).setMiscReg(misc_reg, newVal); 1996 break; 1997 1998 case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3: 1999 case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2: 2000 getGICv3CPUInterface(tc).setMiscReg(misc_reg, newVal); 2001 return; 2002 } 2003 } 2004 setMiscRegNoEffect(misc_reg, newVal); 2005} 2006 2007BaseISADevice & 2008ISA::getGenericTimer(ThreadContext *tc) 2009{ 2010 // We only need to create an ISA interface the first time we try 2011 // to access the timer. 2012 if (timer) 2013 return *timer.get(); 2014 2015 assert(system); 2016 GenericTimer *generic_timer(system->getGenericTimer()); 2017 if (!generic_timer) { 2018 panic("Trying to get a generic timer from a system that hasn't " 2019 "been configured to use a generic timer.\n"); 2020 } 2021 2022 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 2023 timer->setThreadContext(tc); 2024 2025 return *timer.get(); 2026} 2027 2028BaseISADevice & 2029ISA::getGICv3CPUInterface(ThreadContext *tc) 2030{ 2031 panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!"); 2032 return *gicv3CpuInterface.get(); 2033} 2034 2035} 2036 2037ArmISA::ISA * 2038ArmISAParams::create() 2039{ 2040 return new ArmISA::ISA(this); 2041} 2042