isa.cc revision 13502:7803bd430e0e
1/* 2 * Copyright (c) 2010-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 */ 40 41#include "arch/arm/isa.hh" 42#include "arch/arm/pmu.hh" 43#include "arch/arm/system.hh" 44#include "arch/arm/tlb.hh" 45#include "arch/arm/tlbi_op.hh" 46#include "cpu/base.hh" 47#include "cpu/checker/cpu.hh" 48#include "debug/Arm.hh" 49#include "debug/MiscRegs.hh" 50#include "dev/arm/generic_timer.hh" 51#include "params/ArmISA.hh" 52#include "sim/faults.hh" 53#include "sim/stat_control.hh" 54#include "sim/system.hh" 55 56namespace ArmISA 57{ 58 59ISA::ISA(Params *p) 60 : SimObject(p), 61 system(NULL), 62 _decoderFlavour(p->decoderFlavour), 63 _vecRegRenameMode(p->vecRegRenameMode), 64 pmu(p->pmu), 65 impdefAsNop(p->impdef_nop) 66{ 67 miscRegs[MISCREG_SCTLR_RST] = 0; 68 69 // Hook up a dummy device if we haven't been configured with a 70 // real PMU. By using a dummy device, we don't need to check that 71 // the PMU exist every time we try to access a PMU register. 72 if (!pmu) 73 pmu = &dummyDevice; 74 75 // Give all ISA devices a pointer to this ISA 76 pmu->setISA(this); 77 78 system = dynamic_cast<ArmSystem *>(p->system); 79 80 // Cache system-level properties 81 if (FullSystem && system) { 82 highestELIs64 = system->highestELIs64(); 83 haveSecurity = system->haveSecurity(); 84 haveLPAE = system->haveLPAE(); 85 haveCrypto = system->haveCrypto(); 86 haveVirtualization = system->haveVirtualization(); 87 haveLargeAsid64 = system->haveLargeAsid64(); 88 physAddrRange = system->physAddrRange(); 89 } else { 90 highestELIs64 = true; // ArmSystem::highestELIs64 does the same 91 haveSecurity = haveLPAE = haveVirtualization = false; 92 haveCrypto = true; 93 haveLargeAsid64 = false; 94 physAddrRange = 32; // dummy value 95 } 96 97 initializeMiscRegMetadata(); 98 preUnflattenMiscReg(); 99 100 clear(); 101} 102 103std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS); 104 105const ArmISAParams * 106ISA::params() const 107{ 108 return dynamic_cast<const Params *>(_params); 109} 110 111void 112ISA::clear() 113{ 114 const Params *p(params()); 115 116 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 117 memset(miscRegs, 0, sizeof(miscRegs)); 118 119 initID32(p); 120 121 // We always initialize AArch64 ID registers even 122 // if we are in AArch32. This is done since if we 123 // are in SE mode we don't know if our ArmProcess is 124 // AArch32 or AArch64 125 initID64(p); 126 127 // Start with an event in the mailbox 128 miscRegs[MISCREG_SEV_MAILBOX] = 1; 129 130 // Separate Instruction and Data TLBs 131 miscRegs[MISCREG_TLBTR] = 1; 132 133 MVFR0 mvfr0 = 0; 134 mvfr0.advSimdRegisters = 2; 135 mvfr0.singlePrecision = 2; 136 mvfr0.doublePrecision = 2; 137 mvfr0.vfpExceptionTrapping = 0; 138 mvfr0.divide = 1; 139 mvfr0.squareRoot = 1; 140 mvfr0.shortVectors = 1; 141 mvfr0.roundingModes = 1; 142 miscRegs[MISCREG_MVFR0] = mvfr0; 143 144 MVFR1 mvfr1 = 0; 145 mvfr1.flushToZero = 1; 146 mvfr1.defaultNaN = 1; 147 mvfr1.advSimdLoadStore = 1; 148 mvfr1.advSimdInteger = 1; 149 mvfr1.advSimdSinglePrecision = 1; 150 mvfr1.advSimdHalfPrecision = 1; 151 mvfr1.vfpHalfPrecision = 1; 152 miscRegs[MISCREG_MVFR1] = mvfr1; 153 154 // Reset values of PRRR and NMRR are implementation dependent 155 156 // @todo: PRRR and NMRR in secure state? 157 miscRegs[MISCREG_PRRR_NS] = 158 (1 << 19) | // 19 159 (0 << 18) | // 18 160 (0 << 17) | // 17 161 (1 << 16) | // 16 162 (2 << 14) | // 15:14 163 (0 << 12) | // 13:12 164 (2 << 10) | // 11:10 165 (2 << 8) | // 9:8 166 (2 << 6) | // 7:6 167 (2 << 4) | // 5:4 168 (1 << 2) | // 3:2 169 0; // 1:0 170 171 miscRegs[MISCREG_NMRR_NS] = 172 (1 << 30) | // 31:30 173 (0 << 26) | // 27:26 174 (0 << 24) | // 25:24 175 (3 << 22) | // 23:22 176 (2 << 20) | // 21:20 177 (0 << 18) | // 19:18 178 (0 << 16) | // 17:16 179 (1 << 14) | // 15:14 180 (0 << 12) | // 13:12 181 (2 << 10) | // 11:10 182 (0 << 8) | // 9:8 183 (3 << 6) | // 7:6 184 (2 << 4) | // 5:4 185 (0 << 2) | // 3:2 186 0; // 1:0 187 188 if (FullSystem && system->highestELIs64()) { 189 // Initialize AArch64 state 190 clear64(p); 191 return; 192 } 193 194 // Initialize AArch32 state... 195 clear32(p, sctlr_rst); 196} 197 198void 199ISA::clear32(const ArmISAParams *p, const SCTLR &sctlr_rst) 200{ 201 CPSR cpsr = 0; 202 cpsr.mode = MODE_USER; 203 204 if (FullSystem) { 205 miscRegs[MISCREG_MVBAR] = system->resetAddr(); 206 } 207 208 miscRegs[MISCREG_CPSR] = cpsr; 209 updateRegMap(cpsr); 210 211 SCTLR sctlr = 0; 212 sctlr.te = (bool) sctlr_rst.te; 213 sctlr.nmfi = (bool) sctlr_rst.nmfi; 214 sctlr.v = (bool) sctlr_rst.v; 215 sctlr.u = 1; 216 sctlr.xp = 1; 217 sctlr.rao2 = 1; 218 sctlr.rao3 = 1; 219 sctlr.rao4 = 0xf; // SCTLR[6:3] 220 sctlr.uci = 1; 221 sctlr.dze = 1; 222 miscRegs[MISCREG_SCTLR_NS] = sctlr; 223 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 224 miscRegs[MISCREG_HCPTR] = 0; 225 226 miscRegs[MISCREG_CPACR] = 0; 227 228 miscRegs[MISCREG_FPSID] = p->fpsid; 229 230 if (haveLPAE) { 231 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 232 ttbcr.eae = 0; 233 miscRegs[MISCREG_TTBCR_NS] = ttbcr; 234 // Enforce consistency with system-level settings 235 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 236 } 237 238 if (haveSecurity) { 239 miscRegs[MISCREG_SCTLR_S] = sctlr; 240 miscRegs[MISCREG_SCR] = 0; 241 miscRegs[MISCREG_VBAR_S] = 0; 242 } else { 243 // we're always non-secure 244 miscRegs[MISCREG_SCR] = 1; 245 } 246 247 //XXX We need to initialize the rest of the state. 248} 249 250void 251ISA::clear64(const ArmISAParams *p) 252{ 253 CPSR cpsr = 0; 254 Addr rvbar = system->resetAddr(); 255 switch (system->highestEL()) { 256 // Set initial EL to highest implemented EL using associated stack 257 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 258 // value 259 case EL3: 260 cpsr.mode = MODE_EL3H; 261 miscRegs[MISCREG_RVBAR_EL3] = rvbar; 262 break; 263 case EL2: 264 cpsr.mode = MODE_EL2H; 265 miscRegs[MISCREG_RVBAR_EL2] = rvbar; 266 break; 267 case EL1: 268 cpsr.mode = MODE_EL1H; 269 miscRegs[MISCREG_RVBAR_EL1] = rvbar; 270 break; 271 default: 272 panic("Invalid highest implemented exception level"); 273 break; 274 } 275 276 // Initialize rest of CPSR 277 cpsr.daif = 0xf; // Mask all interrupts 278 cpsr.ss = 0; 279 cpsr.il = 0; 280 miscRegs[MISCREG_CPSR] = cpsr; 281 updateRegMap(cpsr); 282 283 // Initialize other control registers 284 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 285 if (haveSecurity) { 286 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830; 287 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 288 } else if (haveVirtualization) { 289 // also MISCREG_SCTLR_EL2 (by mapping) 290 miscRegs[MISCREG_HSCTLR] = 0x30c50830; 291 } else { 292 // also MISCREG_SCTLR_EL1 (by mapping) 293 miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init 294 // Always non-secure 295 miscRegs[MISCREG_SCR_EL3] = 1; 296 } 297} 298 299void 300ISA::initID32(const ArmISAParams *p) 301{ 302 // Initialize configurable default values 303 miscRegs[MISCREG_MIDR] = p->midr; 304 miscRegs[MISCREG_MIDR_EL1] = p->midr; 305 miscRegs[MISCREG_VPIDR] = p->midr; 306 307 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 308 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 309 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 310 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 311 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 312 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 313 314 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 315 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 316 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 317 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 318 319 miscRegs[MISCREG_ID_ISAR5] = insertBits( 320 miscRegs[MISCREG_ID_ISAR5], 19, 4, 321 haveCrypto ? 0x1112 : 0x0); 322} 323 324void 325ISA::initID64(const ArmISAParams *p) 326{ 327 // Initialize configurable id registers 328 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 329 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 330 miscRegs[MISCREG_ID_AA64DFR0_EL1] = 331 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 332 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 333 334 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 335 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 336 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 337 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 338 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 339 miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p->id_aa64mmfr2_el1; 340 341 miscRegs[MISCREG_ID_DFR0_EL1] = 342 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 343 344 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 345 346 // Enforce consistency with system-level settings... 347 348 // EL3 349 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 350 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 351 haveSecurity ? 0x2 : 0x0); 352 // EL2 353 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 354 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 355 haveVirtualization ? 0x2 : 0x0); 356 // Large ASID support 357 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 358 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 359 haveLargeAsid64 ? 0x2 : 0x0); 360 // Physical address size 361 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 362 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 363 encodePhysAddrRange64(physAddrRange)); 364 // Crypto 365 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits( 366 miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4, 367 haveCrypto ? 0x1112 : 0x0); 368} 369 370void 371ISA::startup(ThreadContext *tc) 372{ 373 pmu->setThreadContext(tc); 374 375} 376 377 378MiscReg 379ISA::readMiscRegNoEffect(int misc_reg) const 380{ 381 assert(misc_reg < NumMiscRegs); 382 383 const auto ® = lookUpMiscReg[misc_reg]; // bit masks 384 const auto &map = getMiscIndices(misc_reg); 385 int lower = map.first, upper = map.second; 386 // NB!: apply architectural masks according to desired register, 387 // despite possibly getting value from different (mapped) register. 388 auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32)) 389 |(miscRegs[upper] << 32)); 390 if (val & reg.res0()) { 391 DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n", 392 miscRegName[misc_reg], val & reg.res0()); 393 } 394 if ((val & reg.res1()) != reg.res1()) { 395 DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n", 396 miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1()); 397 } 398 return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao 399} 400 401 402MiscReg 403ISA::readMiscReg(int misc_reg, ThreadContext *tc) 404{ 405 CPSR cpsr = 0; 406 PCState pc = 0; 407 SCR scr = 0; 408 409 if (misc_reg == MISCREG_CPSR) { 410 cpsr = miscRegs[misc_reg]; 411 pc = tc->pcState(); 412 cpsr.j = pc.jazelle() ? 1 : 0; 413 cpsr.t = pc.thumb() ? 1 : 0; 414 return cpsr; 415 } 416 417#ifndef NDEBUG 418 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 419 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 420 warn("Unimplemented system register %s read.\n", 421 miscRegName[misc_reg]); 422 else 423 panic("Unimplemented system register %s read.\n", 424 miscRegName[misc_reg]); 425 } 426#endif 427 428 switch (unflattenMiscReg(misc_reg)) { 429 case MISCREG_HCR: 430 { 431 if (!haveVirtualization) 432 return 0; 433 else 434 return readMiscRegNoEffect(MISCREG_HCR); 435 } 436 case MISCREG_CPACR: 437 { 438 const uint32_t ones = (uint32_t)(-1); 439 CPACR cpacrMask = 0; 440 // Only cp10, cp11, and ase are implemented, nothing else should 441 // be readable? (straight copy from the write code) 442 cpacrMask.cp10 = ones; 443 cpacrMask.cp11 = ones; 444 cpacrMask.asedis = ones; 445 446 // Security Extensions may limit the readability of CPACR 447 if (haveSecurity) { 448 scr = readMiscRegNoEffect(MISCREG_SCR); 449 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 450 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 451 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 452 // NB: Skipping the full loop, here 453 if (!nsacr.cp10) cpacrMask.cp10 = 0; 454 if (!nsacr.cp11) cpacrMask.cp11 = 0; 455 } 456 } 457 MiscReg val = readMiscRegNoEffect(MISCREG_CPACR); 458 val &= cpacrMask; 459 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 460 miscRegName[misc_reg], val); 461 return val; 462 } 463 case MISCREG_MPIDR: 464 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 465 scr = readMiscRegNoEffect(MISCREG_SCR); 466 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 467 return getMPIDR(system, tc); 468 } else { 469 return readMiscReg(MISCREG_VMPIDR, tc); 470 } 471 break; 472 case MISCREG_MPIDR_EL1: 473 // @todo in the absence of v8 virtualization support just return MPIDR_EL1 474 return getMPIDR(system, tc) & 0xffffffff; 475 case MISCREG_VMPIDR: 476 // top bit defined as RES1 477 return readMiscRegNoEffect(misc_reg) | 0x80000000; 478 case MISCREG_ID_AFR0: // not implemented, so alias MIDR 479 case MISCREG_REVIDR: // not implemented, so alias MIDR 480 case MISCREG_MIDR: 481 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 482 scr = readMiscRegNoEffect(MISCREG_SCR); 483 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 484 return readMiscRegNoEffect(misc_reg); 485 } else { 486 return readMiscRegNoEffect(MISCREG_VPIDR); 487 } 488 break; 489 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 490 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 491 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 492 case MISCREG_AIDR: // AUX ID set to 0 493 case MISCREG_TCMTR: // No TCM's 494 return 0; 495 496 case MISCREG_CLIDR: 497 warn_once("The clidr register always reports 0 caches.\n"); 498 warn_once("clidr LoUIS field of 0b001 to match current " 499 "ARM implementations.\n"); 500 return 0x00200000; 501 case MISCREG_CCSIDR: 502 warn_once("The ccsidr register isn't implemented and " 503 "always reads as 0.\n"); 504 break; 505 case MISCREG_CTR: // AArch32, ARMv7, top bit set 506 case MISCREG_CTR_EL0: // AArch64 507 { 508 //all caches have the same line size in gem5 509 //4 byte words in ARM 510 unsigned lineSizeWords = 511 tc->getSystemPtr()->cacheLineSize() / 4; 512 unsigned log2LineSizeWords = 0; 513 514 while (lineSizeWords >>= 1) { 515 ++log2LineSizeWords; 516 } 517 518 CTR ctr = 0; 519 //log2 of minimun i-cache line size (words) 520 ctr.iCacheLineSize = log2LineSizeWords; 521 //b11 - gem5 uses pipt 522 ctr.l1IndexPolicy = 0x3; 523 //log2 of minimum d-cache line size (words) 524 ctr.dCacheLineSize = log2LineSizeWords; 525 //log2 of max reservation size (words) 526 ctr.erg = log2LineSizeWords; 527 //log2 of max writeback size (words) 528 ctr.cwg = log2LineSizeWords; 529 //b100 - gem5 format is ARMv7 530 ctr.format = 0x4; 531 532 return ctr; 533 } 534 case MISCREG_ACTLR: 535 warn("Not doing anything for miscreg ACTLR\n"); 536 break; 537 538 case MISCREG_PMXEVTYPER_PMCCFILTR: 539 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 540 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 541 case MISCREG_PMCR ... MISCREG_PMOVSSET: 542 return pmu->readMiscReg(misc_reg); 543 544 case MISCREG_CPSR_Q: 545 panic("shouldn't be reading this register seperately\n"); 546 case MISCREG_FPSCR_QC: 547 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 548 case MISCREG_FPSCR_EXC: 549 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 550 case MISCREG_FPSR: 551 { 552 const uint32_t ones = (uint32_t)(-1); 553 FPSCR fpscrMask = 0; 554 fpscrMask.ioc = ones; 555 fpscrMask.dzc = ones; 556 fpscrMask.ofc = ones; 557 fpscrMask.ufc = ones; 558 fpscrMask.ixc = ones; 559 fpscrMask.idc = ones; 560 fpscrMask.qc = ones; 561 fpscrMask.v = ones; 562 fpscrMask.c = ones; 563 fpscrMask.z = ones; 564 fpscrMask.n = ones; 565 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 566 } 567 case MISCREG_FPCR: 568 { 569 const uint32_t ones = (uint32_t)(-1); 570 FPSCR fpscrMask = 0; 571 fpscrMask.len = ones; 572 fpscrMask.stride = ones; 573 fpscrMask.rMode = ones; 574 fpscrMask.fz = ones; 575 fpscrMask.dn = ones; 576 fpscrMask.ahp = ones; 577 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 578 } 579 case MISCREG_NZCV: 580 { 581 CPSR cpsr = 0; 582 cpsr.nz = tc->readCCReg(CCREG_NZ); 583 cpsr.c = tc->readCCReg(CCREG_C); 584 cpsr.v = tc->readCCReg(CCREG_V); 585 return cpsr; 586 } 587 case MISCREG_DAIF: 588 { 589 CPSR cpsr = 0; 590 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 591 return cpsr; 592 } 593 case MISCREG_SP_EL0: 594 { 595 return tc->readIntReg(INTREG_SP0); 596 } 597 case MISCREG_SP_EL1: 598 { 599 return tc->readIntReg(INTREG_SP1); 600 } 601 case MISCREG_SP_EL2: 602 { 603 return tc->readIntReg(INTREG_SP2); 604 } 605 case MISCREG_SPSEL: 606 { 607 return miscRegs[MISCREG_CPSR] & 0x1; 608 } 609 case MISCREG_CURRENTEL: 610 { 611 return miscRegs[MISCREG_CPSR] & 0xc; 612 } 613 case MISCREG_L2CTLR: 614 { 615 // mostly unimplemented, just set NumCPUs field from sim and return 616 L2CTLR l2ctlr = 0; 617 // b00:1CPU to b11:4CPUs 618 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 619 return l2ctlr; 620 } 621 case MISCREG_DBGDIDR: 622 /* For now just implement the version number. 623 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 624 */ 625 return 0x5 << 16; 626 case MISCREG_DBGDSCRint: 627 return 0; 628 case MISCREG_ISR: 629 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 630 readMiscRegNoEffect(MISCREG_HCR), 631 readMiscRegNoEffect(MISCREG_CPSR), 632 readMiscRegNoEffect(MISCREG_SCR)); 633 case MISCREG_ISR_EL1: 634 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 635 readMiscRegNoEffect(MISCREG_HCR_EL2), 636 readMiscRegNoEffect(MISCREG_CPSR), 637 readMiscRegNoEffect(MISCREG_SCR_EL3)); 638 case MISCREG_DCZID_EL0: 639 return 0x04; // DC ZVA clear 64-byte chunks 640 case MISCREG_HCPTR: 641 { 642 MiscReg val = readMiscRegNoEffect(misc_reg); 643 // The trap bit associated with CP14 is defined as RAZ 644 val &= ~(1 << 14); 645 // If a CP bit in NSACR is 0 then the corresponding bit in 646 // HCPTR is RAO/WI 647 bool secure_lookup = haveSecurity && 648 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 649 readMiscRegNoEffect(MISCREG_CPSR)); 650 if (!secure_lookup) { 651 MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR); 652 val |= (mask ^ 0x7FFF) & 0xBFFF; 653 } 654 // Set the bits for unimplemented coprocessors to RAO/WI 655 val |= 0x33FF; 656 return (val); 657 } 658 case MISCREG_HDFAR: // alias for secure DFAR 659 return readMiscRegNoEffect(MISCREG_DFAR_S); 660 case MISCREG_HIFAR: // alias for secure IFAR 661 return readMiscRegNoEffect(MISCREG_IFAR_S); 662 663 case MISCREG_ID_PFR0: 664 // !ThumbEE | !Jazelle | Thumb | ARM 665 return 0x00000031; 666 case MISCREG_ID_PFR1: 667 { // Timer | Virti | !M Profile | TrustZone | ARMv4 668 bool haveTimer = (system->getGenericTimer() != NULL); 669 return 0x00000001 670 | (haveSecurity ? 0x00000010 : 0x0) 671 | (haveVirtualization ? 0x00001000 : 0x0) 672 | (haveTimer ? 0x00010000 : 0x0); 673 } 674 case MISCREG_ID_AA64PFR0_EL1: 675 return 0x0000000000000002 // AArch{64,32} supported at EL0 676 | 0x0000000000000020 // EL1 677 | (haveVirtualization ? 0x0000000000000200 : 0) // EL2 678 | (haveSecurity ? 0x0000000000002000 : 0); // EL3 679 case MISCREG_ID_AA64PFR1_EL1: 680 return 0; // bits [63:0] RES0 (reserved for future use) 681 682 // Generic Timer registers 683 case MISCREG_CNTHV_CTL_EL2: 684 case MISCREG_CNTHV_CVAL_EL2: 685 case MISCREG_CNTHV_TVAL_EL2: 686 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 687 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 688 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 689 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 690 return getGenericTimer(tc).readMiscReg(misc_reg); 691 692 default: 693 break; 694 695 } 696 return readMiscRegNoEffect(misc_reg); 697} 698 699void 700ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 701{ 702 assert(misc_reg < NumMiscRegs); 703 704 const auto ® = lookUpMiscReg[misc_reg]; // bit masks 705 const auto &map = getMiscIndices(misc_reg); 706 int lower = map.first, upper = map.second; 707 708 auto v = (val & ~reg.wi()) | reg.rao(); 709 if (upper > 0) { 710 miscRegs[lower] = bits(v, 31, 0); 711 miscRegs[upper] = bits(v, 63, 32); 712 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 713 misc_reg, lower, upper, v); 714 } else { 715 miscRegs[lower] = v; 716 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 717 misc_reg, lower, v); 718 } 719} 720 721void 722ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 723{ 724 725 MiscReg newVal = val; 726 bool secure_lookup; 727 SCR scr; 728 729 if (misc_reg == MISCREG_CPSR) { 730 updateRegMap(val); 731 732 733 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 734 int old_mode = old_cpsr.mode; 735 CPSR cpsr = val; 736 if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) { 737 getITBPtr(tc)->invalidateMiscReg(); 738 getDTBPtr(tc)->invalidateMiscReg(); 739 } 740 741 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 742 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 743 PCState pc = tc->pcState(); 744 pc.nextThumb(cpsr.t); 745 pc.nextJazelle(cpsr.j); 746 pc.illegalExec(cpsr.il == 1); 747 748 // Follow slightly different semantics if a CheckerCPU object 749 // is connected 750 CheckerCPU *checker = tc->getCheckerCpuPtr(); 751 if (checker) { 752 tc->pcStateNoRecord(pc); 753 } else { 754 tc->pcState(pc); 755 } 756 } else { 757#ifndef NDEBUG 758 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 759 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 760 warn("Unimplemented system register %s write with %#x.\n", 761 miscRegName[misc_reg], val); 762 else 763 panic("Unimplemented system register %s write with %#x.\n", 764 miscRegName[misc_reg], val); 765 } 766#endif 767 switch (unflattenMiscReg(misc_reg)) { 768 case MISCREG_CPACR: 769 { 770 771 const uint32_t ones = (uint32_t)(-1); 772 CPACR cpacrMask = 0; 773 // Only cp10, cp11, and ase are implemented, nothing else should 774 // be writable 775 cpacrMask.cp10 = ones; 776 cpacrMask.cp11 = ones; 777 cpacrMask.asedis = ones; 778 779 // Security Extensions may limit the writability of CPACR 780 if (haveSecurity) { 781 scr = readMiscRegNoEffect(MISCREG_SCR); 782 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 783 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 784 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 785 // NB: Skipping the full loop, here 786 if (!nsacr.cp10) cpacrMask.cp10 = 0; 787 if (!nsacr.cp11) cpacrMask.cp11 = 0; 788 } 789 } 790 791 MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR); 792 newVal &= cpacrMask; 793 newVal |= old_val & ~cpacrMask; 794 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 795 miscRegName[misc_reg], newVal); 796 } 797 break; 798 case MISCREG_CPTR_EL2: 799 { 800 const uint32_t ones = (uint32_t)(-1); 801 CPTR cptrMask = 0; 802 cptrMask.tcpac = ones; 803 cptrMask.tta = ones; 804 cptrMask.tfp = ones; 805 newVal &= cptrMask; 806 cptrMask = 0; 807 cptrMask.res1_13_12_el2 = ones; 808 cptrMask.res1_9_0_el2 = ones; 809 newVal |= cptrMask; 810 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 811 miscRegName[misc_reg], newVal); 812 } 813 break; 814 case MISCREG_CPTR_EL3: 815 { 816 const uint32_t ones = (uint32_t)(-1); 817 CPTR cptrMask = 0; 818 cptrMask.tcpac = ones; 819 cptrMask.tta = ones; 820 cptrMask.tfp = ones; 821 newVal &= cptrMask; 822 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 823 miscRegName[misc_reg], newVal); 824 } 825 break; 826 case MISCREG_CSSELR: 827 warn_once("The csselr register isn't implemented.\n"); 828 return; 829 830 case MISCREG_DC_ZVA_Xt: 831 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 832 return; 833 834 case MISCREG_FPSCR: 835 { 836 const uint32_t ones = (uint32_t)(-1); 837 FPSCR fpscrMask = 0; 838 fpscrMask.ioc = ones; 839 fpscrMask.dzc = ones; 840 fpscrMask.ofc = ones; 841 fpscrMask.ufc = ones; 842 fpscrMask.ixc = ones; 843 fpscrMask.idc = ones; 844 fpscrMask.ioe = ones; 845 fpscrMask.dze = ones; 846 fpscrMask.ofe = ones; 847 fpscrMask.ufe = ones; 848 fpscrMask.ixe = ones; 849 fpscrMask.ide = ones; 850 fpscrMask.len = ones; 851 fpscrMask.stride = ones; 852 fpscrMask.rMode = ones; 853 fpscrMask.fz = ones; 854 fpscrMask.dn = ones; 855 fpscrMask.ahp = ones; 856 fpscrMask.qc = ones; 857 fpscrMask.v = ones; 858 fpscrMask.c = ones; 859 fpscrMask.z = ones; 860 fpscrMask.n = ones; 861 newVal = (newVal & (uint32_t)fpscrMask) | 862 (readMiscRegNoEffect(MISCREG_FPSCR) & 863 ~(uint32_t)fpscrMask); 864 tc->getDecoderPtr()->setContext(newVal); 865 } 866 break; 867 case MISCREG_FPSR: 868 { 869 const uint32_t ones = (uint32_t)(-1); 870 FPSCR fpscrMask = 0; 871 fpscrMask.ioc = ones; 872 fpscrMask.dzc = ones; 873 fpscrMask.ofc = ones; 874 fpscrMask.ufc = ones; 875 fpscrMask.ixc = ones; 876 fpscrMask.idc = ones; 877 fpscrMask.qc = ones; 878 fpscrMask.v = ones; 879 fpscrMask.c = ones; 880 fpscrMask.z = ones; 881 fpscrMask.n = ones; 882 newVal = (newVal & (uint32_t)fpscrMask) | 883 (readMiscRegNoEffect(MISCREG_FPSCR) & 884 ~(uint32_t)fpscrMask); 885 misc_reg = MISCREG_FPSCR; 886 } 887 break; 888 case MISCREG_FPCR: 889 { 890 const uint32_t ones = (uint32_t)(-1); 891 FPSCR fpscrMask = 0; 892 fpscrMask.len = ones; 893 fpscrMask.stride = ones; 894 fpscrMask.rMode = ones; 895 fpscrMask.fz = ones; 896 fpscrMask.dn = ones; 897 fpscrMask.ahp = ones; 898 newVal = (newVal & (uint32_t)fpscrMask) | 899 (readMiscRegNoEffect(MISCREG_FPSCR) & 900 ~(uint32_t)fpscrMask); 901 misc_reg = MISCREG_FPSCR; 902 } 903 break; 904 case MISCREG_CPSR_Q: 905 { 906 assert(!(newVal & ~CpsrMaskQ)); 907 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 908 misc_reg = MISCREG_CPSR; 909 } 910 break; 911 case MISCREG_FPSCR_QC: 912 { 913 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 914 (newVal & FpscrQcMask); 915 misc_reg = MISCREG_FPSCR; 916 } 917 break; 918 case MISCREG_FPSCR_EXC: 919 { 920 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 921 (newVal & FpscrExcMask); 922 misc_reg = MISCREG_FPSCR; 923 } 924 break; 925 case MISCREG_FPEXC: 926 { 927 // vfpv3 architecture, section B.6.1 of DDI04068 928 // bit 29 - valid only if fpexc[31] is 0 929 const uint32_t fpexcMask = 0x60000000; 930 newVal = (newVal & fpexcMask) | 931 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 932 } 933 break; 934 case MISCREG_HCR: 935 { 936 if (!haveVirtualization) 937 return; 938 } 939 break; 940 case MISCREG_IFSR: 941 { 942 // ARM ARM (ARM DDI 0406C.b) B4.1.96 943 const uint32_t ifsrMask = 944 mask(31, 13) | mask(11, 11) | mask(8, 6); 945 newVal = newVal & ~ifsrMask; 946 } 947 break; 948 case MISCREG_DFSR: 949 { 950 // ARM ARM (ARM DDI 0406C.b) B4.1.52 951 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 952 newVal = newVal & ~dfsrMask; 953 } 954 break; 955 case MISCREG_AMAIR0: 956 case MISCREG_AMAIR1: 957 { 958 // ARM ARM (ARM DDI 0406C.b) B4.1.5 959 // Valid only with LPAE 960 if (!haveLPAE) 961 return; 962 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 963 } 964 break; 965 case MISCREG_SCR: 966 getITBPtr(tc)->invalidateMiscReg(); 967 getDTBPtr(tc)->invalidateMiscReg(); 968 break; 969 case MISCREG_SCTLR: 970 { 971 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 972 scr = readMiscRegNoEffect(MISCREG_SCR); 973 974 MiscRegIndex sctlr_idx; 975 if (haveSecurity && !highestELIs64 && !scr.ns) { 976 sctlr_idx = MISCREG_SCTLR_S; 977 } else { 978 sctlr_idx = MISCREG_SCTLR_NS; 979 } 980 981 SCTLR sctlr = miscRegs[sctlr_idx]; 982 SCTLR new_sctlr = newVal; 983 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 984 miscRegs[sctlr_idx] = (MiscReg)new_sctlr; 985 getITBPtr(tc)->invalidateMiscReg(); 986 getDTBPtr(tc)->invalidateMiscReg(); 987 } 988 case MISCREG_MIDR: 989 case MISCREG_ID_PFR0: 990 case MISCREG_ID_PFR1: 991 case MISCREG_ID_DFR0: 992 case MISCREG_ID_MMFR0: 993 case MISCREG_ID_MMFR1: 994 case MISCREG_ID_MMFR2: 995 case MISCREG_ID_MMFR3: 996 case MISCREG_ID_ISAR0: 997 case MISCREG_ID_ISAR1: 998 case MISCREG_ID_ISAR2: 999 case MISCREG_ID_ISAR3: 1000 case MISCREG_ID_ISAR4: 1001 case MISCREG_ID_ISAR5: 1002 1003 case MISCREG_MPIDR: 1004 case MISCREG_FPSID: 1005 case MISCREG_TLBTR: 1006 case MISCREG_MVFR0: 1007 case MISCREG_MVFR1: 1008 1009 case MISCREG_ID_AA64AFR0_EL1: 1010 case MISCREG_ID_AA64AFR1_EL1: 1011 case MISCREG_ID_AA64DFR0_EL1: 1012 case MISCREG_ID_AA64DFR1_EL1: 1013 case MISCREG_ID_AA64ISAR0_EL1: 1014 case MISCREG_ID_AA64ISAR1_EL1: 1015 case MISCREG_ID_AA64MMFR0_EL1: 1016 case MISCREG_ID_AA64MMFR1_EL1: 1017 case MISCREG_ID_AA64MMFR2_EL1: 1018 case MISCREG_ID_AA64PFR0_EL1: 1019 case MISCREG_ID_AA64PFR1_EL1: 1020 // ID registers are constants. 1021 return; 1022 1023 // TLB Invalidate All 1024 case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 1025 { 1026 assert32(tc); 1027 scr = readMiscReg(MISCREG_SCR, tc); 1028 1029 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1030 tlbiOp(tc); 1031 return; 1032 } 1033 // TLB Invalidate All, Inner Shareable 1034 case MISCREG_TLBIALLIS: 1035 { 1036 assert32(tc); 1037 scr = readMiscReg(MISCREG_SCR, tc); 1038 1039 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1040 tlbiOp.broadcast(tc); 1041 return; 1042 } 1043 // Instruction TLB Invalidate All 1044 case MISCREG_ITLBIALL: 1045 { 1046 assert32(tc); 1047 scr = readMiscReg(MISCREG_SCR, tc); 1048 1049 ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1050 tlbiOp(tc); 1051 return; 1052 } 1053 // Data TLB Invalidate All 1054 case MISCREG_DTLBIALL: 1055 { 1056 assert32(tc); 1057 scr = readMiscReg(MISCREG_SCR, tc); 1058 1059 DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1060 tlbiOp(tc); 1061 return; 1062 } 1063 // TLB Invalidate by VA 1064 // mcr tlbimval(is) is invalidating all matching entries 1065 // regardless of the level of lookup, since in gem5 we cache 1066 // in the tlb the last level of lookup only. 1067 case MISCREG_TLBIMVA: 1068 case MISCREG_TLBIMVAL: 1069 { 1070 assert32(tc); 1071 scr = readMiscReg(MISCREG_SCR, tc); 1072 1073 TLBIMVA tlbiOp(EL1, 1074 haveSecurity && !scr.ns, 1075 mbits(newVal, 31, 12), 1076 bits(newVal, 7,0)); 1077 1078 tlbiOp(tc); 1079 return; 1080 } 1081 // TLB Invalidate by VA, Inner Shareable 1082 case MISCREG_TLBIMVAIS: 1083 case MISCREG_TLBIMVALIS: 1084 { 1085 assert32(tc); 1086 scr = readMiscReg(MISCREG_SCR, tc); 1087 1088 TLBIMVA tlbiOp(EL1, 1089 haveSecurity && !scr.ns, 1090 mbits(newVal, 31, 12), 1091 bits(newVal, 7,0)); 1092 1093 tlbiOp.broadcast(tc); 1094 return; 1095 } 1096 // TLB Invalidate by ASID match 1097 case MISCREG_TLBIASID: 1098 { 1099 assert32(tc); 1100 scr = readMiscReg(MISCREG_SCR, tc); 1101 1102 TLBIASID tlbiOp(EL1, 1103 haveSecurity && !scr.ns, 1104 bits(newVal, 7,0)); 1105 1106 tlbiOp(tc); 1107 return; 1108 } 1109 // TLB Invalidate by ASID match, Inner Shareable 1110 case MISCREG_TLBIASIDIS: 1111 { 1112 assert32(tc); 1113 scr = readMiscReg(MISCREG_SCR, tc); 1114 1115 TLBIASID tlbiOp(EL1, 1116 haveSecurity && !scr.ns, 1117 bits(newVal, 7,0)); 1118 1119 tlbiOp.broadcast(tc); 1120 return; 1121 } 1122 // mcr tlbimvaal(is) is invalidating all matching entries 1123 // regardless of the level of lookup, since in gem5 we cache 1124 // in the tlb the last level of lookup only. 1125 // TLB Invalidate by VA, All ASID 1126 case MISCREG_TLBIMVAA: 1127 case MISCREG_TLBIMVAAL: 1128 { 1129 assert32(tc); 1130 scr = readMiscReg(MISCREG_SCR, tc); 1131 1132 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1133 mbits(newVal, 31,12), false); 1134 1135 tlbiOp(tc); 1136 return; 1137 } 1138 // TLB Invalidate by VA, All ASID, Inner Shareable 1139 case MISCREG_TLBIMVAAIS: 1140 case MISCREG_TLBIMVAALIS: 1141 { 1142 assert32(tc); 1143 scr = readMiscReg(MISCREG_SCR, tc); 1144 1145 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1146 mbits(newVal, 31,12), false); 1147 1148 tlbiOp.broadcast(tc); 1149 return; 1150 } 1151 // mcr tlbimvalh(is) is invalidating all matching entries 1152 // regardless of the level of lookup, since in gem5 we cache 1153 // in the tlb the last level of lookup only. 1154 // TLB Invalidate by VA, Hyp mode 1155 case MISCREG_TLBIMVAH: 1156 case MISCREG_TLBIMVALH: 1157 { 1158 assert32(tc); 1159 scr = readMiscReg(MISCREG_SCR, tc); 1160 1161 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1162 mbits(newVal, 31,12), true); 1163 1164 tlbiOp(tc); 1165 return; 1166 } 1167 // TLB Invalidate by VA, Hyp mode, Inner Shareable 1168 case MISCREG_TLBIMVAHIS: 1169 case MISCREG_TLBIMVALHIS: 1170 { 1171 assert32(tc); 1172 scr = readMiscReg(MISCREG_SCR, tc); 1173 1174 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1175 mbits(newVal, 31,12), true); 1176 1177 tlbiOp.broadcast(tc); 1178 return; 1179 } 1180 // mcr tlbiipas2l(is) is invalidating all matching entries 1181 // regardless of the level of lookup, since in gem5 we cache 1182 // in the tlb the last level of lookup only. 1183 // TLB Invalidate by Intermediate Physical Address, Stage 2 1184 case MISCREG_TLBIIPAS2: 1185 case MISCREG_TLBIIPAS2L: 1186 { 1187 assert32(tc); 1188 scr = readMiscReg(MISCREG_SCR, tc); 1189 1190 TLBIIPA tlbiOp(EL1, 1191 haveSecurity && !scr.ns, 1192 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1193 1194 tlbiOp(tc); 1195 return; 1196 } 1197 // TLB Invalidate by Intermediate Physical Address, Stage 2, 1198 // Inner Shareable 1199 case MISCREG_TLBIIPAS2IS: 1200 case MISCREG_TLBIIPAS2LIS: 1201 { 1202 assert32(tc); 1203 scr = readMiscReg(MISCREG_SCR, tc); 1204 1205 TLBIIPA tlbiOp(EL1, 1206 haveSecurity && !scr.ns, 1207 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1208 1209 tlbiOp.broadcast(tc); 1210 return; 1211 } 1212 // Instruction TLB Invalidate by VA 1213 case MISCREG_ITLBIMVA: 1214 { 1215 assert32(tc); 1216 scr = readMiscReg(MISCREG_SCR, tc); 1217 1218 ITLBIMVA tlbiOp(EL1, 1219 haveSecurity && !scr.ns, 1220 mbits(newVal, 31, 12), 1221 bits(newVal, 7,0)); 1222 1223 tlbiOp(tc); 1224 return; 1225 } 1226 // Data TLB Invalidate by VA 1227 case MISCREG_DTLBIMVA: 1228 { 1229 assert32(tc); 1230 scr = readMiscReg(MISCREG_SCR, tc); 1231 1232 DTLBIMVA tlbiOp(EL1, 1233 haveSecurity && !scr.ns, 1234 mbits(newVal, 31, 12), 1235 bits(newVal, 7,0)); 1236 1237 tlbiOp(tc); 1238 return; 1239 } 1240 // Instruction TLB Invalidate by ASID match 1241 case MISCREG_ITLBIASID: 1242 { 1243 assert32(tc); 1244 scr = readMiscReg(MISCREG_SCR, tc); 1245 1246 ITLBIASID tlbiOp(EL1, 1247 haveSecurity && !scr.ns, 1248 bits(newVal, 7,0)); 1249 1250 tlbiOp(tc); 1251 return; 1252 } 1253 // Data TLB Invalidate by ASID match 1254 case MISCREG_DTLBIASID: 1255 { 1256 assert32(tc); 1257 scr = readMiscReg(MISCREG_SCR, tc); 1258 1259 DTLBIASID tlbiOp(EL1, 1260 haveSecurity && !scr.ns, 1261 bits(newVal, 7,0)); 1262 1263 tlbiOp(tc); 1264 return; 1265 } 1266 // TLB Invalidate All, Non-Secure Non-Hyp 1267 case MISCREG_TLBIALLNSNH: 1268 { 1269 assert32(tc); 1270 1271 TLBIALLN tlbiOp(EL1, false); 1272 tlbiOp(tc); 1273 return; 1274 } 1275 // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable 1276 case MISCREG_TLBIALLNSNHIS: 1277 { 1278 assert32(tc); 1279 1280 TLBIALLN tlbiOp(EL1, false); 1281 tlbiOp.broadcast(tc); 1282 return; 1283 } 1284 // TLB Invalidate All, Hyp mode 1285 case MISCREG_TLBIALLH: 1286 { 1287 assert32(tc); 1288 1289 TLBIALLN tlbiOp(EL1, true); 1290 tlbiOp(tc); 1291 return; 1292 } 1293 // TLB Invalidate All, Hyp mode, Inner Shareable 1294 case MISCREG_TLBIALLHIS: 1295 { 1296 assert32(tc); 1297 1298 TLBIALLN tlbiOp(EL1, true); 1299 tlbiOp.broadcast(tc); 1300 return; 1301 } 1302 // AArch64 TLB Invalidate All, EL3 1303 case MISCREG_TLBI_ALLE3: 1304 { 1305 assert64(tc); 1306 1307 TLBIALL tlbiOp(EL3, true); 1308 tlbiOp(tc); 1309 return; 1310 } 1311 // AArch64 TLB Invalidate All, EL3, Inner Shareable 1312 case MISCREG_TLBI_ALLE3IS: 1313 { 1314 assert64(tc); 1315 1316 TLBIALL tlbiOp(EL3, true); 1317 tlbiOp.broadcast(tc); 1318 return; 1319 } 1320 // @todo: uncomment this to enable Virtualization 1321 // case MISCREG_TLBI_ALLE2IS: 1322 // case MISCREG_TLBI_ALLE2: 1323 // AArch64 TLB Invalidate All, EL1 1324 case MISCREG_TLBI_ALLE1: 1325 case MISCREG_TLBI_VMALLE1: 1326 case MISCREG_TLBI_VMALLS12E1: 1327 // @todo: handle VMID and stage 2 to enable Virtualization 1328 { 1329 assert64(tc); 1330 scr = readMiscReg(MISCREG_SCR, tc); 1331 1332 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1333 tlbiOp(tc); 1334 return; 1335 } 1336 // AArch64 TLB Invalidate All, EL1, Inner Shareable 1337 case MISCREG_TLBI_ALLE1IS: 1338 case MISCREG_TLBI_VMALLE1IS: 1339 case MISCREG_TLBI_VMALLS12E1IS: 1340 // @todo: handle VMID and stage 2 to enable Virtualization 1341 { 1342 assert64(tc); 1343 scr = readMiscReg(MISCREG_SCR, tc); 1344 1345 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1346 tlbiOp.broadcast(tc); 1347 return; 1348 } 1349 // VAEx(IS) and VALEx(IS) are the same because TLBs 1350 // only store entries 1351 // from the last level of translation table walks 1352 // @todo: handle VMID to enable Virtualization 1353 // AArch64 TLB Invalidate by VA, EL3 1354 case MISCREG_TLBI_VAE3_Xt: 1355 case MISCREG_TLBI_VALE3_Xt: 1356 { 1357 assert64(tc); 1358 1359 TLBIMVA tlbiOp(EL3, true, 1360 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1361 0xbeef); 1362 tlbiOp(tc); 1363 return; 1364 } 1365 // AArch64 TLB Invalidate by VA, EL3, Inner Shareable 1366 case MISCREG_TLBI_VAE3IS_Xt: 1367 case MISCREG_TLBI_VALE3IS_Xt: 1368 { 1369 assert64(tc); 1370 1371 TLBIMVA tlbiOp(EL3, true, 1372 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1373 0xbeef); 1374 1375 tlbiOp.broadcast(tc); 1376 return; 1377 } 1378 // AArch64 TLB Invalidate by VA, EL2 1379 case MISCREG_TLBI_VAE2_Xt: 1380 case MISCREG_TLBI_VALE2_Xt: 1381 { 1382 assert64(tc); 1383 scr = readMiscReg(MISCREG_SCR, tc); 1384 1385 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1386 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1387 0xbeef); 1388 tlbiOp(tc); 1389 return; 1390 } 1391 // AArch64 TLB Invalidate by VA, EL2, Inner Shareable 1392 case MISCREG_TLBI_VAE2IS_Xt: 1393 case MISCREG_TLBI_VALE2IS_Xt: 1394 { 1395 assert64(tc); 1396 scr = readMiscReg(MISCREG_SCR, tc); 1397 1398 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1399 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1400 0xbeef); 1401 1402 tlbiOp.broadcast(tc); 1403 return; 1404 } 1405 // AArch64 TLB Invalidate by VA, EL1 1406 case MISCREG_TLBI_VAE1_Xt: 1407 case MISCREG_TLBI_VALE1_Xt: 1408 { 1409 assert64(tc); 1410 scr = readMiscReg(MISCREG_SCR, tc); 1411 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1412 bits(newVal, 55, 48); 1413 1414 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1415 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1416 asid); 1417 1418 tlbiOp(tc); 1419 return; 1420 } 1421 // AArch64 TLB Invalidate by VA, EL1, Inner Shareable 1422 case MISCREG_TLBI_VAE1IS_Xt: 1423 case MISCREG_TLBI_VALE1IS_Xt: 1424 { 1425 assert64(tc); 1426 scr = readMiscReg(MISCREG_SCR, tc); 1427 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1428 bits(newVal, 55, 48); 1429 1430 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1431 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1432 asid); 1433 1434 tlbiOp.broadcast(tc); 1435 return; 1436 } 1437 // AArch64 TLB Invalidate by ASID, EL1 1438 // @todo: handle VMID to enable Virtualization 1439 case MISCREG_TLBI_ASIDE1_Xt: 1440 { 1441 assert64(tc); 1442 scr = readMiscReg(MISCREG_SCR, tc); 1443 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1444 bits(newVal, 55, 48); 1445 1446 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1447 tlbiOp(tc); 1448 return; 1449 } 1450 // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable 1451 case MISCREG_TLBI_ASIDE1IS_Xt: 1452 { 1453 assert64(tc); 1454 scr = readMiscReg(MISCREG_SCR, tc); 1455 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1456 bits(newVal, 55, 48); 1457 1458 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1459 tlbiOp.broadcast(tc); 1460 return; 1461 } 1462 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 1463 // entries from the last level of translation table walks 1464 // AArch64 TLB Invalidate by VA, All ASID, EL1 1465 case MISCREG_TLBI_VAAE1_Xt: 1466 case MISCREG_TLBI_VAALE1_Xt: 1467 { 1468 assert64(tc); 1469 scr = readMiscReg(MISCREG_SCR, tc); 1470 1471 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1472 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 1473 1474 tlbiOp(tc); 1475 return; 1476 } 1477 // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable 1478 case MISCREG_TLBI_VAAE1IS_Xt: 1479 case MISCREG_TLBI_VAALE1IS_Xt: 1480 { 1481 assert64(tc); 1482 scr = readMiscReg(MISCREG_SCR, tc); 1483 1484 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1485 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 1486 1487 tlbiOp.broadcast(tc); 1488 return; 1489 } 1490 // AArch64 TLB Invalidate by Intermediate Physical Address, 1491 // Stage 2, EL1 1492 case MISCREG_TLBI_IPAS2E1_Xt: 1493 case MISCREG_TLBI_IPAS2LE1_Xt: 1494 { 1495 assert64(tc); 1496 scr = readMiscReg(MISCREG_SCR, tc); 1497 1498 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1499 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1500 1501 tlbiOp(tc); 1502 return; 1503 } 1504 // AArch64 TLB Invalidate by Intermediate Physical Address, 1505 // Stage 2, EL1, Inner Shareable 1506 case MISCREG_TLBI_IPAS2E1IS_Xt: 1507 case MISCREG_TLBI_IPAS2LE1IS_Xt: 1508 { 1509 assert64(tc); 1510 scr = readMiscReg(MISCREG_SCR, tc); 1511 1512 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1513 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1514 1515 tlbiOp.broadcast(tc); 1516 return; 1517 } 1518 case MISCREG_ACTLR: 1519 warn("Not doing anything for write of miscreg ACTLR\n"); 1520 break; 1521 1522 case MISCREG_PMXEVTYPER_PMCCFILTR: 1523 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 1524 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 1525 case MISCREG_PMCR ... MISCREG_PMOVSSET: 1526 pmu->setMiscReg(misc_reg, newVal); 1527 break; 1528 1529 1530 case MISCREG_HSTR: // TJDBX, now redifined to be RES0 1531 { 1532 HSTR hstrMask = 0; 1533 hstrMask.tjdbx = 1; 1534 newVal &= ~((uint32_t) hstrMask); 1535 break; 1536 } 1537 case MISCREG_HCPTR: 1538 { 1539 // If a CP bit in NSACR is 0 then the corresponding bit in 1540 // HCPTR is RAO/WI. Same applies to NSASEDIS 1541 secure_lookup = haveSecurity && 1542 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 1543 readMiscRegNoEffect(MISCREG_CPSR)); 1544 if (!secure_lookup) { 1545 MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 1546 MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 1547 newVal = (newVal & ~mask) | (oldValue & mask); 1548 } 1549 break; 1550 } 1551 case MISCREG_HDFAR: // alias for secure DFAR 1552 misc_reg = MISCREG_DFAR_S; 1553 break; 1554 case MISCREG_HIFAR: // alias for secure IFAR 1555 misc_reg = MISCREG_IFAR_S; 1556 break; 1557 case MISCREG_ATS1CPR: 1558 case MISCREG_ATS1CPW: 1559 case MISCREG_ATS1CUR: 1560 case MISCREG_ATS1CUW: 1561 case MISCREG_ATS12NSOPR: 1562 case MISCREG_ATS12NSOPW: 1563 case MISCREG_ATS12NSOUR: 1564 case MISCREG_ATS12NSOUW: 1565 case MISCREG_ATS1HR: 1566 case MISCREG_ATS1HW: 1567 { 1568 Request::Flags flags = 0; 1569 BaseTLB::Mode mode = BaseTLB::Read; 1570 TLB::ArmTranslationType tranType = TLB::NormalTran; 1571 Fault fault; 1572 switch(misc_reg) { 1573 case MISCREG_ATS1CPR: 1574 flags = TLB::MustBeOne; 1575 tranType = TLB::S1CTran; 1576 mode = BaseTLB::Read; 1577 break; 1578 case MISCREG_ATS1CPW: 1579 flags = TLB::MustBeOne; 1580 tranType = TLB::S1CTran; 1581 mode = BaseTLB::Write; 1582 break; 1583 case MISCREG_ATS1CUR: 1584 flags = TLB::MustBeOne | TLB::UserMode; 1585 tranType = TLB::S1CTran; 1586 mode = BaseTLB::Read; 1587 break; 1588 case MISCREG_ATS1CUW: 1589 flags = TLB::MustBeOne | TLB::UserMode; 1590 tranType = TLB::S1CTran; 1591 mode = BaseTLB::Write; 1592 break; 1593 case MISCREG_ATS12NSOPR: 1594 if (!haveSecurity) 1595 panic("Security Extensions required for ATS12NSOPR"); 1596 flags = TLB::MustBeOne; 1597 tranType = TLB::S1S2NsTran; 1598 mode = BaseTLB::Read; 1599 break; 1600 case MISCREG_ATS12NSOPW: 1601 if (!haveSecurity) 1602 panic("Security Extensions required for ATS12NSOPW"); 1603 flags = TLB::MustBeOne; 1604 tranType = TLB::S1S2NsTran; 1605 mode = BaseTLB::Write; 1606 break; 1607 case MISCREG_ATS12NSOUR: 1608 if (!haveSecurity) 1609 panic("Security Extensions required for ATS12NSOUR"); 1610 flags = TLB::MustBeOne | TLB::UserMode; 1611 tranType = TLB::S1S2NsTran; 1612 mode = BaseTLB::Read; 1613 break; 1614 case MISCREG_ATS12NSOUW: 1615 if (!haveSecurity) 1616 panic("Security Extensions required for ATS12NSOUW"); 1617 flags = TLB::MustBeOne | TLB::UserMode; 1618 tranType = TLB::S1S2NsTran; 1619 mode = BaseTLB::Write; 1620 break; 1621 case MISCREG_ATS1HR: // only really useful from secure mode. 1622 flags = TLB::MustBeOne; 1623 tranType = TLB::HypMode; 1624 mode = BaseTLB::Read; 1625 break; 1626 case MISCREG_ATS1HW: 1627 flags = TLB::MustBeOne; 1628 tranType = TLB::HypMode; 1629 mode = BaseTLB::Write; 1630 break; 1631 } 1632 // If we're in timing mode then doing the translation in 1633 // functional mode then we're slightly distorting performance 1634 // results obtained from simulations. The translation should be 1635 // done in the same mode the core is running in. NOTE: This 1636 // can't be an atomic translation because that causes problems 1637 // with unexpected atomic snoop requests. 1638 warn("Translating via %s in functional mode! Fix Me!\n", 1639 miscRegName[misc_reg]); 1640 1641 auto req = std::make_shared<Request>( 1642 0, val, 0, flags, Request::funcMasterId, 1643 tc->pcState().pc(), tc->contextId()); 1644 1645 fault = getDTBPtr(tc)->translateFunctional( 1646 req, tc, mode, tranType); 1647 1648 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1649 HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 1650 1651 MiscReg newVal; 1652 if (fault == NoFault) { 1653 Addr paddr = req->getPaddr(); 1654 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 1655 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 1656 newVal = (paddr & mask(39, 12)) | 1657 (getDTBPtr(tc)->getAttr()); 1658 } else { 1659 newVal = (paddr & 0xfffff000) | 1660 (getDTBPtr(tc)->getAttr()); 1661 } 1662 DPRINTF(MiscRegs, 1663 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 1664 val, newVal); 1665 } else { 1666 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1667 armFault->update(tc); 1668 // Set fault bit and FSR 1669 FSR fsr = armFault->getFsr(tc); 1670 1671 newVal = ((fsr >> 9) & 1) << 11; 1672 if (newVal) { 1673 // LPAE - rearange fault status 1674 newVal |= ((fsr >> 0) & 0x3f) << 1; 1675 } else { 1676 // VMSA - rearange fault status 1677 newVal |= ((fsr >> 0) & 0xf) << 1; 1678 newVal |= ((fsr >> 10) & 0x1) << 5; 1679 newVal |= ((fsr >> 12) & 0x1) << 6; 1680 } 1681 newVal |= 0x1; // F bit 1682 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1683 newVal |= armFault->isStage2() ? 0x200 : 0; 1684 DPRINTF(MiscRegs, 1685 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 1686 val, fsr, newVal); 1687 } 1688 setMiscRegNoEffect(MISCREG_PAR, newVal); 1689 return; 1690 } 1691 case MISCREG_TTBCR: 1692 { 1693 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1694 const uint32_t ones = (uint32_t)(-1); 1695 TTBCR ttbcrMask = 0; 1696 TTBCR ttbcrNew = newVal; 1697 1698 // ARM DDI 0406C.b, ARMv7-32 1699 ttbcrMask.n = ones; // T0SZ 1700 if (haveSecurity) { 1701 ttbcrMask.pd0 = ones; 1702 ttbcrMask.pd1 = ones; 1703 } 1704 ttbcrMask.epd0 = ones; 1705 ttbcrMask.irgn0 = ones; 1706 ttbcrMask.orgn0 = ones; 1707 ttbcrMask.sh0 = ones; 1708 ttbcrMask.ps = ones; // T1SZ 1709 ttbcrMask.a1 = ones; 1710 ttbcrMask.epd1 = ones; 1711 ttbcrMask.irgn1 = ones; 1712 ttbcrMask.orgn1 = ones; 1713 ttbcrMask.sh1 = ones; 1714 if (haveLPAE) 1715 ttbcrMask.eae = ones; 1716 1717 if (haveLPAE && ttbcrNew.eae) { 1718 newVal = newVal & ttbcrMask; 1719 } else { 1720 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 1721 } 1722 // Invalidate TLB MiscReg 1723 getITBPtr(tc)->invalidateMiscReg(); 1724 getDTBPtr(tc)->invalidateMiscReg(); 1725 break; 1726 } 1727 case MISCREG_TTBR0: 1728 case MISCREG_TTBR1: 1729 { 1730 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1731 if (haveLPAE) { 1732 if (ttbcr.eae) { 1733 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 1734 // ARMv8 AArch32 bit 63-56 only 1735 uint64_t ttbrMask = mask(63,56) | mask(47,40); 1736 newVal = (newVal & (~ttbrMask)); 1737 } 1738 } 1739 // Invalidate TLB MiscReg 1740 getITBPtr(tc)->invalidateMiscReg(); 1741 getDTBPtr(tc)->invalidateMiscReg(); 1742 break; 1743 } 1744 case MISCREG_SCTLR_EL1: 1745 case MISCREG_CONTEXTIDR: 1746 case MISCREG_PRRR: 1747 case MISCREG_NMRR: 1748 case MISCREG_MAIR0: 1749 case MISCREG_MAIR1: 1750 case MISCREG_DACR: 1751 case MISCREG_VTTBR: 1752 case MISCREG_SCR_EL3: 1753 case MISCREG_HCR_EL2: 1754 case MISCREG_TCR_EL1: 1755 case MISCREG_TCR_EL2: 1756 case MISCREG_TCR_EL3: 1757 case MISCREG_SCTLR_EL2: 1758 case MISCREG_SCTLR_EL3: 1759 case MISCREG_HSCTLR: 1760 case MISCREG_TTBR0_EL1: 1761 case MISCREG_TTBR1_EL1: 1762 case MISCREG_TTBR0_EL2: 1763 case MISCREG_TTBR1_EL2: 1764 case MISCREG_TTBR0_EL3: 1765 getITBPtr(tc)->invalidateMiscReg(); 1766 getDTBPtr(tc)->invalidateMiscReg(); 1767 break; 1768 case MISCREG_NZCV: 1769 { 1770 CPSR cpsr = val; 1771 1772 tc->setCCReg(CCREG_NZ, cpsr.nz); 1773 tc->setCCReg(CCREG_C, cpsr.c); 1774 tc->setCCReg(CCREG_V, cpsr.v); 1775 } 1776 break; 1777 case MISCREG_DAIF: 1778 { 1779 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1780 cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 1781 newVal = cpsr; 1782 misc_reg = MISCREG_CPSR; 1783 } 1784 break; 1785 case MISCREG_SP_EL0: 1786 tc->setIntReg(INTREG_SP0, newVal); 1787 break; 1788 case MISCREG_SP_EL1: 1789 tc->setIntReg(INTREG_SP1, newVal); 1790 break; 1791 case MISCREG_SP_EL2: 1792 tc->setIntReg(INTREG_SP2, newVal); 1793 break; 1794 case MISCREG_SPSEL: 1795 { 1796 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1797 cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 1798 newVal = cpsr; 1799 misc_reg = MISCREG_CPSR; 1800 } 1801 break; 1802 case MISCREG_CURRENTEL: 1803 { 1804 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1805 cpsr.el = (uint8_t) ((CPSR) newVal).el; 1806 newVal = cpsr; 1807 misc_reg = MISCREG_CPSR; 1808 } 1809 break; 1810 case MISCREG_AT_S1E1R_Xt: 1811 case MISCREG_AT_S1E1W_Xt: 1812 case MISCREG_AT_S1E0R_Xt: 1813 case MISCREG_AT_S1E0W_Xt: 1814 case MISCREG_AT_S1E2R_Xt: 1815 case MISCREG_AT_S1E2W_Xt: 1816 case MISCREG_AT_S12E1R_Xt: 1817 case MISCREG_AT_S12E1W_Xt: 1818 case MISCREG_AT_S12E0R_Xt: 1819 case MISCREG_AT_S12E0W_Xt: 1820 case MISCREG_AT_S1E3R_Xt: 1821 case MISCREG_AT_S1E3W_Xt: 1822 { 1823 RequestPtr req = std::make_shared<Request>(); 1824 Request::Flags flags = 0; 1825 BaseTLB::Mode mode = BaseTLB::Read; 1826 TLB::ArmTranslationType tranType = TLB::NormalTran; 1827 Fault fault; 1828 switch(misc_reg) { 1829 case MISCREG_AT_S1E1R_Xt: 1830 flags = TLB::MustBeOne; 1831 tranType = TLB::S1E1Tran; 1832 mode = BaseTLB::Read; 1833 break; 1834 case MISCREG_AT_S1E1W_Xt: 1835 flags = TLB::MustBeOne; 1836 tranType = TLB::S1E1Tran; 1837 mode = BaseTLB::Write; 1838 break; 1839 case MISCREG_AT_S1E0R_Xt: 1840 flags = TLB::MustBeOne | TLB::UserMode; 1841 tranType = TLB::S1E0Tran; 1842 mode = BaseTLB::Read; 1843 break; 1844 case MISCREG_AT_S1E0W_Xt: 1845 flags = TLB::MustBeOne | TLB::UserMode; 1846 tranType = TLB::S1E0Tran; 1847 mode = BaseTLB::Write; 1848 break; 1849 case MISCREG_AT_S1E2R_Xt: 1850 flags = TLB::MustBeOne; 1851 tranType = TLB::S1E2Tran; 1852 mode = BaseTLB::Read; 1853 break; 1854 case MISCREG_AT_S1E2W_Xt: 1855 flags = TLB::MustBeOne; 1856 tranType = TLB::S1E2Tran; 1857 mode = BaseTLB::Write; 1858 break; 1859 case MISCREG_AT_S12E0R_Xt: 1860 flags = TLB::MustBeOne | TLB::UserMode; 1861 tranType = TLB::S12E0Tran; 1862 mode = BaseTLB::Read; 1863 break; 1864 case MISCREG_AT_S12E0W_Xt: 1865 flags = TLB::MustBeOne | TLB::UserMode; 1866 tranType = TLB::S12E0Tran; 1867 mode = BaseTLB::Write; 1868 break; 1869 case MISCREG_AT_S12E1R_Xt: 1870 flags = TLB::MustBeOne; 1871 tranType = TLB::S12E1Tran; 1872 mode = BaseTLB::Read; 1873 break; 1874 case MISCREG_AT_S12E1W_Xt: 1875 flags = TLB::MustBeOne; 1876 tranType = TLB::S12E1Tran; 1877 mode = BaseTLB::Write; 1878 break; 1879 case MISCREG_AT_S1E3R_Xt: 1880 flags = TLB::MustBeOne; 1881 tranType = TLB::S1E3Tran; 1882 mode = BaseTLB::Read; 1883 break; 1884 case MISCREG_AT_S1E3W_Xt: 1885 flags = TLB::MustBeOne; 1886 tranType = TLB::S1E3Tran; 1887 mode = BaseTLB::Write; 1888 break; 1889 } 1890 // If we're in timing mode then doing the translation in 1891 // functional mode then we're slightly distorting performance 1892 // results obtained from simulations. The translation should be 1893 // done in the same mode the core is running in. NOTE: This 1894 // can't be an atomic translation because that causes problems 1895 // with unexpected atomic snoop requests. 1896 warn("Translating via %s in functional mode! Fix Me!\n", 1897 miscRegName[misc_reg]); 1898 1899 req->setVirt(0, val, 0, flags, Request::funcMasterId, 1900 tc->pcState().pc()); 1901 req->setContext(tc->contextId()); 1902 fault = getDTBPtr(tc)->translateFunctional(req, tc, mode, 1903 tranType); 1904 1905 MiscReg newVal; 1906 if (fault == NoFault) { 1907 Addr paddr = req->getPaddr(); 1908 uint64_t attr = getDTBPtr(tc)->getAttr(); 1909 uint64_t attr1 = attr >> 56; 1910 if (!attr1 || attr1 ==0x44) { 1911 attr |= 0x100; 1912 attr &= ~ uint64_t(0x80); 1913 } 1914 newVal = (paddr & mask(47, 12)) | attr; 1915 DPRINTF(MiscRegs, 1916 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 1917 val, newVal); 1918 } else { 1919 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1920 armFault->update(tc); 1921 // Set fault bit and FSR 1922 FSR fsr = armFault->getFsr(tc); 1923 1924 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1925 if (cpsr.width) { // AArch32 1926 newVal = ((fsr >> 9) & 1) << 11; 1927 // rearrange fault status 1928 newVal |= ((fsr >> 0) & 0x3f) << 1; 1929 newVal |= 0x1; // F bit 1930 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1931 newVal |= armFault->isStage2() ? 0x200 : 0; 1932 } else { // AArch64 1933 newVal = 1; // F bit 1934 newVal |= fsr << 1; // FST 1935 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit. 1936 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 1937 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 1938 newVal |= 1 << 11; // RES1 1939 } 1940 DPRINTF(MiscRegs, 1941 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 1942 val, fsr, newVal); 1943 } 1944 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 1945 return; 1946 } 1947 case MISCREG_SPSR_EL3: 1948 case MISCREG_SPSR_EL2: 1949 case MISCREG_SPSR_EL1: 1950 // Force bits 23:21 to 0 1951 newVal = val & ~(0x7 << 21); 1952 break; 1953 case MISCREG_L2CTLR: 1954 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 1955 miscRegName[misc_reg], uint32_t(val)); 1956 break; 1957 1958 // Generic Timer registers 1959 case MISCREG_CNTHV_CTL_EL2: 1960 case MISCREG_CNTHV_CVAL_EL2: 1961 case MISCREG_CNTHV_TVAL_EL2: 1962 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 1963 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 1964 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 1965 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 1966 getGenericTimer(tc).setMiscReg(misc_reg, newVal); 1967 break; 1968 } 1969 } 1970 setMiscRegNoEffect(misc_reg, newVal); 1971} 1972 1973BaseISADevice & 1974ISA::getGenericTimer(ThreadContext *tc) 1975{ 1976 // We only need to create an ISA interface the first time we try 1977 // to access the timer. 1978 if (timer) 1979 return *timer.get(); 1980 1981 assert(system); 1982 GenericTimer *generic_timer(system->getGenericTimer()); 1983 if (!generic_timer) { 1984 panic("Trying to get a generic timer from a system that hasn't " 1985 "been configured to use a generic timer.\n"); 1986 } 1987 1988 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 1989 timer->setThreadContext(tc); 1990 1991 return *timer.get(); 1992} 1993 1994} 1995 1996ArmISA::ISA * 1997ArmISAParams::create() 1998{ 1999 return new ArmISA::ISA(this); 2000} 2001