isa.cc revision 13499:7f9d435bac22
1/* 2 * Copyright (c) 2010-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 */ 40 41#include "arch/arm/isa.hh" 42#include "arch/arm/pmu.hh" 43#include "arch/arm/system.hh" 44#include "arch/arm/tlb.hh" 45#include "arch/arm/tlbi_op.hh" 46#include "cpu/base.hh" 47#include "cpu/checker/cpu.hh" 48#include "debug/Arm.hh" 49#include "debug/MiscRegs.hh" 50#include "dev/arm/generic_timer.hh" 51#include "params/ArmISA.hh" 52#include "sim/faults.hh" 53#include "sim/stat_control.hh" 54#include "sim/system.hh" 55 56namespace ArmISA 57{ 58 59ISA::ISA(Params *p) 60 : SimObject(p), 61 system(NULL), 62 _decoderFlavour(p->decoderFlavour), 63 _vecRegRenameMode(p->vecRegRenameMode), 64 pmu(p->pmu), 65 impdefAsNop(p->impdef_nop) 66{ 67 miscRegs[MISCREG_SCTLR_RST] = 0; 68 69 // Hook up a dummy device if we haven't been configured with a 70 // real PMU. By using a dummy device, we don't need to check that 71 // the PMU exist every time we try to access a PMU register. 72 if (!pmu) 73 pmu = &dummyDevice; 74 75 // Give all ISA devices a pointer to this ISA 76 pmu->setISA(this); 77 78 system = dynamic_cast<ArmSystem *>(p->system); 79 80 // Cache system-level properties 81 if (FullSystem && system) { 82 highestELIs64 = system->highestELIs64(); 83 haveSecurity = system->haveSecurity(); 84 haveLPAE = system->haveLPAE(); 85 haveCrypto = system->haveCrypto(); 86 haveVirtualization = system->haveVirtualization(); 87 haveLargeAsid64 = system->haveLargeAsid64(); 88 physAddrRange = system->physAddrRange(); 89 } else { 90 highestELIs64 = true; // ArmSystem::highestELIs64 does the same 91 haveSecurity = haveLPAE = haveVirtualization = false; 92 haveCrypto = true; 93 haveLargeAsid64 = false; 94 physAddrRange = 32; // dummy value 95 } 96 97 initializeMiscRegMetadata(); 98 preUnflattenMiscReg(); 99 100 clear(); 101} 102 103std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS); 104 105const ArmISAParams * 106ISA::params() const 107{ 108 return dynamic_cast<const Params *>(_params); 109} 110 111void 112ISA::clear() 113{ 114 const Params *p(params()); 115 116 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 117 memset(miscRegs, 0, sizeof(miscRegs)); 118 119 initID32(p); 120 121 // We always initialize AArch64 ID registers even 122 // if we are in AArch32. This is done since if we 123 // are in SE mode we don't know if our ArmProcess is 124 // AArch32 or AArch64 125 initID64(p); 126 127 // Start with an event in the mailbox 128 miscRegs[MISCREG_SEV_MAILBOX] = 1; 129 130 // Separate Instruction and Data TLBs 131 miscRegs[MISCREG_TLBTR] = 1; 132 133 MVFR0 mvfr0 = 0; 134 mvfr0.advSimdRegisters = 2; 135 mvfr0.singlePrecision = 2; 136 mvfr0.doublePrecision = 2; 137 mvfr0.vfpExceptionTrapping = 0; 138 mvfr0.divide = 1; 139 mvfr0.squareRoot = 1; 140 mvfr0.shortVectors = 1; 141 mvfr0.roundingModes = 1; 142 miscRegs[MISCREG_MVFR0] = mvfr0; 143 144 MVFR1 mvfr1 = 0; 145 mvfr1.flushToZero = 1; 146 mvfr1.defaultNaN = 1; 147 mvfr1.advSimdLoadStore = 1; 148 mvfr1.advSimdInteger = 1; 149 mvfr1.advSimdSinglePrecision = 1; 150 mvfr1.advSimdHalfPrecision = 1; 151 mvfr1.vfpHalfPrecision = 1; 152 miscRegs[MISCREG_MVFR1] = mvfr1; 153 154 // Reset values of PRRR and NMRR are implementation dependent 155 156 // @todo: PRRR and NMRR in secure state? 157 miscRegs[MISCREG_PRRR_NS] = 158 (1 << 19) | // 19 159 (0 << 18) | // 18 160 (0 << 17) | // 17 161 (1 << 16) | // 16 162 (2 << 14) | // 15:14 163 (0 << 12) | // 13:12 164 (2 << 10) | // 11:10 165 (2 << 8) | // 9:8 166 (2 << 6) | // 7:6 167 (2 << 4) | // 5:4 168 (1 << 2) | // 3:2 169 0; // 1:0 170 171 miscRegs[MISCREG_NMRR_NS] = 172 (1 << 30) | // 31:30 173 (0 << 26) | // 27:26 174 (0 << 24) | // 25:24 175 (3 << 22) | // 23:22 176 (2 << 20) | // 21:20 177 (0 << 18) | // 19:18 178 (0 << 16) | // 17:16 179 (1 << 14) | // 15:14 180 (0 << 12) | // 13:12 181 (2 << 10) | // 11:10 182 (0 << 8) | // 9:8 183 (3 << 6) | // 7:6 184 (2 << 4) | // 5:4 185 (0 << 2) | // 3:2 186 0; // 1:0 187 188 if (FullSystem && system->highestELIs64()) { 189 // Initialize AArch64 state 190 clear64(p); 191 return; 192 } 193 194 // Initialize AArch32 state... 195 clear32(p, sctlr_rst); 196} 197 198void 199ISA::clear32(const ArmISAParams *p, const SCTLR &sctlr_rst) 200{ 201 CPSR cpsr = 0; 202 cpsr.mode = MODE_USER; 203 204 if (FullSystem) { 205 miscRegs[MISCREG_MVBAR] = system->resetAddr(); 206 } 207 208 miscRegs[MISCREG_CPSR] = cpsr; 209 updateRegMap(cpsr); 210 211 SCTLR sctlr = 0; 212 sctlr.te = (bool) sctlr_rst.te; 213 sctlr.nmfi = (bool) sctlr_rst.nmfi; 214 sctlr.v = (bool) sctlr_rst.v; 215 sctlr.u = 1; 216 sctlr.xp = 1; 217 sctlr.rao2 = 1; 218 sctlr.rao3 = 1; 219 sctlr.rao4 = 0xf; // SCTLR[6:3] 220 sctlr.uci = 1; 221 sctlr.dze = 1; 222 miscRegs[MISCREG_SCTLR_NS] = sctlr; 223 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 224 miscRegs[MISCREG_HCPTR] = 0; 225 226 miscRegs[MISCREG_CPACR] = 0; 227 228 miscRegs[MISCREG_FPSID] = p->fpsid; 229 230 if (haveLPAE) { 231 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 232 ttbcr.eae = 0; 233 miscRegs[MISCREG_TTBCR_NS] = ttbcr; 234 // Enforce consistency with system-level settings 235 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 236 } 237 238 if (haveSecurity) { 239 miscRegs[MISCREG_SCTLR_S] = sctlr; 240 miscRegs[MISCREG_SCR] = 0; 241 miscRegs[MISCREG_VBAR_S] = 0; 242 } else { 243 // we're always non-secure 244 miscRegs[MISCREG_SCR] = 1; 245 } 246 247 //XXX We need to initialize the rest of the state. 248} 249 250void 251ISA::clear64(const ArmISAParams *p) 252{ 253 CPSR cpsr = 0; 254 Addr rvbar = system->resetAddr(); 255 switch (system->highestEL()) { 256 // Set initial EL to highest implemented EL using associated stack 257 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 258 // value 259 case EL3: 260 cpsr.mode = MODE_EL3H; 261 miscRegs[MISCREG_RVBAR_EL3] = rvbar; 262 break; 263 case EL2: 264 cpsr.mode = MODE_EL2H; 265 miscRegs[MISCREG_RVBAR_EL2] = rvbar; 266 break; 267 case EL1: 268 cpsr.mode = MODE_EL1H; 269 miscRegs[MISCREG_RVBAR_EL1] = rvbar; 270 break; 271 default: 272 panic("Invalid highest implemented exception level"); 273 break; 274 } 275 276 // Initialize rest of CPSR 277 cpsr.daif = 0xf; // Mask all interrupts 278 cpsr.ss = 0; 279 cpsr.il = 0; 280 miscRegs[MISCREG_CPSR] = cpsr; 281 updateRegMap(cpsr); 282 283 // Initialize other control registers 284 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 285 if (haveSecurity) { 286 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830; 287 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 288 } else if (haveVirtualization) { 289 // also MISCREG_SCTLR_EL2 (by mapping) 290 miscRegs[MISCREG_HSCTLR] = 0x30c50830; 291 } else { 292 // also MISCREG_SCTLR_EL1 (by mapping) 293 miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init 294 // Always non-secure 295 miscRegs[MISCREG_SCR_EL3] = 1; 296 } 297} 298 299void 300ISA::initID32(const ArmISAParams *p) 301{ 302 // Initialize configurable default values 303 miscRegs[MISCREG_MIDR] = p->midr; 304 miscRegs[MISCREG_MIDR_EL1] = p->midr; 305 miscRegs[MISCREG_VPIDR] = p->midr; 306 307 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 308 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 309 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 310 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 311 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 312 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 313 314 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 315 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 316 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 317 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 318 319 miscRegs[MISCREG_ID_ISAR5] = insertBits( 320 miscRegs[MISCREG_ID_ISAR5], 19, 4, 321 haveCrypto ? 0x1112 : 0x0); 322} 323 324void 325ISA::initID64(const ArmISAParams *p) 326{ 327 // Initialize configurable id registers 328 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 329 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 330 miscRegs[MISCREG_ID_AA64DFR0_EL1] = 331 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 332 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 333 334 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 335 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 336 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 337 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 338 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 339 miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p->id_aa64mmfr2_el1; 340 341 miscRegs[MISCREG_ID_DFR0_EL1] = 342 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 343 344 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 345 346 // Enforce consistency with system-level settings... 347 348 // EL3 349 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 350 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 351 haveSecurity ? 0x2 : 0x0); 352 // EL2 353 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 354 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 355 haveVirtualization ? 0x2 : 0x0); 356 // Large ASID support 357 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 358 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 359 haveLargeAsid64 ? 0x2 : 0x0); 360 // Physical address size 361 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 362 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 363 encodePhysAddrRange64(physAddrRange)); 364 // Crypto 365 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits( 366 miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4, 367 haveCrypto ? 0x1112 : 0x0); 368} 369 370void 371ISA::startup(ThreadContext *tc) 372{ 373 pmu->setThreadContext(tc); 374 375} 376 377 378MiscReg 379ISA::readMiscRegNoEffect(int misc_reg) const 380{ 381 assert(misc_reg < NumMiscRegs); 382 383 const auto ® = lookUpMiscReg[misc_reg]; // bit masks 384 const auto &map = getMiscIndices(misc_reg); 385 int lower = map.first, upper = map.second; 386 // NB!: apply architectural masks according to desired register, 387 // despite possibly getting value from different (mapped) register. 388 auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32)) 389 |(miscRegs[upper] << 32)); 390 if (val & reg.res0()) { 391 DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n", 392 miscRegName[misc_reg], val & reg.res0()); 393 } 394 if ((val & reg.res1()) != reg.res1()) { 395 DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n", 396 miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1()); 397 } 398 return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao 399} 400 401 402MiscReg 403ISA::readMiscReg(int misc_reg, ThreadContext *tc) 404{ 405 CPSR cpsr = 0; 406 PCState pc = 0; 407 SCR scr = 0; 408 409 if (misc_reg == MISCREG_CPSR) { 410 cpsr = miscRegs[misc_reg]; 411 pc = tc->pcState(); 412 cpsr.j = pc.jazelle() ? 1 : 0; 413 cpsr.t = pc.thumb() ? 1 : 0; 414 return cpsr; 415 } 416 417#ifndef NDEBUG 418 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 419 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 420 warn("Unimplemented system register %s read.\n", 421 miscRegName[misc_reg]); 422 else 423 panic("Unimplemented system register %s read.\n", 424 miscRegName[misc_reg]); 425 } 426#endif 427 428 switch (unflattenMiscReg(misc_reg)) { 429 case MISCREG_HCR: 430 { 431 if (!haveVirtualization) 432 return 0; 433 else 434 return readMiscRegNoEffect(MISCREG_HCR); 435 } 436 case MISCREG_CPACR: 437 { 438 const uint32_t ones = (uint32_t)(-1); 439 CPACR cpacrMask = 0; 440 // Only cp10, cp11, and ase are implemented, nothing else should 441 // be readable? (straight copy from the write code) 442 cpacrMask.cp10 = ones; 443 cpacrMask.cp11 = ones; 444 cpacrMask.asedis = ones; 445 446 // Security Extensions may limit the readability of CPACR 447 if (haveSecurity) { 448 scr = readMiscRegNoEffect(MISCREG_SCR); 449 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 450 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 451 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 452 // NB: Skipping the full loop, here 453 if (!nsacr.cp10) cpacrMask.cp10 = 0; 454 if (!nsacr.cp11) cpacrMask.cp11 = 0; 455 } 456 } 457 MiscReg val = readMiscRegNoEffect(MISCREG_CPACR); 458 val &= cpacrMask; 459 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 460 miscRegName[misc_reg], val); 461 return val; 462 } 463 case MISCREG_MPIDR: 464 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 465 scr = readMiscRegNoEffect(MISCREG_SCR); 466 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 467 return getMPIDR(system, tc); 468 } else { 469 return readMiscReg(MISCREG_VMPIDR, tc); 470 } 471 break; 472 case MISCREG_MPIDR_EL1: 473 // @todo in the absence of v8 virtualization support just return MPIDR_EL1 474 return getMPIDR(system, tc) & 0xffffffff; 475 case MISCREG_VMPIDR: 476 // top bit defined as RES1 477 return readMiscRegNoEffect(misc_reg) | 0x80000000; 478 case MISCREG_ID_AFR0: // not implemented, so alias MIDR 479 case MISCREG_REVIDR: // not implemented, so alias MIDR 480 case MISCREG_MIDR: 481 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 482 scr = readMiscRegNoEffect(MISCREG_SCR); 483 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 484 return readMiscRegNoEffect(misc_reg); 485 } else { 486 return readMiscRegNoEffect(MISCREG_VPIDR); 487 } 488 break; 489 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 490 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 491 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 492 case MISCREG_AIDR: // AUX ID set to 0 493 case MISCREG_TCMTR: // No TCM's 494 return 0; 495 496 case MISCREG_CLIDR: 497 warn_once("The clidr register always reports 0 caches.\n"); 498 warn_once("clidr LoUIS field of 0b001 to match current " 499 "ARM implementations.\n"); 500 return 0x00200000; 501 case MISCREG_CCSIDR: 502 warn_once("The ccsidr register isn't implemented and " 503 "always reads as 0.\n"); 504 break; 505 case MISCREG_CTR: // AArch32, ARMv7, top bit set 506 case MISCREG_CTR_EL0: // AArch64 507 { 508 //all caches have the same line size in gem5 509 //4 byte words in ARM 510 unsigned lineSizeWords = 511 tc->getSystemPtr()->cacheLineSize() / 4; 512 unsigned log2LineSizeWords = 0; 513 514 while (lineSizeWords >>= 1) { 515 ++log2LineSizeWords; 516 } 517 518 CTR ctr = 0; 519 //log2 of minimun i-cache line size (words) 520 ctr.iCacheLineSize = log2LineSizeWords; 521 //b11 - gem5 uses pipt 522 ctr.l1IndexPolicy = 0x3; 523 //log2 of minimum d-cache line size (words) 524 ctr.dCacheLineSize = log2LineSizeWords; 525 //log2 of max reservation size (words) 526 ctr.erg = log2LineSizeWords; 527 //log2 of max writeback size (words) 528 ctr.cwg = log2LineSizeWords; 529 //b100 - gem5 format is ARMv7 530 ctr.format = 0x4; 531 532 return ctr; 533 } 534 case MISCREG_ACTLR: 535 warn("Not doing anything for miscreg ACTLR\n"); 536 break; 537 538 case MISCREG_PMXEVTYPER_PMCCFILTR: 539 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 540 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 541 case MISCREG_PMCR ... MISCREG_PMOVSSET: 542 return pmu->readMiscReg(misc_reg); 543 544 case MISCREG_CPSR_Q: 545 panic("shouldn't be reading this register seperately\n"); 546 case MISCREG_FPSCR_QC: 547 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 548 case MISCREG_FPSCR_EXC: 549 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 550 case MISCREG_FPSR: 551 { 552 const uint32_t ones = (uint32_t)(-1); 553 FPSCR fpscrMask = 0; 554 fpscrMask.ioc = ones; 555 fpscrMask.dzc = ones; 556 fpscrMask.ofc = ones; 557 fpscrMask.ufc = ones; 558 fpscrMask.ixc = ones; 559 fpscrMask.idc = ones; 560 fpscrMask.qc = ones; 561 fpscrMask.v = ones; 562 fpscrMask.c = ones; 563 fpscrMask.z = ones; 564 fpscrMask.n = ones; 565 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 566 } 567 case MISCREG_FPCR: 568 { 569 const uint32_t ones = (uint32_t)(-1); 570 FPSCR fpscrMask = 0; 571 fpscrMask.len = ones; 572 fpscrMask.stride = ones; 573 fpscrMask.rMode = ones; 574 fpscrMask.fz = ones; 575 fpscrMask.dn = ones; 576 fpscrMask.ahp = ones; 577 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 578 } 579 case MISCREG_NZCV: 580 { 581 CPSR cpsr = 0; 582 cpsr.nz = tc->readCCReg(CCREG_NZ); 583 cpsr.c = tc->readCCReg(CCREG_C); 584 cpsr.v = tc->readCCReg(CCREG_V); 585 return cpsr; 586 } 587 case MISCREG_DAIF: 588 { 589 CPSR cpsr = 0; 590 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 591 return cpsr; 592 } 593 case MISCREG_SP_EL0: 594 { 595 return tc->readIntReg(INTREG_SP0); 596 } 597 case MISCREG_SP_EL1: 598 { 599 return tc->readIntReg(INTREG_SP1); 600 } 601 case MISCREG_SP_EL2: 602 { 603 return tc->readIntReg(INTREG_SP2); 604 } 605 case MISCREG_SPSEL: 606 { 607 return miscRegs[MISCREG_CPSR] & 0x1; 608 } 609 case MISCREG_CURRENTEL: 610 { 611 return miscRegs[MISCREG_CPSR] & 0xc; 612 } 613 case MISCREG_L2CTLR: 614 { 615 // mostly unimplemented, just set NumCPUs field from sim and return 616 L2CTLR l2ctlr = 0; 617 // b00:1CPU to b11:4CPUs 618 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 619 return l2ctlr; 620 } 621 case MISCREG_DBGDIDR: 622 /* For now just implement the version number. 623 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 624 */ 625 return 0x5 << 16; 626 case MISCREG_DBGDSCRint: 627 return 0; 628 case MISCREG_ISR: 629 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 630 readMiscRegNoEffect(MISCREG_HCR), 631 readMiscRegNoEffect(MISCREG_CPSR), 632 readMiscRegNoEffect(MISCREG_SCR)); 633 case MISCREG_ISR_EL1: 634 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 635 readMiscRegNoEffect(MISCREG_HCR_EL2), 636 readMiscRegNoEffect(MISCREG_CPSR), 637 readMiscRegNoEffect(MISCREG_SCR_EL3)); 638 case MISCREG_DCZID_EL0: 639 return 0x04; // DC ZVA clear 64-byte chunks 640 case MISCREG_HCPTR: 641 { 642 MiscReg val = readMiscRegNoEffect(misc_reg); 643 // The trap bit associated with CP14 is defined as RAZ 644 val &= ~(1 << 14); 645 // If a CP bit in NSACR is 0 then the corresponding bit in 646 // HCPTR is RAO/WI 647 bool secure_lookup = haveSecurity && 648 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 649 readMiscRegNoEffect(MISCREG_CPSR)); 650 if (!secure_lookup) { 651 MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR); 652 val |= (mask ^ 0x7FFF) & 0xBFFF; 653 } 654 // Set the bits for unimplemented coprocessors to RAO/WI 655 val |= 0x33FF; 656 return (val); 657 } 658 case MISCREG_HDFAR: // alias for secure DFAR 659 return readMiscRegNoEffect(MISCREG_DFAR_S); 660 case MISCREG_HIFAR: // alias for secure IFAR 661 return readMiscRegNoEffect(MISCREG_IFAR_S); 662 case MISCREG_HVBAR: // bottom bits reserved 663 return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0; 664 case MISCREG_SCTLR: 665 return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818; 666 case MISCREG_SCTLR_EL1: 667 return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800; 668 case MISCREG_SCTLR_EL2: 669 case MISCREG_SCTLR_EL3: 670 case MISCREG_HSCTLR: 671 return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; 672 673 case MISCREG_ID_PFR0: 674 // !ThumbEE | !Jazelle | Thumb | ARM 675 return 0x00000031; 676 case MISCREG_ID_PFR1: 677 { // Timer | Virti | !M Profile | TrustZone | ARMv4 678 bool haveTimer = (system->getGenericTimer() != NULL); 679 return 0x00000001 680 | (haveSecurity ? 0x00000010 : 0x0) 681 | (haveVirtualization ? 0x00001000 : 0x0) 682 | (haveTimer ? 0x00010000 : 0x0); 683 } 684 case MISCREG_ID_AA64PFR0_EL1: 685 return 0x0000000000000002 // AArch{64,32} supported at EL0 686 | 0x0000000000000020 // EL1 687 | (haveVirtualization ? 0x0000000000000200 : 0) // EL2 688 | (haveSecurity ? 0x0000000000002000 : 0); // EL3 689 case MISCREG_ID_AA64PFR1_EL1: 690 return 0; // bits [63:0] RES0 (reserved for future use) 691 692 // Generic Timer registers 693 case MISCREG_CNTHV_CTL_EL2: 694 case MISCREG_CNTHV_CVAL_EL2: 695 case MISCREG_CNTHV_TVAL_EL2: 696 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 697 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 698 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 699 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 700 return getGenericTimer(tc).readMiscReg(misc_reg); 701 702 default: 703 break; 704 705 } 706 return readMiscRegNoEffect(misc_reg); 707} 708 709void 710ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 711{ 712 assert(misc_reg < NumMiscRegs); 713 714 const auto ® = lookUpMiscReg[misc_reg]; // bit masks 715 const auto &map = getMiscIndices(misc_reg); 716 int lower = map.first, upper = map.second; 717 718 auto v = (val & ~reg.wi()) | reg.rao(); 719 if (upper > 0) { 720 miscRegs[lower] = bits(v, 31, 0); 721 miscRegs[upper] = bits(v, 63, 32); 722 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 723 misc_reg, lower, upper, v); 724 } else { 725 miscRegs[lower] = v; 726 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 727 misc_reg, lower, v); 728 } 729} 730 731void 732ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 733{ 734 735 MiscReg newVal = val; 736 bool secure_lookup; 737 SCR scr; 738 739 if (misc_reg == MISCREG_CPSR) { 740 updateRegMap(val); 741 742 743 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 744 int old_mode = old_cpsr.mode; 745 CPSR cpsr = val; 746 if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) { 747 getITBPtr(tc)->invalidateMiscReg(); 748 getDTBPtr(tc)->invalidateMiscReg(); 749 } 750 751 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 752 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 753 PCState pc = tc->pcState(); 754 pc.nextThumb(cpsr.t); 755 pc.nextJazelle(cpsr.j); 756 pc.illegalExec(cpsr.il == 1); 757 758 // Follow slightly different semantics if a CheckerCPU object 759 // is connected 760 CheckerCPU *checker = tc->getCheckerCpuPtr(); 761 if (checker) { 762 tc->pcStateNoRecord(pc); 763 } else { 764 tc->pcState(pc); 765 } 766 } else { 767#ifndef NDEBUG 768 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 769 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 770 warn("Unimplemented system register %s write with %#x.\n", 771 miscRegName[misc_reg], val); 772 else 773 panic("Unimplemented system register %s write with %#x.\n", 774 miscRegName[misc_reg], val); 775 } 776#endif 777 switch (unflattenMiscReg(misc_reg)) { 778 case MISCREG_CPACR: 779 { 780 781 const uint32_t ones = (uint32_t)(-1); 782 CPACR cpacrMask = 0; 783 // Only cp10, cp11, and ase are implemented, nothing else should 784 // be writable 785 cpacrMask.cp10 = ones; 786 cpacrMask.cp11 = ones; 787 cpacrMask.asedis = ones; 788 789 // Security Extensions may limit the writability of CPACR 790 if (haveSecurity) { 791 scr = readMiscRegNoEffect(MISCREG_SCR); 792 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 793 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 794 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 795 // NB: Skipping the full loop, here 796 if (!nsacr.cp10) cpacrMask.cp10 = 0; 797 if (!nsacr.cp11) cpacrMask.cp11 = 0; 798 } 799 } 800 801 MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR); 802 newVal &= cpacrMask; 803 newVal |= old_val & ~cpacrMask; 804 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 805 miscRegName[misc_reg], newVal); 806 } 807 break; 808 case MISCREG_CPTR_EL2: 809 { 810 const uint32_t ones = (uint32_t)(-1); 811 CPTR cptrMask = 0; 812 cptrMask.tcpac = ones; 813 cptrMask.tta = ones; 814 cptrMask.tfp = ones; 815 newVal &= cptrMask; 816 cptrMask = 0; 817 cptrMask.res1_13_12_el2 = ones; 818 cptrMask.res1_9_0_el2 = ones; 819 newVal |= cptrMask; 820 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 821 miscRegName[misc_reg], newVal); 822 } 823 break; 824 case MISCREG_CPTR_EL3: 825 { 826 const uint32_t ones = (uint32_t)(-1); 827 CPTR cptrMask = 0; 828 cptrMask.tcpac = ones; 829 cptrMask.tta = ones; 830 cptrMask.tfp = ones; 831 newVal &= cptrMask; 832 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 833 miscRegName[misc_reg], newVal); 834 } 835 break; 836 case MISCREG_CSSELR: 837 warn_once("The csselr register isn't implemented.\n"); 838 return; 839 840 case MISCREG_DC_ZVA_Xt: 841 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 842 return; 843 844 case MISCREG_FPSCR: 845 { 846 const uint32_t ones = (uint32_t)(-1); 847 FPSCR fpscrMask = 0; 848 fpscrMask.ioc = ones; 849 fpscrMask.dzc = ones; 850 fpscrMask.ofc = ones; 851 fpscrMask.ufc = ones; 852 fpscrMask.ixc = ones; 853 fpscrMask.idc = ones; 854 fpscrMask.ioe = ones; 855 fpscrMask.dze = ones; 856 fpscrMask.ofe = ones; 857 fpscrMask.ufe = ones; 858 fpscrMask.ixe = ones; 859 fpscrMask.ide = ones; 860 fpscrMask.len = ones; 861 fpscrMask.stride = ones; 862 fpscrMask.rMode = ones; 863 fpscrMask.fz = ones; 864 fpscrMask.dn = ones; 865 fpscrMask.ahp = ones; 866 fpscrMask.qc = ones; 867 fpscrMask.v = ones; 868 fpscrMask.c = ones; 869 fpscrMask.z = ones; 870 fpscrMask.n = ones; 871 newVal = (newVal & (uint32_t)fpscrMask) | 872 (readMiscRegNoEffect(MISCREG_FPSCR) & 873 ~(uint32_t)fpscrMask); 874 tc->getDecoderPtr()->setContext(newVal); 875 } 876 break; 877 case MISCREG_FPSR: 878 { 879 const uint32_t ones = (uint32_t)(-1); 880 FPSCR fpscrMask = 0; 881 fpscrMask.ioc = ones; 882 fpscrMask.dzc = ones; 883 fpscrMask.ofc = ones; 884 fpscrMask.ufc = ones; 885 fpscrMask.ixc = ones; 886 fpscrMask.idc = ones; 887 fpscrMask.qc = ones; 888 fpscrMask.v = ones; 889 fpscrMask.c = ones; 890 fpscrMask.z = ones; 891 fpscrMask.n = ones; 892 newVal = (newVal & (uint32_t)fpscrMask) | 893 (readMiscRegNoEffect(MISCREG_FPSCR) & 894 ~(uint32_t)fpscrMask); 895 misc_reg = MISCREG_FPSCR; 896 } 897 break; 898 case MISCREG_FPCR: 899 { 900 const uint32_t ones = (uint32_t)(-1); 901 FPSCR fpscrMask = 0; 902 fpscrMask.len = ones; 903 fpscrMask.stride = ones; 904 fpscrMask.rMode = ones; 905 fpscrMask.fz = ones; 906 fpscrMask.dn = ones; 907 fpscrMask.ahp = ones; 908 newVal = (newVal & (uint32_t)fpscrMask) | 909 (readMiscRegNoEffect(MISCREG_FPSCR) & 910 ~(uint32_t)fpscrMask); 911 misc_reg = MISCREG_FPSCR; 912 } 913 break; 914 case MISCREG_CPSR_Q: 915 { 916 assert(!(newVal & ~CpsrMaskQ)); 917 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 918 misc_reg = MISCREG_CPSR; 919 } 920 break; 921 case MISCREG_FPSCR_QC: 922 { 923 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 924 (newVal & FpscrQcMask); 925 misc_reg = MISCREG_FPSCR; 926 } 927 break; 928 case MISCREG_FPSCR_EXC: 929 { 930 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 931 (newVal & FpscrExcMask); 932 misc_reg = MISCREG_FPSCR; 933 } 934 break; 935 case MISCREG_FPEXC: 936 { 937 // vfpv3 architecture, section B.6.1 of DDI04068 938 // bit 29 - valid only if fpexc[31] is 0 939 const uint32_t fpexcMask = 0x60000000; 940 newVal = (newVal & fpexcMask) | 941 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 942 } 943 break; 944 case MISCREG_HCR: 945 { 946 if (!haveVirtualization) 947 return; 948 } 949 break; 950 case MISCREG_IFSR: 951 { 952 // ARM ARM (ARM DDI 0406C.b) B4.1.96 953 const uint32_t ifsrMask = 954 mask(31, 13) | mask(11, 11) | mask(8, 6); 955 newVal = newVal & ~ifsrMask; 956 } 957 break; 958 case MISCREG_DFSR: 959 { 960 // ARM ARM (ARM DDI 0406C.b) B4.1.52 961 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 962 newVal = newVal & ~dfsrMask; 963 } 964 break; 965 case MISCREG_AMAIR0: 966 case MISCREG_AMAIR1: 967 { 968 // ARM ARM (ARM DDI 0406C.b) B4.1.5 969 // Valid only with LPAE 970 if (!haveLPAE) 971 return; 972 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 973 } 974 break; 975 case MISCREG_SCR: 976 getITBPtr(tc)->invalidateMiscReg(); 977 getDTBPtr(tc)->invalidateMiscReg(); 978 break; 979 case MISCREG_SCTLR: 980 { 981 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 982 scr = readMiscRegNoEffect(MISCREG_SCR); 983 984 MiscRegIndex sctlr_idx; 985 if (haveSecurity && !highestELIs64 && !scr.ns) { 986 sctlr_idx = MISCREG_SCTLR_S; 987 } else { 988 sctlr_idx = MISCREG_SCTLR_NS; 989 } 990 991 SCTLR sctlr = miscRegs[sctlr_idx]; 992 SCTLR new_sctlr = newVal; 993 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 994 miscRegs[sctlr_idx] = (MiscReg)new_sctlr; 995 getITBPtr(tc)->invalidateMiscReg(); 996 getDTBPtr(tc)->invalidateMiscReg(); 997 } 998 case MISCREG_MIDR: 999 case MISCREG_ID_PFR0: 1000 case MISCREG_ID_PFR1: 1001 case MISCREG_ID_DFR0: 1002 case MISCREG_ID_MMFR0: 1003 case MISCREG_ID_MMFR1: 1004 case MISCREG_ID_MMFR2: 1005 case MISCREG_ID_MMFR3: 1006 case MISCREG_ID_ISAR0: 1007 case MISCREG_ID_ISAR1: 1008 case MISCREG_ID_ISAR2: 1009 case MISCREG_ID_ISAR3: 1010 case MISCREG_ID_ISAR4: 1011 case MISCREG_ID_ISAR5: 1012 1013 case MISCREG_MPIDR: 1014 case MISCREG_FPSID: 1015 case MISCREG_TLBTR: 1016 case MISCREG_MVFR0: 1017 case MISCREG_MVFR1: 1018 1019 case MISCREG_ID_AA64AFR0_EL1: 1020 case MISCREG_ID_AA64AFR1_EL1: 1021 case MISCREG_ID_AA64DFR0_EL1: 1022 case MISCREG_ID_AA64DFR1_EL1: 1023 case MISCREG_ID_AA64ISAR0_EL1: 1024 case MISCREG_ID_AA64ISAR1_EL1: 1025 case MISCREG_ID_AA64MMFR0_EL1: 1026 case MISCREG_ID_AA64MMFR1_EL1: 1027 case MISCREG_ID_AA64MMFR2_EL1: 1028 case MISCREG_ID_AA64PFR0_EL1: 1029 case MISCREG_ID_AA64PFR1_EL1: 1030 // ID registers are constants. 1031 return; 1032 1033 // TLB Invalidate All 1034 case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 1035 { 1036 assert32(tc); 1037 scr = readMiscReg(MISCREG_SCR, tc); 1038 1039 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1040 tlbiOp(tc); 1041 return; 1042 } 1043 // TLB Invalidate All, Inner Shareable 1044 case MISCREG_TLBIALLIS: 1045 { 1046 assert32(tc); 1047 scr = readMiscReg(MISCREG_SCR, tc); 1048 1049 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1050 tlbiOp.broadcast(tc); 1051 return; 1052 } 1053 // Instruction TLB Invalidate All 1054 case MISCREG_ITLBIALL: 1055 { 1056 assert32(tc); 1057 scr = readMiscReg(MISCREG_SCR, tc); 1058 1059 ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1060 tlbiOp(tc); 1061 return; 1062 } 1063 // Data TLB Invalidate All 1064 case MISCREG_DTLBIALL: 1065 { 1066 assert32(tc); 1067 scr = readMiscReg(MISCREG_SCR, tc); 1068 1069 DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1070 tlbiOp(tc); 1071 return; 1072 } 1073 // TLB Invalidate by VA 1074 // mcr tlbimval(is) is invalidating all matching entries 1075 // regardless of the level of lookup, since in gem5 we cache 1076 // in the tlb the last level of lookup only. 1077 case MISCREG_TLBIMVA: 1078 case MISCREG_TLBIMVAL: 1079 { 1080 assert32(tc); 1081 scr = readMiscReg(MISCREG_SCR, tc); 1082 1083 TLBIMVA tlbiOp(EL1, 1084 haveSecurity && !scr.ns, 1085 mbits(newVal, 31, 12), 1086 bits(newVal, 7,0)); 1087 1088 tlbiOp(tc); 1089 return; 1090 } 1091 // TLB Invalidate by VA, Inner Shareable 1092 case MISCREG_TLBIMVAIS: 1093 case MISCREG_TLBIMVALIS: 1094 { 1095 assert32(tc); 1096 scr = readMiscReg(MISCREG_SCR, tc); 1097 1098 TLBIMVA tlbiOp(EL1, 1099 haveSecurity && !scr.ns, 1100 mbits(newVal, 31, 12), 1101 bits(newVal, 7,0)); 1102 1103 tlbiOp.broadcast(tc); 1104 return; 1105 } 1106 // TLB Invalidate by ASID match 1107 case MISCREG_TLBIASID: 1108 { 1109 assert32(tc); 1110 scr = readMiscReg(MISCREG_SCR, tc); 1111 1112 TLBIASID tlbiOp(EL1, 1113 haveSecurity && !scr.ns, 1114 bits(newVal, 7,0)); 1115 1116 tlbiOp(tc); 1117 return; 1118 } 1119 // TLB Invalidate by ASID match, Inner Shareable 1120 case MISCREG_TLBIASIDIS: 1121 { 1122 assert32(tc); 1123 scr = readMiscReg(MISCREG_SCR, tc); 1124 1125 TLBIASID tlbiOp(EL1, 1126 haveSecurity && !scr.ns, 1127 bits(newVal, 7,0)); 1128 1129 tlbiOp.broadcast(tc); 1130 return; 1131 } 1132 // mcr tlbimvaal(is) is invalidating all matching entries 1133 // regardless of the level of lookup, since in gem5 we cache 1134 // in the tlb the last level of lookup only. 1135 // TLB Invalidate by VA, All ASID 1136 case MISCREG_TLBIMVAA: 1137 case MISCREG_TLBIMVAAL: 1138 { 1139 assert32(tc); 1140 scr = readMiscReg(MISCREG_SCR, tc); 1141 1142 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1143 mbits(newVal, 31,12), false); 1144 1145 tlbiOp(tc); 1146 return; 1147 } 1148 // TLB Invalidate by VA, All ASID, Inner Shareable 1149 case MISCREG_TLBIMVAAIS: 1150 case MISCREG_TLBIMVAALIS: 1151 { 1152 assert32(tc); 1153 scr = readMiscReg(MISCREG_SCR, tc); 1154 1155 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1156 mbits(newVal, 31,12), false); 1157 1158 tlbiOp.broadcast(tc); 1159 return; 1160 } 1161 // mcr tlbimvalh(is) is invalidating all matching entries 1162 // regardless of the level of lookup, since in gem5 we cache 1163 // in the tlb the last level of lookup only. 1164 // TLB Invalidate by VA, Hyp mode 1165 case MISCREG_TLBIMVAH: 1166 case MISCREG_TLBIMVALH: 1167 { 1168 assert32(tc); 1169 scr = readMiscReg(MISCREG_SCR, tc); 1170 1171 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1172 mbits(newVal, 31,12), true); 1173 1174 tlbiOp(tc); 1175 return; 1176 } 1177 // TLB Invalidate by VA, Hyp mode, Inner Shareable 1178 case MISCREG_TLBIMVAHIS: 1179 case MISCREG_TLBIMVALHIS: 1180 { 1181 assert32(tc); 1182 scr = readMiscReg(MISCREG_SCR, tc); 1183 1184 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1185 mbits(newVal, 31,12), true); 1186 1187 tlbiOp.broadcast(tc); 1188 return; 1189 } 1190 // mcr tlbiipas2l(is) is invalidating all matching entries 1191 // regardless of the level of lookup, since in gem5 we cache 1192 // in the tlb the last level of lookup only. 1193 // TLB Invalidate by Intermediate Physical Address, Stage 2 1194 case MISCREG_TLBIIPAS2: 1195 case MISCREG_TLBIIPAS2L: 1196 { 1197 assert32(tc); 1198 scr = readMiscReg(MISCREG_SCR, tc); 1199 1200 TLBIIPA tlbiOp(EL1, 1201 haveSecurity && !scr.ns, 1202 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1203 1204 tlbiOp(tc); 1205 return; 1206 } 1207 // TLB Invalidate by Intermediate Physical Address, Stage 2, 1208 // Inner Shareable 1209 case MISCREG_TLBIIPAS2IS: 1210 case MISCREG_TLBIIPAS2LIS: 1211 { 1212 assert32(tc); 1213 scr = readMiscReg(MISCREG_SCR, tc); 1214 1215 TLBIIPA tlbiOp(EL1, 1216 haveSecurity && !scr.ns, 1217 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1218 1219 tlbiOp.broadcast(tc); 1220 return; 1221 } 1222 // Instruction TLB Invalidate by VA 1223 case MISCREG_ITLBIMVA: 1224 { 1225 assert32(tc); 1226 scr = readMiscReg(MISCREG_SCR, tc); 1227 1228 ITLBIMVA tlbiOp(EL1, 1229 haveSecurity && !scr.ns, 1230 mbits(newVal, 31, 12), 1231 bits(newVal, 7,0)); 1232 1233 tlbiOp(tc); 1234 return; 1235 } 1236 // Data TLB Invalidate by VA 1237 case MISCREG_DTLBIMVA: 1238 { 1239 assert32(tc); 1240 scr = readMiscReg(MISCREG_SCR, tc); 1241 1242 DTLBIMVA tlbiOp(EL1, 1243 haveSecurity && !scr.ns, 1244 mbits(newVal, 31, 12), 1245 bits(newVal, 7,0)); 1246 1247 tlbiOp(tc); 1248 return; 1249 } 1250 // Instruction TLB Invalidate by ASID match 1251 case MISCREG_ITLBIASID: 1252 { 1253 assert32(tc); 1254 scr = readMiscReg(MISCREG_SCR, tc); 1255 1256 ITLBIASID tlbiOp(EL1, 1257 haveSecurity && !scr.ns, 1258 bits(newVal, 7,0)); 1259 1260 tlbiOp(tc); 1261 return; 1262 } 1263 // Data TLB Invalidate by ASID match 1264 case MISCREG_DTLBIASID: 1265 { 1266 assert32(tc); 1267 scr = readMiscReg(MISCREG_SCR, tc); 1268 1269 DTLBIASID tlbiOp(EL1, 1270 haveSecurity && !scr.ns, 1271 bits(newVal, 7,0)); 1272 1273 tlbiOp(tc); 1274 return; 1275 } 1276 // TLB Invalidate All, Non-Secure Non-Hyp 1277 case MISCREG_TLBIALLNSNH: 1278 { 1279 assert32(tc); 1280 1281 TLBIALLN tlbiOp(EL1, false); 1282 tlbiOp(tc); 1283 return; 1284 } 1285 // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable 1286 case MISCREG_TLBIALLNSNHIS: 1287 { 1288 assert32(tc); 1289 1290 TLBIALLN tlbiOp(EL1, false); 1291 tlbiOp.broadcast(tc); 1292 return; 1293 } 1294 // TLB Invalidate All, Hyp mode 1295 case MISCREG_TLBIALLH: 1296 { 1297 assert32(tc); 1298 1299 TLBIALLN tlbiOp(EL1, true); 1300 tlbiOp(tc); 1301 return; 1302 } 1303 // TLB Invalidate All, Hyp mode, Inner Shareable 1304 case MISCREG_TLBIALLHIS: 1305 { 1306 assert32(tc); 1307 1308 TLBIALLN tlbiOp(EL1, true); 1309 tlbiOp.broadcast(tc); 1310 return; 1311 } 1312 // AArch64 TLB Invalidate All, EL3 1313 case MISCREG_TLBI_ALLE3: 1314 { 1315 assert64(tc); 1316 1317 TLBIALL tlbiOp(EL3, true); 1318 tlbiOp(tc); 1319 return; 1320 } 1321 // AArch64 TLB Invalidate All, EL3, Inner Shareable 1322 case MISCREG_TLBI_ALLE3IS: 1323 { 1324 assert64(tc); 1325 1326 TLBIALL tlbiOp(EL3, true); 1327 tlbiOp.broadcast(tc); 1328 return; 1329 } 1330 // @todo: uncomment this to enable Virtualization 1331 // case MISCREG_TLBI_ALLE2IS: 1332 // case MISCREG_TLBI_ALLE2: 1333 // AArch64 TLB Invalidate All, EL1 1334 case MISCREG_TLBI_ALLE1: 1335 case MISCREG_TLBI_VMALLE1: 1336 case MISCREG_TLBI_VMALLS12E1: 1337 // @todo: handle VMID and stage 2 to enable Virtualization 1338 { 1339 assert64(tc); 1340 scr = readMiscReg(MISCREG_SCR, tc); 1341 1342 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1343 tlbiOp(tc); 1344 return; 1345 } 1346 // AArch64 TLB Invalidate All, EL1, Inner Shareable 1347 case MISCREG_TLBI_ALLE1IS: 1348 case MISCREG_TLBI_VMALLE1IS: 1349 case MISCREG_TLBI_VMALLS12E1IS: 1350 // @todo: handle VMID and stage 2 to enable Virtualization 1351 { 1352 assert64(tc); 1353 scr = readMiscReg(MISCREG_SCR, tc); 1354 1355 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1356 tlbiOp.broadcast(tc); 1357 return; 1358 } 1359 // VAEx(IS) and VALEx(IS) are the same because TLBs 1360 // only store entries 1361 // from the last level of translation table walks 1362 // @todo: handle VMID to enable Virtualization 1363 // AArch64 TLB Invalidate by VA, EL3 1364 case MISCREG_TLBI_VAE3_Xt: 1365 case MISCREG_TLBI_VALE3_Xt: 1366 { 1367 assert64(tc); 1368 1369 TLBIMVA tlbiOp(EL3, true, 1370 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1371 0xbeef); 1372 tlbiOp(tc); 1373 return; 1374 } 1375 // AArch64 TLB Invalidate by VA, EL3, Inner Shareable 1376 case MISCREG_TLBI_VAE3IS_Xt: 1377 case MISCREG_TLBI_VALE3IS_Xt: 1378 { 1379 assert64(tc); 1380 1381 TLBIMVA tlbiOp(EL3, true, 1382 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1383 0xbeef); 1384 1385 tlbiOp.broadcast(tc); 1386 return; 1387 } 1388 // AArch64 TLB Invalidate by VA, EL2 1389 case MISCREG_TLBI_VAE2_Xt: 1390 case MISCREG_TLBI_VALE2_Xt: 1391 { 1392 assert64(tc); 1393 scr = readMiscReg(MISCREG_SCR, tc); 1394 1395 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1396 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1397 0xbeef); 1398 tlbiOp(tc); 1399 return; 1400 } 1401 // AArch64 TLB Invalidate by VA, EL2, Inner Shareable 1402 case MISCREG_TLBI_VAE2IS_Xt: 1403 case MISCREG_TLBI_VALE2IS_Xt: 1404 { 1405 assert64(tc); 1406 scr = readMiscReg(MISCREG_SCR, tc); 1407 1408 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1409 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1410 0xbeef); 1411 1412 tlbiOp.broadcast(tc); 1413 return; 1414 } 1415 // AArch64 TLB Invalidate by VA, EL1 1416 case MISCREG_TLBI_VAE1_Xt: 1417 case MISCREG_TLBI_VALE1_Xt: 1418 { 1419 assert64(tc); 1420 scr = readMiscReg(MISCREG_SCR, tc); 1421 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1422 bits(newVal, 55, 48); 1423 1424 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1425 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1426 asid); 1427 1428 tlbiOp(tc); 1429 return; 1430 } 1431 // AArch64 TLB Invalidate by VA, EL1, Inner Shareable 1432 case MISCREG_TLBI_VAE1IS_Xt: 1433 case MISCREG_TLBI_VALE1IS_Xt: 1434 { 1435 assert64(tc); 1436 scr = readMiscReg(MISCREG_SCR, tc); 1437 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1438 bits(newVal, 55, 48); 1439 1440 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1441 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1442 asid); 1443 1444 tlbiOp.broadcast(tc); 1445 return; 1446 } 1447 // AArch64 TLB Invalidate by ASID, EL1 1448 // @todo: handle VMID to enable Virtualization 1449 case MISCREG_TLBI_ASIDE1_Xt: 1450 { 1451 assert64(tc); 1452 scr = readMiscReg(MISCREG_SCR, tc); 1453 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1454 bits(newVal, 55, 48); 1455 1456 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1457 tlbiOp(tc); 1458 return; 1459 } 1460 // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable 1461 case MISCREG_TLBI_ASIDE1IS_Xt: 1462 { 1463 assert64(tc); 1464 scr = readMiscReg(MISCREG_SCR, tc); 1465 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1466 bits(newVal, 55, 48); 1467 1468 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1469 tlbiOp.broadcast(tc); 1470 return; 1471 } 1472 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 1473 // entries from the last level of translation table walks 1474 // AArch64 TLB Invalidate by VA, All ASID, EL1 1475 case MISCREG_TLBI_VAAE1_Xt: 1476 case MISCREG_TLBI_VAALE1_Xt: 1477 { 1478 assert64(tc); 1479 scr = readMiscReg(MISCREG_SCR, tc); 1480 1481 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1482 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 1483 1484 tlbiOp(tc); 1485 return; 1486 } 1487 // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable 1488 case MISCREG_TLBI_VAAE1IS_Xt: 1489 case MISCREG_TLBI_VAALE1IS_Xt: 1490 { 1491 assert64(tc); 1492 scr = readMiscReg(MISCREG_SCR, tc); 1493 1494 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1495 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 1496 1497 tlbiOp.broadcast(tc); 1498 return; 1499 } 1500 // AArch64 TLB Invalidate by Intermediate Physical Address, 1501 // Stage 2, EL1 1502 case MISCREG_TLBI_IPAS2E1_Xt: 1503 case MISCREG_TLBI_IPAS2LE1_Xt: 1504 { 1505 assert64(tc); 1506 scr = readMiscReg(MISCREG_SCR, tc); 1507 1508 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1509 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1510 1511 tlbiOp(tc); 1512 return; 1513 } 1514 // AArch64 TLB Invalidate by Intermediate Physical Address, 1515 // Stage 2, EL1, Inner Shareable 1516 case MISCREG_TLBI_IPAS2E1IS_Xt: 1517 case MISCREG_TLBI_IPAS2LE1IS_Xt: 1518 { 1519 assert64(tc); 1520 scr = readMiscReg(MISCREG_SCR, tc); 1521 1522 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1523 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1524 1525 tlbiOp.broadcast(tc); 1526 return; 1527 } 1528 case MISCREG_ACTLR: 1529 warn("Not doing anything for write of miscreg ACTLR\n"); 1530 break; 1531 1532 case MISCREG_PMXEVTYPER_PMCCFILTR: 1533 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 1534 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 1535 case MISCREG_PMCR ... MISCREG_PMOVSSET: 1536 pmu->setMiscReg(misc_reg, newVal); 1537 break; 1538 1539 1540 case MISCREG_HSTR: // TJDBX, now redifined to be RES0 1541 { 1542 HSTR hstrMask = 0; 1543 hstrMask.tjdbx = 1; 1544 newVal &= ~((uint32_t) hstrMask); 1545 break; 1546 } 1547 case MISCREG_HCPTR: 1548 { 1549 // If a CP bit in NSACR is 0 then the corresponding bit in 1550 // HCPTR is RAO/WI. Same applies to NSASEDIS 1551 secure_lookup = haveSecurity && 1552 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 1553 readMiscRegNoEffect(MISCREG_CPSR)); 1554 if (!secure_lookup) { 1555 MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 1556 MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 1557 newVal = (newVal & ~mask) | (oldValue & mask); 1558 } 1559 break; 1560 } 1561 case MISCREG_HDFAR: // alias for secure DFAR 1562 misc_reg = MISCREG_DFAR_S; 1563 break; 1564 case MISCREG_HIFAR: // alias for secure IFAR 1565 misc_reg = MISCREG_IFAR_S; 1566 break; 1567 case MISCREG_ATS1CPR: 1568 case MISCREG_ATS1CPW: 1569 case MISCREG_ATS1CUR: 1570 case MISCREG_ATS1CUW: 1571 case MISCREG_ATS12NSOPR: 1572 case MISCREG_ATS12NSOPW: 1573 case MISCREG_ATS12NSOUR: 1574 case MISCREG_ATS12NSOUW: 1575 case MISCREG_ATS1HR: 1576 case MISCREG_ATS1HW: 1577 { 1578 Request::Flags flags = 0; 1579 BaseTLB::Mode mode = BaseTLB::Read; 1580 TLB::ArmTranslationType tranType = TLB::NormalTran; 1581 Fault fault; 1582 switch(misc_reg) { 1583 case MISCREG_ATS1CPR: 1584 flags = TLB::MustBeOne; 1585 tranType = TLB::S1CTran; 1586 mode = BaseTLB::Read; 1587 break; 1588 case MISCREG_ATS1CPW: 1589 flags = TLB::MustBeOne; 1590 tranType = TLB::S1CTran; 1591 mode = BaseTLB::Write; 1592 break; 1593 case MISCREG_ATS1CUR: 1594 flags = TLB::MustBeOne | TLB::UserMode; 1595 tranType = TLB::S1CTran; 1596 mode = BaseTLB::Read; 1597 break; 1598 case MISCREG_ATS1CUW: 1599 flags = TLB::MustBeOne | TLB::UserMode; 1600 tranType = TLB::S1CTran; 1601 mode = BaseTLB::Write; 1602 break; 1603 case MISCREG_ATS12NSOPR: 1604 if (!haveSecurity) 1605 panic("Security Extensions required for ATS12NSOPR"); 1606 flags = TLB::MustBeOne; 1607 tranType = TLB::S1S2NsTran; 1608 mode = BaseTLB::Read; 1609 break; 1610 case MISCREG_ATS12NSOPW: 1611 if (!haveSecurity) 1612 panic("Security Extensions required for ATS12NSOPW"); 1613 flags = TLB::MustBeOne; 1614 tranType = TLB::S1S2NsTran; 1615 mode = BaseTLB::Write; 1616 break; 1617 case MISCREG_ATS12NSOUR: 1618 if (!haveSecurity) 1619 panic("Security Extensions required for ATS12NSOUR"); 1620 flags = TLB::MustBeOne | TLB::UserMode; 1621 tranType = TLB::S1S2NsTran; 1622 mode = BaseTLB::Read; 1623 break; 1624 case MISCREG_ATS12NSOUW: 1625 if (!haveSecurity) 1626 panic("Security Extensions required for ATS12NSOUW"); 1627 flags = TLB::MustBeOne | TLB::UserMode; 1628 tranType = TLB::S1S2NsTran; 1629 mode = BaseTLB::Write; 1630 break; 1631 case MISCREG_ATS1HR: // only really useful from secure mode. 1632 flags = TLB::MustBeOne; 1633 tranType = TLB::HypMode; 1634 mode = BaseTLB::Read; 1635 break; 1636 case MISCREG_ATS1HW: 1637 flags = TLB::MustBeOne; 1638 tranType = TLB::HypMode; 1639 mode = BaseTLB::Write; 1640 break; 1641 } 1642 // If we're in timing mode then doing the translation in 1643 // functional mode then we're slightly distorting performance 1644 // results obtained from simulations. The translation should be 1645 // done in the same mode the core is running in. NOTE: This 1646 // can't be an atomic translation because that causes problems 1647 // with unexpected atomic snoop requests. 1648 warn("Translating via %s in functional mode! Fix Me!\n", 1649 miscRegName[misc_reg]); 1650 1651 auto req = std::make_shared<Request>( 1652 0, val, 0, flags, Request::funcMasterId, 1653 tc->pcState().pc(), tc->contextId()); 1654 1655 fault = getDTBPtr(tc)->translateFunctional( 1656 req, tc, mode, tranType); 1657 1658 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1659 HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 1660 1661 MiscReg newVal; 1662 if (fault == NoFault) { 1663 Addr paddr = req->getPaddr(); 1664 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 1665 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 1666 newVal = (paddr & mask(39, 12)) | 1667 (getDTBPtr(tc)->getAttr()); 1668 } else { 1669 newVal = (paddr & 0xfffff000) | 1670 (getDTBPtr(tc)->getAttr()); 1671 } 1672 DPRINTF(MiscRegs, 1673 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 1674 val, newVal); 1675 } else { 1676 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1677 armFault->update(tc); 1678 // Set fault bit and FSR 1679 FSR fsr = armFault->getFsr(tc); 1680 1681 newVal = ((fsr >> 9) & 1) << 11; 1682 if (newVal) { 1683 // LPAE - rearange fault status 1684 newVal |= ((fsr >> 0) & 0x3f) << 1; 1685 } else { 1686 // VMSA - rearange fault status 1687 newVal |= ((fsr >> 0) & 0xf) << 1; 1688 newVal |= ((fsr >> 10) & 0x1) << 5; 1689 newVal |= ((fsr >> 12) & 0x1) << 6; 1690 } 1691 newVal |= 0x1; // F bit 1692 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1693 newVal |= armFault->isStage2() ? 0x200 : 0; 1694 DPRINTF(MiscRegs, 1695 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 1696 val, fsr, newVal); 1697 } 1698 setMiscRegNoEffect(MISCREG_PAR, newVal); 1699 return; 1700 } 1701 case MISCREG_TTBCR: 1702 { 1703 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1704 const uint32_t ones = (uint32_t)(-1); 1705 TTBCR ttbcrMask = 0; 1706 TTBCR ttbcrNew = newVal; 1707 1708 // ARM DDI 0406C.b, ARMv7-32 1709 ttbcrMask.n = ones; // T0SZ 1710 if (haveSecurity) { 1711 ttbcrMask.pd0 = ones; 1712 ttbcrMask.pd1 = ones; 1713 } 1714 ttbcrMask.epd0 = ones; 1715 ttbcrMask.irgn0 = ones; 1716 ttbcrMask.orgn0 = ones; 1717 ttbcrMask.sh0 = ones; 1718 ttbcrMask.ps = ones; // T1SZ 1719 ttbcrMask.a1 = ones; 1720 ttbcrMask.epd1 = ones; 1721 ttbcrMask.irgn1 = ones; 1722 ttbcrMask.orgn1 = ones; 1723 ttbcrMask.sh1 = ones; 1724 if (haveLPAE) 1725 ttbcrMask.eae = ones; 1726 1727 if (haveLPAE && ttbcrNew.eae) { 1728 newVal = newVal & ttbcrMask; 1729 } else { 1730 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 1731 } 1732 // Invalidate TLB MiscReg 1733 getITBPtr(tc)->invalidateMiscReg(); 1734 getDTBPtr(tc)->invalidateMiscReg(); 1735 break; 1736 } 1737 case MISCREG_TTBR0: 1738 case MISCREG_TTBR1: 1739 { 1740 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1741 if (haveLPAE) { 1742 if (ttbcr.eae) { 1743 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 1744 // ARMv8 AArch32 bit 63-56 only 1745 uint64_t ttbrMask = mask(63,56) | mask(47,40); 1746 newVal = (newVal & (~ttbrMask)); 1747 } 1748 } 1749 // Invalidate TLB MiscReg 1750 getITBPtr(tc)->invalidateMiscReg(); 1751 getDTBPtr(tc)->invalidateMiscReg(); 1752 break; 1753 } 1754 case MISCREG_SCTLR_EL1: 1755 case MISCREG_CONTEXTIDR: 1756 case MISCREG_PRRR: 1757 case MISCREG_NMRR: 1758 case MISCREG_MAIR0: 1759 case MISCREG_MAIR1: 1760 case MISCREG_DACR: 1761 case MISCREG_VTTBR: 1762 case MISCREG_SCR_EL3: 1763 case MISCREG_HCR_EL2: 1764 case MISCREG_TCR_EL1: 1765 case MISCREG_TCR_EL2: 1766 case MISCREG_TCR_EL3: 1767 case MISCREG_SCTLR_EL2: 1768 case MISCREG_SCTLR_EL3: 1769 case MISCREG_HSCTLR: 1770 case MISCREG_TTBR0_EL1: 1771 case MISCREG_TTBR1_EL1: 1772 case MISCREG_TTBR0_EL2: 1773 case MISCREG_TTBR1_EL2: 1774 case MISCREG_TTBR0_EL3: 1775 getITBPtr(tc)->invalidateMiscReg(); 1776 getDTBPtr(tc)->invalidateMiscReg(); 1777 break; 1778 case MISCREG_NZCV: 1779 { 1780 CPSR cpsr = val; 1781 1782 tc->setCCReg(CCREG_NZ, cpsr.nz); 1783 tc->setCCReg(CCREG_C, cpsr.c); 1784 tc->setCCReg(CCREG_V, cpsr.v); 1785 } 1786 break; 1787 case MISCREG_DAIF: 1788 { 1789 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1790 cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 1791 newVal = cpsr; 1792 misc_reg = MISCREG_CPSR; 1793 } 1794 break; 1795 case MISCREG_SP_EL0: 1796 tc->setIntReg(INTREG_SP0, newVal); 1797 break; 1798 case MISCREG_SP_EL1: 1799 tc->setIntReg(INTREG_SP1, newVal); 1800 break; 1801 case MISCREG_SP_EL2: 1802 tc->setIntReg(INTREG_SP2, newVal); 1803 break; 1804 case MISCREG_SPSEL: 1805 { 1806 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1807 cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 1808 newVal = cpsr; 1809 misc_reg = MISCREG_CPSR; 1810 } 1811 break; 1812 case MISCREG_CURRENTEL: 1813 { 1814 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1815 cpsr.el = (uint8_t) ((CPSR) newVal).el; 1816 newVal = cpsr; 1817 misc_reg = MISCREG_CPSR; 1818 } 1819 break; 1820 case MISCREG_AT_S1E1R_Xt: 1821 case MISCREG_AT_S1E1W_Xt: 1822 case MISCREG_AT_S1E0R_Xt: 1823 case MISCREG_AT_S1E0W_Xt: 1824 case MISCREG_AT_S1E2R_Xt: 1825 case MISCREG_AT_S1E2W_Xt: 1826 case MISCREG_AT_S12E1R_Xt: 1827 case MISCREG_AT_S12E1W_Xt: 1828 case MISCREG_AT_S12E0R_Xt: 1829 case MISCREG_AT_S12E0W_Xt: 1830 case MISCREG_AT_S1E3R_Xt: 1831 case MISCREG_AT_S1E3W_Xt: 1832 { 1833 RequestPtr req = std::make_shared<Request>(); 1834 Request::Flags flags = 0; 1835 BaseTLB::Mode mode = BaseTLB::Read; 1836 TLB::ArmTranslationType tranType = TLB::NormalTran; 1837 Fault fault; 1838 switch(misc_reg) { 1839 case MISCREG_AT_S1E1R_Xt: 1840 flags = TLB::MustBeOne; 1841 tranType = TLB::S1E1Tran; 1842 mode = BaseTLB::Read; 1843 break; 1844 case MISCREG_AT_S1E1W_Xt: 1845 flags = TLB::MustBeOne; 1846 tranType = TLB::S1E1Tran; 1847 mode = BaseTLB::Write; 1848 break; 1849 case MISCREG_AT_S1E0R_Xt: 1850 flags = TLB::MustBeOne | TLB::UserMode; 1851 tranType = TLB::S1E0Tran; 1852 mode = BaseTLB::Read; 1853 break; 1854 case MISCREG_AT_S1E0W_Xt: 1855 flags = TLB::MustBeOne | TLB::UserMode; 1856 tranType = TLB::S1E0Tran; 1857 mode = BaseTLB::Write; 1858 break; 1859 case MISCREG_AT_S1E2R_Xt: 1860 flags = TLB::MustBeOne; 1861 tranType = TLB::S1E2Tran; 1862 mode = BaseTLB::Read; 1863 break; 1864 case MISCREG_AT_S1E2W_Xt: 1865 flags = TLB::MustBeOne; 1866 tranType = TLB::S1E2Tran; 1867 mode = BaseTLB::Write; 1868 break; 1869 case MISCREG_AT_S12E0R_Xt: 1870 flags = TLB::MustBeOne | TLB::UserMode; 1871 tranType = TLB::S12E0Tran; 1872 mode = BaseTLB::Read; 1873 break; 1874 case MISCREG_AT_S12E0W_Xt: 1875 flags = TLB::MustBeOne | TLB::UserMode; 1876 tranType = TLB::S12E0Tran; 1877 mode = BaseTLB::Write; 1878 break; 1879 case MISCREG_AT_S12E1R_Xt: 1880 flags = TLB::MustBeOne; 1881 tranType = TLB::S12E1Tran; 1882 mode = BaseTLB::Read; 1883 break; 1884 case MISCREG_AT_S12E1W_Xt: 1885 flags = TLB::MustBeOne; 1886 tranType = TLB::S12E1Tran; 1887 mode = BaseTLB::Write; 1888 break; 1889 case MISCREG_AT_S1E3R_Xt: 1890 flags = TLB::MustBeOne; 1891 tranType = TLB::S1E3Tran; 1892 mode = BaseTLB::Read; 1893 break; 1894 case MISCREG_AT_S1E3W_Xt: 1895 flags = TLB::MustBeOne; 1896 tranType = TLB::S1E3Tran; 1897 mode = BaseTLB::Write; 1898 break; 1899 } 1900 // If we're in timing mode then doing the translation in 1901 // functional mode then we're slightly distorting performance 1902 // results obtained from simulations. The translation should be 1903 // done in the same mode the core is running in. NOTE: This 1904 // can't be an atomic translation because that causes problems 1905 // with unexpected atomic snoop requests. 1906 warn("Translating via %s in functional mode! Fix Me!\n", 1907 miscRegName[misc_reg]); 1908 1909 req->setVirt(0, val, 0, flags, Request::funcMasterId, 1910 tc->pcState().pc()); 1911 req->setContext(tc->contextId()); 1912 fault = getDTBPtr(tc)->translateFunctional(req, tc, mode, 1913 tranType); 1914 1915 MiscReg newVal; 1916 if (fault == NoFault) { 1917 Addr paddr = req->getPaddr(); 1918 uint64_t attr = getDTBPtr(tc)->getAttr(); 1919 uint64_t attr1 = attr >> 56; 1920 if (!attr1 || attr1 ==0x44) { 1921 attr |= 0x100; 1922 attr &= ~ uint64_t(0x80); 1923 } 1924 newVal = (paddr & mask(47, 12)) | attr; 1925 DPRINTF(MiscRegs, 1926 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 1927 val, newVal); 1928 } else { 1929 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1930 armFault->update(tc); 1931 // Set fault bit and FSR 1932 FSR fsr = armFault->getFsr(tc); 1933 1934 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1935 if (cpsr.width) { // AArch32 1936 newVal = ((fsr >> 9) & 1) << 11; 1937 // rearrange fault status 1938 newVal |= ((fsr >> 0) & 0x3f) << 1; 1939 newVal |= 0x1; // F bit 1940 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1941 newVal |= armFault->isStage2() ? 0x200 : 0; 1942 } else { // AArch64 1943 newVal = 1; // F bit 1944 newVal |= fsr << 1; // FST 1945 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit. 1946 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 1947 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 1948 newVal |= 1 << 11; // RES1 1949 } 1950 DPRINTF(MiscRegs, 1951 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 1952 val, fsr, newVal); 1953 } 1954 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 1955 return; 1956 } 1957 case MISCREG_SPSR_EL3: 1958 case MISCREG_SPSR_EL2: 1959 case MISCREG_SPSR_EL1: 1960 // Force bits 23:21 to 0 1961 newVal = val & ~(0x7 << 21); 1962 break; 1963 case MISCREG_L2CTLR: 1964 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 1965 miscRegName[misc_reg], uint32_t(val)); 1966 break; 1967 1968 // Generic Timer registers 1969 case MISCREG_CNTHV_CTL_EL2: 1970 case MISCREG_CNTHV_CVAL_EL2: 1971 case MISCREG_CNTHV_TVAL_EL2: 1972 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 1973 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 1974 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 1975 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 1976 getGenericTimer(tc).setMiscReg(misc_reg, newVal); 1977 break; 1978 } 1979 } 1980 setMiscRegNoEffect(misc_reg, newVal); 1981} 1982 1983BaseISADevice & 1984ISA::getGenericTimer(ThreadContext *tc) 1985{ 1986 // We only need to create an ISA interface the first time we try 1987 // to access the timer. 1988 if (timer) 1989 return *timer.get(); 1990 1991 assert(system); 1992 GenericTimer *generic_timer(system->getGenericTimer()); 1993 if (!generic_timer) { 1994 panic("Trying to get a generic timer from a system that hasn't " 1995 "been configured to use a generic timer.\n"); 1996 } 1997 1998 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 1999 timer->setThreadContext(tc); 2000 2001 return *timer.get(); 2002} 2003 2004} 2005 2006ArmISA::ISA * 2007ArmISAParams::create() 2008{ 2009 return new ArmISA::ISA(this); 2010} 2011