isa.cc revision 13417
1/* 2 * Copyright (c) 2010-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 */ 40 41#include "arch/arm/isa.hh" 42#include "arch/arm/pmu.hh" 43#include "arch/arm/system.hh" 44#include "arch/arm/tlb.hh" 45#include "arch/arm/tlbi_op.hh" 46#include "cpu/base.hh" 47#include "cpu/checker/cpu.hh" 48#include "debug/Arm.hh" 49#include "debug/MiscRegs.hh" 50#include "dev/arm/generic_timer.hh" 51#include "params/ArmISA.hh" 52#include "sim/faults.hh" 53#include "sim/stat_control.hh" 54#include "sim/system.hh" 55 56namespace ArmISA 57{ 58 59ISA::ISA(Params *p) 60 : SimObject(p), 61 system(NULL), 62 _decoderFlavour(p->decoderFlavour), 63 _vecRegRenameMode(p->vecRegRenameMode), 64 pmu(p->pmu), 65 impdefAsNop(p->impdef_nop) 66{ 67 miscRegs[MISCREG_SCTLR_RST] = 0; 68 69 // Hook up a dummy device if we haven't been configured with a 70 // real PMU. By using a dummy device, we don't need to check that 71 // the PMU exist every time we try to access a PMU register. 72 if (!pmu) 73 pmu = &dummyDevice; 74 75 // Give all ISA devices a pointer to this ISA 76 pmu->setISA(this); 77 78 system = dynamic_cast<ArmSystem *>(p->system); 79 80 // Cache system-level properties 81 if (FullSystem && system) { 82 highestELIs64 = system->highestELIs64(); 83 haveSecurity = system->haveSecurity(); 84 haveLPAE = system->haveLPAE(); 85 haveCrypto = system->haveCrypto(); 86 haveVirtualization = system->haveVirtualization(); 87 haveLargeAsid64 = system->haveLargeAsid64(); 88 physAddrRange = system->physAddrRange(); 89 } else { 90 highestELIs64 = true; // ArmSystem::highestELIs64 does the same 91 haveSecurity = haveLPAE = haveVirtualization = false; 92 haveCrypto = false; 93 haveLargeAsid64 = false; 94 physAddrRange = 32; // dummy value 95 } 96 97 initializeMiscRegMetadata(); 98 preUnflattenMiscReg(); 99 100 clear(); 101} 102 103std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS); 104 105const ArmISAParams * 106ISA::params() const 107{ 108 return dynamic_cast<const Params *>(_params); 109} 110 111void 112ISA::clear() 113{ 114 const Params *p(params()); 115 116 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 117 memset(miscRegs, 0, sizeof(miscRegs)); 118 119 initID32(p); 120 121 // We always initialize AArch64 ID registers even 122 // if we are in AArch32. This is done since if we 123 // are in SE mode we don't know if our ArmProcess is 124 // AArch32 or AArch64 125 initID64(p); 126 127 // Start with an event in the mailbox 128 miscRegs[MISCREG_SEV_MAILBOX] = 1; 129 130 // Separate Instruction and Data TLBs 131 miscRegs[MISCREG_TLBTR] = 1; 132 133 MVFR0 mvfr0 = 0; 134 mvfr0.advSimdRegisters = 2; 135 mvfr0.singlePrecision = 2; 136 mvfr0.doublePrecision = 2; 137 mvfr0.vfpExceptionTrapping = 0; 138 mvfr0.divide = 1; 139 mvfr0.squareRoot = 1; 140 mvfr0.shortVectors = 1; 141 mvfr0.roundingModes = 1; 142 miscRegs[MISCREG_MVFR0] = mvfr0; 143 144 MVFR1 mvfr1 = 0; 145 mvfr1.flushToZero = 1; 146 mvfr1.defaultNaN = 1; 147 mvfr1.advSimdLoadStore = 1; 148 mvfr1.advSimdInteger = 1; 149 mvfr1.advSimdSinglePrecision = 1; 150 mvfr1.advSimdHalfPrecision = 1; 151 mvfr1.vfpHalfPrecision = 1; 152 miscRegs[MISCREG_MVFR1] = mvfr1; 153 154 // Reset values of PRRR and NMRR are implementation dependent 155 156 // @todo: PRRR and NMRR in secure state? 157 miscRegs[MISCREG_PRRR_NS] = 158 (1 << 19) | // 19 159 (0 << 18) | // 18 160 (0 << 17) | // 17 161 (1 << 16) | // 16 162 (2 << 14) | // 15:14 163 (0 << 12) | // 13:12 164 (2 << 10) | // 11:10 165 (2 << 8) | // 9:8 166 (2 << 6) | // 7:6 167 (2 << 4) | // 5:4 168 (1 << 2) | // 3:2 169 0; // 1:0 170 171 miscRegs[MISCREG_NMRR_NS] = 172 (1 << 30) | // 31:30 173 (0 << 26) | // 27:26 174 (0 << 24) | // 25:24 175 (3 << 22) | // 23:22 176 (2 << 20) | // 21:20 177 (0 << 18) | // 19:18 178 (0 << 16) | // 17:16 179 (1 << 14) | // 15:14 180 (0 << 12) | // 13:12 181 (2 << 10) | // 11:10 182 (0 << 8) | // 9:8 183 (3 << 6) | // 7:6 184 (2 << 4) | // 5:4 185 (0 << 2) | // 3:2 186 0; // 1:0 187 188 if (FullSystem && system->highestELIs64()) { 189 // Initialize AArch64 state 190 clear64(p); 191 return; 192 } 193 194 // Initialize AArch32 state... 195 clear32(p, sctlr_rst); 196} 197 198void 199ISA::clear32(const ArmISAParams *p, const SCTLR &sctlr_rst) 200{ 201 CPSR cpsr = 0; 202 cpsr.mode = MODE_USER; 203 204 if (FullSystem) { 205 miscRegs[MISCREG_MVBAR] = system->resetAddr(); 206 } 207 208 miscRegs[MISCREG_CPSR] = cpsr; 209 updateRegMap(cpsr); 210 211 SCTLR sctlr = 0; 212 sctlr.te = (bool) sctlr_rst.te; 213 sctlr.nmfi = (bool) sctlr_rst.nmfi; 214 sctlr.v = (bool) sctlr_rst.v; 215 sctlr.u = 1; 216 sctlr.xp = 1; 217 sctlr.rao2 = 1; 218 sctlr.rao3 = 1; 219 sctlr.rao4 = 0xf; // SCTLR[6:3] 220 sctlr.uci = 1; 221 sctlr.dze = 1; 222 miscRegs[MISCREG_SCTLR_NS] = sctlr; 223 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 224 miscRegs[MISCREG_HCPTR] = 0; 225 226 miscRegs[MISCREG_CPACR] = 0; 227 228 miscRegs[MISCREG_FPSID] = p->fpsid; 229 230 if (haveLPAE) { 231 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 232 ttbcr.eae = 0; 233 miscRegs[MISCREG_TTBCR_NS] = ttbcr; 234 // Enforce consistency with system-level settings 235 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 236 } 237 238 if (haveSecurity) { 239 miscRegs[MISCREG_SCTLR_S] = sctlr; 240 miscRegs[MISCREG_SCR] = 0; 241 miscRegs[MISCREG_VBAR_S] = 0; 242 } else { 243 // we're always non-secure 244 miscRegs[MISCREG_SCR] = 1; 245 } 246 247 //XXX We need to initialize the rest of the state. 248} 249 250void 251ISA::clear64(const ArmISAParams *p) 252{ 253 CPSR cpsr = 0; 254 Addr rvbar = system->resetAddr(); 255 switch (system->highestEL()) { 256 // Set initial EL to highest implemented EL using associated stack 257 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 258 // value 259 case EL3: 260 cpsr.mode = MODE_EL3H; 261 miscRegs[MISCREG_RVBAR_EL3] = rvbar; 262 break; 263 case EL2: 264 cpsr.mode = MODE_EL2H; 265 miscRegs[MISCREG_RVBAR_EL2] = rvbar; 266 break; 267 case EL1: 268 cpsr.mode = MODE_EL1H; 269 miscRegs[MISCREG_RVBAR_EL1] = rvbar; 270 break; 271 default: 272 panic("Invalid highest implemented exception level"); 273 break; 274 } 275 276 // Initialize rest of CPSR 277 cpsr.daif = 0xf; // Mask all interrupts 278 cpsr.ss = 0; 279 cpsr.il = 0; 280 miscRegs[MISCREG_CPSR] = cpsr; 281 updateRegMap(cpsr); 282 283 // Initialize other control registers 284 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 285 if (haveSecurity) { 286 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830; 287 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 288 } else if (haveVirtualization) { 289 // also MISCREG_SCTLR_EL2 (by mapping) 290 miscRegs[MISCREG_HSCTLR] = 0x30c50830; 291 } else { 292 // also MISCREG_SCTLR_EL1 (by mapping) 293 miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init 294 // Always non-secure 295 miscRegs[MISCREG_SCR_EL3] = 1; 296 } 297} 298 299void 300ISA::initID32(const ArmISAParams *p) 301{ 302 // Initialize configurable default values 303 miscRegs[MISCREG_MIDR] = p->midr; 304 miscRegs[MISCREG_MIDR_EL1] = p->midr; 305 miscRegs[MISCREG_VPIDR] = p->midr; 306 307 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 308 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 309 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 310 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 311 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 312 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 313 314 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 315 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 316 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 317 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 318} 319 320void 321ISA::initID64(const ArmISAParams *p) 322{ 323 // Initialize configurable id registers 324 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 325 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 326 miscRegs[MISCREG_ID_AA64DFR0_EL1] = 327 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 328 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 329 330 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 331 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 332 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 333 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 334 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 335 miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p->id_aa64mmfr2_el1; 336 337 miscRegs[MISCREG_ID_DFR0_EL1] = 338 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 339 340 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 341 342 // Enforce consistency with system-level settings... 343 344 // EL3 345 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 346 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 347 haveSecurity ? 0x2 : 0x0); 348 // EL2 349 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 350 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 351 haveVirtualization ? 0x2 : 0x0); 352 // Large ASID support 353 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 354 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 355 haveLargeAsid64 ? 0x2 : 0x0); 356 // Physical address size 357 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 358 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 359 encodePhysAddrRange64(physAddrRange)); 360 // Crypto 361 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits( 362 miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4, 363 haveCrypto ? 0x1112 : 0x0); 364} 365 366void 367ISA::startup(ThreadContext *tc) 368{ 369 pmu->setThreadContext(tc); 370 371} 372 373 374MiscReg 375ISA::readMiscRegNoEffect(int misc_reg) const 376{ 377 assert(misc_reg < NumMiscRegs); 378 379 const auto ® = lookUpMiscReg[misc_reg]; // bit masks 380 const auto &map = getMiscIndices(misc_reg); 381 int lower = map.first, upper = map.second; 382 // NB!: apply architectural masks according to desired register, 383 // despite possibly getting value from different (mapped) register. 384 auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32)) 385 |(miscRegs[upper] << 32)); 386 if (val & reg.res0()) { 387 DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n", 388 miscRegName[misc_reg], val & reg.res0()); 389 } 390 if ((val & reg.res1()) != reg.res1()) { 391 DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n", 392 miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1()); 393 } 394 return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao 395} 396 397 398MiscReg 399ISA::readMiscReg(int misc_reg, ThreadContext *tc) 400{ 401 CPSR cpsr = 0; 402 PCState pc = 0; 403 SCR scr = 0; 404 405 if (misc_reg == MISCREG_CPSR) { 406 cpsr = miscRegs[misc_reg]; 407 pc = tc->pcState(); 408 cpsr.j = pc.jazelle() ? 1 : 0; 409 cpsr.t = pc.thumb() ? 1 : 0; 410 return cpsr; 411 } 412 413#ifndef NDEBUG 414 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 415 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 416 warn("Unimplemented system register %s read.\n", 417 miscRegName[misc_reg]); 418 else 419 panic("Unimplemented system register %s read.\n", 420 miscRegName[misc_reg]); 421 } 422#endif 423 424 switch (unflattenMiscReg(misc_reg)) { 425 case MISCREG_HCR: 426 { 427 if (!haveVirtualization) 428 return 0; 429 else 430 return readMiscRegNoEffect(MISCREG_HCR); 431 } 432 case MISCREG_CPACR: 433 { 434 const uint32_t ones = (uint32_t)(-1); 435 CPACR cpacrMask = 0; 436 // Only cp10, cp11, and ase are implemented, nothing else should 437 // be readable? (straight copy from the write code) 438 cpacrMask.cp10 = ones; 439 cpacrMask.cp11 = ones; 440 cpacrMask.asedis = ones; 441 442 // Security Extensions may limit the readability of CPACR 443 if (haveSecurity) { 444 scr = readMiscRegNoEffect(MISCREG_SCR); 445 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 446 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 447 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 448 // NB: Skipping the full loop, here 449 if (!nsacr.cp10) cpacrMask.cp10 = 0; 450 if (!nsacr.cp11) cpacrMask.cp11 = 0; 451 } 452 } 453 MiscReg val = readMiscRegNoEffect(MISCREG_CPACR); 454 val &= cpacrMask; 455 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 456 miscRegName[misc_reg], val); 457 return val; 458 } 459 case MISCREG_MPIDR: 460 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 461 scr = readMiscRegNoEffect(MISCREG_SCR); 462 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 463 return getMPIDR(system, tc); 464 } else { 465 return readMiscReg(MISCREG_VMPIDR, tc); 466 } 467 break; 468 case MISCREG_MPIDR_EL1: 469 // @todo in the absence of v8 virtualization support just return MPIDR_EL1 470 return getMPIDR(system, tc) & 0xffffffff; 471 case MISCREG_VMPIDR: 472 // top bit defined as RES1 473 return readMiscRegNoEffect(misc_reg) | 0x80000000; 474 case MISCREG_ID_AFR0: // not implemented, so alias MIDR 475 case MISCREG_REVIDR: // not implemented, so alias MIDR 476 case MISCREG_MIDR: 477 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 478 scr = readMiscRegNoEffect(MISCREG_SCR); 479 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 480 return readMiscRegNoEffect(misc_reg); 481 } else { 482 return readMiscRegNoEffect(MISCREG_VPIDR); 483 } 484 break; 485 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 486 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 487 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 488 case MISCREG_AIDR: // AUX ID set to 0 489 case MISCREG_TCMTR: // No TCM's 490 return 0; 491 492 case MISCREG_CLIDR: 493 warn_once("The clidr register always reports 0 caches.\n"); 494 warn_once("clidr LoUIS field of 0b001 to match current " 495 "ARM implementations.\n"); 496 return 0x00200000; 497 case MISCREG_CCSIDR: 498 warn_once("The ccsidr register isn't implemented and " 499 "always reads as 0.\n"); 500 break; 501 case MISCREG_CTR: // AArch32, ARMv7, top bit set 502 case MISCREG_CTR_EL0: // AArch64 503 { 504 //all caches have the same line size in gem5 505 //4 byte words in ARM 506 unsigned lineSizeWords = 507 tc->getSystemPtr()->cacheLineSize() / 4; 508 unsigned log2LineSizeWords = 0; 509 510 while (lineSizeWords >>= 1) { 511 ++log2LineSizeWords; 512 } 513 514 CTR ctr = 0; 515 //log2 of minimun i-cache line size (words) 516 ctr.iCacheLineSize = log2LineSizeWords; 517 //b11 - gem5 uses pipt 518 ctr.l1IndexPolicy = 0x3; 519 //log2 of minimum d-cache line size (words) 520 ctr.dCacheLineSize = log2LineSizeWords; 521 //log2 of max reservation size (words) 522 ctr.erg = log2LineSizeWords; 523 //log2 of max writeback size (words) 524 ctr.cwg = log2LineSizeWords; 525 //b100 - gem5 format is ARMv7 526 ctr.format = 0x4; 527 528 return ctr; 529 } 530 case MISCREG_ACTLR: 531 warn("Not doing anything for miscreg ACTLR\n"); 532 break; 533 534 case MISCREG_PMXEVTYPER_PMCCFILTR: 535 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 536 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 537 case MISCREG_PMCR ... MISCREG_PMOVSSET: 538 return pmu->readMiscReg(misc_reg); 539 540 case MISCREG_CPSR_Q: 541 panic("shouldn't be reading this register seperately\n"); 542 case MISCREG_FPSCR_QC: 543 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 544 case MISCREG_FPSCR_EXC: 545 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 546 case MISCREG_FPSR: 547 { 548 const uint32_t ones = (uint32_t)(-1); 549 FPSCR fpscrMask = 0; 550 fpscrMask.ioc = ones; 551 fpscrMask.dzc = ones; 552 fpscrMask.ofc = ones; 553 fpscrMask.ufc = ones; 554 fpscrMask.ixc = ones; 555 fpscrMask.idc = ones; 556 fpscrMask.qc = ones; 557 fpscrMask.v = ones; 558 fpscrMask.c = ones; 559 fpscrMask.z = ones; 560 fpscrMask.n = ones; 561 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 562 } 563 case MISCREG_FPCR: 564 { 565 const uint32_t ones = (uint32_t)(-1); 566 FPSCR fpscrMask = 0; 567 fpscrMask.len = ones; 568 fpscrMask.stride = ones; 569 fpscrMask.rMode = ones; 570 fpscrMask.fz = ones; 571 fpscrMask.dn = ones; 572 fpscrMask.ahp = ones; 573 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 574 } 575 case MISCREG_NZCV: 576 { 577 CPSR cpsr = 0; 578 cpsr.nz = tc->readCCReg(CCREG_NZ); 579 cpsr.c = tc->readCCReg(CCREG_C); 580 cpsr.v = tc->readCCReg(CCREG_V); 581 return cpsr; 582 } 583 case MISCREG_DAIF: 584 { 585 CPSR cpsr = 0; 586 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 587 return cpsr; 588 } 589 case MISCREG_SP_EL0: 590 { 591 return tc->readIntReg(INTREG_SP0); 592 } 593 case MISCREG_SP_EL1: 594 { 595 return tc->readIntReg(INTREG_SP1); 596 } 597 case MISCREG_SP_EL2: 598 { 599 return tc->readIntReg(INTREG_SP2); 600 } 601 case MISCREG_SPSEL: 602 { 603 return miscRegs[MISCREG_CPSR] & 0x1; 604 } 605 case MISCREG_CURRENTEL: 606 { 607 return miscRegs[MISCREG_CPSR] & 0xc; 608 } 609 case MISCREG_L2CTLR: 610 { 611 // mostly unimplemented, just set NumCPUs field from sim and return 612 L2CTLR l2ctlr = 0; 613 // b00:1CPU to b11:4CPUs 614 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 615 return l2ctlr; 616 } 617 case MISCREG_DBGDIDR: 618 /* For now just implement the version number. 619 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 620 */ 621 return 0x5 << 16; 622 case MISCREG_DBGDSCRint: 623 return 0; 624 case MISCREG_ISR: 625 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 626 readMiscRegNoEffect(MISCREG_HCR), 627 readMiscRegNoEffect(MISCREG_CPSR), 628 readMiscRegNoEffect(MISCREG_SCR)); 629 case MISCREG_ISR_EL1: 630 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 631 readMiscRegNoEffect(MISCREG_HCR_EL2), 632 readMiscRegNoEffect(MISCREG_CPSR), 633 readMiscRegNoEffect(MISCREG_SCR_EL3)); 634 case MISCREG_DCZID_EL0: 635 return 0x04; // DC ZVA clear 64-byte chunks 636 case MISCREG_HCPTR: 637 { 638 MiscReg val = readMiscRegNoEffect(misc_reg); 639 // The trap bit associated with CP14 is defined as RAZ 640 val &= ~(1 << 14); 641 // If a CP bit in NSACR is 0 then the corresponding bit in 642 // HCPTR is RAO/WI 643 bool secure_lookup = haveSecurity && 644 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 645 readMiscRegNoEffect(MISCREG_CPSR)); 646 if (!secure_lookup) { 647 MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR); 648 val |= (mask ^ 0x7FFF) & 0xBFFF; 649 } 650 // Set the bits for unimplemented coprocessors to RAO/WI 651 val |= 0x33FF; 652 return (val); 653 } 654 case MISCREG_HDFAR: // alias for secure DFAR 655 return readMiscRegNoEffect(MISCREG_DFAR_S); 656 case MISCREG_HIFAR: // alias for secure IFAR 657 return readMiscRegNoEffect(MISCREG_IFAR_S); 658 case MISCREG_HVBAR: // bottom bits reserved 659 return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0; 660 case MISCREG_SCTLR: 661 return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818; 662 case MISCREG_SCTLR_EL1: 663 return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800; 664 case MISCREG_SCTLR_EL2: 665 case MISCREG_SCTLR_EL3: 666 case MISCREG_HSCTLR: 667 return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; 668 669 case MISCREG_ID_PFR0: 670 // !ThumbEE | !Jazelle | Thumb | ARM 671 return 0x00000031; 672 case MISCREG_ID_PFR1: 673 { // Timer | Virti | !M Profile | TrustZone | ARMv4 674 bool haveTimer = (system->getGenericTimer() != NULL); 675 return 0x00000001 676 | (haveSecurity ? 0x00000010 : 0x0) 677 | (haveVirtualization ? 0x00001000 : 0x0) 678 | (haveTimer ? 0x00010000 : 0x0); 679 } 680 case MISCREG_ID_AA64PFR0_EL1: 681 return 0x0000000000000002 // AArch{64,32} supported at EL0 682 | 0x0000000000000020 // EL1 683 | (haveVirtualization ? 0x0000000000000200 : 0) // EL2 684 | (haveSecurity ? 0x0000000000002000 : 0); // EL3 685 case MISCREG_ID_AA64PFR1_EL1: 686 return 0; // bits [63:0] RES0 (reserved for future use) 687 688 // Generic Timer registers 689 case MISCREG_CNTHV_CTL_EL2: 690 case MISCREG_CNTHV_CVAL_EL2: 691 case MISCREG_CNTHV_TVAL_EL2: 692 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 693 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 694 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 695 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 696 return getGenericTimer(tc).readMiscReg(misc_reg); 697 698 default: 699 break; 700 701 } 702 return readMiscRegNoEffect(misc_reg); 703} 704 705void 706ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 707{ 708 assert(misc_reg < NumMiscRegs); 709 710 const auto ® = lookUpMiscReg[misc_reg]; // bit masks 711 const auto &map = getMiscIndices(misc_reg); 712 int lower = map.first, upper = map.second; 713 714 auto v = (val & ~reg.wi()) | reg.rao(); 715 if (upper > 0) { 716 miscRegs[lower] = bits(v, 31, 0); 717 miscRegs[upper] = bits(v, 63, 32); 718 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 719 misc_reg, lower, upper, v); 720 } else { 721 miscRegs[lower] = v; 722 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 723 misc_reg, lower, v); 724 } 725} 726 727void 728ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 729{ 730 731 MiscReg newVal = val; 732 bool secure_lookup; 733 SCR scr; 734 735 if (misc_reg == MISCREG_CPSR) { 736 updateRegMap(val); 737 738 739 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 740 int old_mode = old_cpsr.mode; 741 CPSR cpsr = val; 742 if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) { 743 getITBPtr(tc)->invalidateMiscReg(); 744 getDTBPtr(tc)->invalidateMiscReg(); 745 } 746 747 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 748 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 749 PCState pc = tc->pcState(); 750 pc.nextThumb(cpsr.t); 751 pc.nextJazelle(cpsr.j); 752 pc.illegalExec(cpsr.il == 1); 753 754 // Follow slightly different semantics if a CheckerCPU object 755 // is connected 756 CheckerCPU *checker = tc->getCheckerCpuPtr(); 757 if (checker) { 758 tc->pcStateNoRecord(pc); 759 } else { 760 tc->pcState(pc); 761 } 762 } else { 763#ifndef NDEBUG 764 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 765 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 766 warn("Unimplemented system register %s write with %#x.\n", 767 miscRegName[misc_reg], val); 768 else 769 panic("Unimplemented system register %s write with %#x.\n", 770 miscRegName[misc_reg], val); 771 } 772#endif 773 switch (unflattenMiscReg(misc_reg)) { 774 case MISCREG_CPACR: 775 { 776 777 const uint32_t ones = (uint32_t)(-1); 778 CPACR cpacrMask = 0; 779 // Only cp10, cp11, and ase are implemented, nothing else should 780 // be writable 781 cpacrMask.cp10 = ones; 782 cpacrMask.cp11 = ones; 783 cpacrMask.asedis = ones; 784 785 // Security Extensions may limit the writability of CPACR 786 if (haveSecurity) { 787 scr = readMiscRegNoEffect(MISCREG_SCR); 788 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 789 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 790 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 791 // NB: Skipping the full loop, here 792 if (!nsacr.cp10) cpacrMask.cp10 = 0; 793 if (!nsacr.cp11) cpacrMask.cp11 = 0; 794 } 795 } 796 797 MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR); 798 newVal &= cpacrMask; 799 newVal |= old_val & ~cpacrMask; 800 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 801 miscRegName[misc_reg], newVal); 802 } 803 break; 804 case MISCREG_CPTR_EL2: 805 { 806 const uint32_t ones = (uint32_t)(-1); 807 CPTR cptrMask = 0; 808 cptrMask.tcpac = ones; 809 cptrMask.tta = ones; 810 cptrMask.tfp = ones; 811 newVal &= cptrMask; 812 cptrMask = 0; 813 cptrMask.res1_13_12_el2 = ones; 814 cptrMask.res1_9_0_el2 = ones; 815 newVal |= cptrMask; 816 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 817 miscRegName[misc_reg], newVal); 818 } 819 break; 820 case MISCREG_CPTR_EL3: 821 { 822 const uint32_t ones = (uint32_t)(-1); 823 CPTR cptrMask = 0; 824 cptrMask.tcpac = ones; 825 cptrMask.tta = ones; 826 cptrMask.tfp = ones; 827 newVal &= cptrMask; 828 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 829 miscRegName[misc_reg], newVal); 830 } 831 break; 832 case MISCREG_CSSELR: 833 warn_once("The csselr register isn't implemented.\n"); 834 return; 835 836 case MISCREG_DC_ZVA_Xt: 837 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 838 return; 839 840 case MISCREG_FPSCR: 841 { 842 const uint32_t ones = (uint32_t)(-1); 843 FPSCR fpscrMask = 0; 844 fpscrMask.ioc = ones; 845 fpscrMask.dzc = ones; 846 fpscrMask.ofc = ones; 847 fpscrMask.ufc = ones; 848 fpscrMask.ixc = ones; 849 fpscrMask.idc = ones; 850 fpscrMask.ioe = ones; 851 fpscrMask.dze = ones; 852 fpscrMask.ofe = ones; 853 fpscrMask.ufe = ones; 854 fpscrMask.ixe = ones; 855 fpscrMask.ide = ones; 856 fpscrMask.len = ones; 857 fpscrMask.stride = ones; 858 fpscrMask.rMode = ones; 859 fpscrMask.fz = ones; 860 fpscrMask.dn = ones; 861 fpscrMask.ahp = ones; 862 fpscrMask.qc = ones; 863 fpscrMask.v = ones; 864 fpscrMask.c = ones; 865 fpscrMask.z = ones; 866 fpscrMask.n = ones; 867 newVal = (newVal & (uint32_t)fpscrMask) | 868 (readMiscRegNoEffect(MISCREG_FPSCR) & 869 ~(uint32_t)fpscrMask); 870 tc->getDecoderPtr()->setContext(newVal); 871 } 872 break; 873 case MISCREG_FPSR: 874 { 875 const uint32_t ones = (uint32_t)(-1); 876 FPSCR fpscrMask = 0; 877 fpscrMask.ioc = ones; 878 fpscrMask.dzc = ones; 879 fpscrMask.ofc = ones; 880 fpscrMask.ufc = ones; 881 fpscrMask.ixc = ones; 882 fpscrMask.idc = ones; 883 fpscrMask.qc = ones; 884 fpscrMask.v = ones; 885 fpscrMask.c = ones; 886 fpscrMask.z = ones; 887 fpscrMask.n = ones; 888 newVal = (newVal & (uint32_t)fpscrMask) | 889 (readMiscRegNoEffect(MISCREG_FPSCR) & 890 ~(uint32_t)fpscrMask); 891 misc_reg = MISCREG_FPSCR; 892 } 893 break; 894 case MISCREG_FPCR: 895 { 896 const uint32_t ones = (uint32_t)(-1); 897 FPSCR fpscrMask = 0; 898 fpscrMask.len = ones; 899 fpscrMask.stride = ones; 900 fpscrMask.rMode = ones; 901 fpscrMask.fz = ones; 902 fpscrMask.dn = ones; 903 fpscrMask.ahp = ones; 904 newVal = (newVal & (uint32_t)fpscrMask) | 905 (readMiscRegNoEffect(MISCREG_FPSCR) & 906 ~(uint32_t)fpscrMask); 907 misc_reg = MISCREG_FPSCR; 908 } 909 break; 910 case MISCREG_CPSR_Q: 911 { 912 assert(!(newVal & ~CpsrMaskQ)); 913 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 914 misc_reg = MISCREG_CPSR; 915 } 916 break; 917 case MISCREG_FPSCR_QC: 918 { 919 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 920 (newVal & FpscrQcMask); 921 misc_reg = MISCREG_FPSCR; 922 } 923 break; 924 case MISCREG_FPSCR_EXC: 925 { 926 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 927 (newVal & FpscrExcMask); 928 misc_reg = MISCREG_FPSCR; 929 } 930 break; 931 case MISCREG_FPEXC: 932 { 933 // vfpv3 architecture, section B.6.1 of DDI04068 934 // bit 29 - valid only if fpexc[31] is 0 935 const uint32_t fpexcMask = 0x60000000; 936 newVal = (newVal & fpexcMask) | 937 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 938 } 939 break; 940 case MISCREG_HCR: 941 { 942 if (!haveVirtualization) 943 return; 944 } 945 break; 946 case MISCREG_IFSR: 947 { 948 // ARM ARM (ARM DDI 0406C.b) B4.1.96 949 const uint32_t ifsrMask = 950 mask(31, 13) | mask(11, 11) | mask(8, 6); 951 newVal = newVal & ~ifsrMask; 952 } 953 break; 954 case MISCREG_DFSR: 955 { 956 // ARM ARM (ARM DDI 0406C.b) B4.1.52 957 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 958 newVal = newVal & ~dfsrMask; 959 } 960 break; 961 case MISCREG_AMAIR0: 962 case MISCREG_AMAIR1: 963 { 964 // ARM ARM (ARM DDI 0406C.b) B4.1.5 965 // Valid only with LPAE 966 if (!haveLPAE) 967 return; 968 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 969 } 970 break; 971 case MISCREG_SCR: 972 getITBPtr(tc)->invalidateMiscReg(); 973 getDTBPtr(tc)->invalidateMiscReg(); 974 break; 975 case MISCREG_SCTLR: 976 { 977 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 978 scr = readMiscRegNoEffect(MISCREG_SCR); 979 980 MiscRegIndex sctlr_idx; 981 if (haveSecurity && !highestELIs64 && !scr.ns) { 982 sctlr_idx = MISCREG_SCTLR_S; 983 } else { 984 sctlr_idx = MISCREG_SCTLR_NS; 985 } 986 987 SCTLR sctlr = miscRegs[sctlr_idx]; 988 SCTLR new_sctlr = newVal; 989 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 990 miscRegs[sctlr_idx] = (MiscReg)new_sctlr; 991 getITBPtr(tc)->invalidateMiscReg(); 992 getDTBPtr(tc)->invalidateMiscReg(); 993 } 994 case MISCREG_MIDR: 995 case MISCREG_ID_PFR0: 996 case MISCREG_ID_PFR1: 997 case MISCREG_ID_DFR0: 998 case MISCREG_ID_MMFR0: 999 case MISCREG_ID_MMFR1: 1000 case MISCREG_ID_MMFR2: 1001 case MISCREG_ID_MMFR3: 1002 case MISCREG_ID_ISAR0: 1003 case MISCREG_ID_ISAR1: 1004 case MISCREG_ID_ISAR2: 1005 case MISCREG_ID_ISAR3: 1006 case MISCREG_ID_ISAR4: 1007 case MISCREG_ID_ISAR5: 1008 1009 case MISCREG_MPIDR: 1010 case MISCREG_FPSID: 1011 case MISCREG_TLBTR: 1012 case MISCREG_MVFR0: 1013 case MISCREG_MVFR1: 1014 1015 case MISCREG_ID_AA64AFR0_EL1: 1016 case MISCREG_ID_AA64AFR1_EL1: 1017 case MISCREG_ID_AA64DFR0_EL1: 1018 case MISCREG_ID_AA64DFR1_EL1: 1019 case MISCREG_ID_AA64ISAR0_EL1: 1020 case MISCREG_ID_AA64ISAR1_EL1: 1021 case MISCREG_ID_AA64MMFR0_EL1: 1022 case MISCREG_ID_AA64MMFR1_EL1: 1023 case MISCREG_ID_AA64MMFR2_EL1: 1024 case MISCREG_ID_AA64PFR0_EL1: 1025 case MISCREG_ID_AA64PFR1_EL1: 1026 // ID registers are constants. 1027 return; 1028 1029 // TLB Invalidate All 1030 case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 1031 { 1032 assert32(tc); 1033 scr = readMiscReg(MISCREG_SCR, tc); 1034 1035 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1036 tlbiOp(tc); 1037 return; 1038 } 1039 // TLB Invalidate All, Inner Shareable 1040 case MISCREG_TLBIALLIS: 1041 { 1042 assert32(tc); 1043 scr = readMiscReg(MISCREG_SCR, tc); 1044 1045 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1046 tlbiOp.broadcast(tc); 1047 return; 1048 } 1049 // Instruction TLB Invalidate All 1050 case MISCREG_ITLBIALL: 1051 { 1052 assert32(tc); 1053 scr = readMiscReg(MISCREG_SCR, tc); 1054 1055 ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1056 tlbiOp(tc); 1057 return; 1058 } 1059 // Data TLB Invalidate All 1060 case MISCREG_DTLBIALL: 1061 { 1062 assert32(tc); 1063 scr = readMiscReg(MISCREG_SCR, tc); 1064 1065 DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1066 tlbiOp(tc); 1067 return; 1068 } 1069 // TLB Invalidate by VA 1070 // mcr tlbimval(is) is invalidating all matching entries 1071 // regardless of the level of lookup, since in gem5 we cache 1072 // in the tlb the last level of lookup only. 1073 case MISCREG_TLBIMVA: 1074 case MISCREG_TLBIMVAL: 1075 { 1076 assert32(tc); 1077 scr = readMiscReg(MISCREG_SCR, tc); 1078 1079 TLBIMVA tlbiOp(EL1, 1080 haveSecurity && !scr.ns, 1081 mbits(newVal, 31, 12), 1082 bits(newVal, 7,0)); 1083 1084 tlbiOp(tc); 1085 return; 1086 } 1087 // TLB Invalidate by VA, Inner Shareable 1088 case MISCREG_TLBIMVAIS: 1089 case MISCREG_TLBIMVALIS: 1090 { 1091 assert32(tc); 1092 scr = readMiscReg(MISCREG_SCR, tc); 1093 1094 TLBIMVA tlbiOp(EL1, 1095 haveSecurity && !scr.ns, 1096 mbits(newVal, 31, 12), 1097 bits(newVal, 7,0)); 1098 1099 tlbiOp.broadcast(tc); 1100 return; 1101 } 1102 // TLB Invalidate by ASID match 1103 case MISCREG_TLBIASID: 1104 { 1105 assert32(tc); 1106 scr = readMiscReg(MISCREG_SCR, tc); 1107 1108 TLBIASID tlbiOp(EL1, 1109 haveSecurity && !scr.ns, 1110 bits(newVal, 7,0)); 1111 1112 tlbiOp(tc); 1113 return; 1114 } 1115 // TLB Invalidate by ASID match, Inner Shareable 1116 case MISCREG_TLBIASIDIS: 1117 { 1118 assert32(tc); 1119 scr = readMiscReg(MISCREG_SCR, tc); 1120 1121 TLBIASID tlbiOp(EL1, 1122 haveSecurity && !scr.ns, 1123 bits(newVal, 7,0)); 1124 1125 tlbiOp.broadcast(tc); 1126 return; 1127 } 1128 // mcr tlbimvaal(is) is invalidating all matching entries 1129 // regardless of the level of lookup, since in gem5 we cache 1130 // in the tlb the last level of lookup only. 1131 // TLB Invalidate by VA, All ASID 1132 case MISCREG_TLBIMVAA: 1133 case MISCREG_TLBIMVAAL: 1134 { 1135 assert32(tc); 1136 scr = readMiscReg(MISCREG_SCR, tc); 1137 1138 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1139 mbits(newVal, 31,12), false); 1140 1141 tlbiOp(tc); 1142 return; 1143 } 1144 // TLB Invalidate by VA, All ASID, Inner Shareable 1145 case MISCREG_TLBIMVAAIS: 1146 case MISCREG_TLBIMVAALIS: 1147 { 1148 assert32(tc); 1149 scr = readMiscReg(MISCREG_SCR, tc); 1150 1151 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1152 mbits(newVal, 31,12), false); 1153 1154 tlbiOp.broadcast(tc); 1155 return; 1156 } 1157 // mcr tlbimvalh(is) is invalidating all matching entries 1158 // regardless of the level of lookup, since in gem5 we cache 1159 // in the tlb the last level of lookup only. 1160 // TLB Invalidate by VA, Hyp mode 1161 case MISCREG_TLBIMVAH: 1162 case MISCREG_TLBIMVALH: 1163 { 1164 assert32(tc); 1165 scr = readMiscReg(MISCREG_SCR, tc); 1166 1167 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1168 mbits(newVal, 31,12), true); 1169 1170 tlbiOp(tc); 1171 return; 1172 } 1173 // TLB Invalidate by VA, Hyp mode, Inner Shareable 1174 case MISCREG_TLBIMVAHIS: 1175 case MISCREG_TLBIMVALHIS: 1176 { 1177 assert32(tc); 1178 scr = readMiscReg(MISCREG_SCR, tc); 1179 1180 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1181 mbits(newVal, 31,12), true); 1182 1183 tlbiOp.broadcast(tc); 1184 return; 1185 } 1186 // mcr tlbiipas2l(is) is invalidating all matching entries 1187 // regardless of the level of lookup, since in gem5 we cache 1188 // in the tlb the last level of lookup only. 1189 // TLB Invalidate by Intermediate Physical Address, Stage 2 1190 case MISCREG_TLBIIPAS2: 1191 case MISCREG_TLBIIPAS2L: 1192 { 1193 assert32(tc); 1194 scr = readMiscReg(MISCREG_SCR, tc); 1195 1196 TLBIIPA tlbiOp(EL1, 1197 haveSecurity && !scr.ns, 1198 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1199 1200 tlbiOp(tc); 1201 return; 1202 } 1203 // TLB Invalidate by Intermediate Physical Address, Stage 2, 1204 // Inner Shareable 1205 case MISCREG_TLBIIPAS2IS: 1206 case MISCREG_TLBIIPAS2LIS: 1207 { 1208 assert32(tc); 1209 scr = readMiscReg(MISCREG_SCR, tc); 1210 1211 TLBIIPA tlbiOp(EL1, 1212 haveSecurity && !scr.ns, 1213 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1214 1215 tlbiOp.broadcast(tc); 1216 return; 1217 } 1218 // Instruction TLB Invalidate by VA 1219 case MISCREG_ITLBIMVA: 1220 { 1221 assert32(tc); 1222 scr = readMiscReg(MISCREG_SCR, tc); 1223 1224 ITLBIMVA tlbiOp(EL1, 1225 haveSecurity && !scr.ns, 1226 mbits(newVal, 31, 12), 1227 bits(newVal, 7,0)); 1228 1229 tlbiOp(tc); 1230 return; 1231 } 1232 // Data TLB Invalidate by VA 1233 case MISCREG_DTLBIMVA: 1234 { 1235 assert32(tc); 1236 scr = readMiscReg(MISCREG_SCR, tc); 1237 1238 DTLBIMVA tlbiOp(EL1, 1239 haveSecurity && !scr.ns, 1240 mbits(newVal, 31, 12), 1241 bits(newVal, 7,0)); 1242 1243 tlbiOp(tc); 1244 return; 1245 } 1246 // Instruction TLB Invalidate by ASID match 1247 case MISCREG_ITLBIASID: 1248 { 1249 assert32(tc); 1250 scr = readMiscReg(MISCREG_SCR, tc); 1251 1252 ITLBIASID tlbiOp(EL1, 1253 haveSecurity && !scr.ns, 1254 bits(newVal, 7,0)); 1255 1256 tlbiOp(tc); 1257 return; 1258 } 1259 // Data TLB Invalidate by ASID match 1260 case MISCREG_DTLBIASID: 1261 { 1262 assert32(tc); 1263 scr = readMiscReg(MISCREG_SCR, tc); 1264 1265 DTLBIASID tlbiOp(EL1, 1266 haveSecurity && !scr.ns, 1267 bits(newVal, 7,0)); 1268 1269 tlbiOp(tc); 1270 return; 1271 } 1272 // TLB Invalidate All, Non-Secure Non-Hyp 1273 case MISCREG_TLBIALLNSNH: 1274 { 1275 assert32(tc); 1276 1277 TLBIALLN tlbiOp(EL1, false); 1278 tlbiOp(tc); 1279 return; 1280 } 1281 // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable 1282 case MISCREG_TLBIALLNSNHIS: 1283 { 1284 assert32(tc); 1285 1286 TLBIALLN tlbiOp(EL1, false); 1287 tlbiOp.broadcast(tc); 1288 return; 1289 } 1290 // TLB Invalidate All, Hyp mode 1291 case MISCREG_TLBIALLH: 1292 { 1293 assert32(tc); 1294 1295 TLBIALLN tlbiOp(EL1, true); 1296 tlbiOp(tc); 1297 return; 1298 } 1299 // TLB Invalidate All, Hyp mode, Inner Shareable 1300 case MISCREG_TLBIALLHIS: 1301 { 1302 assert32(tc); 1303 1304 TLBIALLN tlbiOp(EL1, true); 1305 tlbiOp.broadcast(tc); 1306 return; 1307 } 1308 // AArch64 TLB Invalidate All, EL3 1309 case MISCREG_TLBI_ALLE3: 1310 { 1311 assert64(tc); 1312 1313 TLBIALL tlbiOp(EL3, true); 1314 tlbiOp(tc); 1315 return; 1316 } 1317 // AArch64 TLB Invalidate All, EL3, Inner Shareable 1318 case MISCREG_TLBI_ALLE3IS: 1319 { 1320 assert64(tc); 1321 1322 TLBIALL tlbiOp(EL3, true); 1323 tlbiOp.broadcast(tc); 1324 return; 1325 } 1326 // @todo: uncomment this to enable Virtualization 1327 // case MISCREG_TLBI_ALLE2IS: 1328 // case MISCREG_TLBI_ALLE2: 1329 // AArch64 TLB Invalidate All, EL1 1330 case MISCREG_TLBI_ALLE1: 1331 case MISCREG_TLBI_VMALLE1: 1332 case MISCREG_TLBI_VMALLS12E1: 1333 // @todo: handle VMID and stage 2 to enable Virtualization 1334 { 1335 assert64(tc); 1336 scr = readMiscReg(MISCREG_SCR, tc); 1337 1338 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1339 tlbiOp(tc); 1340 return; 1341 } 1342 // AArch64 TLB Invalidate All, EL1, Inner Shareable 1343 case MISCREG_TLBI_ALLE1IS: 1344 case MISCREG_TLBI_VMALLE1IS: 1345 case MISCREG_TLBI_VMALLS12E1IS: 1346 // @todo: handle VMID and stage 2 to enable Virtualization 1347 { 1348 assert64(tc); 1349 scr = readMiscReg(MISCREG_SCR, tc); 1350 1351 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1352 tlbiOp.broadcast(tc); 1353 return; 1354 } 1355 // VAEx(IS) and VALEx(IS) are the same because TLBs 1356 // only store entries 1357 // from the last level of translation table walks 1358 // @todo: handle VMID to enable Virtualization 1359 // AArch64 TLB Invalidate by VA, EL3 1360 case MISCREG_TLBI_VAE3_Xt: 1361 case MISCREG_TLBI_VALE3_Xt: 1362 { 1363 assert64(tc); 1364 1365 TLBIMVA tlbiOp(EL3, true, 1366 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1367 0xbeef); 1368 tlbiOp(tc); 1369 return; 1370 } 1371 // AArch64 TLB Invalidate by VA, EL3, Inner Shareable 1372 case MISCREG_TLBI_VAE3IS_Xt: 1373 case MISCREG_TLBI_VALE3IS_Xt: 1374 { 1375 assert64(tc); 1376 1377 TLBIMVA tlbiOp(EL3, true, 1378 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1379 0xbeef); 1380 1381 tlbiOp.broadcast(tc); 1382 return; 1383 } 1384 // AArch64 TLB Invalidate by VA, EL2 1385 case MISCREG_TLBI_VAE2_Xt: 1386 case MISCREG_TLBI_VALE2_Xt: 1387 { 1388 assert64(tc); 1389 scr = readMiscReg(MISCREG_SCR, tc); 1390 1391 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1392 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1393 0xbeef); 1394 tlbiOp(tc); 1395 return; 1396 } 1397 // AArch64 TLB Invalidate by VA, EL2, Inner Shareable 1398 case MISCREG_TLBI_VAE2IS_Xt: 1399 case MISCREG_TLBI_VALE2IS_Xt: 1400 { 1401 assert64(tc); 1402 scr = readMiscReg(MISCREG_SCR, tc); 1403 1404 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1405 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1406 0xbeef); 1407 1408 tlbiOp.broadcast(tc); 1409 return; 1410 } 1411 // AArch64 TLB Invalidate by VA, EL1 1412 case MISCREG_TLBI_VAE1_Xt: 1413 case MISCREG_TLBI_VALE1_Xt: 1414 { 1415 assert64(tc); 1416 scr = readMiscReg(MISCREG_SCR, tc); 1417 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1418 bits(newVal, 55, 48); 1419 1420 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1421 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1422 asid); 1423 1424 tlbiOp(tc); 1425 return; 1426 } 1427 // AArch64 TLB Invalidate by VA, EL1, Inner Shareable 1428 case MISCREG_TLBI_VAE1IS_Xt: 1429 case MISCREG_TLBI_VALE1IS_Xt: 1430 { 1431 assert64(tc); 1432 scr = readMiscReg(MISCREG_SCR, tc); 1433 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1434 bits(newVal, 55, 48); 1435 1436 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1437 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1438 asid); 1439 1440 tlbiOp.broadcast(tc); 1441 return; 1442 } 1443 // AArch64 TLB Invalidate by ASID, EL1 1444 // @todo: handle VMID to enable Virtualization 1445 case MISCREG_TLBI_ASIDE1_Xt: 1446 { 1447 assert64(tc); 1448 scr = readMiscReg(MISCREG_SCR, tc); 1449 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1450 bits(newVal, 55, 48); 1451 1452 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1453 tlbiOp(tc); 1454 return; 1455 } 1456 // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable 1457 case MISCREG_TLBI_ASIDE1IS_Xt: 1458 { 1459 assert64(tc); 1460 scr = readMiscReg(MISCREG_SCR, tc); 1461 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1462 bits(newVal, 55, 48); 1463 1464 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1465 tlbiOp.broadcast(tc); 1466 return; 1467 } 1468 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 1469 // entries from the last level of translation table walks 1470 // AArch64 TLB Invalidate by VA, All ASID, EL1 1471 case MISCREG_TLBI_VAAE1_Xt: 1472 case MISCREG_TLBI_VAALE1_Xt: 1473 { 1474 assert64(tc); 1475 scr = readMiscReg(MISCREG_SCR, tc); 1476 1477 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1478 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 1479 1480 tlbiOp(tc); 1481 return; 1482 } 1483 // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable 1484 case MISCREG_TLBI_VAAE1IS_Xt: 1485 case MISCREG_TLBI_VAALE1IS_Xt: 1486 { 1487 assert64(tc); 1488 scr = readMiscReg(MISCREG_SCR, tc); 1489 1490 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1491 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 1492 1493 tlbiOp.broadcast(tc); 1494 return; 1495 } 1496 // AArch64 TLB Invalidate by Intermediate Physical Address, 1497 // Stage 2, EL1 1498 case MISCREG_TLBI_IPAS2E1_Xt: 1499 case MISCREG_TLBI_IPAS2LE1_Xt: 1500 { 1501 assert64(tc); 1502 scr = readMiscReg(MISCREG_SCR, tc); 1503 1504 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1505 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1506 1507 tlbiOp(tc); 1508 return; 1509 } 1510 // AArch64 TLB Invalidate by Intermediate Physical Address, 1511 // Stage 2, EL1, Inner Shareable 1512 case MISCREG_TLBI_IPAS2E1IS_Xt: 1513 case MISCREG_TLBI_IPAS2LE1IS_Xt: 1514 { 1515 assert64(tc); 1516 scr = readMiscReg(MISCREG_SCR, tc); 1517 1518 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1519 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1520 1521 tlbiOp.broadcast(tc); 1522 return; 1523 } 1524 case MISCREG_ACTLR: 1525 warn("Not doing anything for write of miscreg ACTLR\n"); 1526 break; 1527 1528 case MISCREG_PMXEVTYPER_PMCCFILTR: 1529 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 1530 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 1531 case MISCREG_PMCR ... MISCREG_PMOVSSET: 1532 pmu->setMiscReg(misc_reg, newVal); 1533 break; 1534 1535 1536 case MISCREG_HSTR: // TJDBX, now redifined to be RES0 1537 { 1538 HSTR hstrMask = 0; 1539 hstrMask.tjdbx = 1; 1540 newVal &= ~((uint32_t) hstrMask); 1541 break; 1542 } 1543 case MISCREG_HCPTR: 1544 { 1545 // If a CP bit in NSACR is 0 then the corresponding bit in 1546 // HCPTR is RAO/WI. Same applies to NSASEDIS 1547 secure_lookup = haveSecurity && 1548 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 1549 readMiscRegNoEffect(MISCREG_CPSR)); 1550 if (!secure_lookup) { 1551 MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 1552 MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 1553 newVal = (newVal & ~mask) | (oldValue & mask); 1554 } 1555 break; 1556 } 1557 case MISCREG_HDFAR: // alias for secure DFAR 1558 misc_reg = MISCREG_DFAR_S; 1559 break; 1560 case MISCREG_HIFAR: // alias for secure IFAR 1561 misc_reg = MISCREG_IFAR_S; 1562 break; 1563 case MISCREG_ATS1CPR: 1564 case MISCREG_ATS1CPW: 1565 case MISCREG_ATS1CUR: 1566 case MISCREG_ATS1CUW: 1567 case MISCREG_ATS12NSOPR: 1568 case MISCREG_ATS12NSOPW: 1569 case MISCREG_ATS12NSOUR: 1570 case MISCREG_ATS12NSOUW: 1571 case MISCREG_ATS1HR: 1572 case MISCREG_ATS1HW: 1573 { 1574 Request::Flags flags = 0; 1575 BaseTLB::Mode mode = BaseTLB::Read; 1576 TLB::ArmTranslationType tranType = TLB::NormalTran; 1577 Fault fault; 1578 switch(misc_reg) { 1579 case MISCREG_ATS1CPR: 1580 flags = TLB::MustBeOne; 1581 tranType = TLB::S1CTran; 1582 mode = BaseTLB::Read; 1583 break; 1584 case MISCREG_ATS1CPW: 1585 flags = TLB::MustBeOne; 1586 tranType = TLB::S1CTran; 1587 mode = BaseTLB::Write; 1588 break; 1589 case MISCREG_ATS1CUR: 1590 flags = TLB::MustBeOne | TLB::UserMode; 1591 tranType = TLB::S1CTran; 1592 mode = BaseTLB::Read; 1593 break; 1594 case MISCREG_ATS1CUW: 1595 flags = TLB::MustBeOne | TLB::UserMode; 1596 tranType = TLB::S1CTran; 1597 mode = BaseTLB::Write; 1598 break; 1599 case MISCREG_ATS12NSOPR: 1600 if (!haveSecurity) 1601 panic("Security Extensions required for ATS12NSOPR"); 1602 flags = TLB::MustBeOne; 1603 tranType = TLB::S1S2NsTran; 1604 mode = BaseTLB::Read; 1605 break; 1606 case MISCREG_ATS12NSOPW: 1607 if (!haveSecurity) 1608 panic("Security Extensions required for ATS12NSOPW"); 1609 flags = TLB::MustBeOne; 1610 tranType = TLB::S1S2NsTran; 1611 mode = BaseTLB::Write; 1612 break; 1613 case MISCREG_ATS12NSOUR: 1614 if (!haveSecurity) 1615 panic("Security Extensions required for ATS12NSOUR"); 1616 flags = TLB::MustBeOne | TLB::UserMode; 1617 tranType = TLB::S1S2NsTran; 1618 mode = BaseTLB::Read; 1619 break; 1620 case MISCREG_ATS12NSOUW: 1621 if (!haveSecurity) 1622 panic("Security Extensions required for ATS12NSOUW"); 1623 flags = TLB::MustBeOne | TLB::UserMode; 1624 tranType = TLB::S1S2NsTran; 1625 mode = BaseTLB::Write; 1626 break; 1627 case MISCREG_ATS1HR: // only really useful from secure mode. 1628 flags = TLB::MustBeOne; 1629 tranType = TLB::HypMode; 1630 mode = BaseTLB::Read; 1631 break; 1632 case MISCREG_ATS1HW: 1633 flags = TLB::MustBeOne; 1634 tranType = TLB::HypMode; 1635 mode = BaseTLB::Write; 1636 break; 1637 } 1638 // If we're in timing mode then doing the translation in 1639 // functional mode then we're slightly distorting performance 1640 // results obtained from simulations. The translation should be 1641 // done in the same mode the core is running in. NOTE: This 1642 // can't be an atomic translation because that causes problems 1643 // with unexpected atomic snoop requests. 1644 warn("Translating via %s in functional mode! Fix Me!\n", 1645 miscRegName[misc_reg]); 1646 1647 auto req = std::make_shared<Request>( 1648 0, val, 0, flags, Request::funcMasterId, 1649 tc->pcState().pc(), tc->contextId()); 1650 1651 fault = getDTBPtr(tc)->translateFunctional( 1652 req, tc, mode, tranType); 1653 1654 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1655 HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 1656 1657 MiscReg newVal; 1658 if (fault == NoFault) { 1659 Addr paddr = req->getPaddr(); 1660 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 1661 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 1662 newVal = (paddr & mask(39, 12)) | 1663 (getDTBPtr(tc)->getAttr()); 1664 } else { 1665 newVal = (paddr & 0xfffff000) | 1666 (getDTBPtr(tc)->getAttr()); 1667 } 1668 DPRINTF(MiscRegs, 1669 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 1670 val, newVal); 1671 } else { 1672 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1673 armFault->update(tc); 1674 // Set fault bit and FSR 1675 FSR fsr = armFault->getFsr(tc); 1676 1677 newVal = ((fsr >> 9) & 1) << 11; 1678 if (newVal) { 1679 // LPAE - rearange fault status 1680 newVal |= ((fsr >> 0) & 0x3f) << 1; 1681 } else { 1682 // VMSA - rearange fault status 1683 newVal |= ((fsr >> 0) & 0xf) << 1; 1684 newVal |= ((fsr >> 10) & 0x1) << 5; 1685 newVal |= ((fsr >> 12) & 0x1) << 6; 1686 } 1687 newVal |= 0x1; // F bit 1688 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1689 newVal |= armFault->isStage2() ? 0x200 : 0; 1690 DPRINTF(MiscRegs, 1691 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 1692 val, fsr, newVal); 1693 } 1694 setMiscRegNoEffect(MISCREG_PAR, newVal); 1695 return; 1696 } 1697 case MISCREG_TTBCR: 1698 { 1699 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1700 const uint32_t ones = (uint32_t)(-1); 1701 TTBCR ttbcrMask = 0; 1702 TTBCR ttbcrNew = newVal; 1703 1704 // ARM DDI 0406C.b, ARMv7-32 1705 ttbcrMask.n = ones; // T0SZ 1706 if (haveSecurity) { 1707 ttbcrMask.pd0 = ones; 1708 ttbcrMask.pd1 = ones; 1709 } 1710 ttbcrMask.epd0 = ones; 1711 ttbcrMask.irgn0 = ones; 1712 ttbcrMask.orgn0 = ones; 1713 ttbcrMask.sh0 = ones; 1714 ttbcrMask.ps = ones; // T1SZ 1715 ttbcrMask.a1 = ones; 1716 ttbcrMask.epd1 = ones; 1717 ttbcrMask.irgn1 = ones; 1718 ttbcrMask.orgn1 = ones; 1719 ttbcrMask.sh1 = ones; 1720 if (haveLPAE) 1721 ttbcrMask.eae = ones; 1722 1723 if (haveLPAE && ttbcrNew.eae) { 1724 newVal = newVal & ttbcrMask; 1725 } else { 1726 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 1727 } 1728 // Invalidate TLB MiscReg 1729 getITBPtr(tc)->invalidateMiscReg(); 1730 getDTBPtr(tc)->invalidateMiscReg(); 1731 break; 1732 } 1733 case MISCREG_TTBR0: 1734 case MISCREG_TTBR1: 1735 { 1736 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1737 if (haveLPAE) { 1738 if (ttbcr.eae) { 1739 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 1740 // ARMv8 AArch32 bit 63-56 only 1741 uint64_t ttbrMask = mask(63,56) | mask(47,40); 1742 newVal = (newVal & (~ttbrMask)); 1743 } 1744 } 1745 // Invalidate TLB MiscReg 1746 getITBPtr(tc)->invalidateMiscReg(); 1747 getDTBPtr(tc)->invalidateMiscReg(); 1748 break; 1749 } 1750 case MISCREG_SCTLR_EL1: 1751 case MISCREG_CONTEXTIDR: 1752 case MISCREG_PRRR: 1753 case MISCREG_NMRR: 1754 case MISCREG_MAIR0: 1755 case MISCREG_MAIR1: 1756 case MISCREG_DACR: 1757 case MISCREG_VTTBR: 1758 case MISCREG_SCR_EL3: 1759 case MISCREG_HCR_EL2: 1760 case MISCREG_TCR_EL1: 1761 case MISCREG_TCR_EL2: 1762 case MISCREG_TCR_EL3: 1763 case MISCREG_SCTLR_EL2: 1764 case MISCREG_SCTLR_EL3: 1765 case MISCREG_HSCTLR: 1766 case MISCREG_TTBR0_EL1: 1767 case MISCREG_TTBR1_EL1: 1768 case MISCREG_TTBR0_EL2: 1769 case MISCREG_TTBR1_EL2: 1770 case MISCREG_TTBR0_EL3: 1771 getITBPtr(tc)->invalidateMiscReg(); 1772 getDTBPtr(tc)->invalidateMiscReg(); 1773 break; 1774 case MISCREG_NZCV: 1775 { 1776 CPSR cpsr = val; 1777 1778 tc->setCCReg(CCREG_NZ, cpsr.nz); 1779 tc->setCCReg(CCREG_C, cpsr.c); 1780 tc->setCCReg(CCREG_V, cpsr.v); 1781 } 1782 break; 1783 case MISCREG_DAIF: 1784 { 1785 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1786 cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 1787 newVal = cpsr; 1788 misc_reg = MISCREG_CPSR; 1789 } 1790 break; 1791 case MISCREG_SP_EL0: 1792 tc->setIntReg(INTREG_SP0, newVal); 1793 break; 1794 case MISCREG_SP_EL1: 1795 tc->setIntReg(INTREG_SP1, newVal); 1796 break; 1797 case MISCREG_SP_EL2: 1798 tc->setIntReg(INTREG_SP2, newVal); 1799 break; 1800 case MISCREG_SPSEL: 1801 { 1802 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1803 cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 1804 newVal = cpsr; 1805 misc_reg = MISCREG_CPSR; 1806 } 1807 break; 1808 case MISCREG_CURRENTEL: 1809 { 1810 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1811 cpsr.el = (uint8_t) ((CPSR) newVal).el; 1812 newVal = cpsr; 1813 misc_reg = MISCREG_CPSR; 1814 } 1815 break; 1816 case MISCREG_AT_S1E1R_Xt: 1817 case MISCREG_AT_S1E1W_Xt: 1818 case MISCREG_AT_S1E0R_Xt: 1819 case MISCREG_AT_S1E0W_Xt: 1820 case MISCREG_AT_S1E2R_Xt: 1821 case MISCREG_AT_S1E2W_Xt: 1822 case MISCREG_AT_S12E1R_Xt: 1823 case MISCREG_AT_S12E1W_Xt: 1824 case MISCREG_AT_S12E0R_Xt: 1825 case MISCREG_AT_S12E0W_Xt: 1826 case MISCREG_AT_S1E3R_Xt: 1827 case MISCREG_AT_S1E3W_Xt: 1828 { 1829 RequestPtr req = std::make_shared<Request>(); 1830 Request::Flags flags = 0; 1831 BaseTLB::Mode mode = BaseTLB::Read; 1832 TLB::ArmTranslationType tranType = TLB::NormalTran; 1833 Fault fault; 1834 switch(misc_reg) { 1835 case MISCREG_AT_S1E1R_Xt: 1836 flags = TLB::MustBeOne; 1837 tranType = TLB::S1E1Tran; 1838 mode = BaseTLB::Read; 1839 break; 1840 case MISCREG_AT_S1E1W_Xt: 1841 flags = TLB::MustBeOne; 1842 tranType = TLB::S1E1Tran; 1843 mode = BaseTLB::Write; 1844 break; 1845 case MISCREG_AT_S1E0R_Xt: 1846 flags = TLB::MustBeOne | TLB::UserMode; 1847 tranType = TLB::S1E0Tran; 1848 mode = BaseTLB::Read; 1849 break; 1850 case MISCREG_AT_S1E0W_Xt: 1851 flags = TLB::MustBeOne | TLB::UserMode; 1852 tranType = TLB::S1E0Tran; 1853 mode = BaseTLB::Write; 1854 break; 1855 case MISCREG_AT_S1E2R_Xt: 1856 flags = TLB::MustBeOne; 1857 tranType = TLB::S1E2Tran; 1858 mode = BaseTLB::Read; 1859 break; 1860 case MISCREG_AT_S1E2W_Xt: 1861 flags = TLB::MustBeOne; 1862 tranType = TLB::S1E2Tran; 1863 mode = BaseTLB::Write; 1864 break; 1865 case MISCREG_AT_S12E0R_Xt: 1866 flags = TLB::MustBeOne | TLB::UserMode; 1867 tranType = TLB::S12E0Tran; 1868 mode = BaseTLB::Read; 1869 break; 1870 case MISCREG_AT_S12E0W_Xt: 1871 flags = TLB::MustBeOne | TLB::UserMode; 1872 tranType = TLB::S12E0Tran; 1873 mode = BaseTLB::Write; 1874 break; 1875 case MISCREG_AT_S12E1R_Xt: 1876 flags = TLB::MustBeOne; 1877 tranType = TLB::S12E1Tran; 1878 mode = BaseTLB::Read; 1879 break; 1880 case MISCREG_AT_S12E1W_Xt: 1881 flags = TLB::MustBeOne; 1882 tranType = TLB::S12E1Tran; 1883 mode = BaseTLB::Write; 1884 break; 1885 case MISCREG_AT_S1E3R_Xt: 1886 flags = TLB::MustBeOne; 1887 tranType = TLB::S1E3Tran; 1888 mode = BaseTLB::Read; 1889 break; 1890 case MISCREG_AT_S1E3W_Xt: 1891 flags = TLB::MustBeOne; 1892 tranType = TLB::S1E3Tran; 1893 mode = BaseTLB::Write; 1894 break; 1895 } 1896 // If we're in timing mode then doing the translation in 1897 // functional mode then we're slightly distorting performance 1898 // results obtained from simulations. The translation should be 1899 // done in the same mode the core is running in. NOTE: This 1900 // can't be an atomic translation because that causes problems 1901 // with unexpected atomic snoop requests. 1902 warn("Translating via %s in functional mode! Fix Me!\n", 1903 miscRegName[misc_reg]); 1904 1905 req->setVirt(0, val, 0, flags, Request::funcMasterId, 1906 tc->pcState().pc()); 1907 req->setContext(tc->contextId()); 1908 fault = getDTBPtr(tc)->translateFunctional(req, tc, mode, 1909 tranType); 1910 1911 MiscReg newVal; 1912 if (fault == NoFault) { 1913 Addr paddr = req->getPaddr(); 1914 uint64_t attr = getDTBPtr(tc)->getAttr(); 1915 uint64_t attr1 = attr >> 56; 1916 if (!attr1 || attr1 ==0x44) { 1917 attr |= 0x100; 1918 attr &= ~ uint64_t(0x80); 1919 } 1920 newVal = (paddr & mask(47, 12)) | attr; 1921 DPRINTF(MiscRegs, 1922 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 1923 val, newVal); 1924 } else { 1925 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1926 armFault->update(tc); 1927 // Set fault bit and FSR 1928 FSR fsr = armFault->getFsr(tc); 1929 1930 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1931 if (cpsr.width) { // AArch32 1932 newVal = ((fsr >> 9) & 1) << 11; 1933 // rearrange fault status 1934 newVal |= ((fsr >> 0) & 0x3f) << 1; 1935 newVal |= 0x1; // F bit 1936 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1937 newVal |= armFault->isStage2() ? 0x200 : 0; 1938 } else { // AArch64 1939 newVal = 1; // F bit 1940 newVal |= fsr << 1; // FST 1941 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit. 1942 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 1943 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 1944 newVal |= 1 << 11; // RES1 1945 } 1946 DPRINTF(MiscRegs, 1947 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 1948 val, fsr, newVal); 1949 } 1950 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 1951 return; 1952 } 1953 case MISCREG_SPSR_EL3: 1954 case MISCREG_SPSR_EL2: 1955 case MISCREG_SPSR_EL1: 1956 // Force bits 23:21 to 0 1957 newVal = val & ~(0x7 << 21); 1958 break; 1959 case MISCREG_L2CTLR: 1960 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 1961 miscRegName[misc_reg], uint32_t(val)); 1962 break; 1963 1964 // Generic Timer registers 1965 case MISCREG_CNTHV_CTL_EL2: 1966 case MISCREG_CNTHV_CVAL_EL2: 1967 case MISCREG_CNTHV_TVAL_EL2: 1968 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 1969 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 1970 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 1971 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 1972 getGenericTimer(tc).setMiscReg(misc_reg, newVal); 1973 break; 1974 } 1975 } 1976 setMiscRegNoEffect(misc_reg, newVal); 1977} 1978 1979BaseISADevice & 1980ISA::getGenericTimer(ThreadContext *tc) 1981{ 1982 // We only need to create an ISA interface the first time we try 1983 // to access the timer. 1984 if (timer) 1985 return *timer.get(); 1986 1987 assert(system); 1988 GenericTimer *generic_timer(system->getGenericTimer()); 1989 if (!generic_timer) { 1990 panic("Trying to get a generic timer from a system that hasn't " 1991 "been configured to use a generic timer.\n"); 1992 } 1993 1994 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 1995 timer->setThreadContext(tc); 1996 1997 return *timer.get(); 1998} 1999 2000} 2001 2002ArmISA::ISA * 2003ArmISAParams::create() 2004{ 2005 return new ArmISA::ISA(this); 2006} 2007