isa.cc revision 13393:659fdbcd5722
1/* 2 * Copyright (c) 2010-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 */ 40 41#include "arch/arm/isa.hh" 42#include "arch/arm/pmu.hh" 43#include "arch/arm/system.hh" 44#include "arch/arm/tlb.hh" 45#include "arch/arm/tlbi_op.hh" 46#include "cpu/base.hh" 47#include "cpu/checker/cpu.hh" 48#include "debug/Arm.hh" 49#include "debug/MiscRegs.hh" 50#include "dev/arm/generic_timer.hh" 51#include "params/ArmISA.hh" 52#include "sim/faults.hh" 53#include "sim/stat_control.hh" 54#include "sim/system.hh" 55 56namespace ArmISA 57{ 58 59ISA::ISA(Params *p) 60 : SimObject(p), 61 system(NULL), 62 _decoderFlavour(p->decoderFlavour), 63 _vecRegRenameMode(p->vecRegRenameMode), 64 pmu(p->pmu), 65 impdefAsNop(p->impdef_nop) 66{ 67 miscRegs[MISCREG_SCTLR_RST] = 0; 68 69 // Hook up a dummy device if we haven't been configured with a 70 // real PMU. By using a dummy device, we don't need to check that 71 // the PMU exist every time we try to access a PMU register. 72 if (!pmu) 73 pmu = &dummyDevice; 74 75 // Give all ISA devices a pointer to this ISA 76 pmu->setISA(this); 77 78 system = dynamic_cast<ArmSystem *>(p->system); 79 80 // Cache system-level properties 81 if (FullSystem && system) { 82 highestELIs64 = system->highestELIs64(); 83 haveSecurity = system->haveSecurity(); 84 haveLPAE = system->haveLPAE(); 85 haveCrypto = system->haveCrypto(); 86 haveVirtualization = system->haveVirtualization(); 87 haveLargeAsid64 = system->haveLargeAsid64(); 88 physAddrRange = system->physAddrRange(); 89 } else { 90 highestELIs64 = true; // ArmSystem::highestELIs64 does the same 91 haveSecurity = haveLPAE = haveVirtualization = false; 92 haveCrypto = false; 93 haveLargeAsid64 = false; 94 physAddrRange = 32; // dummy value 95 } 96 97 initializeMiscRegMetadata(); 98 preUnflattenMiscReg(); 99 100 clear(); 101} 102 103std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS); 104 105const ArmISAParams * 106ISA::params() const 107{ 108 return dynamic_cast<const Params *>(_params); 109} 110 111void 112ISA::clear() 113{ 114 const Params *p(params()); 115 116 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 117 memset(miscRegs, 0, sizeof(miscRegs)); 118 119 initID32(p); 120 121 // We always initialize AArch64 ID registers even 122 // if we are in AArch32. This is done since if we 123 // are in SE mode we don't know if our ArmProcess is 124 // AArch32 or AArch64 125 initID64(p); 126 127 // Start with an event in the mailbox 128 miscRegs[MISCREG_SEV_MAILBOX] = 1; 129 130 // Separate Instruction and Data TLBs 131 miscRegs[MISCREG_TLBTR] = 1; 132 133 MVFR0 mvfr0 = 0; 134 mvfr0.advSimdRegisters = 2; 135 mvfr0.singlePrecision = 2; 136 mvfr0.doublePrecision = 2; 137 mvfr0.vfpExceptionTrapping = 0; 138 mvfr0.divide = 1; 139 mvfr0.squareRoot = 1; 140 mvfr0.shortVectors = 1; 141 mvfr0.roundingModes = 1; 142 miscRegs[MISCREG_MVFR0] = mvfr0; 143 144 MVFR1 mvfr1 = 0; 145 mvfr1.flushToZero = 1; 146 mvfr1.defaultNaN = 1; 147 mvfr1.advSimdLoadStore = 1; 148 mvfr1.advSimdInteger = 1; 149 mvfr1.advSimdSinglePrecision = 1; 150 mvfr1.advSimdHalfPrecision = 1; 151 mvfr1.vfpHalfPrecision = 1; 152 miscRegs[MISCREG_MVFR1] = mvfr1; 153 154 // Reset values of PRRR and NMRR are implementation dependent 155 156 // @todo: PRRR and NMRR in secure state? 157 miscRegs[MISCREG_PRRR_NS] = 158 (1 << 19) | // 19 159 (0 << 18) | // 18 160 (0 << 17) | // 17 161 (1 << 16) | // 16 162 (2 << 14) | // 15:14 163 (0 << 12) | // 13:12 164 (2 << 10) | // 11:10 165 (2 << 8) | // 9:8 166 (2 << 6) | // 7:6 167 (2 << 4) | // 5:4 168 (1 << 2) | // 3:2 169 0; // 1:0 170 171 miscRegs[MISCREG_NMRR_NS] = 172 (1 << 30) | // 31:30 173 (0 << 26) | // 27:26 174 (0 << 24) | // 25:24 175 (3 << 22) | // 23:22 176 (2 << 20) | // 21:20 177 (0 << 18) | // 19:18 178 (0 << 16) | // 17:16 179 (1 << 14) | // 15:14 180 (0 << 12) | // 13:12 181 (2 << 10) | // 11:10 182 (0 << 8) | // 9:8 183 (3 << 6) | // 7:6 184 (2 << 4) | // 5:4 185 (0 << 2) | // 3:2 186 0; // 1:0 187 188 if (FullSystem && system->highestELIs64()) { 189 // Initialize AArch64 state 190 clear64(p); 191 return; 192 } 193 194 // Initialize AArch32 state... 195 clear32(p, sctlr_rst); 196} 197 198void 199ISA::clear32(const ArmISAParams *p, const SCTLR &sctlr_rst) 200{ 201 CPSR cpsr = 0; 202 cpsr.mode = MODE_USER; 203 204 miscRegs[MISCREG_CPSR] = cpsr; 205 updateRegMap(cpsr); 206 207 SCTLR sctlr = 0; 208 sctlr.te = (bool) sctlr_rst.te; 209 sctlr.nmfi = (bool) sctlr_rst.nmfi; 210 sctlr.v = (bool) sctlr_rst.v; 211 sctlr.u = 1; 212 sctlr.xp = 1; 213 sctlr.rao2 = 1; 214 sctlr.rao3 = 1; 215 sctlr.rao4 = 0xf; // SCTLR[6:3] 216 sctlr.uci = 1; 217 sctlr.dze = 1; 218 miscRegs[MISCREG_SCTLR_NS] = sctlr; 219 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 220 miscRegs[MISCREG_HCPTR] = 0; 221 222 miscRegs[MISCREG_CPACR] = 0; 223 224 miscRegs[MISCREG_FPSID] = p->fpsid; 225 226 if (haveLPAE) { 227 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 228 ttbcr.eae = 0; 229 miscRegs[MISCREG_TTBCR_NS] = ttbcr; 230 // Enforce consistency with system-level settings 231 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 232 } 233 234 if (haveSecurity) { 235 miscRegs[MISCREG_SCTLR_S] = sctlr; 236 miscRegs[MISCREG_SCR] = 0; 237 miscRegs[MISCREG_VBAR_S] = 0; 238 } else { 239 // we're always non-secure 240 miscRegs[MISCREG_SCR] = 1; 241 } 242 243 //XXX We need to initialize the rest of the state. 244} 245 246void 247ISA::clear64(const ArmISAParams *p) 248{ 249 CPSR cpsr = 0; 250 Addr rvbar = system->resetAddr64(); 251 switch (system->highestEL()) { 252 // Set initial EL to highest implemented EL using associated stack 253 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 254 // value 255 case EL3: 256 cpsr.mode = MODE_EL3H; 257 miscRegs[MISCREG_RVBAR_EL3] = rvbar; 258 break; 259 case EL2: 260 cpsr.mode = MODE_EL2H; 261 miscRegs[MISCREG_RVBAR_EL2] = rvbar; 262 break; 263 case EL1: 264 cpsr.mode = MODE_EL1H; 265 miscRegs[MISCREG_RVBAR_EL1] = rvbar; 266 break; 267 default: 268 panic("Invalid highest implemented exception level"); 269 break; 270 } 271 272 // Initialize rest of CPSR 273 cpsr.daif = 0xf; // Mask all interrupts 274 cpsr.ss = 0; 275 cpsr.il = 0; 276 miscRegs[MISCREG_CPSR] = cpsr; 277 updateRegMap(cpsr); 278 279 // Initialize other control registers 280 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 281 if (haveSecurity) { 282 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830; 283 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 284 } else if (haveVirtualization) { 285 // also MISCREG_SCTLR_EL2 (by mapping) 286 miscRegs[MISCREG_HSCTLR] = 0x30c50830; 287 } else { 288 // also MISCREG_SCTLR_EL1 (by mapping) 289 miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init 290 // Always non-secure 291 miscRegs[MISCREG_SCR_EL3] = 1; 292 } 293} 294 295void 296ISA::initID32(const ArmISAParams *p) 297{ 298 // Initialize configurable default values 299 miscRegs[MISCREG_MIDR] = p->midr; 300 miscRegs[MISCREG_MIDR_EL1] = p->midr; 301 miscRegs[MISCREG_VPIDR] = p->midr; 302 303 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 304 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 305 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 306 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 307 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 308 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 309 310 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 311 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 312 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 313 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 314} 315 316void 317ISA::initID64(const ArmISAParams *p) 318{ 319 // Initialize configurable id registers 320 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 321 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 322 miscRegs[MISCREG_ID_AA64DFR0_EL1] = 323 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 324 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 325 326 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 327 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 328 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 329 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 330 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 331 miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p->id_aa64mmfr2_el1; 332 333 miscRegs[MISCREG_ID_DFR0_EL1] = 334 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 335 336 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 337 338 // Enforce consistency with system-level settings... 339 340 // EL3 341 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 342 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 343 haveSecurity ? 0x2 : 0x0); 344 // EL2 345 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 346 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 347 haveVirtualization ? 0x2 : 0x0); 348 // Large ASID support 349 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 350 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 351 haveLargeAsid64 ? 0x2 : 0x0); 352 // Physical address size 353 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 354 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 355 encodePhysAddrRange64(physAddrRange)); 356 // Crypto 357 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits( 358 miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4, 359 haveCrypto ? 0x1112 : 0x0); 360} 361 362void 363ISA::startup(ThreadContext *tc) 364{ 365 pmu->setThreadContext(tc); 366 367} 368 369 370MiscReg 371ISA::readMiscRegNoEffect(int misc_reg) const 372{ 373 assert(misc_reg < NumMiscRegs); 374 375 const auto ® = lookUpMiscReg[misc_reg]; // bit masks 376 const auto &map = getMiscIndices(misc_reg); 377 int lower = map.first, upper = map.second; 378 // NB!: apply architectural masks according to desired register, 379 // despite possibly getting value from different (mapped) register. 380 auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32)) 381 |(miscRegs[upper] << 32)); 382 if (val & reg.res0()) { 383 DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n", 384 miscRegName[misc_reg], val & reg.res0()); 385 } 386 if ((val & reg.res1()) != reg.res1()) { 387 DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n", 388 miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1()); 389 } 390 return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao 391} 392 393 394MiscReg 395ISA::readMiscReg(int misc_reg, ThreadContext *tc) 396{ 397 CPSR cpsr = 0; 398 PCState pc = 0; 399 SCR scr = 0; 400 401 if (misc_reg == MISCREG_CPSR) { 402 cpsr = miscRegs[misc_reg]; 403 pc = tc->pcState(); 404 cpsr.j = pc.jazelle() ? 1 : 0; 405 cpsr.t = pc.thumb() ? 1 : 0; 406 return cpsr; 407 } 408 409#ifndef NDEBUG 410 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 411 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 412 warn("Unimplemented system register %s read.\n", 413 miscRegName[misc_reg]); 414 else 415 panic("Unimplemented system register %s read.\n", 416 miscRegName[misc_reg]); 417 } 418#endif 419 420 switch (unflattenMiscReg(misc_reg)) { 421 case MISCREG_HCR: 422 { 423 if (!haveVirtualization) 424 return 0; 425 else 426 return readMiscRegNoEffect(MISCREG_HCR); 427 } 428 case MISCREG_CPACR: 429 { 430 const uint32_t ones = (uint32_t)(-1); 431 CPACR cpacrMask = 0; 432 // Only cp10, cp11, and ase are implemented, nothing else should 433 // be readable? (straight copy from the write code) 434 cpacrMask.cp10 = ones; 435 cpacrMask.cp11 = ones; 436 cpacrMask.asedis = ones; 437 438 // Security Extensions may limit the readability of CPACR 439 if (haveSecurity) { 440 scr = readMiscRegNoEffect(MISCREG_SCR); 441 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 442 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 443 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 444 // NB: Skipping the full loop, here 445 if (!nsacr.cp10) cpacrMask.cp10 = 0; 446 if (!nsacr.cp11) cpacrMask.cp11 = 0; 447 } 448 } 449 MiscReg val = readMiscRegNoEffect(MISCREG_CPACR); 450 val &= cpacrMask; 451 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 452 miscRegName[misc_reg], val); 453 return val; 454 } 455 case MISCREG_MPIDR: 456 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 457 scr = readMiscRegNoEffect(MISCREG_SCR); 458 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 459 return getMPIDR(system, tc); 460 } else { 461 return readMiscReg(MISCREG_VMPIDR, tc); 462 } 463 break; 464 case MISCREG_MPIDR_EL1: 465 // @todo in the absence of v8 virtualization support just return MPIDR_EL1 466 return getMPIDR(system, tc) & 0xffffffff; 467 case MISCREG_VMPIDR: 468 // top bit defined as RES1 469 return readMiscRegNoEffect(misc_reg) | 0x80000000; 470 case MISCREG_ID_AFR0: // not implemented, so alias MIDR 471 case MISCREG_REVIDR: // not implemented, so alias MIDR 472 case MISCREG_MIDR: 473 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 474 scr = readMiscRegNoEffect(MISCREG_SCR); 475 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 476 return readMiscRegNoEffect(misc_reg); 477 } else { 478 return readMiscRegNoEffect(MISCREG_VPIDR); 479 } 480 break; 481 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 482 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 483 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 484 case MISCREG_AIDR: // AUX ID set to 0 485 case MISCREG_TCMTR: // No TCM's 486 return 0; 487 488 case MISCREG_CLIDR: 489 warn_once("The clidr register always reports 0 caches.\n"); 490 warn_once("clidr LoUIS field of 0b001 to match current " 491 "ARM implementations.\n"); 492 return 0x00200000; 493 case MISCREG_CCSIDR: 494 warn_once("The ccsidr register isn't implemented and " 495 "always reads as 0.\n"); 496 break; 497 case MISCREG_CTR: // AArch32, ARMv7, top bit set 498 case MISCREG_CTR_EL0: // AArch64 499 { 500 //all caches have the same line size in gem5 501 //4 byte words in ARM 502 unsigned lineSizeWords = 503 tc->getSystemPtr()->cacheLineSize() / 4; 504 unsigned log2LineSizeWords = 0; 505 506 while (lineSizeWords >>= 1) { 507 ++log2LineSizeWords; 508 } 509 510 CTR ctr = 0; 511 //log2 of minimun i-cache line size (words) 512 ctr.iCacheLineSize = log2LineSizeWords; 513 //b11 - gem5 uses pipt 514 ctr.l1IndexPolicy = 0x3; 515 //log2 of minimum d-cache line size (words) 516 ctr.dCacheLineSize = log2LineSizeWords; 517 //log2 of max reservation size (words) 518 ctr.erg = log2LineSizeWords; 519 //log2 of max writeback size (words) 520 ctr.cwg = log2LineSizeWords; 521 //b100 - gem5 format is ARMv7 522 ctr.format = 0x4; 523 524 return ctr; 525 } 526 case MISCREG_ACTLR: 527 warn("Not doing anything for miscreg ACTLR\n"); 528 break; 529 530 case MISCREG_PMXEVTYPER_PMCCFILTR: 531 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 532 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 533 case MISCREG_PMCR ... MISCREG_PMOVSSET: 534 return pmu->readMiscReg(misc_reg); 535 536 case MISCREG_CPSR_Q: 537 panic("shouldn't be reading this register seperately\n"); 538 case MISCREG_FPSCR_QC: 539 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 540 case MISCREG_FPSCR_EXC: 541 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 542 case MISCREG_FPSR: 543 { 544 const uint32_t ones = (uint32_t)(-1); 545 FPSCR fpscrMask = 0; 546 fpscrMask.ioc = ones; 547 fpscrMask.dzc = ones; 548 fpscrMask.ofc = ones; 549 fpscrMask.ufc = ones; 550 fpscrMask.ixc = ones; 551 fpscrMask.idc = ones; 552 fpscrMask.qc = ones; 553 fpscrMask.v = ones; 554 fpscrMask.c = ones; 555 fpscrMask.z = ones; 556 fpscrMask.n = ones; 557 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 558 } 559 case MISCREG_FPCR: 560 { 561 const uint32_t ones = (uint32_t)(-1); 562 FPSCR fpscrMask = 0; 563 fpscrMask.len = ones; 564 fpscrMask.stride = ones; 565 fpscrMask.rMode = ones; 566 fpscrMask.fz = ones; 567 fpscrMask.dn = ones; 568 fpscrMask.ahp = ones; 569 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 570 } 571 case MISCREG_NZCV: 572 { 573 CPSR cpsr = 0; 574 cpsr.nz = tc->readCCReg(CCREG_NZ); 575 cpsr.c = tc->readCCReg(CCREG_C); 576 cpsr.v = tc->readCCReg(CCREG_V); 577 return cpsr; 578 } 579 case MISCREG_DAIF: 580 { 581 CPSR cpsr = 0; 582 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 583 return cpsr; 584 } 585 case MISCREG_SP_EL0: 586 { 587 return tc->readIntReg(INTREG_SP0); 588 } 589 case MISCREG_SP_EL1: 590 { 591 return tc->readIntReg(INTREG_SP1); 592 } 593 case MISCREG_SP_EL2: 594 { 595 return tc->readIntReg(INTREG_SP2); 596 } 597 case MISCREG_SPSEL: 598 { 599 return miscRegs[MISCREG_CPSR] & 0x1; 600 } 601 case MISCREG_CURRENTEL: 602 { 603 return miscRegs[MISCREG_CPSR] & 0xc; 604 } 605 case MISCREG_L2CTLR: 606 { 607 // mostly unimplemented, just set NumCPUs field from sim and return 608 L2CTLR l2ctlr = 0; 609 // b00:1CPU to b11:4CPUs 610 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 611 return l2ctlr; 612 } 613 case MISCREG_DBGDIDR: 614 /* For now just implement the version number. 615 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 616 */ 617 return 0x5 << 16; 618 case MISCREG_DBGDSCRint: 619 return 0; 620 case MISCREG_ISR: 621 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 622 readMiscRegNoEffect(MISCREG_HCR), 623 readMiscRegNoEffect(MISCREG_CPSR), 624 readMiscRegNoEffect(MISCREG_SCR)); 625 case MISCREG_ISR_EL1: 626 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 627 readMiscRegNoEffect(MISCREG_HCR_EL2), 628 readMiscRegNoEffect(MISCREG_CPSR), 629 readMiscRegNoEffect(MISCREG_SCR_EL3)); 630 case MISCREG_DCZID_EL0: 631 return 0x04; // DC ZVA clear 64-byte chunks 632 case MISCREG_HCPTR: 633 { 634 MiscReg val = readMiscRegNoEffect(misc_reg); 635 // The trap bit associated with CP14 is defined as RAZ 636 val &= ~(1 << 14); 637 // If a CP bit in NSACR is 0 then the corresponding bit in 638 // HCPTR is RAO/WI 639 bool secure_lookup = haveSecurity && 640 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 641 readMiscRegNoEffect(MISCREG_CPSR)); 642 if (!secure_lookup) { 643 MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR); 644 val |= (mask ^ 0x7FFF) & 0xBFFF; 645 } 646 // Set the bits for unimplemented coprocessors to RAO/WI 647 val |= 0x33FF; 648 return (val); 649 } 650 case MISCREG_HDFAR: // alias for secure DFAR 651 return readMiscRegNoEffect(MISCREG_DFAR_S); 652 case MISCREG_HIFAR: // alias for secure IFAR 653 return readMiscRegNoEffect(MISCREG_IFAR_S); 654 case MISCREG_HVBAR: // bottom bits reserved 655 return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0; 656 case MISCREG_SCTLR: 657 return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818; 658 case MISCREG_SCTLR_EL1: 659 return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800; 660 case MISCREG_SCTLR_EL2: 661 case MISCREG_SCTLR_EL3: 662 case MISCREG_HSCTLR: 663 return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; 664 665 case MISCREG_ID_PFR0: 666 // !ThumbEE | !Jazelle | Thumb | ARM 667 return 0x00000031; 668 case MISCREG_ID_PFR1: 669 { // Timer | Virti | !M Profile | TrustZone | ARMv4 670 bool haveTimer = (system->getGenericTimer() != NULL); 671 return 0x00000001 672 | (haveSecurity ? 0x00000010 : 0x0) 673 | (haveVirtualization ? 0x00001000 : 0x0) 674 | (haveTimer ? 0x00010000 : 0x0); 675 } 676 case MISCREG_ID_AA64PFR0_EL1: 677 return 0x0000000000000002 // AArch{64,32} supported at EL0 678 | 0x0000000000000020 // EL1 679 | (haveVirtualization ? 0x0000000000000200 : 0) // EL2 680 | (haveSecurity ? 0x0000000000002000 : 0); // EL3 681 case MISCREG_ID_AA64PFR1_EL1: 682 return 0; // bits [63:0] RES0 (reserved for future use) 683 684 // Generic Timer registers 685 case MISCREG_CNTHV_CTL_EL2: 686 case MISCREG_CNTHV_CVAL_EL2: 687 case MISCREG_CNTHV_TVAL_EL2: 688 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 689 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 690 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 691 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 692 return getGenericTimer(tc).readMiscReg(misc_reg); 693 694 default: 695 break; 696 697 } 698 return readMiscRegNoEffect(misc_reg); 699} 700 701void 702ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 703{ 704 assert(misc_reg < NumMiscRegs); 705 706 const auto ® = lookUpMiscReg[misc_reg]; // bit masks 707 const auto &map = getMiscIndices(misc_reg); 708 int lower = map.first, upper = map.second; 709 710 auto v = (val & ~reg.wi()) | reg.rao(); 711 if (upper > 0) { 712 miscRegs[lower] = bits(v, 31, 0); 713 miscRegs[upper] = bits(v, 63, 32); 714 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 715 misc_reg, lower, upper, v); 716 } else { 717 miscRegs[lower] = v; 718 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 719 misc_reg, lower, v); 720 } 721} 722 723void 724ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 725{ 726 727 MiscReg newVal = val; 728 bool secure_lookup; 729 SCR scr; 730 731 if (misc_reg == MISCREG_CPSR) { 732 updateRegMap(val); 733 734 735 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 736 int old_mode = old_cpsr.mode; 737 CPSR cpsr = val; 738 if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) { 739 getITBPtr(tc)->invalidateMiscReg(); 740 getDTBPtr(tc)->invalidateMiscReg(); 741 } 742 743 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 744 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 745 PCState pc = tc->pcState(); 746 pc.nextThumb(cpsr.t); 747 pc.nextJazelle(cpsr.j); 748 pc.illegalExec(cpsr.il == 1); 749 750 // Follow slightly different semantics if a CheckerCPU object 751 // is connected 752 CheckerCPU *checker = tc->getCheckerCpuPtr(); 753 if (checker) { 754 tc->pcStateNoRecord(pc); 755 } else { 756 tc->pcState(pc); 757 } 758 } else { 759#ifndef NDEBUG 760 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 761 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 762 warn("Unimplemented system register %s write with %#x.\n", 763 miscRegName[misc_reg], val); 764 else 765 panic("Unimplemented system register %s write with %#x.\n", 766 miscRegName[misc_reg], val); 767 } 768#endif 769 switch (unflattenMiscReg(misc_reg)) { 770 case MISCREG_CPACR: 771 { 772 773 const uint32_t ones = (uint32_t)(-1); 774 CPACR cpacrMask = 0; 775 // Only cp10, cp11, and ase are implemented, nothing else should 776 // be writable 777 cpacrMask.cp10 = ones; 778 cpacrMask.cp11 = ones; 779 cpacrMask.asedis = ones; 780 781 // Security Extensions may limit the writability of CPACR 782 if (haveSecurity) { 783 scr = readMiscRegNoEffect(MISCREG_SCR); 784 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 785 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 786 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 787 // NB: Skipping the full loop, here 788 if (!nsacr.cp10) cpacrMask.cp10 = 0; 789 if (!nsacr.cp11) cpacrMask.cp11 = 0; 790 } 791 } 792 793 MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR); 794 newVal &= cpacrMask; 795 newVal |= old_val & ~cpacrMask; 796 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 797 miscRegName[misc_reg], newVal); 798 } 799 break; 800 case MISCREG_CPTR_EL2: 801 { 802 const uint32_t ones = (uint32_t)(-1); 803 CPTR cptrMask = 0; 804 cptrMask.tcpac = ones; 805 cptrMask.tta = ones; 806 cptrMask.tfp = ones; 807 newVal &= cptrMask; 808 cptrMask = 0; 809 cptrMask.res1_13_12_el2 = ones; 810 cptrMask.res1_9_0_el2 = ones; 811 newVal |= cptrMask; 812 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 813 miscRegName[misc_reg], newVal); 814 } 815 break; 816 case MISCREG_CPTR_EL3: 817 { 818 const uint32_t ones = (uint32_t)(-1); 819 CPTR cptrMask = 0; 820 cptrMask.tcpac = ones; 821 cptrMask.tta = ones; 822 cptrMask.tfp = ones; 823 newVal &= cptrMask; 824 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 825 miscRegName[misc_reg], newVal); 826 } 827 break; 828 case MISCREG_CSSELR: 829 warn_once("The csselr register isn't implemented.\n"); 830 return; 831 832 case MISCREG_DC_ZVA_Xt: 833 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 834 return; 835 836 case MISCREG_FPSCR: 837 { 838 const uint32_t ones = (uint32_t)(-1); 839 FPSCR fpscrMask = 0; 840 fpscrMask.ioc = ones; 841 fpscrMask.dzc = ones; 842 fpscrMask.ofc = ones; 843 fpscrMask.ufc = ones; 844 fpscrMask.ixc = ones; 845 fpscrMask.idc = ones; 846 fpscrMask.ioe = ones; 847 fpscrMask.dze = ones; 848 fpscrMask.ofe = ones; 849 fpscrMask.ufe = ones; 850 fpscrMask.ixe = ones; 851 fpscrMask.ide = ones; 852 fpscrMask.len = ones; 853 fpscrMask.stride = ones; 854 fpscrMask.rMode = ones; 855 fpscrMask.fz = ones; 856 fpscrMask.dn = ones; 857 fpscrMask.ahp = ones; 858 fpscrMask.qc = ones; 859 fpscrMask.v = ones; 860 fpscrMask.c = ones; 861 fpscrMask.z = ones; 862 fpscrMask.n = ones; 863 newVal = (newVal & (uint32_t)fpscrMask) | 864 (readMiscRegNoEffect(MISCREG_FPSCR) & 865 ~(uint32_t)fpscrMask); 866 tc->getDecoderPtr()->setContext(newVal); 867 } 868 break; 869 case MISCREG_FPSR: 870 { 871 const uint32_t ones = (uint32_t)(-1); 872 FPSCR fpscrMask = 0; 873 fpscrMask.ioc = ones; 874 fpscrMask.dzc = ones; 875 fpscrMask.ofc = ones; 876 fpscrMask.ufc = ones; 877 fpscrMask.ixc = ones; 878 fpscrMask.idc = ones; 879 fpscrMask.qc = ones; 880 fpscrMask.v = ones; 881 fpscrMask.c = ones; 882 fpscrMask.z = ones; 883 fpscrMask.n = ones; 884 newVal = (newVal & (uint32_t)fpscrMask) | 885 (readMiscRegNoEffect(MISCREG_FPSCR) & 886 ~(uint32_t)fpscrMask); 887 misc_reg = MISCREG_FPSCR; 888 } 889 break; 890 case MISCREG_FPCR: 891 { 892 const uint32_t ones = (uint32_t)(-1); 893 FPSCR fpscrMask = 0; 894 fpscrMask.len = ones; 895 fpscrMask.stride = ones; 896 fpscrMask.rMode = ones; 897 fpscrMask.fz = ones; 898 fpscrMask.dn = ones; 899 fpscrMask.ahp = ones; 900 newVal = (newVal & (uint32_t)fpscrMask) | 901 (readMiscRegNoEffect(MISCREG_FPSCR) & 902 ~(uint32_t)fpscrMask); 903 misc_reg = MISCREG_FPSCR; 904 } 905 break; 906 case MISCREG_CPSR_Q: 907 { 908 assert(!(newVal & ~CpsrMaskQ)); 909 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 910 misc_reg = MISCREG_CPSR; 911 } 912 break; 913 case MISCREG_FPSCR_QC: 914 { 915 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 916 (newVal & FpscrQcMask); 917 misc_reg = MISCREG_FPSCR; 918 } 919 break; 920 case MISCREG_FPSCR_EXC: 921 { 922 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 923 (newVal & FpscrExcMask); 924 misc_reg = MISCREG_FPSCR; 925 } 926 break; 927 case MISCREG_FPEXC: 928 { 929 // vfpv3 architecture, section B.6.1 of DDI04068 930 // bit 29 - valid only if fpexc[31] is 0 931 const uint32_t fpexcMask = 0x60000000; 932 newVal = (newVal & fpexcMask) | 933 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 934 } 935 break; 936 case MISCREG_HCR: 937 { 938 if (!haveVirtualization) 939 return; 940 } 941 break; 942 case MISCREG_IFSR: 943 { 944 // ARM ARM (ARM DDI 0406C.b) B4.1.96 945 const uint32_t ifsrMask = 946 mask(31, 13) | mask(11, 11) | mask(8, 6); 947 newVal = newVal & ~ifsrMask; 948 } 949 break; 950 case MISCREG_DFSR: 951 { 952 // ARM ARM (ARM DDI 0406C.b) B4.1.52 953 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 954 newVal = newVal & ~dfsrMask; 955 } 956 break; 957 case MISCREG_AMAIR0: 958 case MISCREG_AMAIR1: 959 { 960 // ARM ARM (ARM DDI 0406C.b) B4.1.5 961 // Valid only with LPAE 962 if (!haveLPAE) 963 return; 964 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 965 } 966 break; 967 case MISCREG_SCR: 968 getITBPtr(tc)->invalidateMiscReg(); 969 getDTBPtr(tc)->invalidateMiscReg(); 970 break; 971 case MISCREG_SCTLR: 972 { 973 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 974 scr = readMiscRegNoEffect(MISCREG_SCR); 975 976 MiscRegIndex sctlr_idx; 977 if (haveSecurity && !highestELIs64 && !scr.ns) { 978 sctlr_idx = MISCREG_SCTLR_S; 979 } else { 980 sctlr_idx = MISCREG_SCTLR_NS; 981 } 982 983 SCTLR sctlr = miscRegs[sctlr_idx]; 984 SCTLR new_sctlr = newVal; 985 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 986 miscRegs[sctlr_idx] = (MiscReg)new_sctlr; 987 getITBPtr(tc)->invalidateMiscReg(); 988 getDTBPtr(tc)->invalidateMiscReg(); 989 } 990 case MISCREG_MIDR: 991 case MISCREG_ID_PFR0: 992 case MISCREG_ID_PFR1: 993 case MISCREG_ID_DFR0: 994 case MISCREG_ID_MMFR0: 995 case MISCREG_ID_MMFR1: 996 case MISCREG_ID_MMFR2: 997 case MISCREG_ID_MMFR3: 998 case MISCREG_ID_ISAR0: 999 case MISCREG_ID_ISAR1: 1000 case MISCREG_ID_ISAR2: 1001 case MISCREG_ID_ISAR3: 1002 case MISCREG_ID_ISAR4: 1003 case MISCREG_ID_ISAR5: 1004 1005 case MISCREG_MPIDR: 1006 case MISCREG_FPSID: 1007 case MISCREG_TLBTR: 1008 case MISCREG_MVFR0: 1009 case MISCREG_MVFR1: 1010 1011 case MISCREG_ID_AA64AFR0_EL1: 1012 case MISCREG_ID_AA64AFR1_EL1: 1013 case MISCREG_ID_AA64DFR0_EL1: 1014 case MISCREG_ID_AA64DFR1_EL1: 1015 case MISCREG_ID_AA64ISAR0_EL1: 1016 case MISCREG_ID_AA64ISAR1_EL1: 1017 case MISCREG_ID_AA64MMFR0_EL1: 1018 case MISCREG_ID_AA64MMFR1_EL1: 1019 case MISCREG_ID_AA64MMFR2_EL1: 1020 case MISCREG_ID_AA64PFR0_EL1: 1021 case MISCREG_ID_AA64PFR1_EL1: 1022 // ID registers are constants. 1023 return; 1024 1025 // TLB Invalidate All 1026 case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 1027 { 1028 assert32(tc); 1029 scr = readMiscReg(MISCREG_SCR, tc); 1030 1031 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1032 tlbiOp(tc); 1033 return; 1034 } 1035 // TLB Invalidate All, Inner Shareable 1036 case MISCREG_TLBIALLIS: 1037 { 1038 assert32(tc); 1039 scr = readMiscReg(MISCREG_SCR, tc); 1040 1041 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1042 tlbiOp.broadcast(tc); 1043 return; 1044 } 1045 // Instruction TLB Invalidate All 1046 case MISCREG_ITLBIALL: 1047 { 1048 assert32(tc); 1049 scr = readMiscReg(MISCREG_SCR, tc); 1050 1051 ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1052 tlbiOp(tc); 1053 return; 1054 } 1055 // Data TLB Invalidate All 1056 case MISCREG_DTLBIALL: 1057 { 1058 assert32(tc); 1059 scr = readMiscReg(MISCREG_SCR, tc); 1060 1061 DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1062 tlbiOp(tc); 1063 return; 1064 } 1065 // TLB Invalidate by VA 1066 // mcr tlbimval(is) is invalidating all matching entries 1067 // regardless of the level of lookup, since in gem5 we cache 1068 // in the tlb the last level of lookup only. 1069 case MISCREG_TLBIMVA: 1070 case MISCREG_TLBIMVAL: 1071 { 1072 assert32(tc); 1073 scr = readMiscReg(MISCREG_SCR, tc); 1074 1075 TLBIMVA tlbiOp(EL1, 1076 haveSecurity && !scr.ns, 1077 mbits(newVal, 31, 12), 1078 bits(newVal, 7,0)); 1079 1080 tlbiOp(tc); 1081 return; 1082 } 1083 // TLB Invalidate by VA, Inner Shareable 1084 case MISCREG_TLBIMVAIS: 1085 case MISCREG_TLBIMVALIS: 1086 { 1087 assert32(tc); 1088 scr = readMiscReg(MISCREG_SCR, tc); 1089 1090 TLBIMVA tlbiOp(EL1, 1091 haveSecurity && !scr.ns, 1092 mbits(newVal, 31, 12), 1093 bits(newVal, 7,0)); 1094 1095 tlbiOp.broadcast(tc); 1096 return; 1097 } 1098 // TLB Invalidate by ASID match 1099 case MISCREG_TLBIASID: 1100 { 1101 assert32(tc); 1102 scr = readMiscReg(MISCREG_SCR, tc); 1103 1104 TLBIASID tlbiOp(EL1, 1105 haveSecurity && !scr.ns, 1106 bits(newVal, 7,0)); 1107 1108 tlbiOp(tc); 1109 return; 1110 } 1111 // TLB Invalidate by ASID match, Inner Shareable 1112 case MISCREG_TLBIASIDIS: 1113 { 1114 assert32(tc); 1115 scr = readMiscReg(MISCREG_SCR, tc); 1116 1117 TLBIASID tlbiOp(EL1, 1118 haveSecurity && !scr.ns, 1119 bits(newVal, 7,0)); 1120 1121 tlbiOp.broadcast(tc); 1122 return; 1123 } 1124 // mcr tlbimvaal(is) is invalidating all matching entries 1125 // regardless of the level of lookup, since in gem5 we cache 1126 // in the tlb the last level of lookup only. 1127 // TLB Invalidate by VA, All ASID 1128 case MISCREG_TLBIMVAA: 1129 case MISCREG_TLBIMVAAL: 1130 { 1131 assert32(tc); 1132 scr = readMiscReg(MISCREG_SCR, tc); 1133 1134 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1135 mbits(newVal, 31,12), false); 1136 1137 tlbiOp(tc); 1138 return; 1139 } 1140 // TLB Invalidate by VA, All ASID, Inner Shareable 1141 case MISCREG_TLBIMVAAIS: 1142 case MISCREG_TLBIMVAALIS: 1143 { 1144 assert32(tc); 1145 scr = readMiscReg(MISCREG_SCR, tc); 1146 1147 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1148 mbits(newVal, 31,12), false); 1149 1150 tlbiOp.broadcast(tc); 1151 return; 1152 } 1153 // mcr tlbimvalh(is) is invalidating all matching entries 1154 // regardless of the level of lookup, since in gem5 we cache 1155 // in the tlb the last level of lookup only. 1156 // TLB Invalidate by VA, Hyp mode 1157 case MISCREG_TLBIMVAH: 1158 case MISCREG_TLBIMVALH: 1159 { 1160 assert32(tc); 1161 scr = readMiscReg(MISCREG_SCR, tc); 1162 1163 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1164 mbits(newVal, 31,12), true); 1165 1166 tlbiOp(tc); 1167 return; 1168 } 1169 // TLB Invalidate by VA, Hyp mode, Inner Shareable 1170 case MISCREG_TLBIMVAHIS: 1171 case MISCREG_TLBIMVALHIS: 1172 { 1173 assert32(tc); 1174 scr = readMiscReg(MISCREG_SCR, tc); 1175 1176 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1177 mbits(newVal, 31,12), true); 1178 1179 tlbiOp.broadcast(tc); 1180 return; 1181 } 1182 // mcr tlbiipas2l(is) is invalidating all matching entries 1183 // regardless of the level of lookup, since in gem5 we cache 1184 // in the tlb the last level of lookup only. 1185 // TLB Invalidate by Intermediate Physical Address, Stage 2 1186 case MISCREG_TLBIIPAS2: 1187 case MISCREG_TLBIIPAS2L: 1188 { 1189 assert32(tc); 1190 scr = readMiscReg(MISCREG_SCR, tc); 1191 1192 TLBIIPA tlbiOp(EL1, 1193 haveSecurity && !scr.ns, 1194 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1195 1196 tlbiOp(tc); 1197 return; 1198 } 1199 // TLB Invalidate by Intermediate Physical Address, Stage 2, 1200 // Inner Shareable 1201 case MISCREG_TLBIIPAS2IS: 1202 case MISCREG_TLBIIPAS2LIS: 1203 { 1204 assert32(tc); 1205 scr = readMiscReg(MISCREG_SCR, tc); 1206 1207 TLBIIPA tlbiOp(EL1, 1208 haveSecurity && !scr.ns, 1209 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1210 1211 tlbiOp.broadcast(tc); 1212 return; 1213 } 1214 // Instruction TLB Invalidate by VA 1215 case MISCREG_ITLBIMVA: 1216 { 1217 assert32(tc); 1218 scr = readMiscReg(MISCREG_SCR, tc); 1219 1220 ITLBIMVA tlbiOp(EL1, 1221 haveSecurity && !scr.ns, 1222 mbits(newVal, 31, 12), 1223 bits(newVal, 7,0)); 1224 1225 tlbiOp(tc); 1226 return; 1227 } 1228 // Data TLB Invalidate by VA 1229 case MISCREG_DTLBIMVA: 1230 { 1231 assert32(tc); 1232 scr = readMiscReg(MISCREG_SCR, tc); 1233 1234 DTLBIMVA tlbiOp(EL1, 1235 haveSecurity && !scr.ns, 1236 mbits(newVal, 31, 12), 1237 bits(newVal, 7,0)); 1238 1239 tlbiOp(tc); 1240 return; 1241 } 1242 // Instruction TLB Invalidate by ASID match 1243 case MISCREG_ITLBIASID: 1244 { 1245 assert32(tc); 1246 scr = readMiscReg(MISCREG_SCR, tc); 1247 1248 ITLBIASID tlbiOp(EL1, 1249 haveSecurity && !scr.ns, 1250 bits(newVal, 7,0)); 1251 1252 tlbiOp(tc); 1253 return; 1254 } 1255 // Data TLB Invalidate by ASID match 1256 case MISCREG_DTLBIASID: 1257 { 1258 assert32(tc); 1259 scr = readMiscReg(MISCREG_SCR, tc); 1260 1261 DTLBIASID tlbiOp(EL1, 1262 haveSecurity && !scr.ns, 1263 bits(newVal, 7,0)); 1264 1265 tlbiOp(tc); 1266 return; 1267 } 1268 // TLB Invalidate All, Non-Secure Non-Hyp 1269 case MISCREG_TLBIALLNSNH: 1270 { 1271 assert32(tc); 1272 1273 TLBIALLN tlbiOp(EL1, false); 1274 tlbiOp(tc); 1275 return; 1276 } 1277 // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable 1278 case MISCREG_TLBIALLNSNHIS: 1279 { 1280 assert32(tc); 1281 1282 TLBIALLN tlbiOp(EL1, false); 1283 tlbiOp.broadcast(tc); 1284 return; 1285 } 1286 // TLB Invalidate All, Hyp mode 1287 case MISCREG_TLBIALLH: 1288 { 1289 assert32(tc); 1290 1291 TLBIALLN tlbiOp(EL1, true); 1292 tlbiOp(tc); 1293 return; 1294 } 1295 // TLB Invalidate All, Hyp mode, Inner Shareable 1296 case MISCREG_TLBIALLHIS: 1297 { 1298 assert32(tc); 1299 1300 TLBIALLN tlbiOp(EL1, true); 1301 tlbiOp.broadcast(tc); 1302 return; 1303 } 1304 // AArch64 TLB Invalidate All, EL3 1305 case MISCREG_TLBI_ALLE3: 1306 { 1307 assert64(tc); 1308 1309 TLBIALL tlbiOp(EL3, true); 1310 tlbiOp(tc); 1311 return; 1312 } 1313 // AArch64 TLB Invalidate All, EL3, Inner Shareable 1314 case MISCREG_TLBI_ALLE3IS: 1315 { 1316 assert64(tc); 1317 1318 TLBIALL tlbiOp(EL3, true); 1319 tlbiOp.broadcast(tc); 1320 return; 1321 } 1322 // @todo: uncomment this to enable Virtualization 1323 // case MISCREG_TLBI_ALLE2IS: 1324 // case MISCREG_TLBI_ALLE2: 1325 // AArch64 TLB Invalidate All, EL1 1326 case MISCREG_TLBI_ALLE1: 1327 case MISCREG_TLBI_VMALLE1: 1328 case MISCREG_TLBI_VMALLS12E1: 1329 // @todo: handle VMID and stage 2 to enable Virtualization 1330 { 1331 assert64(tc); 1332 scr = readMiscReg(MISCREG_SCR, tc); 1333 1334 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1335 tlbiOp(tc); 1336 return; 1337 } 1338 // AArch64 TLB Invalidate All, EL1, Inner Shareable 1339 case MISCREG_TLBI_ALLE1IS: 1340 case MISCREG_TLBI_VMALLE1IS: 1341 case MISCREG_TLBI_VMALLS12E1IS: 1342 // @todo: handle VMID and stage 2 to enable Virtualization 1343 { 1344 assert64(tc); 1345 scr = readMiscReg(MISCREG_SCR, tc); 1346 1347 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1348 tlbiOp.broadcast(tc); 1349 return; 1350 } 1351 // VAEx(IS) and VALEx(IS) are the same because TLBs 1352 // only store entries 1353 // from the last level of translation table walks 1354 // @todo: handle VMID to enable Virtualization 1355 // AArch64 TLB Invalidate by VA, EL3 1356 case MISCREG_TLBI_VAE3_Xt: 1357 case MISCREG_TLBI_VALE3_Xt: 1358 { 1359 assert64(tc); 1360 1361 TLBIMVA tlbiOp(EL3, true, 1362 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1363 0xbeef); 1364 tlbiOp(tc); 1365 return; 1366 } 1367 // AArch64 TLB Invalidate by VA, EL3, Inner Shareable 1368 case MISCREG_TLBI_VAE3IS_Xt: 1369 case MISCREG_TLBI_VALE3IS_Xt: 1370 { 1371 assert64(tc); 1372 1373 TLBIMVA tlbiOp(EL3, true, 1374 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1375 0xbeef); 1376 1377 tlbiOp.broadcast(tc); 1378 return; 1379 } 1380 // AArch64 TLB Invalidate by VA, EL2 1381 case MISCREG_TLBI_VAE2_Xt: 1382 case MISCREG_TLBI_VALE2_Xt: 1383 { 1384 assert64(tc); 1385 scr = readMiscReg(MISCREG_SCR, tc); 1386 1387 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1388 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1389 0xbeef); 1390 tlbiOp(tc); 1391 return; 1392 } 1393 // AArch64 TLB Invalidate by VA, EL2, Inner Shareable 1394 case MISCREG_TLBI_VAE2IS_Xt: 1395 case MISCREG_TLBI_VALE2IS_Xt: 1396 { 1397 assert64(tc); 1398 scr = readMiscReg(MISCREG_SCR, tc); 1399 1400 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1401 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1402 0xbeef); 1403 1404 tlbiOp.broadcast(tc); 1405 return; 1406 } 1407 // AArch64 TLB Invalidate by VA, EL1 1408 case MISCREG_TLBI_VAE1_Xt: 1409 case MISCREG_TLBI_VALE1_Xt: 1410 { 1411 assert64(tc); 1412 scr = readMiscReg(MISCREG_SCR, tc); 1413 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1414 bits(newVal, 55, 48); 1415 1416 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1417 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1418 asid); 1419 1420 tlbiOp(tc); 1421 return; 1422 } 1423 // AArch64 TLB Invalidate by VA, EL1, Inner Shareable 1424 case MISCREG_TLBI_VAE1IS_Xt: 1425 case MISCREG_TLBI_VALE1IS_Xt: 1426 { 1427 assert64(tc); 1428 scr = readMiscReg(MISCREG_SCR, tc); 1429 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1430 bits(newVal, 55, 48); 1431 1432 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1433 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1434 asid); 1435 1436 tlbiOp.broadcast(tc); 1437 return; 1438 } 1439 // AArch64 TLB Invalidate by ASID, EL1 1440 // @todo: handle VMID to enable Virtualization 1441 case MISCREG_TLBI_ASIDE1_Xt: 1442 { 1443 assert64(tc); 1444 scr = readMiscReg(MISCREG_SCR, tc); 1445 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1446 bits(newVal, 55, 48); 1447 1448 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1449 tlbiOp(tc); 1450 return; 1451 } 1452 // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable 1453 case MISCREG_TLBI_ASIDE1IS_Xt: 1454 { 1455 assert64(tc); 1456 scr = readMiscReg(MISCREG_SCR, tc); 1457 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1458 bits(newVal, 55, 48); 1459 1460 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1461 tlbiOp.broadcast(tc); 1462 return; 1463 } 1464 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 1465 // entries from the last level of translation table walks 1466 // AArch64 TLB Invalidate by VA, All ASID, EL1 1467 case MISCREG_TLBI_VAAE1_Xt: 1468 case MISCREG_TLBI_VAALE1_Xt: 1469 { 1470 assert64(tc); 1471 scr = readMiscReg(MISCREG_SCR, tc); 1472 1473 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1474 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 1475 1476 tlbiOp(tc); 1477 return; 1478 } 1479 // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable 1480 case MISCREG_TLBI_VAAE1IS_Xt: 1481 case MISCREG_TLBI_VAALE1IS_Xt: 1482 { 1483 assert64(tc); 1484 scr = readMiscReg(MISCREG_SCR, tc); 1485 1486 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1487 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 1488 1489 tlbiOp.broadcast(tc); 1490 return; 1491 } 1492 // AArch64 TLB Invalidate by Intermediate Physical Address, 1493 // Stage 2, EL1 1494 case MISCREG_TLBI_IPAS2E1_Xt: 1495 case MISCREG_TLBI_IPAS2LE1_Xt: 1496 { 1497 assert64(tc); 1498 scr = readMiscReg(MISCREG_SCR, tc); 1499 1500 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1501 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1502 1503 tlbiOp(tc); 1504 return; 1505 } 1506 // AArch64 TLB Invalidate by Intermediate Physical Address, 1507 // Stage 2, EL1, Inner Shareable 1508 case MISCREG_TLBI_IPAS2E1IS_Xt: 1509 case MISCREG_TLBI_IPAS2LE1IS_Xt: 1510 { 1511 assert64(tc); 1512 scr = readMiscReg(MISCREG_SCR, tc); 1513 1514 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1515 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1516 1517 tlbiOp.broadcast(tc); 1518 return; 1519 } 1520 case MISCREG_ACTLR: 1521 warn("Not doing anything for write of miscreg ACTLR\n"); 1522 break; 1523 1524 case MISCREG_PMXEVTYPER_PMCCFILTR: 1525 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 1526 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 1527 case MISCREG_PMCR ... MISCREG_PMOVSSET: 1528 pmu->setMiscReg(misc_reg, newVal); 1529 break; 1530 1531 1532 case MISCREG_HSTR: // TJDBX, now redifined to be RES0 1533 { 1534 HSTR hstrMask = 0; 1535 hstrMask.tjdbx = 1; 1536 newVal &= ~((uint32_t) hstrMask); 1537 break; 1538 } 1539 case MISCREG_HCPTR: 1540 { 1541 // If a CP bit in NSACR is 0 then the corresponding bit in 1542 // HCPTR is RAO/WI. Same applies to NSASEDIS 1543 secure_lookup = haveSecurity && 1544 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 1545 readMiscRegNoEffect(MISCREG_CPSR)); 1546 if (!secure_lookup) { 1547 MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 1548 MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 1549 newVal = (newVal & ~mask) | (oldValue & mask); 1550 } 1551 break; 1552 } 1553 case MISCREG_HDFAR: // alias for secure DFAR 1554 misc_reg = MISCREG_DFAR_S; 1555 break; 1556 case MISCREG_HIFAR: // alias for secure IFAR 1557 misc_reg = MISCREG_IFAR_S; 1558 break; 1559 case MISCREG_ATS1CPR: 1560 case MISCREG_ATS1CPW: 1561 case MISCREG_ATS1CUR: 1562 case MISCREG_ATS1CUW: 1563 case MISCREG_ATS12NSOPR: 1564 case MISCREG_ATS12NSOPW: 1565 case MISCREG_ATS12NSOUR: 1566 case MISCREG_ATS12NSOUW: 1567 case MISCREG_ATS1HR: 1568 case MISCREG_ATS1HW: 1569 { 1570 Request::Flags flags = 0; 1571 BaseTLB::Mode mode = BaseTLB::Read; 1572 TLB::ArmTranslationType tranType = TLB::NormalTran; 1573 Fault fault; 1574 switch(misc_reg) { 1575 case MISCREG_ATS1CPR: 1576 flags = TLB::MustBeOne; 1577 tranType = TLB::S1CTran; 1578 mode = BaseTLB::Read; 1579 break; 1580 case MISCREG_ATS1CPW: 1581 flags = TLB::MustBeOne; 1582 tranType = TLB::S1CTran; 1583 mode = BaseTLB::Write; 1584 break; 1585 case MISCREG_ATS1CUR: 1586 flags = TLB::MustBeOne | TLB::UserMode; 1587 tranType = TLB::S1CTran; 1588 mode = BaseTLB::Read; 1589 break; 1590 case MISCREG_ATS1CUW: 1591 flags = TLB::MustBeOne | TLB::UserMode; 1592 tranType = TLB::S1CTran; 1593 mode = BaseTLB::Write; 1594 break; 1595 case MISCREG_ATS12NSOPR: 1596 if (!haveSecurity) 1597 panic("Security Extensions required for ATS12NSOPR"); 1598 flags = TLB::MustBeOne; 1599 tranType = TLB::S1S2NsTran; 1600 mode = BaseTLB::Read; 1601 break; 1602 case MISCREG_ATS12NSOPW: 1603 if (!haveSecurity) 1604 panic("Security Extensions required for ATS12NSOPW"); 1605 flags = TLB::MustBeOne; 1606 tranType = TLB::S1S2NsTran; 1607 mode = BaseTLB::Write; 1608 break; 1609 case MISCREG_ATS12NSOUR: 1610 if (!haveSecurity) 1611 panic("Security Extensions required for ATS12NSOUR"); 1612 flags = TLB::MustBeOne | TLB::UserMode; 1613 tranType = TLB::S1S2NsTran; 1614 mode = BaseTLB::Read; 1615 break; 1616 case MISCREG_ATS12NSOUW: 1617 if (!haveSecurity) 1618 panic("Security Extensions required for ATS12NSOUW"); 1619 flags = TLB::MustBeOne | TLB::UserMode; 1620 tranType = TLB::S1S2NsTran; 1621 mode = BaseTLB::Write; 1622 break; 1623 case MISCREG_ATS1HR: // only really useful from secure mode. 1624 flags = TLB::MustBeOne; 1625 tranType = TLB::HypMode; 1626 mode = BaseTLB::Read; 1627 break; 1628 case MISCREG_ATS1HW: 1629 flags = TLB::MustBeOne; 1630 tranType = TLB::HypMode; 1631 mode = BaseTLB::Write; 1632 break; 1633 } 1634 // If we're in timing mode then doing the translation in 1635 // functional mode then we're slightly distorting performance 1636 // results obtained from simulations. The translation should be 1637 // done in the same mode the core is running in. NOTE: This 1638 // can't be an atomic translation because that causes problems 1639 // with unexpected atomic snoop requests. 1640 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1641 1642 auto req = std::make_shared<Request>( 1643 0, val, 0, flags, Request::funcMasterId, 1644 tc->pcState().pc(), tc->contextId()); 1645 1646 fault = getDTBPtr(tc)->translateFunctional( 1647 req, tc, mode, tranType); 1648 1649 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1650 HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 1651 1652 MiscReg newVal; 1653 if (fault == NoFault) { 1654 Addr paddr = req->getPaddr(); 1655 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 1656 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 1657 newVal = (paddr & mask(39, 12)) | 1658 (getDTBPtr(tc)->getAttr()); 1659 } else { 1660 newVal = (paddr & 0xfffff000) | 1661 (getDTBPtr(tc)->getAttr()); 1662 } 1663 DPRINTF(MiscRegs, 1664 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 1665 val, newVal); 1666 } else { 1667 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1668 armFault->update(tc); 1669 // Set fault bit and FSR 1670 FSR fsr = armFault->getFsr(tc); 1671 1672 newVal = ((fsr >> 9) & 1) << 11; 1673 if (newVal) { 1674 // LPAE - rearange fault status 1675 newVal |= ((fsr >> 0) & 0x3f) << 1; 1676 } else { 1677 // VMSA - rearange fault status 1678 newVal |= ((fsr >> 0) & 0xf) << 1; 1679 newVal |= ((fsr >> 10) & 0x1) << 5; 1680 newVal |= ((fsr >> 12) & 0x1) << 6; 1681 } 1682 newVal |= 0x1; // F bit 1683 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1684 newVal |= armFault->isStage2() ? 0x200 : 0; 1685 DPRINTF(MiscRegs, 1686 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 1687 val, fsr, newVal); 1688 } 1689 setMiscRegNoEffect(MISCREG_PAR, newVal); 1690 return; 1691 } 1692 case MISCREG_TTBCR: 1693 { 1694 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1695 const uint32_t ones = (uint32_t)(-1); 1696 TTBCR ttbcrMask = 0; 1697 TTBCR ttbcrNew = newVal; 1698 1699 // ARM DDI 0406C.b, ARMv7-32 1700 ttbcrMask.n = ones; // T0SZ 1701 if (haveSecurity) { 1702 ttbcrMask.pd0 = ones; 1703 ttbcrMask.pd1 = ones; 1704 } 1705 ttbcrMask.epd0 = ones; 1706 ttbcrMask.irgn0 = ones; 1707 ttbcrMask.orgn0 = ones; 1708 ttbcrMask.sh0 = ones; 1709 ttbcrMask.ps = ones; // T1SZ 1710 ttbcrMask.a1 = ones; 1711 ttbcrMask.epd1 = ones; 1712 ttbcrMask.irgn1 = ones; 1713 ttbcrMask.orgn1 = ones; 1714 ttbcrMask.sh1 = ones; 1715 if (haveLPAE) 1716 ttbcrMask.eae = ones; 1717 1718 if (haveLPAE && ttbcrNew.eae) { 1719 newVal = newVal & ttbcrMask; 1720 } else { 1721 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 1722 } 1723 // Invalidate TLB MiscReg 1724 getITBPtr(tc)->invalidateMiscReg(); 1725 getDTBPtr(tc)->invalidateMiscReg(); 1726 break; 1727 } 1728 case MISCREG_TTBR0: 1729 case MISCREG_TTBR1: 1730 { 1731 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1732 if (haveLPAE) { 1733 if (ttbcr.eae) { 1734 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 1735 // ARMv8 AArch32 bit 63-56 only 1736 uint64_t ttbrMask = mask(63,56) | mask(47,40); 1737 newVal = (newVal & (~ttbrMask)); 1738 } 1739 } 1740 // Invalidate TLB MiscReg 1741 getITBPtr(tc)->invalidateMiscReg(); 1742 getDTBPtr(tc)->invalidateMiscReg(); 1743 break; 1744 } 1745 case MISCREG_SCTLR_EL1: 1746 case MISCREG_CONTEXTIDR: 1747 case MISCREG_PRRR: 1748 case MISCREG_NMRR: 1749 case MISCREG_MAIR0: 1750 case MISCREG_MAIR1: 1751 case MISCREG_DACR: 1752 case MISCREG_VTTBR: 1753 case MISCREG_SCR_EL3: 1754 case MISCREG_HCR_EL2: 1755 case MISCREG_TCR_EL1: 1756 case MISCREG_TCR_EL2: 1757 case MISCREG_TCR_EL3: 1758 case MISCREG_SCTLR_EL2: 1759 case MISCREG_SCTLR_EL3: 1760 case MISCREG_HSCTLR: 1761 case MISCREG_TTBR0_EL1: 1762 case MISCREG_TTBR1_EL1: 1763 case MISCREG_TTBR0_EL2: 1764 case MISCREG_TTBR1_EL2: 1765 case MISCREG_TTBR0_EL3: 1766 getITBPtr(tc)->invalidateMiscReg(); 1767 getDTBPtr(tc)->invalidateMiscReg(); 1768 break; 1769 case MISCREG_NZCV: 1770 { 1771 CPSR cpsr = val; 1772 1773 tc->setCCReg(CCREG_NZ, cpsr.nz); 1774 tc->setCCReg(CCREG_C, cpsr.c); 1775 tc->setCCReg(CCREG_V, cpsr.v); 1776 } 1777 break; 1778 case MISCREG_DAIF: 1779 { 1780 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1781 cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 1782 newVal = cpsr; 1783 misc_reg = MISCREG_CPSR; 1784 } 1785 break; 1786 case MISCREG_SP_EL0: 1787 tc->setIntReg(INTREG_SP0, newVal); 1788 break; 1789 case MISCREG_SP_EL1: 1790 tc->setIntReg(INTREG_SP1, newVal); 1791 break; 1792 case MISCREG_SP_EL2: 1793 tc->setIntReg(INTREG_SP2, newVal); 1794 break; 1795 case MISCREG_SPSEL: 1796 { 1797 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1798 cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 1799 newVal = cpsr; 1800 misc_reg = MISCREG_CPSR; 1801 } 1802 break; 1803 case MISCREG_CURRENTEL: 1804 { 1805 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1806 cpsr.el = (uint8_t) ((CPSR) newVal).el; 1807 newVal = cpsr; 1808 misc_reg = MISCREG_CPSR; 1809 } 1810 break; 1811 case MISCREG_AT_S1E1R_Xt: 1812 case MISCREG_AT_S1E1W_Xt: 1813 case MISCREG_AT_S1E0R_Xt: 1814 case MISCREG_AT_S1E0W_Xt: 1815 case MISCREG_AT_S1E2R_Xt: 1816 case MISCREG_AT_S1E2W_Xt: 1817 case MISCREG_AT_S12E1R_Xt: 1818 case MISCREG_AT_S12E1W_Xt: 1819 case MISCREG_AT_S12E0R_Xt: 1820 case MISCREG_AT_S12E0W_Xt: 1821 case MISCREG_AT_S1E3R_Xt: 1822 case MISCREG_AT_S1E3W_Xt: 1823 { 1824 RequestPtr req = std::make_shared<Request>(); 1825 Request::Flags flags = 0; 1826 BaseTLB::Mode mode = BaseTLB::Read; 1827 TLB::ArmTranslationType tranType = TLB::NormalTran; 1828 Fault fault; 1829 switch(misc_reg) { 1830 case MISCREG_AT_S1E1R_Xt: 1831 flags = TLB::MustBeOne; 1832 tranType = TLB::S1E1Tran; 1833 mode = BaseTLB::Read; 1834 break; 1835 case MISCREG_AT_S1E1W_Xt: 1836 flags = TLB::MustBeOne; 1837 tranType = TLB::S1E1Tran; 1838 mode = BaseTLB::Write; 1839 break; 1840 case MISCREG_AT_S1E0R_Xt: 1841 flags = TLB::MustBeOne | TLB::UserMode; 1842 tranType = TLB::S1E0Tran; 1843 mode = BaseTLB::Read; 1844 break; 1845 case MISCREG_AT_S1E0W_Xt: 1846 flags = TLB::MustBeOne | TLB::UserMode; 1847 tranType = TLB::S1E0Tran; 1848 mode = BaseTLB::Write; 1849 break; 1850 case MISCREG_AT_S1E2R_Xt: 1851 flags = TLB::MustBeOne; 1852 tranType = TLB::S1E2Tran; 1853 mode = BaseTLB::Read; 1854 break; 1855 case MISCREG_AT_S1E2W_Xt: 1856 flags = TLB::MustBeOne; 1857 tranType = TLB::S1E2Tran; 1858 mode = BaseTLB::Write; 1859 break; 1860 case MISCREG_AT_S12E0R_Xt: 1861 flags = TLB::MustBeOne | TLB::UserMode; 1862 tranType = TLB::S12E0Tran; 1863 mode = BaseTLB::Read; 1864 break; 1865 case MISCREG_AT_S12E0W_Xt: 1866 flags = TLB::MustBeOne | TLB::UserMode; 1867 tranType = TLB::S12E0Tran; 1868 mode = BaseTLB::Write; 1869 break; 1870 case MISCREG_AT_S12E1R_Xt: 1871 flags = TLB::MustBeOne; 1872 tranType = TLB::S12E1Tran; 1873 mode = BaseTLB::Read; 1874 break; 1875 case MISCREG_AT_S12E1W_Xt: 1876 flags = TLB::MustBeOne; 1877 tranType = TLB::S12E1Tran; 1878 mode = BaseTLB::Write; 1879 break; 1880 case MISCREG_AT_S1E3R_Xt: 1881 flags = TLB::MustBeOne; 1882 tranType = TLB::S1E3Tran; 1883 mode = BaseTLB::Read; 1884 break; 1885 case MISCREG_AT_S1E3W_Xt: 1886 flags = TLB::MustBeOne; 1887 tranType = TLB::S1E3Tran; 1888 mode = BaseTLB::Write; 1889 break; 1890 } 1891 // If we're in timing mode then doing the translation in 1892 // functional mode then we're slightly distorting performance 1893 // results obtained from simulations. The translation should be 1894 // done in the same mode the core is running in. NOTE: This 1895 // can't be an atomic translation because that causes problems 1896 // with unexpected atomic snoop requests. 1897 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1898 req->setVirt(0, val, 0, flags, Request::funcMasterId, 1899 tc->pcState().pc()); 1900 req->setContext(tc->contextId()); 1901 fault = getDTBPtr(tc)->translateFunctional(req, tc, mode, 1902 tranType); 1903 1904 MiscReg newVal; 1905 if (fault == NoFault) { 1906 Addr paddr = req->getPaddr(); 1907 uint64_t attr = getDTBPtr(tc)->getAttr(); 1908 uint64_t attr1 = attr >> 56; 1909 if (!attr1 || attr1 ==0x44) { 1910 attr |= 0x100; 1911 attr &= ~ uint64_t(0x80); 1912 } 1913 newVal = (paddr & mask(47, 12)) | attr; 1914 DPRINTF(MiscRegs, 1915 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 1916 val, newVal); 1917 } else { 1918 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1919 armFault->update(tc); 1920 // Set fault bit and FSR 1921 FSR fsr = armFault->getFsr(tc); 1922 1923 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1924 if (cpsr.width) { // AArch32 1925 newVal = ((fsr >> 9) & 1) << 11; 1926 // rearrange fault status 1927 newVal |= ((fsr >> 0) & 0x3f) << 1; 1928 newVal |= 0x1; // F bit 1929 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1930 newVal |= armFault->isStage2() ? 0x200 : 0; 1931 } else { // AArch64 1932 newVal = 1; // F bit 1933 newVal |= fsr << 1; // FST 1934 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit. 1935 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 1936 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 1937 newVal |= 1 << 11; // RES1 1938 } 1939 DPRINTF(MiscRegs, 1940 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 1941 val, fsr, newVal); 1942 } 1943 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 1944 return; 1945 } 1946 case MISCREG_SPSR_EL3: 1947 case MISCREG_SPSR_EL2: 1948 case MISCREG_SPSR_EL1: 1949 // Force bits 23:21 to 0 1950 newVal = val & ~(0x7 << 21); 1951 break; 1952 case MISCREG_L2CTLR: 1953 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 1954 miscRegName[misc_reg], uint32_t(val)); 1955 break; 1956 1957 // Generic Timer registers 1958 case MISCREG_CNTHV_CTL_EL2: 1959 case MISCREG_CNTHV_CVAL_EL2: 1960 case MISCREG_CNTHV_TVAL_EL2: 1961 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 1962 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 1963 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 1964 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 1965 getGenericTimer(tc).setMiscReg(misc_reg, newVal); 1966 break; 1967 } 1968 } 1969 setMiscRegNoEffect(misc_reg, newVal); 1970} 1971 1972BaseISADevice & 1973ISA::getGenericTimer(ThreadContext *tc) 1974{ 1975 // We only need to create an ISA interface the first time we try 1976 // to access the timer. 1977 if (timer) 1978 return *timer.get(); 1979 1980 assert(system); 1981 GenericTimer *generic_timer(system->getGenericTimer()); 1982 if (!generic_timer) { 1983 panic("Trying to get a generic timer from a system that hasn't " 1984 "been configured to use a generic timer.\n"); 1985 } 1986 1987 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 1988 timer->setThreadContext(tc); 1989 1990 return *timer.get(); 1991} 1992 1993} 1994 1995ArmISA::ISA * 1996ArmISAParams::create() 1997{ 1998 return new ArmISA::ISA(this); 1999} 2000