isa.cc revision 13173:210b6fc57533
1/* 2 * Copyright (c) 2010-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 */ 40 41#include "arch/arm/isa.hh" 42#include "arch/arm/pmu.hh" 43#include "arch/arm/system.hh" 44#include "arch/arm/tlb.hh" 45#include "arch/arm/tlbi_op.hh" 46#include "cpu/base.hh" 47#include "cpu/checker/cpu.hh" 48#include "debug/Arm.hh" 49#include "debug/MiscRegs.hh" 50#include "dev/arm/generic_timer.hh" 51#include "params/ArmISA.hh" 52#include "sim/faults.hh" 53#include "sim/stat_control.hh" 54#include "sim/system.hh" 55 56namespace ArmISA 57{ 58 59ISA::ISA(Params *p) 60 : SimObject(p), 61 system(NULL), 62 _decoderFlavour(p->decoderFlavour), 63 _vecRegRenameMode(p->vecRegRenameMode), 64 pmu(p->pmu), 65 impdefAsNop(p->impdef_nop) 66{ 67 miscRegs[MISCREG_SCTLR_RST] = 0; 68 69 // Hook up a dummy device if we haven't been configured with a 70 // real PMU. By using a dummy device, we don't need to check that 71 // the PMU exist every time we try to access a PMU register. 72 if (!pmu) 73 pmu = &dummyDevice; 74 75 // Give all ISA devices a pointer to this ISA 76 pmu->setISA(this); 77 78 system = dynamic_cast<ArmSystem *>(p->system); 79 80 // Cache system-level properties 81 if (FullSystem && system) { 82 highestELIs64 = system->highestELIs64(); 83 haveSecurity = system->haveSecurity(); 84 haveLPAE = system->haveLPAE(); 85 haveCrypto = system->haveCrypto(); 86 haveVirtualization = system->haveVirtualization(); 87 haveLargeAsid64 = system->haveLargeAsid64(); 88 physAddrRange = system->physAddrRange(); 89 } else { 90 highestELIs64 = true; // ArmSystem::highestELIs64 does the same 91 haveSecurity = haveLPAE = haveVirtualization = false; 92 haveCrypto = false; 93 haveLargeAsid64 = false; 94 physAddrRange = 32; // dummy value 95 } 96 97 initializeMiscRegMetadata(); 98 preUnflattenMiscReg(); 99 100 clear(); 101} 102 103std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS); 104 105const ArmISAParams * 106ISA::params() const 107{ 108 return dynamic_cast<const Params *>(_params); 109} 110 111void 112ISA::clear() 113{ 114 const Params *p(params()); 115 116 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 117 memset(miscRegs, 0, sizeof(miscRegs)); 118 119 initID32(p); 120 121 // We always initialize AArch64 ID registers even 122 // if we are in AArch32. This is done since if we 123 // are in SE mode we don't know if our ArmProcess is 124 // AArch32 or AArch64 125 initID64(p); 126 127 miscRegs[MISCREG_ID_ISAR5] = insertBits( 128 miscRegs[MISCREG_ID_ISAR5], 19, 4, 129 haveCrypto ? 0x1112 : 0x0); 130 131 if (FullSystem && system->highestELIs64()) { 132 // Initialize AArch64 state 133 clear64(p); 134 return; 135 } 136 137 // Initialize AArch32 state... 138 139 CPSR cpsr = 0; 140 cpsr.mode = MODE_USER; 141 miscRegs[MISCREG_CPSR] = cpsr; 142 updateRegMap(cpsr); 143 144 SCTLR sctlr = 0; 145 sctlr.te = (bool) sctlr_rst.te; 146 sctlr.nmfi = (bool) sctlr_rst.nmfi; 147 sctlr.v = (bool) sctlr_rst.v; 148 sctlr.u = 1; 149 sctlr.xp = 1; 150 sctlr.rao2 = 1; 151 sctlr.rao3 = 1; 152 sctlr.rao4 = 0xf; // SCTLR[6:3] 153 sctlr.uci = 1; 154 sctlr.dze = 1; 155 miscRegs[MISCREG_SCTLR_NS] = sctlr; 156 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 157 miscRegs[MISCREG_HCPTR] = 0; 158 159 // Start with an event in the mailbox 160 miscRegs[MISCREG_SEV_MAILBOX] = 1; 161 162 // Separate Instruction and Data TLBs 163 miscRegs[MISCREG_TLBTR] = 1; 164 165 MVFR0 mvfr0 = 0; 166 mvfr0.advSimdRegisters = 2; 167 mvfr0.singlePrecision = 2; 168 mvfr0.doublePrecision = 2; 169 mvfr0.vfpExceptionTrapping = 0; 170 mvfr0.divide = 1; 171 mvfr0.squareRoot = 1; 172 mvfr0.shortVectors = 1; 173 mvfr0.roundingModes = 1; 174 miscRegs[MISCREG_MVFR0] = mvfr0; 175 176 MVFR1 mvfr1 = 0; 177 mvfr1.flushToZero = 1; 178 mvfr1.defaultNaN = 1; 179 mvfr1.advSimdLoadStore = 1; 180 mvfr1.advSimdInteger = 1; 181 mvfr1.advSimdSinglePrecision = 1; 182 mvfr1.advSimdHalfPrecision = 1; 183 mvfr1.vfpHalfPrecision = 1; 184 miscRegs[MISCREG_MVFR1] = mvfr1; 185 186 // Reset values of PRRR and NMRR are implementation dependent 187 188 // @todo: PRRR and NMRR in secure state? 189 miscRegs[MISCREG_PRRR_NS] = 190 (1 << 19) | // 19 191 (0 << 18) | // 18 192 (0 << 17) | // 17 193 (1 << 16) | // 16 194 (2 << 14) | // 15:14 195 (0 << 12) | // 13:12 196 (2 << 10) | // 11:10 197 (2 << 8) | // 9:8 198 (2 << 6) | // 7:6 199 (2 << 4) | // 5:4 200 (1 << 2) | // 3:2 201 0; // 1:0 202 miscRegs[MISCREG_NMRR_NS] = 203 (1 << 30) | // 31:30 204 (0 << 26) | // 27:26 205 (0 << 24) | // 25:24 206 (3 << 22) | // 23:22 207 (2 << 20) | // 21:20 208 (0 << 18) | // 19:18 209 (0 << 16) | // 17:16 210 (1 << 14) | // 15:14 211 (0 << 12) | // 13:12 212 (2 << 10) | // 11:10 213 (0 << 8) | // 9:8 214 (3 << 6) | // 7:6 215 (2 << 4) | // 5:4 216 (0 << 2) | // 3:2 217 0; // 1:0 218 219 miscRegs[MISCREG_CPACR] = 0; 220 221 miscRegs[MISCREG_FPSID] = p->fpsid; 222 223 if (haveLPAE) { 224 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 225 ttbcr.eae = 0; 226 miscRegs[MISCREG_TTBCR_NS] = ttbcr; 227 // Enforce consistency with system-level settings 228 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 229 } 230 231 if (haveSecurity) { 232 miscRegs[MISCREG_SCTLR_S] = sctlr; 233 miscRegs[MISCREG_SCR] = 0; 234 miscRegs[MISCREG_VBAR_S] = 0; 235 } else { 236 // we're always non-secure 237 miscRegs[MISCREG_SCR] = 1; 238 } 239 240 //XXX We need to initialize the rest of the state. 241} 242 243void 244ISA::clear64(const ArmISAParams *p) 245{ 246 CPSR cpsr = 0; 247 Addr rvbar = system->resetAddr64(); 248 switch (system->highestEL()) { 249 // Set initial EL to highest implemented EL using associated stack 250 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 251 // value 252 case EL3: 253 cpsr.mode = MODE_EL3H; 254 miscRegs[MISCREG_RVBAR_EL3] = rvbar; 255 break; 256 case EL2: 257 cpsr.mode = MODE_EL2H; 258 miscRegs[MISCREG_RVBAR_EL2] = rvbar; 259 break; 260 case EL1: 261 cpsr.mode = MODE_EL1H; 262 miscRegs[MISCREG_RVBAR_EL1] = rvbar; 263 break; 264 default: 265 panic("Invalid highest implemented exception level"); 266 break; 267 } 268 269 // Initialize rest of CPSR 270 cpsr.daif = 0xf; // Mask all interrupts 271 cpsr.ss = 0; 272 cpsr.il = 0; 273 miscRegs[MISCREG_CPSR] = cpsr; 274 updateRegMap(cpsr); 275 276 // Initialize other control registers 277 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 278 if (haveSecurity) { 279 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830; 280 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 281 } else if (haveVirtualization) { 282 // also MISCREG_SCTLR_EL2 (by mapping) 283 miscRegs[MISCREG_HSCTLR] = 0x30c50830; 284 } else { 285 // also MISCREG_SCTLR_EL1 (by mapping) 286 miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init 287 // Always non-secure 288 miscRegs[MISCREG_SCR_EL3] = 1; 289 } 290} 291 292void 293ISA::initID32(const ArmISAParams *p) 294{ 295 // Initialize configurable default values 296 miscRegs[MISCREG_MIDR] = p->midr; 297 miscRegs[MISCREG_MIDR_EL1] = p->midr; 298 miscRegs[MISCREG_VPIDR] = p->midr; 299 300 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 301 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 302 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 303 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 304 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 305 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 306 307 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 308 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 309 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 310 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 311} 312 313void 314ISA::initID64(const ArmISAParams *p) 315{ 316 // Initialize configurable id registers 317 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 318 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 319 miscRegs[MISCREG_ID_AA64DFR0_EL1] = 320 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 321 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 322 323 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 324 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 325 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 326 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 327 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 328 miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p->id_aa64mmfr2_el1; 329 330 miscRegs[MISCREG_ID_DFR0_EL1] = 331 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 332 333 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 334 335 // Enforce consistency with system-level settings... 336 337 // EL3 338 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 339 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 340 haveSecurity ? 0x2 : 0x0); 341 // EL2 342 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 343 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 344 haveVirtualization ? 0x2 : 0x0); 345 // Large ASID support 346 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 347 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 348 haveLargeAsid64 ? 0x2 : 0x0); 349 // Physical address size 350 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 351 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 352 encodePhysAddrRange64(physAddrRange)); 353 // Crypto 354 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits( 355 miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4, 356 haveCrypto ? 0x1112 : 0x0); 357} 358 359void 360ISA::startup(ThreadContext *tc) 361{ 362 pmu->setThreadContext(tc); 363 364} 365 366 367MiscReg 368ISA::readMiscRegNoEffect(int misc_reg) const 369{ 370 assert(misc_reg < NumMiscRegs); 371 372 const auto ® = lookUpMiscReg[misc_reg]; // bit masks 373 const auto &map = getMiscIndices(misc_reg); 374 int lower = map.first, upper = map.second; 375 // NB!: apply architectural masks according to desired register, 376 // despite possibly getting value from different (mapped) register. 377 auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32)) 378 |(miscRegs[upper] << 32)); 379 if (val & reg.res0()) { 380 DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n", 381 miscRegName[misc_reg], val & reg.res0()); 382 } 383 if ((val & reg.res1()) != reg.res1()) { 384 DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n", 385 miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1()); 386 } 387 return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao 388} 389 390 391MiscReg 392ISA::readMiscReg(int misc_reg, ThreadContext *tc) 393{ 394 CPSR cpsr = 0; 395 PCState pc = 0; 396 SCR scr = 0; 397 398 if (misc_reg == MISCREG_CPSR) { 399 cpsr = miscRegs[misc_reg]; 400 pc = tc->pcState(); 401 cpsr.j = pc.jazelle() ? 1 : 0; 402 cpsr.t = pc.thumb() ? 1 : 0; 403 return cpsr; 404 } 405 406#ifndef NDEBUG 407 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 408 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 409 warn("Unimplemented system register %s read.\n", 410 miscRegName[misc_reg]); 411 else 412 panic("Unimplemented system register %s read.\n", 413 miscRegName[misc_reg]); 414 } 415#endif 416 417 switch (unflattenMiscReg(misc_reg)) { 418 case MISCREG_HCR: 419 { 420 if (!haveVirtualization) 421 return 0; 422 else 423 return readMiscRegNoEffect(MISCREG_HCR); 424 } 425 case MISCREG_CPACR: 426 { 427 const uint32_t ones = (uint32_t)(-1); 428 CPACR cpacrMask = 0; 429 // Only cp10, cp11, and ase are implemented, nothing else should 430 // be readable? (straight copy from the write code) 431 cpacrMask.cp10 = ones; 432 cpacrMask.cp11 = ones; 433 cpacrMask.asedis = ones; 434 435 // Security Extensions may limit the readability of CPACR 436 if (haveSecurity) { 437 scr = readMiscRegNoEffect(MISCREG_SCR); 438 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 439 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 440 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 441 // NB: Skipping the full loop, here 442 if (!nsacr.cp10) cpacrMask.cp10 = 0; 443 if (!nsacr.cp11) cpacrMask.cp11 = 0; 444 } 445 } 446 MiscReg val = readMiscRegNoEffect(MISCREG_CPACR); 447 val &= cpacrMask; 448 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 449 miscRegName[misc_reg], val); 450 return val; 451 } 452 case MISCREG_MPIDR: 453 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 454 scr = readMiscRegNoEffect(MISCREG_SCR); 455 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 456 return getMPIDR(system, tc); 457 } else { 458 return readMiscReg(MISCREG_VMPIDR, tc); 459 } 460 break; 461 case MISCREG_MPIDR_EL1: 462 // @todo in the absence of v8 virtualization support just return MPIDR_EL1 463 return getMPIDR(system, tc) & 0xffffffff; 464 case MISCREG_VMPIDR: 465 // top bit defined as RES1 466 return readMiscRegNoEffect(misc_reg) | 0x80000000; 467 case MISCREG_ID_AFR0: // not implemented, so alias MIDR 468 case MISCREG_REVIDR: // not implemented, so alias MIDR 469 case MISCREG_MIDR: 470 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 471 scr = readMiscRegNoEffect(MISCREG_SCR); 472 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 473 return readMiscRegNoEffect(misc_reg); 474 } else { 475 return readMiscRegNoEffect(MISCREG_VPIDR); 476 } 477 break; 478 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 479 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 480 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 481 case MISCREG_AIDR: // AUX ID set to 0 482 case MISCREG_TCMTR: // No TCM's 483 return 0; 484 485 case MISCREG_CLIDR: 486 warn_once("The clidr register always reports 0 caches.\n"); 487 warn_once("clidr LoUIS field of 0b001 to match current " 488 "ARM implementations.\n"); 489 return 0x00200000; 490 case MISCREG_CCSIDR: 491 warn_once("The ccsidr register isn't implemented and " 492 "always reads as 0.\n"); 493 break; 494 case MISCREG_CTR: // AArch32, ARMv7, top bit set 495 case MISCREG_CTR_EL0: // AArch64 496 { 497 //all caches have the same line size in gem5 498 //4 byte words in ARM 499 unsigned lineSizeWords = 500 tc->getSystemPtr()->cacheLineSize() / 4; 501 unsigned log2LineSizeWords = 0; 502 503 while (lineSizeWords >>= 1) { 504 ++log2LineSizeWords; 505 } 506 507 CTR ctr = 0; 508 //log2 of minimun i-cache line size (words) 509 ctr.iCacheLineSize = log2LineSizeWords; 510 //b11 - gem5 uses pipt 511 ctr.l1IndexPolicy = 0x3; 512 //log2 of minimum d-cache line size (words) 513 ctr.dCacheLineSize = log2LineSizeWords; 514 //log2 of max reservation size (words) 515 ctr.erg = log2LineSizeWords; 516 //log2 of max writeback size (words) 517 ctr.cwg = log2LineSizeWords; 518 //b100 - gem5 format is ARMv7 519 ctr.format = 0x4; 520 521 return ctr; 522 } 523 case MISCREG_ACTLR: 524 warn("Not doing anything for miscreg ACTLR\n"); 525 break; 526 527 case MISCREG_PMXEVTYPER_PMCCFILTR: 528 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 529 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 530 case MISCREG_PMCR ... MISCREG_PMOVSSET: 531 return pmu->readMiscReg(misc_reg); 532 533 case MISCREG_CPSR_Q: 534 panic("shouldn't be reading this register seperately\n"); 535 case MISCREG_FPSCR_QC: 536 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 537 case MISCREG_FPSCR_EXC: 538 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 539 case MISCREG_FPSR: 540 { 541 const uint32_t ones = (uint32_t)(-1); 542 FPSCR fpscrMask = 0; 543 fpscrMask.ioc = ones; 544 fpscrMask.dzc = ones; 545 fpscrMask.ofc = ones; 546 fpscrMask.ufc = ones; 547 fpscrMask.ixc = ones; 548 fpscrMask.idc = ones; 549 fpscrMask.qc = ones; 550 fpscrMask.v = ones; 551 fpscrMask.c = ones; 552 fpscrMask.z = ones; 553 fpscrMask.n = ones; 554 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 555 } 556 case MISCREG_FPCR: 557 { 558 const uint32_t ones = (uint32_t)(-1); 559 FPSCR fpscrMask = 0; 560 fpscrMask.len = ones; 561 fpscrMask.stride = ones; 562 fpscrMask.rMode = ones; 563 fpscrMask.fz = ones; 564 fpscrMask.dn = ones; 565 fpscrMask.ahp = ones; 566 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 567 } 568 case MISCREG_NZCV: 569 { 570 CPSR cpsr = 0; 571 cpsr.nz = tc->readCCReg(CCREG_NZ); 572 cpsr.c = tc->readCCReg(CCREG_C); 573 cpsr.v = tc->readCCReg(CCREG_V); 574 return cpsr; 575 } 576 case MISCREG_DAIF: 577 { 578 CPSR cpsr = 0; 579 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 580 return cpsr; 581 } 582 case MISCREG_SP_EL0: 583 { 584 return tc->readIntReg(INTREG_SP0); 585 } 586 case MISCREG_SP_EL1: 587 { 588 return tc->readIntReg(INTREG_SP1); 589 } 590 case MISCREG_SP_EL2: 591 { 592 return tc->readIntReg(INTREG_SP2); 593 } 594 case MISCREG_SPSEL: 595 { 596 return miscRegs[MISCREG_CPSR] & 0x1; 597 } 598 case MISCREG_CURRENTEL: 599 { 600 return miscRegs[MISCREG_CPSR] & 0xc; 601 } 602 case MISCREG_L2CTLR: 603 { 604 // mostly unimplemented, just set NumCPUs field from sim and return 605 L2CTLR l2ctlr = 0; 606 // b00:1CPU to b11:4CPUs 607 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 608 return l2ctlr; 609 } 610 case MISCREG_DBGDIDR: 611 /* For now just implement the version number. 612 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 613 */ 614 return 0x5 << 16; 615 case MISCREG_DBGDSCRint: 616 return 0; 617 case MISCREG_ISR: 618 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 619 readMiscRegNoEffect(MISCREG_HCR), 620 readMiscRegNoEffect(MISCREG_CPSR), 621 readMiscRegNoEffect(MISCREG_SCR)); 622 case MISCREG_ISR_EL1: 623 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 624 readMiscRegNoEffect(MISCREG_HCR_EL2), 625 readMiscRegNoEffect(MISCREG_CPSR), 626 readMiscRegNoEffect(MISCREG_SCR_EL3)); 627 case MISCREG_DCZID_EL0: 628 return 0x04; // DC ZVA clear 64-byte chunks 629 case MISCREG_HCPTR: 630 { 631 MiscReg val = readMiscRegNoEffect(misc_reg); 632 // The trap bit associated with CP14 is defined as RAZ 633 val &= ~(1 << 14); 634 // If a CP bit in NSACR is 0 then the corresponding bit in 635 // HCPTR is RAO/WI 636 bool secure_lookup = haveSecurity && 637 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 638 readMiscRegNoEffect(MISCREG_CPSR)); 639 if (!secure_lookup) { 640 MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR); 641 val |= (mask ^ 0x7FFF) & 0xBFFF; 642 } 643 // Set the bits for unimplemented coprocessors to RAO/WI 644 val |= 0x33FF; 645 return (val); 646 } 647 case MISCREG_HDFAR: // alias for secure DFAR 648 return readMiscRegNoEffect(MISCREG_DFAR_S); 649 case MISCREG_HIFAR: // alias for secure IFAR 650 return readMiscRegNoEffect(MISCREG_IFAR_S); 651 case MISCREG_HVBAR: // bottom bits reserved 652 return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0; 653 case MISCREG_SCTLR: 654 return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818; 655 case MISCREG_SCTLR_EL1: 656 return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800; 657 case MISCREG_SCTLR_EL2: 658 case MISCREG_SCTLR_EL3: 659 case MISCREG_HSCTLR: 660 return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; 661 662 case MISCREG_ID_PFR0: 663 // !ThumbEE | !Jazelle | Thumb | ARM 664 return 0x00000031; 665 case MISCREG_ID_PFR1: 666 { // Timer | Virti | !M Profile | TrustZone | ARMv4 667 bool haveTimer = (system->getGenericTimer() != NULL); 668 return 0x00000001 669 | (haveSecurity ? 0x00000010 : 0x0) 670 | (haveVirtualization ? 0x00001000 : 0x0) 671 | (haveTimer ? 0x00010000 : 0x0); 672 } 673 case MISCREG_ID_AA64PFR0_EL1: 674 return 0x0000000000000002 // AArch{64,32} supported at EL0 675 | 0x0000000000000020 // EL1 676 | (haveVirtualization ? 0x0000000000000200 : 0) // EL2 677 | (haveSecurity ? 0x0000000000002000 : 0); // EL3 678 case MISCREG_ID_AA64PFR1_EL1: 679 return 0; // bits [63:0] RES0 (reserved for future use) 680 681 // Generic Timer registers 682 case MISCREG_CNTHV_CTL_EL2: 683 case MISCREG_CNTHV_CVAL_EL2: 684 case MISCREG_CNTHV_TVAL_EL2: 685 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 686 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 687 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 688 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 689 return getGenericTimer(tc).readMiscReg(misc_reg); 690 691 default: 692 break; 693 694 } 695 return readMiscRegNoEffect(misc_reg); 696} 697 698void 699ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 700{ 701 assert(misc_reg < NumMiscRegs); 702 703 const auto ® = lookUpMiscReg[misc_reg]; // bit masks 704 const auto &map = getMiscIndices(misc_reg); 705 int lower = map.first, upper = map.second; 706 707 auto v = (val & ~reg.wi()) | reg.rao(); 708 if (upper > 0) { 709 miscRegs[lower] = bits(v, 31, 0); 710 miscRegs[upper] = bits(v, 63, 32); 711 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 712 misc_reg, lower, upper, v); 713 } else { 714 miscRegs[lower] = v; 715 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 716 misc_reg, lower, v); 717 } 718} 719 720void 721ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 722{ 723 724 MiscReg newVal = val; 725 bool secure_lookup; 726 SCR scr; 727 728 if (misc_reg == MISCREG_CPSR) { 729 updateRegMap(val); 730 731 732 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 733 int old_mode = old_cpsr.mode; 734 CPSR cpsr = val; 735 if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) { 736 getITBPtr(tc)->invalidateMiscReg(); 737 getDTBPtr(tc)->invalidateMiscReg(); 738 } 739 740 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 741 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 742 PCState pc = tc->pcState(); 743 pc.nextThumb(cpsr.t); 744 pc.nextJazelle(cpsr.j); 745 pc.illegalExec(cpsr.il == 1); 746 747 // Follow slightly different semantics if a CheckerCPU object 748 // is connected 749 CheckerCPU *checker = tc->getCheckerCpuPtr(); 750 if (checker) { 751 tc->pcStateNoRecord(pc); 752 } else { 753 tc->pcState(pc); 754 } 755 } else { 756#ifndef NDEBUG 757 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 758 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 759 warn("Unimplemented system register %s write with %#x.\n", 760 miscRegName[misc_reg], val); 761 else 762 panic("Unimplemented system register %s write with %#x.\n", 763 miscRegName[misc_reg], val); 764 } 765#endif 766 switch (unflattenMiscReg(misc_reg)) { 767 case MISCREG_CPACR: 768 { 769 770 const uint32_t ones = (uint32_t)(-1); 771 CPACR cpacrMask = 0; 772 // Only cp10, cp11, and ase are implemented, nothing else should 773 // be writable 774 cpacrMask.cp10 = ones; 775 cpacrMask.cp11 = ones; 776 cpacrMask.asedis = ones; 777 778 // Security Extensions may limit the writability of CPACR 779 if (haveSecurity) { 780 scr = readMiscRegNoEffect(MISCREG_SCR); 781 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 782 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 783 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 784 // NB: Skipping the full loop, here 785 if (!nsacr.cp10) cpacrMask.cp10 = 0; 786 if (!nsacr.cp11) cpacrMask.cp11 = 0; 787 } 788 } 789 790 MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR); 791 newVal &= cpacrMask; 792 newVal |= old_val & ~cpacrMask; 793 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 794 miscRegName[misc_reg], newVal); 795 } 796 break; 797 case MISCREG_CPTR_EL2: 798 { 799 const uint32_t ones = (uint32_t)(-1); 800 CPTR cptrMask = 0; 801 cptrMask.tcpac = ones; 802 cptrMask.tta = ones; 803 cptrMask.tfp = ones; 804 newVal &= cptrMask; 805 cptrMask = 0; 806 cptrMask.res1_13_12_el2 = ones; 807 cptrMask.res1_9_0_el2 = ones; 808 newVal |= cptrMask; 809 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 810 miscRegName[misc_reg], newVal); 811 } 812 break; 813 case MISCREG_CPTR_EL3: 814 { 815 const uint32_t ones = (uint32_t)(-1); 816 CPTR cptrMask = 0; 817 cptrMask.tcpac = ones; 818 cptrMask.tta = ones; 819 cptrMask.tfp = ones; 820 newVal &= cptrMask; 821 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 822 miscRegName[misc_reg], newVal); 823 } 824 break; 825 case MISCREG_CSSELR: 826 warn_once("The csselr register isn't implemented.\n"); 827 return; 828 829 case MISCREG_DC_ZVA_Xt: 830 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 831 return; 832 833 case MISCREG_FPSCR: 834 { 835 const uint32_t ones = (uint32_t)(-1); 836 FPSCR fpscrMask = 0; 837 fpscrMask.ioc = ones; 838 fpscrMask.dzc = ones; 839 fpscrMask.ofc = ones; 840 fpscrMask.ufc = ones; 841 fpscrMask.ixc = ones; 842 fpscrMask.idc = ones; 843 fpscrMask.ioe = ones; 844 fpscrMask.dze = ones; 845 fpscrMask.ofe = ones; 846 fpscrMask.ufe = ones; 847 fpscrMask.ixe = ones; 848 fpscrMask.ide = ones; 849 fpscrMask.len = ones; 850 fpscrMask.stride = ones; 851 fpscrMask.rMode = ones; 852 fpscrMask.fz = ones; 853 fpscrMask.dn = ones; 854 fpscrMask.ahp = ones; 855 fpscrMask.qc = ones; 856 fpscrMask.v = ones; 857 fpscrMask.c = ones; 858 fpscrMask.z = ones; 859 fpscrMask.n = ones; 860 newVal = (newVal & (uint32_t)fpscrMask) | 861 (readMiscRegNoEffect(MISCREG_FPSCR) & 862 ~(uint32_t)fpscrMask); 863 tc->getDecoderPtr()->setContext(newVal); 864 } 865 break; 866 case MISCREG_FPSR: 867 { 868 const uint32_t ones = (uint32_t)(-1); 869 FPSCR fpscrMask = 0; 870 fpscrMask.ioc = ones; 871 fpscrMask.dzc = ones; 872 fpscrMask.ofc = ones; 873 fpscrMask.ufc = ones; 874 fpscrMask.ixc = ones; 875 fpscrMask.idc = ones; 876 fpscrMask.qc = ones; 877 fpscrMask.v = ones; 878 fpscrMask.c = ones; 879 fpscrMask.z = ones; 880 fpscrMask.n = ones; 881 newVal = (newVal & (uint32_t)fpscrMask) | 882 (readMiscRegNoEffect(MISCREG_FPSCR) & 883 ~(uint32_t)fpscrMask); 884 misc_reg = MISCREG_FPSCR; 885 } 886 break; 887 case MISCREG_FPCR: 888 { 889 const uint32_t ones = (uint32_t)(-1); 890 FPSCR fpscrMask = 0; 891 fpscrMask.len = ones; 892 fpscrMask.stride = ones; 893 fpscrMask.rMode = ones; 894 fpscrMask.fz = ones; 895 fpscrMask.dn = ones; 896 fpscrMask.ahp = ones; 897 newVal = (newVal & (uint32_t)fpscrMask) | 898 (readMiscRegNoEffect(MISCREG_FPSCR) & 899 ~(uint32_t)fpscrMask); 900 misc_reg = MISCREG_FPSCR; 901 } 902 break; 903 case MISCREG_CPSR_Q: 904 { 905 assert(!(newVal & ~CpsrMaskQ)); 906 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 907 misc_reg = MISCREG_CPSR; 908 } 909 break; 910 case MISCREG_FPSCR_QC: 911 { 912 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 913 (newVal & FpscrQcMask); 914 misc_reg = MISCREG_FPSCR; 915 } 916 break; 917 case MISCREG_FPSCR_EXC: 918 { 919 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 920 (newVal & FpscrExcMask); 921 misc_reg = MISCREG_FPSCR; 922 } 923 break; 924 case MISCREG_FPEXC: 925 { 926 // vfpv3 architecture, section B.6.1 of DDI04068 927 // bit 29 - valid only if fpexc[31] is 0 928 const uint32_t fpexcMask = 0x60000000; 929 newVal = (newVal & fpexcMask) | 930 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 931 } 932 break; 933 case MISCREG_HCR: 934 { 935 if (!haveVirtualization) 936 return; 937 } 938 break; 939 case MISCREG_IFSR: 940 { 941 // ARM ARM (ARM DDI 0406C.b) B4.1.96 942 const uint32_t ifsrMask = 943 mask(31, 13) | mask(11, 11) | mask(8, 6); 944 newVal = newVal & ~ifsrMask; 945 } 946 break; 947 case MISCREG_DFSR: 948 { 949 // ARM ARM (ARM DDI 0406C.b) B4.1.52 950 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 951 newVal = newVal & ~dfsrMask; 952 } 953 break; 954 case MISCREG_AMAIR0: 955 case MISCREG_AMAIR1: 956 { 957 // ARM ARM (ARM DDI 0406C.b) B4.1.5 958 // Valid only with LPAE 959 if (!haveLPAE) 960 return; 961 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 962 } 963 break; 964 case MISCREG_SCR: 965 getITBPtr(tc)->invalidateMiscReg(); 966 getDTBPtr(tc)->invalidateMiscReg(); 967 break; 968 case MISCREG_SCTLR: 969 { 970 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 971 scr = readMiscRegNoEffect(MISCREG_SCR); 972 973 MiscRegIndex sctlr_idx; 974 if (haveSecurity && !highestELIs64 && !scr.ns) { 975 sctlr_idx = MISCREG_SCTLR_S; 976 } else { 977 sctlr_idx = MISCREG_SCTLR_NS; 978 } 979 980 SCTLR sctlr = miscRegs[sctlr_idx]; 981 SCTLR new_sctlr = newVal; 982 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 983 miscRegs[sctlr_idx] = (MiscReg)new_sctlr; 984 getITBPtr(tc)->invalidateMiscReg(); 985 getDTBPtr(tc)->invalidateMiscReg(); 986 } 987 case MISCREG_MIDR: 988 case MISCREG_ID_PFR0: 989 case MISCREG_ID_PFR1: 990 case MISCREG_ID_DFR0: 991 case MISCREG_ID_MMFR0: 992 case MISCREG_ID_MMFR1: 993 case MISCREG_ID_MMFR2: 994 case MISCREG_ID_MMFR3: 995 case MISCREG_ID_ISAR0: 996 case MISCREG_ID_ISAR1: 997 case MISCREG_ID_ISAR2: 998 case MISCREG_ID_ISAR3: 999 case MISCREG_ID_ISAR4: 1000 case MISCREG_ID_ISAR5: 1001 1002 case MISCREG_MPIDR: 1003 case MISCREG_FPSID: 1004 case MISCREG_TLBTR: 1005 case MISCREG_MVFR0: 1006 case MISCREG_MVFR1: 1007 1008 case MISCREG_ID_AA64AFR0_EL1: 1009 case MISCREG_ID_AA64AFR1_EL1: 1010 case MISCREG_ID_AA64DFR0_EL1: 1011 case MISCREG_ID_AA64DFR1_EL1: 1012 case MISCREG_ID_AA64ISAR0_EL1: 1013 case MISCREG_ID_AA64ISAR1_EL1: 1014 case MISCREG_ID_AA64MMFR0_EL1: 1015 case MISCREG_ID_AA64MMFR1_EL1: 1016 case MISCREG_ID_AA64MMFR2_EL1: 1017 case MISCREG_ID_AA64PFR0_EL1: 1018 case MISCREG_ID_AA64PFR1_EL1: 1019 // ID registers are constants. 1020 return; 1021 1022 // TLB Invalidate All 1023 case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 1024 { 1025 assert32(tc); 1026 scr = readMiscReg(MISCREG_SCR, tc); 1027 1028 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1029 tlbiOp(tc); 1030 return; 1031 } 1032 // TLB Invalidate All, Inner Shareable 1033 case MISCREG_TLBIALLIS: 1034 { 1035 assert32(tc); 1036 scr = readMiscReg(MISCREG_SCR, tc); 1037 1038 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1039 tlbiOp.broadcast(tc); 1040 return; 1041 } 1042 // Instruction TLB Invalidate All 1043 case MISCREG_ITLBIALL: 1044 { 1045 assert32(tc); 1046 scr = readMiscReg(MISCREG_SCR, tc); 1047 1048 ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1049 tlbiOp(tc); 1050 return; 1051 } 1052 // Data TLB Invalidate All 1053 case MISCREG_DTLBIALL: 1054 { 1055 assert32(tc); 1056 scr = readMiscReg(MISCREG_SCR, tc); 1057 1058 DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1059 tlbiOp(tc); 1060 return; 1061 } 1062 // TLB Invalidate by VA 1063 // mcr tlbimval(is) is invalidating all matching entries 1064 // regardless of the level of lookup, since in gem5 we cache 1065 // in the tlb the last level of lookup only. 1066 case MISCREG_TLBIMVA: 1067 case MISCREG_TLBIMVAL: 1068 { 1069 assert32(tc); 1070 scr = readMiscReg(MISCREG_SCR, tc); 1071 1072 TLBIMVA tlbiOp(EL1, 1073 haveSecurity && !scr.ns, 1074 mbits(newVal, 31, 12), 1075 bits(newVal, 7,0)); 1076 1077 tlbiOp(tc); 1078 return; 1079 } 1080 // TLB Invalidate by VA, Inner Shareable 1081 case MISCREG_TLBIMVAIS: 1082 case MISCREG_TLBIMVALIS: 1083 { 1084 assert32(tc); 1085 scr = readMiscReg(MISCREG_SCR, tc); 1086 1087 TLBIMVA tlbiOp(EL1, 1088 haveSecurity && !scr.ns, 1089 mbits(newVal, 31, 12), 1090 bits(newVal, 7,0)); 1091 1092 tlbiOp.broadcast(tc); 1093 return; 1094 } 1095 // TLB Invalidate by ASID match 1096 case MISCREG_TLBIASID: 1097 { 1098 assert32(tc); 1099 scr = readMiscReg(MISCREG_SCR, tc); 1100 1101 TLBIASID tlbiOp(EL1, 1102 haveSecurity && !scr.ns, 1103 bits(newVal, 7,0)); 1104 1105 tlbiOp(tc); 1106 return; 1107 } 1108 // TLB Invalidate by ASID match, Inner Shareable 1109 case MISCREG_TLBIASIDIS: 1110 { 1111 assert32(tc); 1112 scr = readMiscReg(MISCREG_SCR, tc); 1113 1114 TLBIASID tlbiOp(EL1, 1115 haveSecurity && !scr.ns, 1116 bits(newVal, 7,0)); 1117 1118 tlbiOp.broadcast(tc); 1119 return; 1120 } 1121 // mcr tlbimvaal(is) is invalidating all matching entries 1122 // regardless of the level of lookup, since in gem5 we cache 1123 // in the tlb the last level of lookup only. 1124 // TLB Invalidate by VA, All ASID 1125 case MISCREG_TLBIMVAA: 1126 case MISCREG_TLBIMVAAL: 1127 { 1128 assert32(tc); 1129 scr = readMiscReg(MISCREG_SCR, tc); 1130 1131 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1132 mbits(newVal, 31,12), false); 1133 1134 tlbiOp(tc); 1135 return; 1136 } 1137 // TLB Invalidate by VA, All ASID, Inner Shareable 1138 case MISCREG_TLBIMVAAIS: 1139 case MISCREG_TLBIMVAALIS: 1140 { 1141 assert32(tc); 1142 scr = readMiscReg(MISCREG_SCR, tc); 1143 1144 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1145 mbits(newVal, 31,12), false); 1146 1147 tlbiOp.broadcast(tc); 1148 return; 1149 } 1150 // mcr tlbimvalh(is) is invalidating all matching entries 1151 // regardless of the level of lookup, since in gem5 we cache 1152 // in the tlb the last level of lookup only. 1153 // TLB Invalidate by VA, Hyp mode 1154 case MISCREG_TLBIMVAH: 1155 case MISCREG_TLBIMVALH: 1156 { 1157 assert32(tc); 1158 scr = readMiscReg(MISCREG_SCR, tc); 1159 1160 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1161 mbits(newVal, 31,12), true); 1162 1163 tlbiOp(tc); 1164 return; 1165 } 1166 // TLB Invalidate by VA, Hyp mode, Inner Shareable 1167 case MISCREG_TLBIMVAHIS: 1168 case MISCREG_TLBIMVALHIS: 1169 { 1170 assert32(tc); 1171 scr = readMiscReg(MISCREG_SCR, tc); 1172 1173 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1174 mbits(newVal, 31,12), true); 1175 1176 tlbiOp.broadcast(tc); 1177 return; 1178 } 1179 // mcr tlbiipas2l(is) is invalidating all matching entries 1180 // regardless of the level of lookup, since in gem5 we cache 1181 // in the tlb the last level of lookup only. 1182 // TLB Invalidate by Intermediate Physical Address, Stage 2 1183 case MISCREG_TLBIIPAS2: 1184 case MISCREG_TLBIIPAS2L: 1185 { 1186 assert32(tc); 1187 scr = readMiscReg(MISCREG_SCR, tc); 1188 1189 TLBIIPA tlbiOp(EL1, 1190 haveSecurity && !scr.ns, 1191 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1192 1193 tlbiOp(tc); 1194 return; 1195 } 1196 // TLB Invalidate by Intermediate Physical Address, Stage 2, 1197 // Inner Shareable 1198 case MISCREG_TLBIIPAS2IS: 1199 case MISCREG_TLBIIPAS2LIS: 1200 { 1201 assert32(tc); 1202 scr = readMiscReg(MISCREG_SCR, tc); 1203 1204 TLBIIPA tlbiOp(EL1, 1205 haveSecurity && !scr.ns, 1206 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1207 1208 tlbiOp.broadcast(tc); 1209 return; 1210 } 1211 // Instruction TLB Invalidate by VA 1212 case MISCREG_ITLBIMVA: 1213 { 1214 assert32(tc); 1215 scr = readMiscReg(MISCREG_SCR, tc); 1216 1217 ITLBIMVA tlbiOp(EL1, 1218 haveSecurity && !scr.ns, 1219 mbits(newVal, 31, 12), 1220 bits(newVal, 7,0)); 1221 1222 tlbiOp(tc); 1223 return; 1224 } 1225 // Data TLB Invalidate by VA 1226 case MISCREG_DTLBIMVA: 1227 { 1228 assert32(tc); 1229 scr = readMiscReg(MISCREG_SCR, tc); 1230 1231 DTLBIMVA tlbiOp(EL1, 1232 haveSecurity && !scr.ns, 1233 mbits(newVal, 31, 12), 1234 bits(newVal, 7,0)); 1235 1236 tlbiOp(tc); 1237 return; 1238 } 1239 // Instruction TLB Invalidate by ASID match 1240 case MISCREG_ITLBIASID: 1241 { 1242 assert32(tc); 1243 scr = readMiscReg(MISCREG_SCR, tc); 1244 1245 ITLBIASID tlbiOp(EL1, 1246 haveSecurity && !scr.ns, 1247 bits(newVal, 7,0)); 1248 1249 tlbiOp(tc); 1250 return; 1251 } 1252 // Data TLB Invalidate by ASID match 1253 case MISCREG_DTLBIASID: 1254 { 1255 assert32(tc); 1256 scr = readMiscReg(MISCREG_SCR, tc); 1257 1258 DTLBIASID tlbiOp(EL1, 1259 haveSecurity && !scr.ns, 1260 bits(newVal, 7,0)); 1261 1262 tlbiOp(tc); 1263 return; 1264 } 1265 // TLB Invalidate All, Non-Secure Non-Hyp 1266 case MISCREG_TLBIALLNSNH: 1267 { 1268 assert32(tc); 1269 1270 TLBIALLN tlbiOp(EL1, false); 1271 tlbiOp(tc); 1272 return; 1273 } 1274 // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable 1275 case MISCREG_TLBIALLNSNHIS: 1276 { 1277 assert32(tc); 1278 1279 TLBIALLN tlbiOp(EL1, false); 1280 tlbiOp.broadcast(tc); 1281 return; 1282 } 1283 // TLB Invalidate All, Hyp mode 1284 case MISCREG_TLBIALLH: 1285 { 1286 assert32(tc); 1287 1288 TLBIALLN tlbiOp(EL1, true); 1289 tlbiOp(tc); 1290 return; 1291 } 1292 // TLB Invalidate All, Hyp mode, Inner Shareable 1293 case MISCREG_TLBIALLHIS: 1294 { 1295 assert32(tc); 1296 1297 TLBIALLN tlbiOp(EL1, true); 1298 tlbiOp.broadcast(tc); 1299 return; 1300 } 1301 // AArch64 TLB Invalidate All, EL3 1302 case MISCREG_TLBI_ALLE3: 1303 { 1304 assert64(tc); 1305 1306 TLBIALL tlbiOp(EL3, true); 1307 tlbiOp(tc); 1308 return; 1309 } 1310 // AArch64 TLB Invalidate All, EL3, Inner Shareable 1311 case MISCREG_TLBI_ALLE3IS: 1312 { 1313 assert64(tc); 1314 1315 TLBIALL tlbiOp(EL3, true); 1316 tlbiOp.broadcast(tc); 1317 return; 1318 } 1319 // @todo: uncomment this to enable Virtualization 1320 // case MISCREG_TLBI_ALLE2IS: 1321 // case MISCREG_TLBI_ALLE2: 1322 // AArch64 TLB Invalidate All, EL1 1323 case MISCREG_TLBI_ALLE1: 1324 case MISCREG_TLBI_VMALLE1: 1325 case MISCREG_TLBI_VMALLS12E1: 1326 // @todo: handle VMID and stage 2 to enable Virtualization 1327 { 1328 assert64(tc); 1329 scr = readMiscReg(MISCREG_SCR, tc); 1330 1331 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1332 tlbiOp(tc); 1333 return; 1334 } 1335 // AArch64 TLB Invalidate All, EL1, Inner Shareable 1336 case MISCREG_TLBI_ALLE1IS: 1337 case MISCREG_TLBI_VMALLE1IS: 1338 case MISCREG_TLBI_VMALLS12E1IS: 1339 // @todo: handle VMID and stage 2 to enable Virtualization 1340 { 1341 assert64(tc); 1342 scr = readMiscReg(MISCREG_SCR, tc); 1343 1344 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1345 tlbiOp.broadcast(tc); 1346 return; 1347 } 1348 // VAEx(IS) and VALEx(IS) are the same because TLBs 1349 // only store entries 1350 // from the last level of translation table walks 1351 // @todo: handle VMID to enable Virtualization 1352 // AArch64 TLB Invalidate by VA, EL3 1353 case MISCREG_TLBI_VAE3_Xt: 1354 case MISCREG_TLBI_VALE3_Xt: 1355 { 1356 assert64(tc); 1357 1358 TLBIMVA tlbiOp(EL3, true, 1359 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1360 0xbeef); 1361 tlbiOp(tc); 1362 return; 1363 } 1364 // AArch64 TLB Invalidate by VA, EL3, Inner Shareable 1365 case MISCREG_TLBI_VAE3IS_Xt: 1366 case MISCREG_TLBI_VALE3IS_Xt: 1367 { 1368 assert64(tc); 1369 1370 TLBIMVA tlbiOp(EL3, true, 1371 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1372 0xbeef); 1373 1374 tlbiOp.broadcast(tc); 1375 return; 1376 } 1377 // AArch64 TLB Invalidate by VA, EL2 1378 case MISCREG_TLBI_VAE2_Xt: 1379 case MISCREG_TLBI_VALE2_Xt: 1380 { 1381 assert64(tc); 1382 scr = readMiscReg(MISCREG_SCR, tc); 1383 1384 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1385 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1386 0xbeef); 1387 tlbiOp(tc); 1388 return; 1389 } 1390 // AArch64 TLB Invalidate by VA, EL2, Inner Shareable 1391 case MISCREG_TLBI_VAE2IS_Xt: 1392 case MISCREG_TLBI_VALE2IS_Xt: 1393 { 1394 assert64(tc); 1395 scr = readMiscReg(MISCREG_SCR, tc); 1396 1397 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1398 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1399 0xbeef); 1400 1401 tlbiOp.broadcast(tc); 1402 return; 1403 } 1404 // AArch64 TLB Invalidate by VA, EL1 1405 case MISCREG_TLBI_VAE1_Xt: 1406 case MISCREG_TLBI_VALE1_Xt: 1407 { 1408 assert64(tc); 1409 scr = readMiscReg(MISCREG_SCR, tc); 1410 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1411 bits(newVal, 55, 48); 1412 1413 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1414 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1415 asid); 1416 1417 tlbiOp(tc); 1418 return; 1419 } 1420 // AArch64 TLB Invalidate by VA, EL1, Inner Shareable 1421 case MISCREG_TLBI_VAE1IS_Xt: 1422 case MISCREG_TLBI_VALE1IS_Xt: 1423 { 1424 assert64(tc); 1425 scr = readMiscReg(MISCREG_SCR, tc); 1426 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1427 bits(newVal, 55, 48); 1428 1429 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1430 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1431 asid); 1432 1433 tlbiOp.broadcast(tc); 1434 return; 1435 } 1436 // AArch64 TLB Invalidate by ASID, EL1 1437 // @todo: handle VMID to enable Virtualization 1438 case MISCREG_TLBI_ASIDE1_Xt: 1439 { 1440 assert64(tc); 1441 scr = readMiscReg(MISCREG_SCR, tc); 1442 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1443 bits(newVal, 55, 48); 1444 1445 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1446 tlbiOp(tc); 1447 return; 1448 } 1449 // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable 1450 case MISCREG_TLBI_ASIDE1IS_Xt: 1451 { 1452 assert64(tc); 1453 scr = readMiscReg(MISCREG_SCR, tc); 1454 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1455 bits(newVal, 55, 48); 1456 1457 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1458 tlbiOp.broadcast(tc); 1459 return; 1460 } 1461 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 1462 // entries from the last level of translation table walks 1463 // AArch64 TLB Invalidate by VA, All ASID, EL1 1464 case MISCREG_TLBI_VAAE1_Xt: 1465 case MISCREG_TLBI_VAALE1_Xt: 1466 { 1467 assert64(tc); 1468 scr = readMiscReg(MISCREG_SCR, tc); 1469 1470 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1471 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 1472 1473 tlbiOp(tc); 1474 return; 1475 } 1476 // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable 1477 case MISCREG_TLBI_VAAE1IS_Xt: 1478 case MISCREG_TLBI_VAALE1IS_Xt: 1479 { 1480 assert64(tc); 1481 scr = readMiscReg(MISCREG_SCR, tc); 1482 1483 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1484 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 1485 1486 tlbiOp.broadcast(tc); 1487 return; 1488 } 1489 // AArch64 TLB Invalidate by Intermediate Physical Address, 1490 // Stage 2, EL1 1491 case MISCREG_TLBI_IPAS2E1_Xt: 1492 case MISCREG_TLBI_IPAS2LE1_Xt: 1493 { 1494 assert64(tc); 1495 scr = readMiscReg(MISCREG_SCR, tc); 1496 1497 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1498 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1499 1500 tlbiOp(tc); 1501 return; 1502 } 1503 // AArch64 TLB Invalidate by Intermediate Physical Address, 1504 // Stage 2, EL1, Inner Shareable 1505 case MISCREG_TLBI_IPAS2E1IS_Xt: 1506 case MISCREG_TLBI_IPAS2LE1IS_Xt: 1507 { 1508 assert64(tc); 1509 scr = readMiscReg(MISCREG_SCR, tc); 1510 1511 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1512 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1513 1514 tlbiOp.broadcast(tc); 1515 return; 1516 } 1517 case MISCREG_ACTLR: 1518 warn("Not doing anything for write of miscreg ACTLR\n"); 1519 break; 1520 1521 case MISCREG_PMXEVTYPER_PMCCFILTR: 1522 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 1523 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 1524 case MISCREG_PMCR ... MISCREG_PMOVSSET: 1525 pmu->setMiscReg(misc_reg, newVal); 1526 break; 1527 1528 1529 case MISCREG_HSTR: // TJDBX, now redifined to be RES0 1530 { 1531 HSTR hstrMask = 0; 1532 hstrMask.tjdbx = 1; 1533 newVal &= ~((uint32_t) hstrMask); 1534 break; 1535 } 1536 case MISCREG_HCPTR: 1537 { 1538 // If a CP bit in NSACR is 0 then the corresponding bit in 1539 // HCPTR is RAO/WI. Same applies to NSASEDIS 1540 secure_lookup = haveSecurity && 1541 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 1542 readMiscRegNoEffect(MISCREG_CPSR)); 1543 if (!secure_lookup) { 1544 MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 1545 MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 1546 newVal = (newVal & ~mask) | (oldValue & mask); 1547 } 1548 break; 1549 } 1550 case MISCREG_HDFAR: // alias for secure DFAR 1551 misc_reg = MISCREG_DFAR_S; 1552 break; 1553 case MISCREG_HIFAR: // alias for secure IFAR 1554 misc_reg = MISCREG_IFAR_S; 1555 break; 1556 case MISCREG_ATS1CPR: 1557 case MISCREG_ATS1CPW: 1558 case MISCREG_ATS1CUR: 1559 case MISCREG_ATS1CUW: 1560 case MISCREG_ATS12NSOPR: 1561 case MISCREG_ATS12NSOPW: 1562 case MISCREG_ATS12NSOUR: 1563 case MISCREG_ATS12NSOUW: 1564 case MISCREG_ATS1HR: 1565 case MISCREG_ATS1HW: 1566 { 1567 Request::Flags flags = 0; 1568 BaseTLB::Mode mode = BaseTLB::Read; 1569 TLB::ArmTranslationType tranType = TLB::NormalTran; 1570 Fault fault; 1571 switch(misc_reg) { 1572 case MISCREG_ATS1CPR: 1573 flags = TLB::MustBeOne; 1574 tranType = TLB::S1CTran; 1575 mode = BaseTLB::Read; 1576 break; 1577 case MISCREG_ATS1CPW: 1578 flags = TLB::MustBeOne; 1579 tranType = TLB::S1CTran; 1580 mode = BaseTLB::Write; 1581 break; 1582 case MISCREG_ATS1CUR: 1583 flags = TLB::MustBeOne | TLB::UserMode; 1584 tranType = TLB::S1CTran; 1585 mode = BaseTLB::Read; 1586 break; 1587 case MISCREG_ATS1CUW: 1588 flags = TLB::MustBeOne | TLB::UserMode; 1589 tranType = TLB::S1CTran; 1590 mode = BaseTLB::Write; 1591 break; 1592 case MISCREG_ATS12NSOPR: 1593 if (!haveSecurity) 1594 panic("Security Extensions required for ATS12NSOPR"); 1595 flags = TLB::MustBeOne; 1596 tranType = TLB::S1S2NsTran; 1597 mode = BaseTLB::Read; 1598 break; 1599 case MISCREG_ATS12NSOPW: 1600 if (!haveSecurity) 1601 panic("Security Extensions required for ATS12NSOPW"); 1602 flags = TLB::MustBeOne; 1603 tranType = TLB::S1S2NsTran; 1604 mode = BaseTLB::Write; 1605 break; 1606 case MISCREG_ATS12NSOUR: 1607 if (!haveSecurity) 1608 panic("Security Extensions required for ATS12NSOUR"); 1609 flags = TLB::MustBeOne | TLB::UserMode; 1610 tranType = TLB::S1S2NsTran; 1611 mode = BaseTLB::Read; 1612 break; 1613 case MISCREG_ATS12NSOUW: 1614 if (!haveSecurity) 1615 panic("Security Extensions required for ATS12NSOUW"); 1616 flags = TLB::MustBeOne | TLB::UserMode; 1617 tranType = TLB::S1S2NsTran; 1618 mode = BaseTLB::Write; 1619 break; 1620 case MISCREG_ATS1HR: // only really useful from secure mode. 1621 flags = TLB::MustBeOne; 1622 tranType = TLB::HypMode; 1623 mode = BaseTLB::Read; 1624 break; 1625 case MISCREG_ATS1HW: 1626 flags = TLB::MustBeOne; 1627 tranType = TLB::HypMode; 1628 mode = BaseTLB::Write; 1629 break; 1630 } 1631 // If we're in timing mode then doing the translation in 1632 // functional mode then we're slightly distorting performance 1633 // results obtained from simulations. The translation should be 1634 // done in the same mode the core is running in. NOTE: This 1635 // can't be an atomic translation because that causes problems 1636 // with unexpected atomic snoop requests. 1637 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1638 1639 auto req = std::make_shared<Request>( 1640 0, val, 0, flags, Request::funcMasterId, 1641 tc->pcState().pc(), tc->contextId()); 1642 1643 fault = getDTBPtr(tc)->translateFunctional( 1644 req, tc, mode, tranType); 1645 1646 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1647 HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 1648 1649 MiscReg newVal; 1650 if (fault == NoFault) { 1651 Addr paddr = req->getPaddr(); 1652 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 1653 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 1654 newVal = (paddr & mask(39, 12)) | 1655 (getDTBPtr(tc)->getAttr()); 1656 } else { 1657 newVal = (paddr & 0xfffff000) | 1658 (getDTBPtr(tc)->getAttr()); 1659 } 1660 DPRINTF(MiscRegs, 1661 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 1662 val, newVal); 1663 } else { 1664 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1665 armFault->update(tc); 1666 // Set fault bit and FSR 1667 FSR fsr = armFault->getFsr(tc); 1668 1669 newVal = ((fsr >> 9) & 1) << 11; 1670 if (newVal) { 1671 // LPAE - rearange fault status 1672 newVal |= ((fsr >> 0) & 0x3f) << 1; 1673 } else { 1674 // VMSA - rearange fault status 1675 newVal |= ((fsr >> 0) & 0xf) << 1; 1676 newVal |= ((fsr >> 10) & 0x1) << 5; 1677 newVal |= ((fsr >> 12) & 0x1) << 6; 1678 } 1679 newVal |= 0x1; // F bit 1680 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1681 newVal |= armFault->isStage2() ? 0x200 : 0; 1682 DPRINTF(MiscRegs, 1683 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 1684 val, fsr, newVal); 1685 } 1686 setMiscRegNoEffect(MISCREG_PAR, newVal); 1687 return; 1688 } 1689 case MISCREG_TTBCR: 1690 { 1691 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1692 const uint32_t ones = (uint32_t)(-1); 1693 TTBCR ttbcrMask = 0; 1694 TTBCR ttbcrNew = newVal; 1695 1696 // ARM DDI 0406C.b, ARMv7-32 1697 ttbcrMask.n = ones; // T0SZ 1698 if (haveSecurity) { 1699 ttbcrMask.pd0 = ones; 1700 ttbcrMask.pd1 = ones; 1701 } 1702 ttbcrMask.epd0 = ones; 1703 ttbcrMask.irgn0 = ones; 1704 ttbcrMask.orgn0 = ones; 1705 ttbcrMask.sh0 = ones; 1706 ttbcrMask.ps = ones; // T1SZ 1707 ttbcrMask.a1 = ones; 1708 ttbcrMask.epd1 = ones; 1709 ttbcrMask.irgn1 = ones; 1710 ttbcrMask.orgn1 = ones; 1711 ttbcrMask.sh1 = ones; 1712 if (haveLPAE) 1713 ttbcrMask.eae = ones; 1714 1715 if (haveLPAE && ttbcrNew.eae) { 1716 newVal = newVal & ttbcrMask; 1717 } else { 1718 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 1719 } 1720 // Invalidate TLB MiscReg 1721 getITBPtr(tc)->invalidateMiscReg(); 1722 getDTBPtr(tc)->invalidateMiscReg(); 1723 break; 1724 } 1725 case MISCREG_TTBR0: 1726 case MISCREG_TTBR1: 1727 { 1728 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1729 if (haveLPAE) { 1730 if (ttbcr.eae) { 1731 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 1732 // ARMv8 AArch32 bit 63-56 only 1733 uint64_t ttbrMask = mask(63,56) | mask(47,40); 1734 newVal = (newVal & (~ttbrMask)); 1735 } 1736 } 1737 // Invalidate TLB MiscReg 1738 getITBPtr(tc)->invalidateMiscReg(); 1739 getDTBPtr(tc)->invalidateMiscReg(); 1740 break; 1741 } 1742 case MISCREG_SCTLR_EL1: 1743 case MISCREG_CONTEXTIDR: 1744 case MISCREG_PRRR: 1745 case MISCREG_NMRR: 1746 case MISCREG_MAIR0: 1747 case MISCREG_MAIR1: 1748 case MISCREG_DACR: 1749 case MISCREG_VTTBR: 1750 case MISCREG_SCR_EL3: 1751 case MISCREG_HCR_EL2: 1752 case MISCREG_TCR_EL1: 1753 case MISCREG_TCR_EL2: 1754 case MISCREG_TCR_EL3: 1755 case MISCREG_SCTLR_EL2: 1756 case MISCREG_SCTLR_EL3: 1757 case MISCREG_HSCTLR: 1758 case MISCREG_TTBR0_EL1: 1759 case MISCREG_TTBR1_EL1: 1760 case MISCREG_TTBR0_EL2: 1761 case MISCREG_TTBR1_EL2: 1762 case MISCREG_TTBR0_EL3: 1763 getITBPtr(tc)->invalidateMiscReg(); 1764 getDTBPtr(tc)->invalidateMiscReg(); 1765 break; 1766 case MISCREG_NZCV: 1767 { 1768 CPSR cpsr = val; 1769 1770 tc->setCCReg(CCREG_NZ, cpsr.nz); 1771 tc->setCCReg(CCREG_C, cpsr.c); 1772 tc->setCCReg(CCREG_V, cpsr.v); 1773 } 1774 break; 1775 case MISCREG_DAIF: 1776 { 1777 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1778 cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 1779 newVal = cpsr; 1780 misc_reg = MISCREG_CPSR; 1781 } 1782 break; 1783 case MISCREG_SP_EL0: 1784 tc->setIntReg(INTREG_SP0, newVal); 1785 break; 1786 case MISCREG_SP_EL1: 1787 tc->setIntReg(INTREG_SP1, newVal); 1788 break; 1789 case MISCREG_SP_EL2: 1790 tc->setIntReg(INTREG_SP2, newVal); 1791 break; 1792 case MISCREG_SPSEL: 1793 { 1794 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1795 cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 1796 newVal = cpsr; 1797 misc_reg = MISCREG_CPSR; 1798 } 1799 break; 1800 case MISCREG_CURRENTEL: 1801 { 1802 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1803 cpsr.el = (uint8_t) ((CPSR) newVal).el; 1804 newVal = cpsr; 1805 misc_reg = MISCREG_CPSR; 1806 } 1807 break; 1808 case MISCREG_AT_S1E1R_Xt: 1809 case MISCREG_AT_S1E1W_Xt: 1810 case MISCREG_AT_S1E0R_Xt: 1811 case MISCREG_AT_S1E0W_Xt: 1812 case MISCREG_AT_S1E2R_Xt: 1813 case MISCREG_AT_S1E2W_Xt: 1814 case MISCREG_AT_S12E1R_Xt: 1815 case MISCREG_AT_S12E1W_Xt: 1816 case MISCREG_AT_S12E0R_Xt: 1817 case MISCREG_AT_S12E0W_Xt: 1818 case MISCREG_AT_S1E3R_Xt: 1819 case MISCREG_AT_S1E3W_Xt: 1820 { 1821 RequestPtr req = std::make_shared<Request>(); 1822 Request::Flags flags = 0; 1823 BaseTLB::Mode mode = BaseTLB::Read; 1824 TLB::ArmTranslationType tranType = TLB::NormalTran; 1825 Fault fault; 1826 switch(misc_reg) { 1827 case MISCREG_AT_S1E1R_Xt: 1828 flags = TLB::MustBeOne; 1829 tranType = TLB::S1E1Tran; 1830 mode = BaseTLB::Read; 1831 break; 1832 case MISCREG_AT_S1E1W_Xt: 1833 flags = TLB::MustBeOne; 1834 tranType = TLB::S1E1Tran; 1835 mode = BaseTLB::Write; 1836 break; 1837 case MISCREG_AT_S1E0R_Xt: 1838 flags = TLB::MustBeOne | TLB::UserMode; 1839 tranType = TLB::S1E0Tran; 1840 mode = BaseTLB::Read; 1841 break; 1842 case MISCREG_AT_S1E0W_Xt: 1843 flags = TLB::MustBeOne | TLB::UserMode; 1844 tranType = TLB::S1E0Tran; 1845 mode = BaseTLB::Write; 1846 break; 1847 case MISCREG_AT_S1E2R_Xt: 1848 flags = TLB::MustBeOne; 1849 tranType = TLB::S1E2Tran; 1850 mode = BaseTLB::Read; 1851 break; 1852 case MISCREG_AT_S1E2W_Xt: 1853 flags = TLB::MustBeOne; 1854 tranType = TLB::S1E2Tran; 1855 mode = BaseTLB::Write; 1856 break; 1857 case MISCREG_AT_S12E0R_Xt: 1858 flags = TLB::MustBeOne | TLB::UserMode; 1859 tranType = TLB::S12E0Tran; 1860 mode = BaseTLB::Read; 1861 break; 1862 case MISCREG_AT_S12E0W_Xt: 1863 flags = TLB::MustBeOne | TLB::UserMode; 1864 tranType = TLB::S12E0Tran; 1865 mode = BaseTLB::Write; 1866 break; 1867 case MISCREG_AT_S12E1R_Xt: 1868 flags = TLB::MustBeOne; 1869 tranType = TLB::S12E1Tran; 1870 mode = BaseTLB::Read; 1871 break; 1872 case MISCREG_AT_S12E1W_Xt: 1873 flags = TLB::MustBeOne; 1874 tranType = TLB::S12E1Tran; 1875 mode = BaseTLB::Write; 1876 break; 1877 case MISCREG_AT_S1E3R_Xt: 1878 flags = TLB::MustBeOne; 1879 tranType = TLB::S1E3Tran; 1880 mode = BaseTLB::Read; 1881 break; 1882 case MISCREG_AT_S1E3W_Xt: 1883 flags = TLB::MustBeOne; 1884 tranType = TLB::S1E3Tran; 1885 mode = BaseTLB::Write; 1886 break; 1887 } 1888 // If we're in timing mode then doing the translation in 1889 // functional mode then we're slightly distorting performance 1890 // results obtained from simulations. The translation should be 1891 // done in the same mode the core is running in. NOTE: This 1892 // can't be an atomic translation because that causes problems 1893 // with unexpected atomic snoop requests. 1894 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1895 req->setVirt(0, val, 0, flags, Request::funcMasterId, 1896 tc->pcState().pc()); 1897 req->setContext(tc->contextId()); 1898 fault = getDTBPtr(tc)->translateFunctional(req, tc, mode, 1899 tranType); 1900 1901 MiscReg newVal; 1902 if (fault == NoFault) { 1903 Addr paddr = req->getPaddr(); 1904 uint64_t attr = getDTBPtr(tc)->getAttr(); 1905 uint64_t attr1 = attr >> 56; 1906 if (!attr1 || attr1 ==0x44) { 1907 attr |= 0x100; 1908 attr &= ~ uint64_t(0x80); 1909 } 1910 newVal = (paddr & mask(47, 12)) | attr; 1911 DPRINTF(MiscRegs, 1912 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 1913 val, newVal); 1914 } else { 1915 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1916 armFault->update(tc); 1917 // Set fault bit and FSR 1918 FSR fsr = armFault->getFsr(tc); 1919 1920 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1921 if (cpsr.width) { // AArch32 1922 newVal = ((fsr >> 9) & 1) << 11; 1923 // rearrange fault status 1924 newVal |= ((fsr >> 0) & 0x3f) << 1; 1925 newVal |= 0x1; // F bit 1926 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1927 newVal |= armFault->isStage2() ? 0x200 : 0; 1928 } else { // AArch64 1929 newVal = 1; // F bit 1930 newVal |= fsr << 1; // FST 1931 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit. 1932 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 1933 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 1934 newVal |= 1 << 11; // RES1 1935 } 1936 DPRINTF(MiscRegs, 1937 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 1938 val, fsr, newVal); 1939 } 1940 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 1941 return; 1942 } 1943 case MISCREG_SPSR_EL3: 1944 case MISCREG_SPSR_EL2: 1945 case MISCREG_SPSR_EL1: 1946 // Force bits 23:21 to 0 1947 newVal = val & ~(0x7 << 21); 1948 break; 1949 case MISCREG_L2CTLR: 1950 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 1951 miscRegName[misc_reg], uint32_t(val)); 1952 break; 1953 1954 // Generic Timer registers 1955 case MISCREG_CNTHV_CTL_EL2: 1956 case MISCREG_CNTHV_CVAL_EL2: 1957 case MISCREG_CNTHV_TVAL_EL2: 1958 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 1959 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 1960 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 1961 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 1962 getGenericTimer(tc).setMiscReg(misc_reg, newVal); 1963 break; 1964 } 1965 } 1966 setMiscRegNoEffect(misc_reg, newVal); 1967} 1968 1969BaseISADevice & 1970ISA::getGenericTimer(ThreadContext *tc) 1971{ 1972 // We only need to create an ISA interface the first time we try 1973 // to access the timer. 1974 if (timer) 1975 return *timer.get(); 1976 1977 assert(system); 1978 GenericTimer *generic_timer(system->getGenericTimer()); 1979 if (!generic_timer) { 1980 panic("Trying to get a generic timer from a system that hasn't " 1981 "been configured to use a generic timer.\n"); 1982 } 1983 1984 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 1985 timer->setThreadContext(tc); 1986 1987 return *timer.get(); 1988} 1989 1990} 1991 1992ArmISA::ISA * 1993ArmISAParams::create() 1994{ 1995 return new ArmISA::ISA(this); 1996} 1997