isa.cc revision 13114:777d445423d6
1/* 2 * Copyright (c) 2010-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 */ 40 41#include "arch/arm/isa.hh" 42#include "arch/arm/pmu.hh" 43#include "arch/arm/system.hh" 44#include "arch/arm/tlb.hh" 45#include "arch/arm/tlbi_op.hh" 46#include "cpu/base.hh" 47#include "cpu/checker/cpu.hh" 48#include "debug/Arm.hh" 49#include "debug/MiscRegs.hh" 50#include "dev/arm/generic_timer.hh" 51#include "params/ArmISA.hh" 52#include "sim/faults.hh" 53#include "sim/stat_control.hh" 54#include "sim/system.hh" 55 56namespace ArmISA 57{ 58 59ISA::ISA(Params *p) 60 : SimObject(p), 61 system(NULL), 62 _decoderFlavour(p->decoderFlavour), 63 _vecRegRenameMode(p->vecRegRenameMode), 64 pmu(p->pmu), 65 impdefAsNop(p->impdef_nop) 66{ 67 miscRegs[MISCREG_SCTLR_RST] = 0; 68 69 // Hook up a dummy device if we haven't been configured with a 70 // real PMU. By using a dummy device, we don't need to check that 71 // the PMU exist every time we try to access a PMU register. 72 if (!pmu) 73 pmu = &dummyDevice; 74 75 // Give all ISA devices a pointer to this ISA 76 pmu->setISA(this); 77 78 system = dynamic_cast<ArmSystem *>(p->system); 79 80 // Cache system-level properties 81 if (FullSystem && system) { 82 highestELIs64 = system->highestELIs64(); 83 haveSecurity = system->haveSecurity(); 84 haveLPAE = system->haveLPAE(); 85 haveVirtualization = system->haveVirtualization(); 86 haveLargeAsid64 = system->haveLargeAsid64(); 87 physAddrRange = system->physAddrRange(); 88 } else { 89 highestELIs64 = true; // ArmSystem::highestELIs64 does the same 90 haveSecurity = haveLPAE = haveVirtualization = false; 91 haveLargeAsid64 = false; 92 physAddrRange = 32; // dummy value 93 } 94 95 initializeMiscRegMetadata(); 96 preUnflattenMiscReg(); 97 98 clear(); 99} 100 101std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS); 102 103const ArmISAParams * 104ISA::params() const 105{ 106 return dynamic_cast<const Params *>(_params); 107} 108 109void 110ISA::clear() 111{ 112 const Params *p(params()); 113 114 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 115 memset(miscRegs, 0, sizeof(miscRegs)); 116 117 initID32(p); 118 119 // We always initialize AArch64 ID registers even 120 // if we are in AArch32. This is done since if we 121 // are in SE mode we don't know if our ArmProcess is 122 // AArch32 or AArch64 123 initID64(p); 124 125 if (FullSystem && system->highestELIs64()) { 126 // Initialize AArch64 state 127 clear64(p); 128 return; 129 } 130 131 // Initialize AArch32 state... 132 133 CPSR cpsr = 0; 134 cpsr.mode = MODE_USER; 135 miscRegs[MISCREG_CPSR] = cpsr; 136 updateRegMap(cpsr); 137 138 SCTLR sctlr = 0; 139 sctlr.te = (bool) sctlr_rst.te; 140 sctlr.nmfi = (bool) sctlr_rst.nmfi; 141 sctlr.v = (bool) sctlr_rst.v; 142 sctlr.u = 1; 143 sctlr.xp = 1; 144 sctlr.rao2 = 1; 145 sctlr.rao3 = 1; 146 sctlr.rao4 = 0xf; // SCTLR[6:3] 147 sctlr.uci = 1; 148 sctlr.dze = 1; 149 miscRegs[MISCREG_SCTLR_NS] = sctlr; 150 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 151 miscRegs[MISCREG_HCPTR] = 0; 152 153 // Start with an event in the mailbox 154 miscRegs[MISCREG_SEV_MAILBOX] = 1; 155 156 // Separate Instruction and Data TLBs 157 miscRegs[MISCREG_TLBTR] = 1; 158 159 MVFR0 mvfr0 = 0; 160 mvfr0.advSimdRegisters = 2; 161 mvfr0.singlePrecision = 2; 162 mvfr0.doublePrecision = 2; 163 mvfr0.vfpExceptionTrapping = 0; 164 mvfr0.divide = 1; 165 mvfr0.squareRoot = 1; 166 mvfr0.shortVectors = 1; 167 mvfr0.roundingModes = 1; 168 miscRegs[MISCREG_MVFR0] = mvfr0; 169 170 MVFR1 mvfr1 = 0; 171 mvfr1.flushToZero = 1; 172 mvfr1.defaultNaN = 1; 173 mvfr1.advSimdLoadStore = 1; 174 mvfr1.advSimdInteger = 1; 175 mvfr1.advSimdSinglePrecision = 1; 176 mvfr1.advSimdHalfPrecision = 1; 177 mvfr1.vfpHalfPrecision = 1; 178 miscRegs[MISCREG_MVFR1] = mvfr1; 179 180 // Reset values of PRRR and NMRR are implementation dependent 181 182 // @todo: PRRR and NMRR in secure state? 183 miscRegs[MISCREG_PRRR_NS] = 184 (1 << 19) | // 19 185 (0 << 18) | // 18 186 (0 << 17) | // 17 187 (1 << 16) | // 16 188 (2 << 14) | // 15:14 189 (0 << 12) | // 13:12 190 (2 << 10) | // 11:10 191 (2 << 8) | // 9:8 192 (2 << 6) | // 7:6 193 (2 << 4) | // 5:4 194 (1 << 2) | // 3:2 195 0; // 1:0 196 miscRegs[MISCREG_NMRR_NS] = 197 (1 << 30) | // 31:30 198 (0 << 26) | // 27:26 199 (0 << 24) | // 25:24 200 (3 << 22) | // 23:22 201 (2 << 20) | // 21:20 202 (0 << 18) | // 19:18 203 (0 << 16) | // 17:16 204 (1 << 14) | // 15:14 205 (0 << 12) | // 13:12 206 (2 << 10) | // 11:10 207 (0 << 8) | // 9:8 208 (3 << 6) | // 7:6 209 (2 << 4) | // 5:4 210 (0 << 2) | // 3:2 211 0; // 1:0 212 213 miscRegs[MISCREG_CPACR] = 0; 214 215 miscRegs[MISCREG_FPSID] = p->fpsid; 216 217 if (haveLPAE) { 218 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 219 ttbcr.eae = 0; 220 miscRegs[MISCREG_TTBCR_NS] = ttbcr; 221 // Enforce consistency with system-level settings 222 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 223 } 224 225 if (haveSecurity) { 226 miscRegs[MISCREG_SCTLR_S] = sctlr; 227 miscRegs[MISCREG_SCR] = 0; 228 miscRegs[MISCREG_VBAR_S] = 0; 229 } else { 230 // we're always non-secure 231 miscRegs[MISCREG_SCR] = 1; 232 } 233 234 //XXX We need to initialize the rest of the state. 235} 236 237void 238ISA::clear64(const ArmISAParams *p) 239{ 240 CPSR cpsr = 0; 241 Addr rvbar = system->resetAddr64(); 242 switch (system->highestEL()) { 243 // Set initial EL to highest implemented EL using associated stack 244 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 245 // value 246 case EL3: 247 cpsr.mode = MODE_EL3H; 248 miscRegs[MISCREG_RVBAR_EL3] = rvbar; 249 break; 250 case EL2: 251 cpsr.mode = MODE_EL2H; 252 miscRegs[MISCREG_RVBAR_EL2] = rvbar; 253 break; 254 case EL1: 255 cpsr.mode = MODE_EL1H; 256 miscRegs[MISCREG_RVBAR_EL1] = rvbar; 257 break; 258 default: 259 panic("Invalid highest implemented exception level"); 260 break; 261 } 262 263 // Initialize rest of CPSR 264 cpsr.daif = 0xf; // Mask all interrupts 265 cpsr.ss = 0; 266 cpsr.il = 0; 267 miscRegs[MISCREG_CPSR] = cpsr; 268 updateRegMap(cpsr); 269 270 // Initialize other control registers 271 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 272 if (haveSecurity) { 273 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830; 274 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 275 } else if (haveVirtualization) { 276 // also MISCREG_SCTLR_EL2 (by mapping) 277 miscRegs[MISCREG_HSCTLR] = 0x30c50830; 278 } else { 279 // also MISCREG_SCTLR_EL1 (by mapping) 280 miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init 281 // Always non-secure 282 miscRegs[MISCREG_SCR_EL3] = 1; 283 } 284} 285 286void 287ISA::initID32(const ArmISAParams *p) 288{ 289 // Initialize configurable default values 290 miscRegs[MISCREG_MIDR] = p->midr; 291 miscRegs[MISCREG_MIDR_EL1] = p->midr; 292 miscRegs[MISCREG_VPIDR] = p->midr; 293 294 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 295 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 296 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 297 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 298 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 299 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 300 301 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 302 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 303 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 304 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 305} 306 307void 308ISA::initID64(const ArmISAParams *p) 309{ 310 // Initialize configurable id registers 311 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 312 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 313 miscRegs[MISCREG_ID_AA64DFR0_EL1] = 314 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 315 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 316 317 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 318 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 319 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 320 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 321 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 322 323 miscRegs[MISCREG_ID_DFR0_EL1] = 324 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 325 326 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 327 328 // Enforce consistency with system-level settings... 329 330 // EL3 331 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 332 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 333 haveSecurity ? 0x2 : 0x0); 334 // EL2 335 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 336 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 337 haveVirtualization ? 0x2 : 0x0); 338 // Large ASID support 339 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 340 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 341 haveLargeAsid64 ? 0x2 : 0x0); 342 // Physical address size 343 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 344 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 345 encodePhysAddrRange64(physAddrRange)); 346} 347 348void 349ISA::startup(ThreadContext *tc) 350{ 351 pmu->setThreadContext(tc); 352 353} 354 355 356MiscReg 357ISA::readMiscRegNoEffect(int misc_reg) const 358{ 359 assert(misc_reg < NumMiscRegs); 360 361 const auto ® = lookUpMiscReg[misc_reg]; // bit masks 362 const auto &map = getMiscIndices(misc_reg); 363 int lower = map.first, upper = map.second; 364 // NB!: apply architectural masks according to desired register, 365 // despite possibly getting value from different (mapped) register. 366 auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32)) 367 |(miscRegs[upper] << 32)); 368 if (val & reg.res0()) { 369 DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n", 370 miscRegName[misc_reg], val & reg.res0()); 371 } 372 if ((val & reg.res1()) != reg.res1()) { 373 DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n", 374 miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1()); 375 } 376 return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao 377} 378 379 380MiscReg 381ISA::readMiscReg(int misc_reg, ThreadContext *tc) 382{ 383 CPSR cpsr = 0; 384 PCState pc = 0; 385 SCR scr = 0; 386 387 if (misc_reg == MISCREG_CPSR) { 388 cpsr = miscRegs[misc_reg]; 389 pc = tc->pcState(); 390 cpsr.j = pc.jazelle() ? 1 : 0; 391 cpsr.t = pc.thumb() ? 1 : 0; 392 return cpsr; 393 } 394 395#ifndef NDEBUG 396 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 397 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 398 warn("Unimplemented system register %s read.\n", 399 miscRegName[misc_reg]); 400 else 401 panic("Unimplemented system register %s read.\n", 402 miscRegName[misc_reg]); 403 } 404#endif 405 406 switch (unflattenMiscReg(misc_reg)) { 407 case MISCREG_HCR: 408 { 409 if (!haveVirtualization) 410 return 0; 411 else 412 return readMiscRegNoEffect(MISCREG_HCR); 413 } 414 case MISCREG_CPACR: 415 { 416 const uint32_t ones = (uint32_t)(-1); 417 CPACR cpacrMask = 0; 418 // Only cp10, cp11, and ase are implemented, nothing else should 419 // be readable? (straight copy from the write code) 420 cpacrMask.cp10 = ones; 421 cpacrMask.cp11 = ones; 422 cpacrMask.asedis = ones; 423 424 // Security Extensions may limit the readability of CPACR 425 if (haveSecurity) { 426 scr = readMiscRegNoEffect(MISCREG_SCR); 427 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 428 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 429 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 430 // NB: Skipping the full loop, here 431 if (!nsacr.cp10) cpacrMask.cp10 = 0; 432 if (!nsacr.cp11) cpacrMask.cp11 = 0; 433 } 434 } 435 MiscReg val = readMiscRegNoEffect(MISCREG_CPACR); 436 val &= cpacrMask; 437 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 438 miscRegName[misc_reg], val); 439 return val; 440 } 441 case MISCREG_MPIDR: 442 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 443 scr = readMiscRegNoEffect(MISCREG_SCR); 444 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 445 return getMPIDR(system, tc); 446 } else { 447 return readMiscReg(MISCREG_VMPIDR, tc); 448 } 449 break; 450 case MISCREG_MPIDR_EL1: 451 // @todo in the absence of v8 virtualization support just return MPIDR_EL1 452 return getMPIDR(system, tc) & 0xffffffff; 453 case MISCREG_VMPIDR: 454 // top bit defined as RES1 455 return readMiscRegNoEffect(misc_reg) | 0x80000000; 456 case MISCREG_ID_AFR0: // not implemented, so alias MIDR 457 case MISCREG_REVIDR: // not implemented, so alias MIDR 458 case MISCREG_MIDR: 459 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 460 scr = readMiscRegNoEffect(MISCREG_SCR); 461 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 462 return readMiscRegNoEffect(misc_reg); 463 } else { 464 return readMiscRegNoEffect(MISCREG_VPIDR); 465 } 466 break; 467 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 468 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 469 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 470 case MISCREG_AIDR: // AUX ID set to 0 471 case MISCREG_TCMTR: // No TCM's 472 return 0; 473 474 case MISCREG_CLIDR: 475 warn_once("The clidr register always reports 0 caches.\n"); 476 warn_once("clidr LoUIS field of 0b001 to match current " 477 "ARM implementations.\n"); 478 return 0x00200000; 479 case MISCREG_CCSIDR: 480 warn_once("The ccsidr register isn't implemented and " 481 "always reads as 0.\n"); 482 break; 483 case MISCREG_CTR: // AArch32, ARMv7, top bit set 484 case MISCREG_CTR_EL0: // AArch64 485 { 486 //all caches have the same line size in gem5 487 //4 byte words in ARM 488 unsigned lineSizeWords = 489 tc->getSystemPtr()->cacheLineSize() / 4; 490 unsigned log2LineSizeWords = 0; 491 492 while (lineSizeWords >>= 1) { 493 ++log2LineSizeWords; 494 } 495 496 CTR ctr = 0; 497 //log2 of minimun i-cache line size (words) 498 ctr.iCacheLineSize = log2LineSizeWords; 499 //b11 - gem5 uses pipt 500 ctr.l1IndexPolicy = 0x3; 501 //log2 of minimum d-cache line size (words) 502 ctr.dCacheLineSize = log2LineSizeWords; 503 //log2 of max reservation size (words) 504 ctr.erg = log2LineSizeWords; 505 //log2 of max writeback size (words) 506 ctr.cwg = log2LineSizeWords; 507 //b100 - gem5 format is ARMv7 508 ctr.format = 0x4; 509 510 return ctr; 511 } 512 case MISCREG_ACTLR: 513 warn("Not doing anything for miscreg ACTLR\n"); 514 break; 515 516 case MISCREG_PMXEVTYPER_PMCCFILTR: 517 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 518 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 519 case MISCREG_PMCR ... MISCREG_PMOVSSET: 520 return pmu->readMiscReg(misc_reg); 521 522 case MISCREG_CPSR_Q: 523 panic("shouldn't be reading this register seperately\n"); 524 case MISCREG_FPSCR_QC: 525 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 526 case MISCREG_FPSCR_EXC: 527 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 528 case MISCREG_FPSR: 529 { 530 const uint32_t ones = (uint32_t)(-1); 531 FPSCR fpscrMask = 0; 532 fpscrMask.ioc = ones; 533 fpscrMask.dzc = ones; 534 fpscrMask.ofc = ones; 535 fpscrMask.ufc = ones; 536 fpscrMask.ixc = ones; 537 fpscrMask.idc = ones; 538 fpscrMask.qc = ones; 539 fpscrMask.v = ones; 540 fpscrMask.c = ones; 541 fpscrMask.z = ones; 542 fpscrMask.n = ones; 543 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 544 } 545 case MISCREG_FPCR: 546 { 547 const uint32_t ones = (uint32_t)(-1); 548 FPSCR fpscrMask = 0; 549 fpscrMask.len = ones; 550 fpscrMask.stride = ones; 551 fpscrMask.rMode = ones; 552 fpscrMask.fz = ones; 553 fpscrMask.dn = ones; 554 fpscrMask.ahp = ones; 555 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 556 } 557 case MISCREG_NZCV: 558 { 559 CPSR cpsr = 0; 560 cpsr.nz = tc->readCCReg(CCREG_NZ); 561 cpsr.c = tc->readCCReg(CCREG_C); 562 cpsr.v = tc->readCCReg(CCREG_V); 563 return cpsr; 564 } 565 case MISCREG_DAIF: 566 { 567 CPSR cpsr = 0; 568 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 569 return cpsr; 570 } 571 case MISCREG_SP_EL0: 572 { 573 return tc->readIntReg(INTREG_SP0); 574 } 575 case MISCREG_SP_EL1: 576 { 577 return tc->readIntReg(INTREG_SP1); 578 } 579 case MISCREG_SP_EL2: 580 { 581 return tc->readIntReg(INTREG_SP2); 582 } 583 case MISCREG_SPSEL: 584 { 585 return miscRegs[MISCREG_CPSR] & 0x1; 586 } 587 case MISCREG_CURRENTEL: 588 { 589 return miscRegs[MISCREG_CPSR] & 0xc; 590 } 591 case MISCREG_L2CTLR: 592 { 593 // mostly unimplemented, just set NumCPUs field from sim and return 594 L2CTLR l2ctlr = 0; 595 // b00:1CPU to b11:4CPUs 596 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 597 return l2ctlr; 598 } 599 case MISCREG_DBGDIDR: 600 /* For now just implement the version number. 601 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 602 */ 603 return 0x5 << 16; 604 case MISCREG_DBGDSCRint: 605 return 0; 606 case MISCREG_ISR: 607 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 608 readMiscRegNoEffect(MISCREG_HCR), 609 readMiscRegNoEffect(MISCREG_CPSR), 610 readMiscRegNoEffect(MISCREG_SCR)); 611 case MISCREG_ISR_EL1: 612 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 613 readMiscRegNoEffect(MISCREG_HCR_EL2), 614 readMiscRegNoEffect(MISCREG_CPSR), 615 readMiscRegNoEffect(MISCREG_SCR_EL3)); 616 case MISCREG_DCZID_EL0: 617 return 0x04; // DC ZVA clear 64-byte chunks 618 case MISCREG_HCPTR: 619 { 620 MiscReg val = readMiscRegNoEffect(misc_reg); 621 // The trap bit associated with CP14 is defined as RAZ 622 val &= ~(1 << 14); 623 // If a CP bit in NSACR is 0 then the corresponding bit in 624 // HCPTR is RAO/WI 625 bool secure_lookup = haveSecurity && 626 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 627 readMiscRegNoEffect(MISCREG_CPSR)); 628 if (!secure_lookup) { 629 MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR); 630 val |= (mask ^ 0x7FFF) & 0xBFFF; 631 } 632 // Set the bits for unimplemented coprocessors to RAO/WI 633 val |= 0x33FF; 634 return (val); 635 } 636 case MISCREG_HDFAR: // alias for secure DFAR 637 return readMiscRegNoEffect(MISCREG_DFAR_S); 638 case MISCREG_HIFAR: // alias for secure IFAR 639 return readMiscRegNoEffect(MISCREG_IFAR_S); 640 case MISCREG_HVBAR: // bottom bits reserved 641 return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0; 642 case MISCREG_SCTLR: 643 return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818; 644 case MISCREG_SCTLR_EL1: 645 return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800; 646 case MISCREG_SCTLR_EL2: 647 case MISCREG_SCTLR_EL3: 648 case MISCREG_HSCTLR: 649 return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; 650 651 case MISCREG_ID_PFR0: 652 // !ThumbEE | !Jazelle | Thumb | ARM 653 return 0x00000031; 654 case MISCREG_ID_PFR1: 655 { // Timer | Virti | !M Profile | TrustZone | ARMv4 656 bool haveTimer = (system->getGenericTimer() != NULL); 657 return 0x00000001 658 | (haveSecurity ? 0x00000010 : 0x0) 659 | (haveVirtualization ? 0x00001000 : 0x0) 660 | (haveTimer ? 0x00010000 : 0x0); 661 } 662 case MISCREG_ID_AA64PFR0_EL1: 663 return 0x0000000000000002 // AArch{64,32} supported at EL0 664 | 0x0000000000000020 // EL1 665 | (haveVirtualization ? 0x0000000000000200 : 0) // EL2 666 | (haveSecurity ? 0x0000000000002000 : 0); // EL3 667 case MISCREG_ID_AA64PFR1_EL1: 668 return 0; // bits [63:0] RES0 (reserved for future use) 669 670 // Generic Timer registers 671 case MISCREG_CNTHV_CTL_EL2: 672 case MISCREG_CNTHV_CVAL_EL2: 673 case MISCREG_CNTHV_TVAL_EL2: 674 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 675 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 676 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 677 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 678 return getGenericTimer(tc).readMiscReg(misc_reg); 679 680 default: 681 break; 682 683 } 684 return readMiscRegNoEffect(misc_reg); 685} 686 687void 688ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 689{ 690 assert(misc_reg < NumMiscRegs); 691 692 const auto ® = lookUpMiscReg[misc_reg]; // bit masks 693 const auto &map = getMiscIndices(misc_reg); 694 int lower = map.first, upper = map.second; 695 696 auto v = (val & ~reg.wi()) | reg.rao(); 697 if (upper > 0) { 698 miscRegs[lower] = bits(v, 31, 0); 699 miscRegs[upper] = bits(v, 63, 32); 700 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 701 misc_reg, lower, upper, v); 702 } else { 703 miscRegs[lower] = v; 704 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 705 misc_reg, lower, v); 706 } 707} 708 709void 710ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 711{ 712 713 MiscReg newVal = val; 714 bool secure_lookup; 715 SCR scr; 716 717 if (misc_reg == MISCREG_CPSR) { 718 updateRegMap(val); 719 720 721 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 722 int old_mode = old_cpsr.mode; 723 CPSR cpsr = val; 724 if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) { 725 getITBPtr(tc)->invalidateMiscReg(); 726 getDTBPtr(tc)->invalidateMiscReg(); 727 } 728 729 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 730 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 731 PCState pc = tc->pcState(); 732 pc.nextThumb(cpsr.t); 733 pc.nextJazelle(cpsr.j); 734 pc.illegalExec(cpsr.il == 1); 735 736 // Follow slightly different semantics if a CheckerCPU object 737 // is connected 738 CheckerCPU *checker = tc->getCheckerCpuPtr(); 739 if (checker) { 740 tc->pcStateNoRecord(pc); 741 } else { 742 tc->pcState(pc); 743 } 744 } else { 745#ifndef NDEBUG 746 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 747 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 748 warn("Unimplemented system register %s write with %#x.\n", 749 miscRegName[misc_reg], val); 750 else 751 panic("Unimplemented system register %s write with %#x.\n", 752 miscRegName[misc_reg], val); 753 } 754#endif 755 switch (unflattenMiscReg(misc_reg)) { 756 case MISCREG_CPACR: 757 { 758 759 const uint32_t ones = (uint32_t)(-1); 760 CPACR cpacrMask = 0; 761 // Only cp10, cp11, and ase are implemented, nothing else should 762 // be writable 763 cpacrMask.cp10 = ones; 764 cpacrMask.cp11 = ones; 765 cpacrMask.asedis = ones; 766 767 // Security Extensions may limit the writability of CPACR 768 if (haveSecurity) { 769 scr = readMiscRegNoEffect(MISCREG_SCR); 770 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 771 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 772 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 773 // NB: Skipping the full loop, here 774 if (!nsacr.cp10) cpacrMask.cp10 = 0; 775 if (!nsacr.cp11) cpacrMask.cp11 = 0; 776 } 777 } 778 779 MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR); 780 newVal &= cpacrMask; 781 newVal |= old_val & ~cpacrMask; 782 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 783 miscRegName[misc_reg], newVal); 784 } 785 break; 786 case MISCREG_CPTR_EL2: 787 { 788 const uint32_t ones = (uint32_t)(-1); 789 CPTR cptrMask = 0; 790 cptrMask.tcpac = ones; 791 cptrMask.tta = ones; 792 cptrMask.tfp = ones; 793 newVal &= cptrMask; 794 cptrMask = 0; 795 cptrMask.res1_13_12_el2 = ones; 796 cptrMask.res1_9_0_el2 = ones; 797 newVal |= cptrMask; 798 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 799 miscRegName[misc_reg], newVal); 800 } 801 break; 802 case MISCREG_CPTR_EL3: 803 { 804 const uint32_t ones = (uint32_t)(-1); 805 CPTR cptrMask = 0; 806 cptrMask.tcpac = ones; 807 cptrMask.tta = ones; 808 cptrMask.tfp = ones; 809 newVal &= cptrMask; 810 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 811 miscRegName[misc_reg], newVal); 812 } 813 break; 814 case MISCREG_CSSELR: 815 warn_once("The csselr register isn't implemented.\n"); 816 return; 817 818 case MISCREG_DC_ZVA_Xt: 819 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 820 return; 821 822 case MISCREG_FPSCR: 823 { 824 const uint32_t ones = (uint32_t)(-1); 825 FPSCR fpscrMask = 0; 826 fpscrMask.ioc = ones; 827 fpscrMask.dzc = ones; 828 fpscrMask.ofc = ones; 829 fpscrMask.ufc = ones; 830 fpscrMask.ixc = ones; 831 fpscrMask.idc = ones; 832 fpscrMask.ioe = ones; 833 fpscrMask.dze = ones; 834 fpscrMask.ofe = ones; 835 fpscrMask.ufe = ones; 836 fpscrMask.ixe = ones; 837 fpscrMask.ide = ones; 838 fpscrMask.len = ones; 839 fpscrMask.stride = ones; 840 fpscrMask.rMode = ones; 841 fpscrMask.fz = ones; 842 fpscrMask.dn = ones; 843 fpscrMask.ahp = ones; 844 fpscrMask.qc = ones; 845 fpscrMask.v = ones; 846 fpscrMask.c = ones; 847 fpscrMask.z = ones; 848 fpscrMask.n = ones; 849 newVal = (newVal & (uint32_t)fpscrMask) | 850 (readMiscRegNoEffect(MISCREG_FPSCR) & 851 ~(uint32_t)fpscrMask); 852 tc->getDecoderPtr()->setContext(newVal); 853 } 854 break; 855 case MISCREG_FPSR: 856 { 857 const uint32_t ones = (uint32_t)(-1); 858 FPSCR fpscrMask = 0; 859 fpscrMask.ioc = ones; 860 fpscrMask.dzc = ones; 861 fpscrMask.ofc = ones; 862 fpscrMask.ufc = ones; 863 fpscrMask.ixc = ones; 864 fpscrMask.idc = ones; 865 fpscrMask.qc = ones; 866 fpscrMask.v = ones; 867 fpscrMask.c = ones; 868 fpscrMask.z = ones; 869 fpscrMask.n = ones; 870 newVal = (newVal & (uint32_t)fpscrMask) | 871 (readMiscRegNoEffect(MISCREG_FPSCR) & 872 ~(uint32_t)fpscrMask); 873 misc_reg = MISCREG_FPSCR; 874 } 875 break; 876 case MISCREG_FPCR: 877 { 878 const uint32_t ones = (uint32_t)(-1); 879 FPSCR fpscrMask = 0; 880 fpscrMask.len = ones; 881 fpscrMask.stride = ones; 882 fpscrMask.rMode = ones; 883 fpscrMask.fz = ones; 884 fpscrMask.dn = ones; 885 fpscrMask.ahp = ones; 886 newVal = (newVal & (uint32_t)fpscrMask) | 887 (readMiscRegNoEffect(MISCREG_FPSCR) & 888 ~(uint32_t)fpscrMask); 889 misc_reg = MISCREG_FPSCR; 890 } 891 break; 892 case MISCREG_CPSR_Q: 893 { 894 assert(!(newVal & ~CpsrMaskQ)); 895 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 896 misc_reg = MISCREG_CPSR; 897 } 898 break; 899 case MISCREG_FPSCR_QC: 900 { 901 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 902 (newVal & FpscrQcMask); 903 misc_reg = MISCREG_FPSCR; 904 } 905 break; 906 case MISCREG_FPSCR_EXC: 907 { 908 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 909 (newVal & FpscrExcMask); 910 misc_reg = MISCREG_FPSCR; 911 } 912 break; 913 case MISCREG_FPEXC: 914 { 915 // vfpv3 architecture, section B.6.1 of DDI04068 916 // bit 29 - valid only if fpexc[31] is 0 917 const uint32_t fpexcMask = 0x60000000; 918 newVal = (newVal & fpexcMask) | 919 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 920 } 921 break; 922 case MISCREG_HCR: 923 { 924 if (!haveVirtualization) 925 return; 926 } 927 break; 928 case MISCREG_IFSR: 929 { 930 // ARM ARM (ARM DDI 0406C.b) B4.1.96 931 const uint32_t ifsrMask = 932 mask(31, 13) | mask(11, 11) | mask(8, 6); 933 newVal = newVal & ~ifsrMask; 934 } 935 break; 936 case MISCREG_DFSR: 937 { 938 // ARM ARM (ARM DDI 0406C.b) B4.1.52 939 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 940 newVal = newVal & ~dfsrMask; 941 } 942 break; 943 case MISCREG_AMAIR0: 944 case MISCREG_AMAIR1: 945 { 946 // ARM ARM (ARM DDI 0406C.b) B4.1.5 947 // Valid only with LPAE 948 if (!haveLPAE) 949 return; 950 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 951 } 952 break; 953 case MISCREG_SCR: 954 getITBPtr(tc)->invalidateMiscReg(); 955 getDTBPtr(tc)->invalidateMiscReg(); 956 break; 957 case MISCREG_SCTLR: 958 { 959 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 960 scr = readMiscRegNoEffect(MISCREG_SCR); 961 962 MiscRegIndex sctlr_idx; 963 if (haveSecurity && !highestELIs64 && !scr.ns) { 964 sctlr_idx = MISCREG_SCTLR_S; 965 } else { 966 sctlr_idx = MISCREG_SCTLR_NS; 967 } 968 969 SCTLR sctlr = miscRegs[sctlr_idx]; 970 SCTLR new_sctlr = newVal; 971 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 972 miscRegs[sctlr_idx] = (MiscReg)new_sctlr; 973 getITBPtr(tc)->invalidateMiscReg(); 974 getDTBPtr(tc)->invalidateMiscReg(); 975 } 976 case MISCREG_MIDR: 977 case MISCREG_ID_PFR0: 978 case MISCREG_ID_PFR1: 979 case MISCREG_ID_DFR0: 980 case MISCREG_ID_MMFR0: 981 case MISCREG_ID_MMFR1: 982 case MISCREG_ID_MMFR2: 983 case MISCREG_ID_MMFR3: 984 case MISCREG_ID_ISAR0: 985 case MISCREG_ID_ISAR1: 986 case MISCREG_ID_ISAR2: 987 case MISCREG_ID_ISAR3: 988 case MISCREG_ID_ISAR4: 989 case MISCREG_ID_ISAR5: 990 991 case MISCREG_MPIDR: 992 case MISCREG_FPSID: 993 case MISCREG_TLBTR: 994 case MISCREG_MVFR0: 995 case MISCREG_MVFR1: 996 997 case MISCREG_ID_AA64AFR0_EL1: 998 case MISCREG_ID_AA64AFR1_EL1: 999 case MISCREG_ID_AA64DFR0_EL1: 1000 case MISCREG_ID_AA64DFR1_EL1: 1001 case MISCREG_ID_AA64ISAR0_EL1: 1002 case MISCREG_ID_AA64ISAR1_EL1: 1003 case MISCREG_ID_AA64MMFR0_EL1: 1004 case MISCREG_ID_AA64MMFR1_EL1: 1005 case MISCREG_ID_AA64PFR0_EL1: 1006 case MISCREG_ID_AA64PFR1_EL1: 1007 // ID registers are constants. 1008 return; 1009 1010 // TLB Invalidate All 1011 case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 1012 { 1013 assert32(tc); 1014 scr = readMiscReg(MISCREG_SCR, tc); 1015 1016 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1017 tlbiOp(tc); 1018 return; 1019 } 1020 // TLB Invalidate All, Inner Shareable 1021 case MISCREG_TLBIALLIS: 1022 { 1023 assert32(tc); 1024 scr = readMiscReg(MISCREG_SCR, tc); 1025 1026 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1027 tlbiOp.broadcast(tc); 1028 return; 1029 } 1030 // Instruction TLB Invalidate All 1031 case MISCREG_ITLBIALL: 1032 { 1033 assert32(tc); 1034 scr = readMiscReg(MISCREG_SCR, tc); 1035 1036 ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1037 tlbiOp(tc); 1038 return; 1039 } 1040 // Data TLB Invalidate All 1041 case MISCREG_DTLBIALL: 1042 { 1043 assert32(tc); 1044 scr = readMiscReg(MISCREG_SCR, tc); 1045 1046 DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1047 tlbiOp(tc); 1048 return; 1049 } 1050 // TLB Invalidate by VA 1051 // mcr tlbimval(is) is invalidating all matching entries 1052 // regardless of the level of lookup, since in gem5 we cache 1053 // in the tlb the last level of lookup only. 1054 case MISCREG_TLBIMVA: 1055 case MISCREG_TLBIMVAL: 1056 { 1057 assert32(tc); 1058 scr = readMiscReg(MISCREG_SCR, tc); 1059 1060 TLBIMVA tlbiOp(EL1, 1061 haveSecurity && !scr.ns, 1062 mbits(newVal, 31, 12), 1063 bits(newVal, 7,0)); 1064 1065 tlbiOp(tc); 1066 return; 1067 } 1068 // TLB Invalidate by VA, Inner Shareable 1069 case MISCREG_TLBIMVAIS: 1070 case MISCREG_TLBIMVALIS: 1071 { 1072 assert32(tc); 1073 scr = readMiscReg(MISCREG_SCR, tc); 1074 1075 TLBIMVA tlbiOp(EL1, 1076 haveSecurity && !scr.ns, 1077 mbits(newVal, 31, 12), 1078 bits(newVal, 7,0)); 1079 1080 tlbiOp.broadcast(tc); 1081 return; 1082 } 1083 // TLB Invalidate by ASID match 1084 case MISCREG_TLBIASID: 1085 { 1086 assert32(tc); 1087 scr = readMiscReg(MISCREG_SCR, tc); 1088 1089 TLBIASID tlbiOp(EL1, 1090 haveSecurity && !scr.ns, 1091 bits(newVal, 7,0)); 1092 1093 tlbiOp(tc); 1094 return; 1095 } 1096 // TLB Invalidate by ASID match, Inner Shareable 1097 case MISCREG_TLBIASIDIS: 1098 { 1099 assert32(tc); 1100 scr = readMiscReg(MISCREG_SCR, tc); 1101 1102 TLBIASID tlbiOp(EL1, 1103 haveSecurity && !scr.ns, 1104 bits(newVal, 7,0)); 1105 1106 tlbiOp.broadcast(tc); 1107 return; 1108 } 1109 // mcr tlbimvaal(is) is invalidating all matching entries 1110 // regardless of the level of lookup, since in gem5 we cache 1111 // in the tlb the last level of lookup only. 1112 // TLB Invalidate by VA, All ASID 1113 case MISCREG_TLBIMVAA: 1114 case MISCREG_TLBIMVAAL: 1115 { 1116 assert32(tc); 1117 scr = readMiscReg(MISCREG_SCR, tc); 1118 1119 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1120 mbits(newVal, 31,12), false); 1121 1122 tlbiOp(tc); 1123 return; 1124 } 1125 // TLB Invalidate by VA, All ASID, Inner Shareable 1126 case MISCREG_TLBIMVAAIS: 1127 case MISCREG_TLBIMVAALIS: 1128 { 1129 assert32(tc); 1130 scr = readMiscReg(MISCREG_SCR, tc); 1131 1132 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1133 mbits(newVal, 31,12), false); 1134 1135 tlbiOp.broadcast(tc); 1136 return; 1137 } 1138 // mcr tlbimvalh(is) is invalidating all matching entries 1139 // regardless of the level of lookup, since in gem5 we cache 1140 // in the tlb the last level of lookup only. 1141 // TLB Invalidate by VA, Hyp mode 1142 case MISCREG_TLBIMVAH: 1143 case MISCREG_TLBIMVALH: 1144 { 1145 assert32(tc); 1146 scr = readMiscReg(MISCREG_SCR, tc); 1147 1148 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1149 mbits(newVal, 31,12), true); 1150 1151 tlbiOp(tc); 1152 return; 1153 } 1154 // TLB Invalidate by VA, Hyp mode, Inner Shareable 1155 case MISCREG_TLBIMVAHIS: 1156 case MISCREG_TLBIMVALHIS: 1157 { 1158 assert32(tc); 1159 scr = readMiscReg(MISCREG_SCR, tc); 1160 1161 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1162 mbits(newVal, 31,12), true); 1163 1164 tlbiOp.broadcast(tc); 1165 return; 1166 } 1167 // mcr tlbiipas2l(is) is invalidating all matching entries 1168 // regardless of the level of lookup, since in gem5 we cache 1169 // in the tlb the last level of lookup only. 1170 // TLB Invalidate by Intermediate Physical Address, Stage 2 1171 case MISCREG_TLBIIPAS2: 1172 case MISCREG_TLBIIPAS2L: 1173 { 1174 assert32(tc); 1175 scr = readMiscReg(MISCREG_SCR, tc); 1176 1177 TLBIIPA tlbiOp(EL1, 1178 haveSecurity && !scr.ns, 1179 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1180 1181 tlbiOp(tc); 1182 return; 1183 } 1184 // TLB Invalidate by Intermediate Physical Address, Stage 2, 1185 // Inner Shareable 1186 case MISCREG_TLBIIPAS2IS: 1187 case MISCREG_TLBIIPAS2LIS: 1188 { 1189 assert32(tc); 1190 scr = readMiscReg(MISCREG_SCR, tc); 1191 1192 TLBIIPA tlbiOp(EL1, 1193 haveSecurity && !scr.ns, 1194 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1195 1196 tlbiOp.broadcast(tc); 1197 return; 1198 } 1199 // Instruction TLB Invalidate by VA 1200 case MISCREG_ITLBIMVA: 1201 { 1202 assert32(tc); 1203 scr = readMiscReg(MISCREG_SCR, tc); 1204 1205 ITLBIMVA tlbiOp(EL1, 1206 haveSecurity && !scr.ns, 1207 mbits(newVal, 31, 12), 1208 bits(newVal, 7,0)); 1209 1210 tlbiOp(tc); 1211 return; 1212 } 1213 // Data TLB Invalidate by VA 1214 case MISCREG_DTLBIMVA: 1215 { 1216 assert32(tc); 1217 scr = readMiscReg(MISCREG_SCR, tc); 1218 1219 DTLBIMVA tlbiOp(EL1, 1220 haveSecurity && !scr.ns, 1221 mbits(newVal, 31, 12), 1222 bits(newVal, 7,0)); 1223 1224 tlbiOp(tc); 1225 return; 1226 } 1227 // Instruction TLB Invalidate by ASID match 1228 case MISCREG_ITLBIASID: 1229 { 1230 assert32(tc); 1231 scr = readMiscReg(MISCREG_SCR, tc); 1232 1233 ITLBIASID tlbiOp(EL1, 1234 haveSecurity && !scr.ns, 1235 bits(newVal, 7,0)); 1236 1237 tlbiOp(tc); 1238 return; 1239 } 1240 // Data TLB Invalidate by ASID match 1241 case MISCREG_DTLBIASID: 1242 { 1243 assert32(tc); 1244 scr = readMiscReg(MISCREG_SCR, tc); 1245 1246 DTLBIASID tlbiOp(EL1, 1247 haveSecurity && !scr.ns, 1248 bits(newVal, 7,0)); 1249 1250 tlbiOp(tc); 1251 return; 1252 } 1253 // TLB Invalidate All, Non-Secure Non-Hyp 1254 case MISCREG_TLBIALLNSNH: 1255 { 1256 assert32(tc); 1257 1258 TLBIALLN tlbiOp(EL1, false); 1259 tlbiOp(tc); 1260 return; 1261 } 1262 // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable 1263 case MISCREG_TLBIALLNSNHIS: 1264 { 1265 assert32(tc); 1266 1267 TLBIALLN tlbiOp(EL1, false); 1268 tlbiOp.broadcast(tc); 1269 return; 1270 } 1271 // TLB Invalidate All, Hyp mode 1272 case MISCREG_TLBIALLH: 1273 { 1274 assert32(tc); 1275 1276 TLBIALLN tlbiOp(EL1, true); 1277 tlbiOp(tc); 1278 return; 1279 } 1280 // TLB Invalidate All, Hyp mode, Inner Shareable 1281 case MISCREG_TLBIALLHIS: 1282 { 1283 assert32(tc); 1284 1285 TLBIALLN tlbiOp(EL1, true); 1286 tlbiOp.broadcast(tc); 1287 return; 1288 } 1289 // AArch64 TLB Invalidate All, EL3 1290 case MISCREG_TLBI_ALLE3: 1291 { 1292 assert64(tc); 1293 1294 TLBIALL tlbiOp(EL3, true); 1295 tlbiOp(tc); 1296 return; 1297 } 1298 // AArch64 TLB Invalidate All, EL3, Inner Shareable 1299 case MISCREG_TLBI_ALLE3IS: 1300 { 1301 assert64(tc); 1302 1303 TLBIALL tlbiOp(EL3, true); 1304 tlbiOp.broadcast(tc); 1305 return; 1306 } 1307 // @todo: uncomment this to enable Virtualization 1308 // case MISCREG_TLBI_ALLE2IS: 1309 // case MISCREG_TLBI_ALLE2: 1310 // AArch64 TLB Invalidate All, EL1 1311 case MISCREG_TLBI_ALLE1: 1312 case MISCREG_TLBI_VMALLE1: 1313 case MISCREG_TLBI_VMALLS12E1: 1314 // @todo: handle VMID and stage 2 to enable Virtualization 1315 { 1316 assert64(tc); 1317 scr = readMiscReg(MISCREG_SCR, tc); 1318 1319 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1320 tlbiOp(tc); 1321 return; 1322 } 1323 // AArch64 TLB Invalidate All, EL1, Inner Shareable 1324 case MISCREG_TLBI_ALLE1IS: 1325 case MISCREG_TLBI_VMALLE1IS: 1326 case MISCREG_TLBI_VMALLS12E1IS: 1327 // @todo: handle VMID and stage 2 to enable Virtualization 1328 { 1329 assert64(tc); 1330 scr = readMiscReg(MISCREG_SCR, tc); 1331 1332 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1333 tlbiOp.broadcast(tc); 1334 return; 1335 } 1336 // VAEx(IS) and VALEx(IS) are the same because TLBs 1337 // only store entries 1338 // from the last level of translation table walks 1339 // @todo: handle VMID to enable Virtualization 1340 // AArch64 TLB Invalidate by VA, EL3 1341 case MISCREG_TLBI_VAE3_Xt: 1342 case MISCREG_TLBI_VALE3_Xt: 1343 { 1344 assert64(tc); 1345 1346 TLBIMVA tlbiOp(EL3, true, 1347 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1348 0xbeef); 1349 tlbiOp(tc); 1350 return; 1351 } 1352 // AArch64 TLB Invalidate by VA, EL3, Inner Shareable 1353 case MISCREG_TLBI_VAE3IS_Xt: 1354 case MISCREG_TLBI_VALE3IS_Xt: 1355 { 1356 assert64(tc); 1357 1358 TLBIMVA tlbiOp(EL3, true, 1359 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1360 0xbeef); 1361 1362 tlbiOp.broadcast(tc); 1363 return; 1364 } 1365 // AArch64 TLB Invalidate by VA, EL2 1366 case MISCREG_TLBI_VAE2_Xt: 1367 case MISCREG_TLBI_VALE2_Xt: 1368 { 1369 assert64(tc); 1370 scr = readMiscReg(MISCREG_SCR, tc); 1371 1372 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1373 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1374 0xbeef); 1375 tlbiOp(tc); 1376 return; 1377 } 1378 // AArch64 TLB Invalidate by VA, EL2, Inner Shareable 1379 case MISCREG_TLBI_VAE2IS_Xt: 1380 case MISCREG_TLBI_VALE2IS_Xt: 1381 { 1382 assert64(tc); 1383 scr = readMiscReg(MISCREG_SCR, tc); 1384 1385 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1386 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1387 0xbeef); 1388 1389 tlbiOp.broadcast(tc); 1390 return; 1391 } 1392 // AArch64 TLB Invalidate by VA, EL1 1393 case MISCREG_TLBI_VAE1_Xt: 1394 case MISCREG_TLBI_VALE1_Xt: 1395 { 1396 assert64(tc); 1397 scr = readMiscReg(MISCREG_SCR, tc); 1398 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1399 bits(newVal, 55, 48); 1400 1401 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1402 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1403 asid); 1404 1405 tlbiOp(tc); 1406 return; 1407 } 1408 // AArch64 TLB Invalidate by VA, EL1, Inner Shareable 1409 case MISCREG_TLBI_VAE1IS_Xt: 1410 case MISCREG_TLBI_VALE1IS_Xt: 1411 { 1412 assert64(tc); 1413 scr = readMiscReg(MISCREG_SCR, tc); 1414 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1415 bits(newVal, 55, 48); 1416 1417 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1418 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1419 asid); 1420 1421 tlbiOp.broadcast(tc); 1422 return; 1423 } 1424 // AArch64 TLB Invalidate by ASID, EL1 1425 // @todo: handle VMID to enable Virtualization 1426 case MISCREG_TLBI_ASIDE1_Xt: 1427 { 1428 assert64(tc); 1429 scr = readMiscReg(MISCREG_SCR, tc); 1430 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1431 bits(newVal, 55, 48); 1432 1433 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1434 tlbiOp(tc); 1435 return; 1436 } 1437 // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable 1438 case MISCREG_TLBI_ASIDE1IS_Xt: 1439 { 1440 assert64(tc); 1441 scr = readMiscReg(MISCREG_SCR, tc); 1442 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1443 bits(newVal, 55, 48); 1444 1445 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1446 tlbiOp.broadcast(tc); 1447 return; 1448 } 1449 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 1450 // entries from the last level of translation table walks 1451 // AArch64 TLB Invalidate by VA, All ASID, EL1 1452 case MISCREG_TLBI_VAAE1_Xt: 1453 case MISCREG_TLBI_VAALE1_Xt: 1454 { 1455 assert64(tc); 1456 scr = readMiscReg(MISCREG_SCR, tc); 1457 1458 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1459 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 1460 1461 tlbiOp(tc); 1462 return; 1463 } 1464 // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable 1465 case MISCREG_TLBI_VAAE1IS_Xt: 1466 case MISCREG_TLBI_VAALE1IS_Xt: 1467 { 1468 assert64(tc); 1469 scr = readMiscReg(MISCREG_SCR, tc); 1470 1471 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1472 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 1473 1474 tlbiOp.broadcast(tc); 1475 return; 1476 } 1477 // AArch64 TLB Invalidate by Intermediate Physical Address, 1478 // Stage 2, EL1 1479 case MISCREG_TLBI_IPAS2E1_Xt: 1480 case MISCREG_TLBI_IPAS2LE1_Xt: 1481 { 1482 assert64(tc); 1483 scr = readMiscReg(MISCREG_SCR, tc); 1484 1485 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1486 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1487 1488 tlbiOp(tc); 1489 return; 1490 } 1491 // AArch64 TLB Invalidate by Intermediate Physical Address, 1492 // Stage 2, EL1, Inner Shareable 1493 case MISCREG_TLBI_IPAS2E1IS_Xt: 1494 case MISCREG_TLBI_IPAS2LE1IS_Xt: 1495 { 1496 assert64(tc); 1497 scr = readMiscReg(MISCREG_SCR, tc); 1498 1499 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1500 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1501 1502 tlbiOp.broadcast(tc); 1503 return; 1504 } 1505 case MISCREG_ACTLR: 1506 warn("Not doing anything for write of miscreg ACTLR\n"); 1507 break; 1508 1509 case MISCREG_PMXEVTYPER_PMCCFILTR: 1510 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 1511 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 1512 case MISCREG_PMCR ... MISCREG_PMOVSSET: 1513 pmu->setMiscReg(misc_reg, newVal); 1514 break; 1515 1516 1517 case MISCREG_HSTR: // TJDBX, now redifined to be RES0 1518 { 1519 HSTR hstrMask = 0; 1520 hstrMask.tjdbx = 1; 1521 newVal &= ~((uint32_t) hstrMask); 1522 break; 1523 } 1524 case MISCREG_HCPTR: 1525 { 1526 // If a CP bit in NSACR is 0 then the corresponding bit in 1527 // HCPTR is RAO/WI. Same applies to NSASEDIS 1528 secure_lookup = haveSecurity && 1529 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 1530 readMiscRegNoEffect(MISCREG_CPSR)); 1531 if (!secure_lookup) { 1532 MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 1533 MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 1534 newVal = (newVal & ~mask) | (oldValue & mask); 1535 } 1536 break; 1537 } 1538 case MISCREG_HDFAR: // alias for secure DFAR 1539 misc_reg = MISCREG_DFAR_S; 1540 break; 1541 case MISCREG_HIFAR: // alias for secure IFAR 1542 misc_reg = MISCREG_IFAR_S; 1543 break; 1544 case MISCREG_ATS1CPR: 1545 case MISCREG_ATS1CPW: 1546 case MISCREG_ATS1CUR: 1547 case MISCREG_ATS1CUW: 1548 case MISCREG_ATS12NSOPR: 1549 case MISCREG_ATS12NSOPW: 1550 case MISCREG_ATS12NSOUR: 1551 case MISCREG_ATS12NSOUW: 1552 case MISCREG_ATS1HR: 1553 case MISCREG_ATS1HW: 1554 { 1555 Request::Flags flags = 0; 1556 BaseTLB::Mode mode = BaseTLB::Read; 1557 TLB::ArmTranslationType tranType = TLB::NormalTran; 1558 Fault fault; 1559 switch(misc_reg) { 1560 case MISCREG_ATS1CPR: 1561 flags = TLB::MustBeOne; 1562 tranType = TLB::S1CTran; 1563 mode = BaseTLB::Read; 1564 break; 1565 case MISCREG_ATS1CPW: 1566 flags = TLB::MustBeOne; 1567 tranType = TLB::S1CTran; 1568 mode = BaseTLB::Write; 1569 break; 1570 case MISCREG_ATS1CUR: 1571 flags = TLB::MustBeOne | TLB::UserMode; 1572 tranType = TLB::S1CTran; 1573 mode = BaseTLB::Read; 1574 break; 1575 case MISCREG_ATS1CUW: 1576 flags = TLB::MustBeOne | TLB::UserMode; 1577 tranType = TLB::S1CTran; 1578 mode = BaseTLB::Write; 1579 break; 1580 case MISCREG_ATS12NSOPR: 1581 if (!haveSecurity) 1582 panic("Security Extensions required for ATS12NSOPR"); 1583 flags = TLB::MustBeOne; 1584 tranType = TLB::S1S2NsTran; 1585 mode = BaseTLB::Read; 1586 break; 1587 case MISCREG_ATS12NSOPW: 1588 if (!haveSecurity) 1589 panic("Security Extensions required for ATS12NSOPW"); 1590 flags = TLB::MustBeOne; 1591 tranType = TLB::S1S2NsTran; 1592 mode = BaseTLB::Write; 1593 break; 1594 case MISCREG_ATS12NSOUR: 1595 if (!haveSecurity) 1596 panic("Security Extensions required for ATS12NSOUR"); 1597 flags = TLB::MustBeOne | TLB::UserMode; 1598 tranType = TLB::S1S2NsTran; 1599 mode = BaseTLB::Read; 1600 break; 1601 case MISCREG_ATS12NSOUW: 1602 if (!haveSecurity) 1603 panic("Security Extensions required for ATS12NSOUW"); 1604 flags = TLB::MustBeOne | TLB::UserMode; 1605 tranType = TLB::S1S2NsTran; 1606 mode = BaseTLB::Write; 1607 break; 1608 case MISCREG_ATS1HR: // only really useful from secure mode. 1609 flags = TLB::MustBeOne; 1610 tranType = TLB::HypMode; 1611 mode = BaseTLB::Read; 1612 break; 1613 case MISCREG_ATS1HW: 1614 flags = TLB::MustBeOne; 1615 tranType = TLB::HypMode; 1616 mode = BaseTLB::Write; 1617 break; 1618 } 1619 // If we're in timing mode then doing the translation in 1620 // functional mode then we're slightly distorting performance 1621 // results obtained from simulations. The translation should be 1622 // done in the same mode the core is running in. NOTE: This 1623 // can't be an atomic translation because that causes problems 1624 // with unexpected atomic snoop requests. 1625 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1626 1627 auto req = std::make_shared<Request>( 1628 0, val, 0, flags, Request::funcMasterId, 1629 tc->pcState().pc(), tc->contextId()); 1630 1631 fault = getDTBPtr(tc)->translateFunctional( 1632 req, tc, mode, tranType); 1633 1634 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1635 HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 1636 1637 MiscReg newVal; 1638 if (fault == NoFault) { 1639 Addr paddr = req->getPaddr(); 1640 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 1641 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 1642 newVal = (paddr & mask(39, 12)) | 1643 (getDTBPtr(tc)->getAttr()); 1644 } else { 1645 newVal = (paddr & 0xfffff000) | 1646 (getDTBPtr(tc)->getAttr()); 1647 } 1648 DPRINTF(MiscRegs, 1649 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 1650 val, newVal); 1651 } else { 1652 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1653 armFault->update(tc); 1654 // Set fault bit and FSR 1655 FSR fsr = armFault->getFsr(tc); 1656 1657 newVal = ((fsr >> 9) & 1) << 11; 1658 if (newVal) { 1659 // LPAE - rearange fault status 1660 newVal |= ((fsr >> 0) & 0x3f) << 1; 1661 } else { 1662 // VMSA - rearange fault status 1663 newVal |= ((fsr >> 0) & 0xf) << 1; 1664 newVal |= ((fsr >> 10) & 0x1) << 5; 1665 newVal |= ((fsr >> 12) & 0x1) << 6; 1666 } 1667 newVal |= 0x1; // F bit 1668 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1669 newVal |= armFault->isStage2() ? 0x200 : 0; 1670 DPRINTF(MiscRegs, 1671 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 1672 val, fsr, newVal); 1673 } 1674 setMiscRegNoEffect(MISCREG_PAR, newVal); 1675 return; 1676 } 1677 case MISCREG_TTBCR: 1678 { 1679 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1680 const uint32_t ones = (uint32_t)(-1); 1681 TTBCR ttbcrMask = 0; 1682 TTBCR ttbcrNew = newVal; 1683 1684 // ARM DDI 0406C.b, ARMv7-32 1685 ttbcrMask.n = ones; // T0SZ 1686 if (haveSecurity) { 1687 ttbcrMask.pd0 = ones; 1688 ttbcrMask.pd1 = ones; 1689 } 1690 ttbcrMask.epd0 = ones; 1691 ttbcrMask.irgn0 = ones; 1692 ttbcrMask.orgn0 = ones; 1693 ttbcrMask.sh0 = ones; 1694 ttbcrMask.ps = ones; // T1SZ 1695 ttbcrMask.a1 = ones; 1696 ttbcrMask.epd1 = ones; 1697 ttbcrMask.irgn1 = ones; 1698 ttbcrMask.orgn1 = ones; 1699 ttbcrMask.sh1 = ones; 1700 if (haveLPAE) 1701 ttbcrMask.eae = ones; 1702 1703 if (haveLPAE && ttbcrNew.eae) { 1704 newVal = newVal & ttbcrMask; 1705 } else { 1706 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 1707 } 1708 // Invalidate TLB MiscReg 1709 getITBPtr(tc)->invalidateMiscReg(); 1710 getDTBPtr(tc)->invalidateMiscReg(); 1711 break; 1712 } 1713 case MISCREG_TTBR0: 1714 case MISCREG_TTBR1: 1715 { 1716 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1717 if (haveLPAE) { 1718 if (ttbcr.eae) { 1719 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 1720 // ARMv8 AArch32 bit 63-56 only 1721 uint64_t ttbrMask = mask(63,56) | mask(47,40); 1722 newVal = (newVal & (~ttbrMask)); 1723 } 1724 } 1725 // Invalidate TLB MiscReg 1726 getITBPtr(tc)->invalidateMiscReg(); 1727 getDTBPtr(tc)->invalidateMiscReg(); 1728 break; 1729 } 1730 case MISCREG_SCTLR_EL1: 1731 case MISCREG_CONTEXTIDR: 1732 case MISCREG_PRRR: 1733 case MISCREG_NMRR: 1734 case MISCREG_MAIR0: 1735 case MISCREG_MAIR1: 1736 case MISCREG_DACR: 1737 case MISCREG_VTTBR: 1738 case MISCREG_SCR_EL3: 1739 case MISCREG_HCR_EL2: 1740 case MISCREG_TCR_EL1: 1741 case MISCREG_TCR_EL2: 1742 case MISCREG_TCR_EL3: 1743 case MISCREG_SCTLR_EL2: 1744 case MISCREG_SCTLR_EL3: 1745 case MISCREG_HSCTLR: 1746 case MISCREG_TTBR0_EL1: 1747 case MISCREG_TTBR1_EL1: 1748 case MISCREG_TTBR0_EL2: 1749 case MISCREG_TTBR1_EL2: 1750 case MISCREG_TTBR0_EL3: 1751 getITBPtr(tc)->invalidateMiscReg(); 1752 getDTBPtr(tc)->invalidateMiscReg(); 1753 break; 1754 case MISCREG_NZCV: 1755 { 1756 CPSR cpsr = val; 1757 1758 tc->setCCReg(CCREG_NZ, cpsr.nz); 1759 tc->setCCReg(CCREG_C, cpsr.c); 1760 tc->setCCReg(CCREG_V, cpsr.v); 1761 } 1762 break; 1763 case MISCREG_DAIF: 1764 { 1765 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1766 cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 1767 newVal = cpsr; 1768 misc_reg = MISCREG_CPSR; 1769 } 1770 break; 1771 case MISCREG_SP_EL0: 1772 tc->setIntReg(INTREG_SP0, newVal); 1773 break; 1774 case MISCREG_SP_EL1: 1775 tc->setIntReg(INTREG_SP1, newVal); 1776 break; 1777 case MISCREG_SP_EL2: 1778 tc->setIntReg(INTREG_SP2, newVal); 1779 break; 1780 case MISCREG_SPSEL: 1781 { 1782 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1783 cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 1784 newVal = cpsr; 1785 misc_reg = MISCREG_CPSR; 1786 } 1787 break; 1788 case MISCREG_CURRENTEL: 1789 { 1790 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1791 cpsr.el = (uint8_t) ((CPSR) newVal).el; 1792 newVal = cpsr; 1793 misc_reg = MISCREG_CPSR; 1794 } 1795 break; 1796 case MISCREG_AT_S1E1R_Xt: 1797 case MISCREG_AT_S1E1W_Xt: 1798 case MISCREG_AT_S1E0R_Xt: 1799 case MISCREG_AT_S1E0W_Xt: 1800 case MISCREG_AT_S1E2R_Xt: 1801 case MISCREG_AT_S1E2W_Xt: 1802 case MISCREG_AT_S12E1R_Xt: 1803 case MISCREG_AT_S12E1W_Xt: 1804 case MISCREG_AT_S12E0R_Xt: 1805 case MISCREG_AT_S12E0W_Xt: 1806 case MISCREG_AT_S1E3R_Xt: 1807 case MISCREG_AT_S1E3W_Xt: 1808 { 1809 RequestPtr req = std::make_shared<Request>(); 1810 Request::Flags flags = 0; 1811 BaseTLB::Mode mode = BaseTLB::Read; 1812 TLB::ArmTranslationType tranType = TLB::NormalTran; 1813 Fault fault; 1814 switch(misc_reg) { 1815 case MISCREG_AT_S1E1R_Xt: 1816 flags = TLB::MustBeOne; 1817 tranType = TLB::S1E1Tran; 1818 mode = BaseTLB::Read; 1819 break; 1820 case MISCREG_AT_S1E1W_Xt: 1821 flags = TLB::MustBeOne; 1822 tranType = TLB::S1E1Tran; 1823 mode = BaseTLB::Write; 1824 break; 1825 case MISCREG_AT_S1E0R_Xt: 1826 flags = TLB::MustBeOne | TLB::UserMode; 1827 tranType = TLB::S1E0Tran; 1828 mode = BaseTLB::Read; 1829 break; 1830 case MISCREG_AT_S1E0W_Xt: 1831 flags = TLB::MustBeOne | TLB::UserMode; 1832 tranType = TLB::S1E0Tran; 1833 mode = BaseTLB::Write; 1834 break; 1835 case MISCREG_AT_S1E2R_Xt: 1836 flags = TLB::MustBeOne; 1837 tranType = TLB::S1E2Tran; 1838 mode = BaseTLB::Read; 1839 break; 1840 case MISCREG_AT_S1E2W_Xt: 1841 flags = TLB::MustBeOne; 1842 tranType = TLB::S1E2Tran; 1843 mode = BaseTLB::Write; 1844 break; 1845 case MISCREG_AT_S12E0R_Xt: 1846 flags = TLB::MustBeOne | TLB::UserMode; 1847 tranType = TLB::S12E0Tran; 1848 mode = BaseTLB::Read; 1849 break; 1850 case MISCREG_AT_S12E0W_Xt: 1851 flags = TLB::MustBeOne | TLB::UserMode; 1852 tranType = TLB::S12E0Tran; 1853 mode = BaseTLB::Write; 1854 break; 1855 case MISCREG_AT_S12E1R_Xt: 1856 flags = TLB::MustBeOne; 1857 tranType = TLB::S12E1Tran; 1858 mode = BaseTLB::Read; 1859 break; 1860 case MISCREG_AT_S12E1W_Xt: 1861 flags = TLB::MustBeOne; 1862 tranType = TLB::S12E1Tran; 1863 mode = BaseTLB::Write; 1864 break; 1865 case MISCREG_AT_S1E3R_Xt: 1866 flags = TLB::MustBeOne; 1867 tranType = TLB::S1E3Tran; 1868 mode = BaseTLB::Read; 1869 break; 1870 case MISCREG_AT_S1E3W_Xt: 1871 flags = TLB::MustBeOne; 1872 tranType = TLB::S1E3Tran; 1873 mode = BaseTLB::Write; 1874 break; 1875 } 1876 // If we're in timing mode then doing the translation in 1877 // functional mode then we're slightly distorting performance 1878 // results obtained from simulations. The translation should be 1879 // done in the same mode the core is running in. NOTE: This 1880 // can't be an atomic translation because that causes problems 1881 // with unexpected atomic snoop requests. 1882 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1883 req->setVirt(0, val, 0, flags, Request::funcMasterId, 1884 tc->pcState().pc()); 1885 req->setContext(tc->contextId()); 1886 fault = getDTBPtr(tc)->translateFunctional(req, tc, mode, 1887 tranType); 1888 1889 MiscReg newVal; 1890 if (fault == NoFault) { 1891 Addr paddr = req->getPaddr(); 1892 uint64_t attr = getDTBPtr(tc)->getAttr(); 1893 uint64_t attr1 = attr >> 56; 1894 if (!attr1 || attr1 ==0x44) { 1895 attr |= 0x100; 1896 attr &= ~ uint64_t(0x80); 1897 } 1898 newVal = (paddr & mask(47, 12)) | attr; 1899 DPRINTF(MiscRegs, 1900 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 1901 val, newVal); 1902 } else { 1903 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1904 armFault->update(tc); 1905 // Set fault bit and FSR 1906 FSR fsr = armFault->getFsr(tc); 1907 1908 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1909 if (cpsr.width) { // AArch32 1910 newVal = ((fsr >> 9) & 1) << 11; 1911 // rearrange fault status 1912 newVal |= ((fsr >> 0) & 0x3f) << 1; 1913 newVal |= 0x1; // F bit 1914 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1915 newVal |= armFault->isStage2() ? 0x200 : 0; 1916 } else { // AArch64 1917 newVal = 1; // F bit 1918 newVal |= fsr << 1; // FST 1919 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit. 1920 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 1921 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 1922 newVal |= 1 << 11; // RES1 1923 } 1924 DPRINTF(MiscRegs, 1925 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 1926 val, fsr, newVal); 1927 } 1928 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 1929 return; 1930 } 1931 case MISCREG_SPSR_EL3: 1932 case MISCREG_SPSR_EL2: 1933 case MISCREG_SPSR_EL1: 1934 // Force bits 23:21 to 0 1935 newVal = val & ~(0x7 << 21); 1936 break; 1937 case MISCREG_L2CTLR: 1938 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 1939 miscRegName[misc_reg], uint32_t(val)); 1940 break; 1941 1942 // Generic Timer registers 1943 case MISCREG_CNTHV_CTL_EL2: 1944 case MISCREG_CNTHV_CVAL_EL2: 1945 case MISCREG_CNTHV_TVAL_EL2: 1946 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 1947 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 1948 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 1949 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 1950 getGenericTimer(tc).setMiscReg(misc_reg, newVal); 1951 break; 1952 } 1953 } 1954 setMiscRegNoEffect(misc_reg, newVal); 1955} 1956 1957BaseISADevice & 1958ISA::getGenericTimer(ThreadContext *tc) 1959{ 1960 // We only need to create an ISA interface the first time we try 1961 // to access the timer. 1962 if (timer) 1963 return *timer.get(); 1964 1965 assert(system); 1966 GenericTimer *generic_timer(system->getGenericTimer()); 1967 if (!generic_timer) { 1968 panic("Trying to get a generic timer from a system that hasn't " 1969 "been configured to use a generic timer.\n"); 1970 } 1971 1972 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 1973 timer->setThreadContext(tc); 1974 1975 return *timer.get(); 1976} 1977 1978} 1979 1980ArmISA::ISA * 1981ArmISAParams::create() 1982{ 1983 return new ArmISA::ISA(this); 1984} 1985