isa.cc revision 12816:9e9bd9e6e206
1/* 2 * Copyright (c) 2010-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 */ 40 41#include "arch/arm/isa.hh" 42#include "arch/arm/pmu.hh" 43#include "arch/arm/system.hh" 44#include "arch/arm/tlb.hh" 45#include "arch/arm/tlbi_op.hh" 46#include "cpu/base.hh" 47#include "cpu/checker/cpu.hh" 48#include "debug/Arm.hh" 49#include "debug/MiscRegs.hh" 50#include "dev/arm/generic_timer.hh" 51#include "params/ArmISA.hh" 52#include "sim/faults.hh" 53#include "sim/stat_control.hh" 54#include "sim/system.hh" 55 56namespace ArmISA 57{ 58 59ISA::ISA(Params *p) 60 : SimObject(p), 61 system(NULL), 62 _decoderFlavour(p->decoderFlavour), 63 _vecRegRenameMode(p->vecRegRenameMode), 64 pmu(p->pmu), 65 impdefAsNop(p->impdef_nop) 66{ 67 miscRegs[MISCREG_SCTLR_RST] = 0; 68 69 // Hook up a dummy device if we haven't been configured with a 70 // real PMU. By using a dummy device, we don't need to check that 71 // the PMU exist every time we try to access a PMU register. 72 if (!pmu) 73 pmu = &dummyDevice; 74 75 // Give all ISA devices a pointer to this ISA 76 pmu->setISA(this); 77 78 system = dynamic_cast<ArmSystem *>(p->system); 79 80 // Cache system-level properties 81 if (FullSystem && system) { 82 highestELIs64 = system->highestELIs64(); 83 haveSecurity = system->haveSecurity(); 84 haveLPAE = system->haveLPAE(); 85 haveVirtualization = system->haveVirtualization(); 86 haveLargeAsid64 = system->haveLargeAsid64(); 87 physAddrRange64 = system->physAddrRange64(); 88 } else { 89 highestELIs64 = true; // ArmSystem::highestELIs64 does the same 90 haveSecurity = haveLPAE = haveVirtualization = false; 91 haveLargeAsid64 = false; 92 physAddrRange64 = 32; // dummy value 93 } 94 95 initializeMiscRegMetadata(); 96 preUnflattenMiscReg(); 97 98 clear(); 99} 100 101std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS); 102 103const ArmISAParams * 104ISA::params() const 105{ 106 return dynamic_cast<const Params *>(_params); 107} 108 109void 110ISA::clear() 111{ 112 const Params *p(params()); 113 114 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 115 memset(miscRegs, 0, sizeof(miscRegs)); 116 117 // Initialize configurable default values 118 miscRegs[MISCREG_MIDR] = p->midr; 119 miscRegs[MISCREG_MIDR_EL1] = p->midr; 120 miscRegs[MISCREG_VPIDR] = p->midr; 121 122 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 123 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 124 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 125 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 126 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 127 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 128 129 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 130 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 131 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 132 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 133 134 if (FullSystem && system->highestELIs64()) { 135 // Initialize AArch64 state 136 clear64(p); 137 return; 138 } 139 140 // Initialize AArch32 state... 141 142 CPSR cpsr = 0; 143 cpsr.mode = MODE_USER; 144 miscRegs[MISCREG_CPSR] = cpsr; 145 updateRegMap(cpsr); 146 147 SCTLR sctlr = 0; 148 sctlr.te = (bool) sctlr_rst.te; 149 sctlr.nmfi = (bool) sctlr_rst.nmfi; 150 sctlr.v = (bool) sctlr_rst.v; 151 sctlr.u = 1; 152 sctlr.xp = 1; 153 sctlr.rao2 = 1; 154 sctlr.rao3 = 1; 155 sctlr.rao4 = 0xf; // SCTLR[6:3] 156 sctlr.uci = 1; 157 sctlr.dze = 1; 158 miscRegs[MISCREG_SCTLR_NS] = sctlr; 159 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 160 miscRegs[MISCREG_HCPTR] = 0; 161 162 // Start with an event in the mailbox 163 miscRegs[MISCREG_SEV_MAILBOX] = 1; 164 165 // Separate Instruction and Data TLBs 166 miscRegs[MISCREG_TLBTR] = 1; 167 168 MVFR0 mvfr0 = 0; 169 mvfr0.advSimdRegisters = 2; 170 mvfr0.singlePrecision = 2; 171 mvfr0.doublePrecision = 2; 172 mvfr0.vfpExceptionTrapping = 0; 173 mvfr0.divide = 1; 174 mvfr0.squareRoot = 1; 175 mvfr0.shortVectors = 1; 176 mvfr0.roundingModes = 1; 177 miscRegs[MISCREG_MVFR0] = mvfr0; 178 179 MVFR1 mvfr1 = 0; 180 mvfr1.flushToZero = 1; 181 mvfr1.defaultNaN = 1; 182 mvfr1.advSimdLoadStore = 1; 183 mvfr1.advSimdInteger = 1; 184 mvfr1.advSimdSinglePrecision = 1; 185 mvfr1.advSimdHalfPrecision = 1; 186 mvfr1.vfpHalfPrecision = 1; 187 miscRegs[MISCREG_MVFR1] = mvfr1; 188 189 // Reset values of PRRR and NMRR are implementation dependent 190 191 // @todo: PRRR and NMRR in secure state? 192 miscRegs[MISCREG_PRRR_NS] = 193 (1 << 19) | // 19 194 (0 << 18) | // 18 195 (0 << 17) | // 17 196 (1 << 16) | // 16 197 (2 << 14) | // 15:14 198 (0 << 12) | // 13:12 199 (2 << 10) | // 11:10 200 (2 << 8) | // 9:8 201 (2 << 6) | // 7:6 202 (2 << 4) | // 5:4 203 (1 << 2) | // 3:2 204 0; // 1:0 205 miscRegs[MISCREG_NMRR_NS] = 206 (1 << 30) | // 31:30 207 (0 << 26) | // 27:26 208 (0 << 24) | // 25:24 209 (3 << 22) | // 23:22 210 (2 << 20) | // 21:20 211 (0 << 18) | // 19:18 212 (0 << 16) | // 17:16 213 (1 << 14) | // 15:14 214 (0 << 12) | // 13:12 215 (2 << 10) | // 11:10 216 (0 << 8) | // 9:8 217 (3 << 6) | // 7:6 218 (2 << 4) | // 5:4 219 (0 << 2) | // 3:2 220 0; // 1:0 221 222 miscRegs[MISCREG_CPACR] = 0; 223 224 miscRegs[MISCREG_FPSID] = p->fpsid; 225 226 if (haveLPAE) { 227 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 228 ttbcr.eae = 0; 229 miscRegs[MISCREG_TTBCR_NS] = ttbcr; 230 // Enforce consistency with system-level settings 231 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 232 } 233 234 if (haveSecurity) { 235 miscRegs[MISCREG_SCTLR_S] = sctlr; 236 miscRegs[MISCREG_SCR] = 0; 237 miscRegs[MISCREG_VBAR_S] = 0; 238 } else { 239 // we're always non-secure 240 miscRegs[MISCREG_SCR] = 1; 241 } 242 243 //XXX We need to initialize the rest of the state. 244} 245 246void 247ISA::clear64(const ArmISAParams *p) 248{ 249 CPSR cpsr = 0; 250 Addr rvbar = system->resetAddr64(); 251 switch (system->highestEL()) { 252 // Set initial EL to highest implemented EL using associated stack 253 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 254 // value 255 case EL3: 256 cpsr.mode = MODE_EL3H; 257 miscRegs[MISCREG_RVBAR_EL3] = rvbar; 258 break; 259 case EL2: 260 cpsr.mode = MODE_EL2H; 261 miscRegs[MISCREG_RVBAR_EL2] = rvbar; 262 break; 263 case EL1: 264 cpsr.mode = MODE_EL1H; 265 miscRegs[MISCREG_RVBAR_EL1] = rvbar; 266 break; 267 default: 268 panic("Invalid highest implemented exception level"); 269 break; 270 } 271 272 // Initialize rest of CPSR 273 cpsr.daif = 0xf; // Mask all interrupts 274 cpsr.ss = 0; 275 cpsr.il = 0; 276 miscRegs[MISCREG_CPSR] = cpsr; 277 updateRegMap(cpsr); 278 279 // Initialize other control registers 280 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 281 if (haveSecurity) { 282 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830; 283 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 284 } else if (haveVirtualization) { 285 // also MISCREG_SCTLR_EL2 (by mapping) 286 miscRegs[MISCREG_HSCTLR] = 0x30c50830; 287 } else { 288 // also MISCREG_SCTLR_EL1 (by mapping) 289 miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init 290 // Always non-secure 291 miscRegs[MISCREG_SCR_EL3] = 1; 292 } 293 294 // Initialize configurable id registers 295 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 296 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 297 miscRegs[MISCREG_ID_AA64DFR0_EL1] = 298 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 299 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 300 301 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 302 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 303 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 304 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 305 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 306 307 miscRegs[MISCREG_ID_DFR0_EL1] = 308 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 309 310 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 311 312 // Enforce consistency with system-level settings... 313 314 // EL3 315 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 316 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 317 haveSecurity ? 0x2 : 0x0); 318 // EL2 319 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 320 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 321 haveVirtualization ? 0x2 : 0x0); 322 // Large ASID support 323 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 324 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 325 haveLargeAsid64 ? 0x2 : 0x0); 326 // Physical address size 327 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 328 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 329 encodePhysAddrRange64(physAddrRange64)); 330} 331 332MiscReg 333ISA::readMiscRegNoEffect(int misc_reg) const 334{ 335 assert(misc_reg < NumMiscRegs); 336 337 const auto ® = lookUpMiscReg[misc_reg]; // bit masks 338 const auto &map = getMiscIndices(misc_reg); 339 int lower = map.first, upper = map.second; 340 // NB!: apply architectural masks according to desired register, 341 // despite possibly getting value from different (mapped) register. 342 auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32)) 343 |(miscRegs[upper] << 32)); 344 if (val & reg.res0()) { 345 DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n", 346 miscRegName[misc_reg], val & reg.res0()); 347 } 348 if ((val & reg.res1()) != reg.res1()) { 349 DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n", 350 miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1()); 351 } 352 return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao 353} 354 355 356MiscReg 357ISA::readMiscReg(int misc_reg, ThreadContext *tc) 358{ 359 CPSR cpsr = 0; 360 PCState pc = 0; 361 SCR scr = 0; 362 363 if (misc_reg == MISCREG_CPSR) { 364 cpsr = miscRegs[misc_reg]; 365 pc = tc->pcState(); 366 cpsr.j = pc.jazelle() ? 1 : 0; 367 cpsr.t = pc.thumb() ? 1 : 0; 368 return cpsr; 369 } 370 371#ifndef NDEBUG 372 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 373 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 374 warn("Unimplemented system register %s read.\n", 375 miscRegName[misc_reg]); 376 else 377 panic("Unimplemented system register %s read.\n", 378 miscRegName[misc_reg]); 379 } 380#endif 381 382 switch (unflattenMiscReg(misc_reg)) { 383 case MISCREG_HCR: 384 { 385 if (!haveVirtualization) 386 return 0; 387 else 388 return readMiscRegNoEffect(MISCREG_HCR); 389 } 390 case MISCREG_CPACR: 391 { 392 const uint32_t ones = (uint32_t)(-1); 393 CPACR cpacrMask = 0; 394 // Only cp10, cp11, and ase are implemented, nothing else should 395 // be readable? (straight copy from the write code) 396 cpacrMask.cp10 = ones; 397 cpacrMask.cp11 = ones; 398 cpacrMask.asedis = ones; 399 400 // Security Extensions may limit the readability of CPACR 401 if (haveSecurity) { 402 scr = readMiscRegNoEffect(MISCREG_SCR); 403 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 404 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 405 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 406 // NB: Skipping the full loop, here 407 if (!nsacr.cp10) cpacrMask.cp10 = 0; 408 if (!nsacr.cp11) cpacrMask.cp11 = 0; 409 } 410 } 411 MiscReg val = readMiscRegNoEffect(MISCREG_CPACR); 412 val &= cpacrMask; 413 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 414 miscRegName[misc_reg], val); 415 return val; 416 } 417 case MISCREG_MPIDR: 418 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 419 scr = readMiscRegNoEffect(MISCREG_SCR); 420 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 421 return getMPIDR(system, tc); 422 } else { 423 return readMiscReg(MISCREG_VMPIDR, tc); 424 } 425 break; 426 case MISCREG_MPIDR_EL1: 427 // @todo in the absence of v8 virtualization support just return MPIDR_EL1 428 return getMPIDR(system, tc) & 0xffffffff; 429 case MISCREG_VMPIDR: 430 // top bit defined as RES1 431 return readMiscRegNoEffect(misc_reg) | 0x80000000; 432 case MISCREG_ID_AFR0: // not implemented, so alias MIDR 433 case MISCREG_REVIDR: // not implemented, so alias MIDR 434 case MISCREG_MIDR: 435 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 436 scr = readMiscRegNoEffect(MISCREG_SCR); 437 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 438 return readMiscRegNoEffect(misc_reg); 439 } else { 440 return readMiscRegNoEffect(MISCREG_VPIDR); 441 } 442 break; 443 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 444 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 445 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 446 case MISCREG_AIDR: // AUX ID set to 0 447 case MISCREG_TCMTR: // No TCM's 448 return 0; 449 450 case MISCREG_CLIDR: 451 warn_once("The clidr register always reports 0 caches.\n"); 452 warn_once("clidr LoUIS field of 0b001 to match current " 453 "ARM implementations.\n"); 454 return 0x00200000; 455 case MISCREG_CCSIDR: 456 warn_once("The ccsidr register isn't implemented and " 457 "always reads as 0.\n"); 458 break; 459 case MISCREG_CTR: // AArch32, ARMv7, top bit set 460 case MISCREG_CTR_EL0: // AArch64 461 { 462 //all caches have the same line size in gem5 463 //4 byte words in ARM 464 unsigned lineSizeWords = 465 tc->getSystemPtr()->cacheLineSize() / 4; 466 unsigned log2LineSizeWords = 0; 467 468 while (lineSizeWords >>= 1) { 469 ++log2LineSizeWords; 470 } 471 472 CTR ctr = 0; 473 //log2 of minimun i-cache line size (words) 474 ctr.iCacheLineSize = log2LineSizeWords; 475 //b11 - gem5 uses pipt 476 ctr.l1IndexPolicy = 0x3; 477 //log2 of minimum d-cache line size (words) 478 ctr.dCacheLineSize = log2LineSizeWords; 479 //log2 of max reservation size (words) 480 ctr.erg = log2LineSizeWords; 481 //log2 of max writeback size (words) 482 ctr.cwg = log2LineSizeWords; 483 //b100 - gem5 format is ARMv7 484 ctr.format = 0x4; 485 486 return ctr; 487 } 488 case MISCREG_ACTLR: 489 warn("Not doing anything for miscreg ACTLR\n"); 490 break; 491 492 case MISCREG_PMXEVTYPER_PMCCFILTR: 493 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 494 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 495 case MISCREG_PMCR ... MISCREG_PMOVSSET: 496 return pmu->readMiscReg(misc_reg); 497 498 case MISCREG_CPSR_Q: 499 panic("shouldn't be reading this register seperately\n"); 500 case MISCREG_FPSCR_QC: 501 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 502 case MISCREG_FPSCR_EXC: 503 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 504 case MISCREG_FPSR: 505 { 506 const uint32_t ones = (uint32_t)(-1); 507 FPSCR fpscrMask = 0; 508 fpscrMask.ioc = ones; 509 fpscrMask.dzc = ones; 510 fpscrMask.ofc = ones; 511 fpscrMask.ufc = ones; 512 fpscrMask.ixc = ones; 513 fpscrMask.idc = ones; 514 fpscrMask.qc = ones; 515 fpscrMask.v = ones; 516 fpscrMask.c = ones; 517 fpscrMask.z = ones; 518 fpscrMask.n = ones; 519 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 520 } 521 case MISCREG_FPCR: 522 { 523 const uint32_t ones = (uint32_t)(-1); 524 FPSCR fpscrMask = 0; 525 fpscrMask.len = ones; 526 fpscrMask.stride = ones; 527 fpscrMask.rMode = ones; 528 fpscrMask.fz = ones; 529 fpscrMask.dn = ones; 530 fpscrMask.ahp = ones; 531 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 532 } 533 case MISCREG_NZCV: 534 { 535 CPSR cpsr = 0; 536 cpsr.nz = tc->readCCReg(CCREG_NZ); 537 cpsr.c = tc->readCCReg(CCREG_C); 538 cpsr.v = tc->readCCReg(CCREG_V); 539 return cpsr; 540 } 541 case MISCREG_DAIF: 542 { 543 CPSR cpsr = 0; 544 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 545 return cpsr; 546 } 547 case MISCREG_SP_EL0: 548 { 549 return tc->readIntReg(INTREG_SP0); 550 } 551 case MISCREG_SP_EL1: 552 { 553 return tc->readIntReg(INTREG_SP1); 554 } 555 case MISCREG_SP_EL2: 556 { 557 return tc->readIntReg(INTREG_SP2); 558 } 559 case MISCREG_SPSEL: 560 { 561 return miscRegs[MISCREG_CPSR] & 0x1; 562 } 563 case MISCREG_CURRENTEL: 564 { 565 return miscRegs[MISCREG_CPSR] & 0xc; 566 } 567 case MISCREG_L2CTLR: 568 { 569 // mostly unimplemented, just set NumCPUs field from sim and return 570 L2CTLR l2ctlr = 0; 571 // b00:1CPU to b11:4CPUs 572 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 573 return l2ctlr; 574 } 575 case MISCREG_DBGDIDR: 576 /* For now just implement the version number. 577 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 578 */ 579 return 0x5 << 16; 580 case MISCREG_DBGDSCRint: 581 return 0; 582 case MISCREG_ISR: 583 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 584 readMiscRegNoEffect(MISCREG_HCR), 585 readMiscRegNoEffect(MISCREG_CPSR), 586 readMiscRegNoEffect(MISCREG_SCR)); 587 case MISCREG_ISR_EL1: 588 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 589 readMiscRegNoEffect(MISCREG_HCR_EL2), 590 readMiscRegNoEffect(MISCREG_CPSR), 591 readMiscRegNoEffect(MISCREG_SCR_EL3)); 592 case MISCREG_DCZID_EL0: 593 return 0x04; // DC ZVA clear 64-byte chunks 594 case MISCREG_HCPTR: 595 { 596 MiscReg val = readMiscRegNoEffect(misc_reg); 597 // The trap bit associated with CP14 is defined as RAZ 598 val &= ~(1 << 14); 599 // If a CP bit in NSACR is 0 then the corresponding bit in 600 // HCPTR is RAO/WI 601 bool secure_lookup = haveSecurity && 602 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 603 readMiscRegNoEffect(MISCREG_CPSR)); 604 if (!secure_lookup) { 605 MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR); 606 val |= (mask ^ 0x7FFF) & 0xBFFF; 607 } 608 // Set the bits for unimplemented coprocessors to RAO/WI 609 val |= 0x33FF; 610 return (val); 611 } 612 case MISCREG_HDFAR: // alias for secure DFAR 613 return readMiscRegNoEffect(MISCREG_DFAR_S); 614 case MISCREG_HIFAR: // alias for secure IFAR 615 return readMiscRegNoEffect(MISCREG_IFAR_S); 616 case MISCREG_HVBAR: // bottom bits reserved 617 return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0; 618 case MISCREG_SCTLR: 619 return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818; 620 case MISCREG_SCTLR_EL1: 621 return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800; 622 case MISCREG_SCTLR_EL2: 623 case MISCREG_SCTLR_EL3: 624 case MISCREG_HSCTLR: 625 return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; 626 627 case MISCREG_ID_PFR0: 628 // !ThumbEE | !Jazelle | Thumb | ARM 629 return 0x00000031; 630 case MISCREG_ID_PFR1: 631 { // Timer | Virti | !M Profile | TrustZone | ARMv4 632 bool haveTimer = (system->getGenericTimer() != NULL); 633 return 0x00000001 634 | (haveSecurity ? 0x00000010 : 0x0) 635 | (haveVirtualization ? 0x00001000 : 0x0) 636 | (haveTimer ? 0x00010000 : 0x0); 637 } 638 case MISCREG_ID_AA64PFR0_EL1: 639 return 0x0000000000000002 // AArch{64,32} supported at EL0 640 | 0x0000000000000020 // EL1 641 | (haveVirtualization ? 0x0000000000000200 : 0) // EL2 642 | (haveSecurity ? 0x0000000000002000 : 0); // EL3 643 case MISCREG_ID_AA64PFR1_EL1: 644 return 0; // bits [63:0] RES0 (reserved for future use) 645 646 // Generic Timer registers 647 case MISCREG_CNTHV_CTL_EL2: 648 case MISCREG_CNTHV_CVAL_EL2: 649 case MISCREG_CNTHV_TVAL_EL2: 650 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 651 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 652 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 653 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 654 return getGenericTimer(tc).readMiscReg(misc_reg); 655 656 default: 657 break; 658 659 } 660 return readMiscRegNoEffect(misc_reg); 661} 662 663void 664ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 665{ 666 assert(misc_reg < NumMiscRegs); 667 668 const auto ® = lookUpMiscReg[misc_reg]; // bit masks 669 const auto &map = getMiscIndices(misc_reg); 670 int lower = map.first, upper = map.second; 671 672 auto v = (val & ~reg.wi()) | reg.rao(); 673 if (upper > 0) { 674 miscRegs[lower] = bits(v, 31, 0); 675 miscRegs[upper] = bits(v, 63, 32); 676 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 677 misc_reg, lower, upper, v); 678 } else { 679 miscRegs[lower] = v; 680 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 681 misc_reg, lower, v); 682 } 683} 684 685void 686ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 687{ 688 689 MiscReg newVal = val; 690 bool secure_lookup; 691 SCR scr; 692 693 if (misc_reg == MISCREG_CPSR) { 694 updateRegMap(val); 695 696 697 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 698 int old_mode = old_cpsr.mode; 699 CPSR cpsr = val; 700 if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) { 701 getITBPtr(tc)->invalidateMiscReg(); 702 getDTBPtr(tc)->invalidateMiscReg(); 703 } 704 705 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 706 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 707 PCState pc = tc->pcState(); 708 pc.nextThumb(cpsr.t); 709 pc.nextJazelle(cpsr.j); 710 pc.illegalExec(cpsr.il == 1); 711 712 // Follow slightly different semantics if a CheckerCPU object 713 // is connected 714 CheckerCPU *checker = tc->getCheckerCpuPtr(); 715 if (checker) { 716 tc->pcStateNoRecord(pc); 717 } else { 718 tc->pcState(pc); 719 } 720 } else { 721#ifndef NDEBUG 722 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 723 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 724 warn("Unimplemented system register %s write with %#x.\n", 725 miscRegName[misc_reg], val); 726 else 727 panic("Unimplemented system register %s write with %#x.\n", 728 miscRegName[misc_reg], val); 729 } 730#endif 731 switch (unflattenMiscReg(misc_reg)) { 732 case MISCREG_CPACR: 733 { 734 735 const uint32_t ones = (uint32_t)(-1); 736 CPACR cpacrMask = 0; 737 // Only cp10, cp11, and ase are implemented, nothing else should 738 // be writable 739 cpacrMask.cp10 = ones; 740 cpacrMask.cp11 = ones; 741 cpacrMask.asedis = ones; 742 743 // Security Extensions may limit the writability of CPACR 744 if (haveSecurity) { 745 scr = readMiscRegNoEffect(MISCREG_SCR); 746 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 747 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 748 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 749 // NB: Skipping the full loop, here 750 if (!nsacr.cp10) cpacrMask.cp10 = 0; 751 if (!nsacr.cp11) cpacrMask.cp11 = 0; 752 } 753 } 754 755 MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR); 756 newVal &= cpacrMask; 757 newVal |= old_val & ~cpacrMask; 758 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 759 miscRegName[misc_reg], newVal); 760 } 761 break; 762 case MISCREG_CPTR_EL2: 763 { 764 const uint32_t ones = (uint32_t)(-1); 765 CPTR cptrMask = 0; 766 cptrMask.tcpac = ones; 767 cptrMask.tta = ones; 768 cptrMask.tfp = ones; 769 newVal &= cptrMask; 770 cptrMask = 0; 771 cptrMask.res1_13_12_el2 = ones; 772 cptrMask.res1_9_0_el2 = ones; 773 newVal |= cptrMask; 774 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 775 miscRegName[misc_reg], newVal); 776 } 777 break; 778 case MISCREG_CPTR_EL3: 779 { 780 const uint32_t ones = (uint32_t)(-1); 781 CPTR cptrMask = 0; 782 cptrMask.tcpac = ones; 783 cptrMask.tta = ones; 784 cptrMask.tfp = ones; 785 newVal &= cptrMask; 786 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 787 miscRegName[misc_reg], newVal); 788 } 789 break; 790 case MISCREG_CSSELR: 791 warn_once("The csselr register isn't implemented.\n"); 792 return; 793 794 case MISCREG_DC_ZVA_Xt: 795 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 796 return; 797 798 case MISCREG_FPSCR: 799 { 800 const uint32_t ones = (uint32_t)(-1); 801 FPSCR fpscrMask = 0; 802 fpscrMask.ioc = ones; 803 fpscrMask.dzc = ones; 804 fpscrMask.ofc = ones; 805 fpscrMask.ufc = ones; 806 fpscrMask.ixc = ones; 807 fpscrMask.idc = ones; 808 fpscrMask.ioe = ones; 809 fpscrMask.dze = ones; 810 fpscrMask.ofe = ones; 811 fpscrMask.ufe = ones; 812 fpscrMask.ixe = ones; 813 fpscrMask.ide = ones; 814 fpscrMask.len = ones; 815 fpscrMask.stride = ones; 816 fpscrMask.rMode = ones; 817 fpscrMask.fz = ones; 818 fpscrMask.dn = ones; 819 fpscrMask.ahp = ones; 820 fpscrMask.qc = ones; 821 fpscrMask.v = ones; 822 fpscrMask.c = ones; 823 fpscrMask.z = ones; 824 fpscrMask.n = ones; 825 newVal = (newVal & (uint32_t)fpscrMask) | 826 (readMiscRegNoEffect(MISCREG_FPSCR) & 827 ~(uint32_t)fpscrMask); 828 tc->getDecoderPtr()->setContext(newVal); 829 } 830 break; 831 case MISCREG_FPSR: 832 { 833 const uint32_t ones = (uint32_t)(-1); 834 FPSCR fpscrMask = 0; 835 fpscrMask.ioc = ones; 836 fpscrMask.dzc = ones; 837 fpscrMask.ofc = ones; 838 fpscrMask.ufc = ones; 839 fpscrMask.ixc = ones; 840 fpscrMask.idc = ones; 841 fpscrMask.qc = ones; 842 fpscrMask.v = ones; 843 fpscrMask.c = ones; 844 fpscrMask.z = ones; 845 fpscrMask.n = ones; 846 newVal = (newVal & (uint32_t)fpscrMask) | 847 (readMiscRegNoEffect(MISCREG_FPSCR) & 848 ~(uint32_t)fpscrMask); 849 misc_reg = MISCREG_FPSCR; 850 } 851 break; 852 case MISCREG_FPCR: 853 { 854 const uint32_t ones = (uint32_t)(-1); 855 FPSCR fpscrMask = 0; 856 fpscrMask.len = ones; 857 fpscrMask.stride = ones; 858 fpscrMask.rMode = ones; 859 fpscrMask.fz = ones; 860 fpscrMask.dn = ones; 861 fpscrMask.ahp = ones; 862 newVal = (newVal & (uint32_t)fpscrMask) | 863 (readMiscRegNoEffect(MISCREG_FPSCR) & 864 ~(uint32_t)fpscrMask); 865 misc_reg = MISCREG_FPSCR; 866 } 867 break; 868 case MISCREG_CPSR_Q: 869 { 870 assert(!(newVal & ~CpsrMaskQ)); 871 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 872 misc_reg = MISCREG_CPSR; 873 } 874 break; 875 case MISCREG_FPSCR_QC: 876 { 877 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 878 (newVal & FpscrQcMask); 879 misc_reg = MISCREG_FPSCR; 880 } 881 break; 882 case MISCREG_FPSCR_EXC: 883 { 884 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 885 (newVal & FpscrExcMask); 886 misc_reg = MISCREG_FPSCR; 887 } 888 break; 889 case MISCREG_FPEXC: 890 { 891 // vfpv3 architecture, section B.6.1 of DDI04068 892 // bit 29 - valid only if fpexc[31] is 0 893 const uint32_t fpexcMask = 0x60000000; 894 newVal = (newVal & fpexcMask) | 895 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 896 } 897 break; 898 case MISCREG_HCR: 899 { 900 if (!haveVirtualization) 901 return; 902 } 903 break; 904 case MISCREG_IFSR: 905 { 906 // ARM ARM (ARM DDI 0406C.b) B4.1.96 907 const uint32_t ifsrMask = 908 mask(31, 13) | mask(11, 11) | mask(8, 6); 909 newVal = newVal & ~ifsrMask; 910 } 911 break; 912 case MISCREG_DFSR: 913 { 914 // ARM ARM (ARM DDI 0406C.b) B4.1.52 915 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 916 newVal = newVal & ~dfsrMask; 917 } 918 break; 919 case MISCREG_AMAIR0: 920 case MISCREG_AMAIR1: 921 { 922 // ARM ARM (ARM DDI 0406C.b) B4.1.5 923 // Valid only with LPAE 924 if (!haveLPAE) 925 return; 926 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 927 } 928 break; 929 case MISCREG_SCR: 930 getITBPtr(tc)->invalidateMiscReg(); 931 getDTBPtr(tc)->invalidateMiscReg(); 932 break; 933 case MISCREG_SCTLR: 934 { 935 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 936 scr = readMiscRegNoEffect(MISCREG_SCR); 937 938 MiscRegIndex sctlr_idx; 939 if (haveSecurity && !highestELIs64 && !scr.ns) { 940 sctlr_idx = MISCREG_SCTLR_S; 941 } else { 942 sctlr_idx = MISCREG_SCTLR_NS; 943 } 944 945 SCTLR sctlr = miscRegs[sctlr_idx]; 946 SCTLR new_sctlr = newVal; 947 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 948 miscRegs[sctlr_idx] = (MiscReg)new_sctlr; 949 getITBPtr(tc)->invalidateMiscReg(); 950 getDTBPtr(tc)->invalidateMiscReg(); 951 } 952 case MISCREG_MIDR: 953 case MISCREG_ID_PFR0: 954 case MISCREG_ID_PFR1: 955 case MISCREG_ID_DFR0: 956 case MISCREG_ID_MMFR0: 957 case MISCREG_ID_MMFR1: 958 case MISCREG_ID_MMFR2: 959 case MISCREG_ID_MMFR3: 960 case MISCREG_ID_ISAR0: 961 case MISCREG_ID_ISAR1: 962 case MISCREG_ID_ISAR2: 963 case MISCREG_ID_ISAR3: 964 case MISCREG_ID_ISAR4: 965 case MISCREG_ID_ISAR5: 966 967 case MISCREG_MPIDR: 968 case MISCREG_FPSID: 969 case MISCREG_TLBTR: 970 case MISCREG_MVFR0: 971 case MISCREG_MVFR1: 972 973 case MISCREG_ID_AA64AFR0_EL1: 974 case MISCREG_ID_AA64AFR1_EL1: 975 case MISCREG_ID_AA64DFR0_EL1: 976 case MISCREG_ID_AA64DFR1_EL1: 977 case MISCREG_ID_AA64ISAR0_EL1: 978 case MISCREG_ID_AA64ISAR1_EL1: 979 case MISCREG_ID_AA64MMFR0_EL1: 980 case MISCREG_ID_AA64MMFR1_EL1: 981 case MISCREG_ID_AA64PFR0_EL1: 982 case MISCREG_ID_AA64PFR1_EL1: 983 // ID registers are constants. 984 return; 985 986 // TLB Invalidate All 987 case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 988 { 989 assert32(tc); 990 scr = readMiscReg(MISCREG_SCR, tc); 991 992 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 993 tlbiOp(tc); 994 return; 995 } 996 // TLB Invalidate All, Inner Shareable 997 case MISCREG_TLBIALLIS: 998 { 999 assert32(tc); 1000 scr = readMiscReg(MISCREG_SCR, tc); 1001 1002 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1003 tlbiOp.broadcast(tc); 1004 return; 1005 } 1006 // Instruction TLB Invalidate All 1007 case MISCREG_ITLBIALL: 1008 { 1009 assert32(tc); 1010 scr = readMiscReg(MISCREG_SCR, tc); 1011 1012 ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1013 tlbiOp(tc); 1014 return; 1015 } 1016 // Data TLB Invalidate All 1017 case MISCREG_DTLBIALL: 1018 { 1019 assert32(tc); 1020 scr = readMiscReg(MISCREG_SCR, tc); 1021 1022 DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1023 tlbiOp(tc); 1024 return; 1025 } 1026 // TLB Invalidate by VA 1027 // mcr tlbimval(is) is invalidating all matching entries 1028 // regardless of the level of lookup, since in gem5 we cache 1029 // in the tlb the last level of lookup only. 1030 case MISCREG_TLBIMVA: 1031 case MISCREG_TLBIMVAL: 1032 { 1033 assert32(tc); 1034 scr = readMiscReg(MISCREG_SCR, tc); 1035 1036 TLBIMVA tlbiOp(EL1, 1037 haveSecurity && !scr.ns, 1038 mbits(newVal, 31, 12), 1039 bits(newVal, 7,0)); 1040 1041 tlbiOp(tc); 1042 return; 1043 } 1044 // TLB Invalidate by VA, Inner Shareable 1045 case MISCREG_TLBIMVAIS: 1046 case MISCREG_TLBIMVALIS: 1047 { 1048 assert32(tc); 1049 scr = readMiscReg(MISCREG_SCR, tc); 1050 1051 TLBIMVA tlbiOp(EL1, 1052 haveSecurity && !scr.ns, 1053 mbits(newVal, 31, 12), 1054 bits(newVal, 7,0)); 1055 1056 tlbiOp.broadcast(tc); 1057 return; 1058 } 1059 // TLB Invalidate by ASID match 1060 case MISCREG_TLBIASID: 1061 { 1062 assert32(tc); 1063 scr = readMiscReg(MISCREG_SCR, tc); 1064 1065 TLBIASID tlbiOp(EL1, 1066 haveSecurity && !scr.ns, 1067 bits(newVal, 7,0)); 1068 1069 tlbiOp(tc); 1070 return; 1071 } 1072 // TLB Invalidate by ASID match, Inner Shareable 1073 case MISCREG_TLBIASIDIS: 1074 { 1075 assert32(tc); 1076 scr = readMiscReg(MISCREG_SCR, tc); 1077 1078 TLBIASID tlbiOp(EL1, 1079 haveSecurity && !scr.ns, 1080 bits(newVal, 7,0)); 1081 1082 tlbiOp.broadcast(tc); 1083 return; 1084 } 1085 // mcr tlbimvaal(is) is invalidating all matching entries 1086 // regardless of the level of lookup, since in gem5 we cache 1087 // in the tlb the last level of lookup only. 1088 // TLB Invalidate by VA, All ASID 1089 case MISCREG_TLBIMVAA: 1090 case MISCREG_TLBIMVAAL: 1091 { 1092 assert32(tc); 1093 scr = readMiscReg(MISCREG_SCR, tc); 1094 1095 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1096 mbits(newVal, 31,12), false); 1097 1098 tlbiOp(tc); 1099 return; 1100 } 1101 // TLB Invalidate by VA, All ASID, Inner Shareable 1102 case MISCREG_TLBIMVAAIS: 1103 case MISCREG_TLBIMVAALIS: 1104 { 1105 assert32(tc); 1106 scr = readMiscReg(MISCREG_SCR, tc); 1107 1108 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1109 mbits(newVal, 31,12), false); 1110 1111 tlbiOp.broadcast(tc); 1112 return; 1113 } 1114 // mcr tlbimvalh(is) is invalidating all matching entries 1115 // regardless of the level of lookup, since in gem5 we cache 1116 // in the tlb the last level of lookup only. 1117 // TLB Invalidate by VA, Hyp mode 1118 case MISCREG_TLBIMVAH: 1119 case MISCREG_TLBIMVALH: 1120 { 1121 assert32(tc); 1122 scr = readMiscReg(MISCREG_SCR, tc); 1123 1124 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1125 mbits(newVal, 31,12), true); 1126 1127 tlbiOp(tc); 1128 return; 1129 } 1130 // TLB Invalidate by VA, Hyp mode, Inner Shareable 1131 case MISCREG_TLBIMVAHIS: 1132 case MISCREG_TLBIMVALHIS: 1133 { 1134 assert32(tc); 1135 scr = readMiscReg(MISCREG_SCR, tc); 1136 1137 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1138 mbits(newVal, 31,12), true); 1139 1140 tlbiOp.broadcast(tc); 1141 return; 1142 } 1143 // mcr tlbiipas2l(is) is invalidating all matching entries 1144 // regardless of the level of lookup, since in gem5 we cache 1145 // in the tlb the last level of lookup only. 1146 // TLB Invalidate by Intermediate Physical Address, Stage 2 1147 case MISCREG_TLBIIPAS2: 1148 case MISCREG_TLBIIPAS2L: 1149 { 1150 assert32(tc); 1151 scr = readMiscReg(MISCREG_SCR, tc); 1152 1153 TLBIIPA tlbiOp(EL1, 1154 haveSecurity && !scr.ns, 1155 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1156 1157 tlbiOp(tc); 1158 return; 1159 } 1160 // TLB Invalidate by Intermediate Physical Address, Stage 2, 1161 // Inner Shareable 1162 case MISCREG_TLBIIPAS2IS: 1163 case MISCREG_TLBIIPAS2LIS: 1164 { 1165 assert32(tc); 1166 scr = readMiscReg(MISCREG_SCR, tc); 1167 1168 TLBIIPA tlbiOp(EL1, 1169 haveSecurity && !scr.ns, 1170 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1171 1172 tlbiOp.broadcast(tc); 1173 return; 1174 } 1175 // Instruction TLB Invalidate by VA 1176 case MISCREG_ITLBIMVA: 1177 { 1178 assert32(tc); 1179 scr = readMiscReg(MISCREG_SCR, tc); 1180 1181 ITLBIMVA tlbiOp(EL1, 1182 haveSecurity && !scr.ns, 1183 mbits(newVal, 31, 12), 1184 bits(newVal, 7,0)); 1185 1186 tlbiOp(tc); 1187 return; 1188 } 1189 // Data TLB Invalidate by VA 1190 case MISCREG_DTLBIMVA: 1191 { 1192 assert32(tc); 1193 scr = readMiscReg(MISCREG_SCR, tc); 1194 1195 DTLBIMVA tlbiOp(EL1, 1196 haveSecurity && !scr.ns, 1197 mbits(newVal, 31, 12), 1198 bits(newVal, 7,0)); 1199 1200 tlbiOp(tc); 1201 return; 1202 } 1203 // Instruction TLB Invalidate by ASID match 1204 case MISCREG_ITLBIASID: 1205 { 1206 assert32(tc); 1207 scr = readMiscReg(MISCREG_SCR, tc); 1208 1209 ITLBIASID tlbiOp(EL1, 1210 haveSecurity && !scr.ns, 1211 bits(newVal, 7,0)); 1212 1213 tlbiOp(tc); 1214 return; 1215 } 1216 // Data TLB Invalidate by ASID match 1217 case MISCREG_DTLBIASID: 1218 { 1219 assert32(tc); 1220 scr = readMiscReg(MISCREG_SCR, tc); 1221 1222 DTLBIASID tlbiOp(EL1, 1223 haveSecurity && !scr.ns, 1224 bits(newVal, 7,0)); 1225 1226 tlbiOp(tc); 1227 return; 1228 } 1229 // TLB Invalidate All, Non-Secure Non-Hyp 1230 case MISCREG_TLBIALLNSNH: 1231 { 1232 assert32(tc); 1233 1234 TLBIALLN tlbiOp(EL1, false); 1235 tlbiOp(tc); 1236 return; 1237 } 1238 // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable 1239 case MISCREG_TLBIALLNSNHIS: 1240 { 1241 assert32(tc); 1242 1243 TLBIALLN tlbiOp(EL1, false); 1244 tlbiOp.broadcast(tc); 1245 return; 1246 } 1247 // TLB Invalidate All, Hyp mode 1248 case MISCREG_TLBIALLH: 1249 { 1250 assert32(tc); 1251 1252 TLBIALLN tlbiOp(EL1, true); 1253 tlbiOp(tc); 1254 return; 1255 } 1256 // TLB Invalidate All, Hyp mode, Inner Shareable 1257 case MISCREG_TLBIALLHIS: 1258 { 1259 assert32(tc); 1260 1261 TLBIALLN tlbiOp(EL1, true); 1262 tlbiOp.broadcast(tc); 1263 return; 1264 } 1265 // AArch64 TLB Invalidate All, EL3 1266 case MISCREG_TLBI_ALLE3: 1267 { 1268 assert64(tc); 1269 1270 TLBIALL tlbiOp(EL3, true); 1271 tlbiOp(tc); 1272 return; 1273 } 1274 // AArch64 TLB Invalidate All, EL3, Inner Shareable 1275 case MISCREG_TLBI_ALLE3IS: 1276 { 1277 assert64(tc); 1278 1279 TLBIALL tlbiOp(EL3, true); 1280 tlbiOp.broadcast(tc); 1281 return; 1282 } 1283 // @todo: uncomment this to enable Virtualization 1284 // case MISCREG_TLBI_ALLE2IS: 1285 // case MISCREG_TLBI_ALLE2: 1286 // AArch64 TLB Invalidate All, EL1 1287 case MISCREG_TLBI_ALLE1: 1288 case MISCREG_TLBI_VMALLE1: 1289 case MISCREG_TLBI_VMALLS12E1: 1290 // @todo: handle VMID and stage 2 to enable Virtualization 1291 { 1292 assert64(tc); 1293 scr = readMiscReg(MISCREG_SCR, tc); 1294 1295 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1296 tlbiOp(tc); 1297 return; 1298 } 1299 // AArch64 TLB Invalidate All, EL1, Inner Shareable 1300 case MISCREG_TLBI_ALLE1IS: 1301 case MISCREG_TLBI_VMALLE1IS: 1302 case MISCREG_TLBI_VMALLS12E1IS: 1303 // @todo: handle VMID and stage 2 to enable Virtualization 1304 { 1305 assert64(tc); 1306 scr = readMiscReg(MISCREG_SCR, tc); 1307 1308 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1309 tlbiOp.broadcast(tc); 1310 return; 1311 } 1312 // VAEx(IS) and VALEx(IS) are the same because TLBs 1313 // only store entries 1314 // from the last level of translation table walks 1315 // @todo: handle VMID to enable Virtualization 1316 // AArch64 TLB Invalidate by VA, EL3 1317 case MISCREG_TLBI_VAE3_Xt: 1318 case MISCREG_TLBI_VALE3_Xt: 1319 { 1320 assert64(tc); 1321 1322 TLBIMVA tlbiOp(EL3, true, 1323 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1324 0xbeef); 1325 tlbiOp(tc); 1326 return; 1327 } 1328 // AArch64 TLB Invalidate by VA, EL3, Inner Shareable 1329 case MISCREG_TLBI_VAE3IS_Xt: 1330 case MISCREG_TLBI_VALE3IS_Xt: 1331 { 1332 assert64(tc); 1333 1334 TLBIMVA tlbiOp(EL3, true, 1335 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1336 0xbeef); 1337 1338 tlbiOp.broadcast(tc); 1339 return; 1340 } 1341 // AArch64 TLB Invalidate by VA, EL2 1342 case MISCREG_TLBI_VAE2_Xt: 1343 case MISCREG_TLBI_VALE2_Xt: 1344 { 1345 assert64(tc); 1346 scr = readMiscReg(MISCREG_SCR, tc); 1347 1348 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1349 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1350 0xbeef); 1351 tlbiOp(tc); 1352 return; 1353 } 1354 // AArch64 TLB Invalidate by VA, EL2, Inner Shareable 1355 case MISCREG_TLBI_VAE2IS_Xt: 1356 case MISCREG_TLBI_VALE2IS_Xt: 1357 { 1358 assert64(tc); 1359 scr = readMiscReg(MISCREG_SCR, tc); 1360 1361 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1362 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1363 0xbeef); 1364 1365 tlbiOp.broadcast(tc); 1366 return; 1367 } 1368 // AArch64 TLB Invalidate by VA, EL1 1369 case MISCREG_TLBI_VAE1_Xt: 1370 case MISCREG_TLBI_VALE1_Xt: 1371 { 1372 assert64(tc); 1373 scr = readMiscReg(MISCREG_SCR, tc); 1374 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1375 bits(newVal, 55, 48); 1376 1377 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1378 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1379 asid); 1380 1381 tlbiOp(tc); 1382 return; 1383 } 1384 // AArch64 TLB Invalidate by VA, EL1, Inner Shareable 1385 case MISCREG_TLBI_VAE1IS_Xt: 1386 case MISCREG_TLBI_VALE1IS_Xt: 1387 { 1388 assert64(tc); 1389 scr = readMiscReg(MISCREG_SCR, tc); 1390 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1391 bits(newVal, 55, 48); 1392 1393 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1394 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1395 asid); 1396 1397 tlbiOp.broadcast(tc); 1398 return; 1399 } 1400 // AArch64 TLB Invalidate by ASID, EL1 1401 // @todo: handle VMID to enable Virtualization 1402 case MISCREG_TLBI_ASIDE1_Xt: 1403 { 1404 assert64(tc); 1405 scr = readMiscReg(MISCREG_SCR, tc); 1406 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1407 bits(newVal, 55, 48); 1408 1409 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1410 tlbiOp(tc); 1411 return; 1412 } 1413 // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable 1414 case MISCREG_TLBI_ASIDE1IS_Xt: 1415 { 1416 assert64(tc); 1417 scr = readMiscReg(MISCREG_SCR, tc); 1418 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1419 bits(newVal, 55, 48); 1420 1421 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1422 tlbiOp.broadcast(tc); 1423 return; 1424 } 1425 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 1426 // entries from the last level of translation table walks 1427 // AArch64 TLB Invalidate by VA, All ASID, EL1 1428 case MISCREG_TLBI_VAAE1_Xt: 1429 case MISCREG_TLBI_VAALE1_Xt: 1430 { 1431 assert64(tc); 1432 scr = readMiscReg(MISCREG_SCR, tc); 1433 1434 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1435 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 1436 1437 tlbiOp(tc); 1438 return; 1439 } 1440 // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable 1441 case MISCREG_TLBI_VAAE1IS_Xt: 1442 case MISCREG_TLBI_VAALE1IS_Xt: 1443 { 1444 assert64(tc); 1445 scr = readMiscReg(MISCREG_SCR, tc); 1446 1447 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1448 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 1449 1450 tlbiOp.broadcast(tc); 1451 return; 1452 } 1453 // AArch64 TLB Invalidate by Intermediate Physical Address, 1454 // Stage 2, EL1 1455 case MISCREG_TLBI_IPAS2E1_Xt: 1456 case MISCREG_TLBI_IPAS2LE1_Xt: 1457 { 1458 assert64(tc); 1459 scr = readMiscReg(MISCREG_SCR, tc); 1460 1461 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1462 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1463 1464 tlbiOp(tc); 1465 return; 1466 } 1467 // AArch64 TLB Invalidate by Intermediate Physical Address, 1468 // Stage 2, EL1, Inner Shareable 1469 case MISCREG_TLBI_IPAS2E1IS_Xt: 1470 case MISCREG_TLBI_IPAS2LE1IS_Xt: 1471 { 1472 assert64(tc); 1473 scr = readMiscReg(MISCREG_SCR, tc); 1474 1475 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1476 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1477 1478 tlbiOp.broadcast(tc); 1479 return; 1480 } 1481 case MISCREG_ACTLR: 1482 warn("Not doing anything for write of miscreg ACTLR\n"); 1483 break; 1484 1485 case MISCREG_PMXEVTYPER_PMCCFILTR: 1486 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 1487 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 1488 case MISCREG_PMCR ... MISCREG_PMOVSSET: 1489 pmu->setMiscReg(misc_reg, newVal); 1490 break; 1491 1492 1493 case MISCREG_HSTR: // TJDBX, now redifined to be RES0 1494 { 1495 HSTR hstrMask = 0; 1496 hstrMask.tjdbx = 1; 1497 newVal &= ~((uint32_t) hstrMask); 1498 break; 1499 } 1500 case MISCREG_HCPTR: 1501 { 1502 // If a CP bit in NSACR is 0 then the corresponding bit in 1503 // HCPTR is RAO/WI. Same applies to NSASEDIS 1504 secure_lookup = haveSecurity && 1505 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 1506 readMiscRegNoEffect(MISCREG_CPSR)); 1507 if (!secure_lookup) { 1508 MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 1509 MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 1510 newVal = (newVal & ~mask) | (oldValue & mask); 1511 } 1512 break; 1513 } 1514 case MISCREG_HDFAR: // alias for secure DFAR 1515 misc_reg = MISCREG_DFAR_S; 1516 break; 1517 case MISCREG_HIFAR: // alias for secure IFAR 1518 misc_reg = MISCREG_IFAR_S; 1519 break; 1520 case MISCREG_ATS1CPR: 1521 case MISCREG_ATS1CPW: 1522 case MISCREG_ATS1CUR: 1523 case MISCREG_ATS1CUW: 1524 case MISCREG_ATS12NSOPR: 1525 case MISCREG_ATS12NSOPW: 1526 case MISCREG_ATS12NSOUR: 1527 case MISCREG_ATS12NSOUW: 1528 case MISCREG_ATS1HR: 1529 case MISCREG_ATS1HW: 1530 { 1531 Request::Flags flags = 0; 1532 BaseTLB::Mode mode = BaseTLB::Read; 1533 TLB::ArmTranslationType tranType = TLB::NormalTran; 1534 Fault fault; 1535 switch(misc_reg) { 1536 case MISCREG_ATS1CPR: 1537 flags = TLB::MustBeOne; 1538 tranType = TLB::S1CTran; 1539 mode = BaseTLB::Read; 1540 break; 1541 case MISCREG_ATS1CPW: 1542 flags = TLB::MustBeOne; 1543 tranType = TLB::S1CTran; 1544 mode = BaseTLB::Write; 1545 break; 1546 case MISCREG_ATS1CUR: 1547 flags = TLB::MustBeOne | TLB::UserMode; 1548 tranType = TLB::S1CTran; 1549 mode = BaseTLB::Read; 1550 break; 1551 case MISCREG_ATS1CUW: 1552 flags = TLB::MustBeOne | TLB::UserMode; 1553 tranType = TLB::S1CTran; 1554 mode = BaseTLB::Write; 1555 break; 1556 case MISCREG_ATS12NSOPR: 1557 if (!haveSecurity) 1558 panic("Security Extensions required for ATS12NSOPR"); 1559 flags = TLB::MustBeOne; 1560 tranType = TLB::S1S2NsTran; 1561 mode = BaseTLB::Read; 1562 break; 1563 case MISCREG_ATS12NSOPW: 1564 if (!haveSecurity) 1565 panic("Security Extensions required for ATS12NSOPW"); 1566 flags = TLB::MustBeOne; 1567 tranType = TLB::S1S2NsTran; 1568 mode = BaseTLB::Write; 1569 break; 1570 case MISCREG_ATS12NSOUR: 1571 if (!haveSecurity) 1572 panic("Security Extensions required for ATS12NSOUR"); 1573 flags = TLB::MustBeOne | TLB::UserMode; 1574 tranType = TLB::S1S2NsTran; 1575 mode = BaseTLB::Read; 1576 break; 1577 case MISCREG_ATS12NSOUW: 1578 if (!haveSecurity) 1579 panic("Security Extensions required for ATS12NSOUW"); 1580 flags = TLB::MustBeOne | TLB::UserMode; 1581 tranType = TLB::S1S2NsTran; 1582 mode = BaseTLB::Write; 1583 break; 1584 case MISCREG_ATS1HR: // only really useful from secure mode. 1585 flags = TLB::MustBeOne; 1586 tranType = TLB::HypMode; 1587 mode = BaseTLB::Read; 1588 break; 1589 case MISCREG_ATS1HW: 1590 flags = TLB::MustBeOne; 1591 tranType = TLB::HypMode; 1592 mode = BaseTLB::Write; 1593 break; 1594 } 1595 // If we're in timing mode then doing the translation in 1596 // functional mode then we're slightly distorting performance 1597 // results obtained from simulations. The translation should be 1598 // done in the same mode the core is running in. NOTE: This 1599 // can't be an atomic translation because that causes problems 1600 // with unexpected atomic snoop requests. 1601 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1602 1603 auto req = std::make_shared<Request>( 1604 0, val, 0, flags, Request::funcMasterId, 1605 tc->pcState().pc(), tc->contextId()); 1606 1607 fault = getDTBPtr(tc)->translateFunctional( 1608 req, tc, mode, tranType); 1609 1610 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1611 HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 1612 1613 MiscReg newVal; 1614 if (fault == NoFault) { 1615 Addr paddr = req->getPaddr(); 1616 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 1617 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 1618 newVal = (paddr & mask(39, 12)) | 1619 (getDTBPtr(tc)->getAttr()); 1620 } else { 1621 newVal = (paddr & 0xfffff000) | 1622 (getDTBPtr(tc)->getAttr()); 1623 } 1624 DPRINTF(MiscRegs, 1625 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 1626 val, newVal); 1627 } else { 1628 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1629 armFault->update(tc); 1630 // Set fault bit and FSR 1631 FSR fsr = armFault->getFsr(tc); 1632 1633 newVal = ((fsr >> 9) & 1) << 11; 1634 if (newVal) { 1635 // LPAE - rearange fault status 1636 newVal |= ((fsr >> 0) & 0x3f) << 1; 1637 } else { 1638 // VMSA - rearange fault status 1639 newVal |= ((fsr >> 0) & 0xf) << 1; 1640 newVal |= ((fsr >> 10) & 0x1) << 5; 1641 newVal |= ((fsr >> 12) & 0x1) << 6; 1642 } 1643 newVal |= 0x1; // F bit 1644 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1645 newVal |= armFault->isStage2() ? 0x200 : 0; 1646 DPRINTF(MiscRegs, 1647 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 1648 val, fsr, newVal); 1649 } 1650 setMiscRegNoEffect(MISCREG_PAR, newVal); 1651 return; 1652 } 1653 case MISCREG_TTBCR: 1654 { 1655 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1656 const uint32_t ones = (uint32_t)(-1); 1657 TTBCR ttbcrMask = 0; 1658 TTBCR ttbcrNew = newVal; 1659 1660 // ARM DDI 0406C.b, ARMv7-32 1661 ttbcrMask.n = ones; // T0SZ 1662 if (haveSecurity) { 1663 ttbcrMask.pd0 = ones; 1664 ttbcrMask.pd1 = ones; 1665 } 1666 ttbcrMask.epd0 = ones; 1667 ttbcrMask.irgn0 = ones; 1668 ttbcrMask.orgn0 = ones; 1669 ttbcrMask.sh0 = ones; 1670 ttbcrMask.ps = ones; // T1SZ 1671 ttbcrMask.a1 = ones; 1672 ttbcrMask.epd1 = ones; 1673 ttbcrMask.irgn1 = ones; 1674 ttbcrMask.orgn1 = ones; 1675 ttbcrMask.sh1 = ones; 1676 if (haveLPAE) 1677 ttbcrMask.eae = ones; 1678 1679 if (haveLPAE && ttbcrNew.eae) { 1680 newVal = newVal & ttbcrMask; 1681 } else { 1682 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 1683 } 1684 // Invalidate TLB MiscReg 1685 getITBPtr(tc)->invalidateMiscReg(); 1686 getDTBPtr(tc)->invalidateMiscReg(); 1687 break; 1688 } 1689 case MISCREG_TTBR0: 1690 case MISCREG_TTBR1: 1691 { 1692 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1693 if (haveLPAE) { 1694 if (ttbcr.eae) { 1695 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 1696 // ARMv8 AArch32 bit 63-56 only 1697 uint64_t ttbrMask = mask(63,56) | mask(47,40); 1698 newVal = (newVal & (~ttbrMask)); 1699 } 1700 } 1701 // Invalidate TLB MiscReg 1702 getITBPtr(tc)->invalidateMiscReg(); 1703 getDTBPtr(tc)->invalidateMiscReg(); 1704 break; 1705 } 1706 case MISCREG_SCTLR_EL1: 1707 case MISCREG_CONTEXTIDR: 1708 case MISCREG_PRRR: 1709 case MISCREG_NMRR: 1710 case MISCREG_MAIR0: 1711 case MISCREG_MAIR1: 1712 case MISCREG_DACR: 1713 case MISCREG_VTTBR: 1714 case MISCREG_SCR_EL3: 1715 case MISCREG_HCR_EL2: 1716 case MISCREG_TCR_EL1: 1717 case MISCREG_TCR_EL2: 1718 case MISCREG_TCR_EL3: 1719 case MISCREG_SCTLR_EL2: 1720 case MISCREG_SCTLR_EL3: 1721 case MISCREG_HSCTLR: 1722 case MISCREG_TTBR0_EL1: 1723 case MISCREG_TTBR1_EL1: 1724 case MISCREG_TTBR0_EL2: 1725 case MISCREG_TTBR1_EL2: 1726 case MISCREG_TTBR0_EL3: 1727 getITBPtr(tc)->invalidateMiscReg(); 1728 getDTBPtr(tc)->invalidateMiscReg(); 1729 break; 1730 case MISCREG_NZCV: 1731 { 1732 CPSR cpsr = val; 1733 1734 tc->setCCReg(CCREG_NZ, cpsr.nz); 1735 tc->setCCReg(CCREG_C, cpsr.c); 1736 tc->setCCReg(CCREG_V, cpsr.v); 1737 } 1738 break; 1739 case MISCREG_DAIF: 1740 { 1741 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1742 cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 1743 newVal = cpsr; 1744 misc_reg = MISCREG_CPSR; 1745 } 1746 break; 1747 case MISCREG_SP_EL0: 1748 tc->setIntReg(INTREG_SP0, newVal); 1749 break; 1750 case MISCREG_SP_EL1: 1751 tc->setIntReg(INTREG_SP1, newVal); 1752 break; 1753 case MISCREG_SP_EL2: 1754 tc->setIntReg(INTREG_SP2, newVal); 1755 break; 1756 case MISCREG_SPSEL: 1757 { 1758 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1759 cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 1760 newVal = cpsr; 1761 misc_reg = MISCREG_CPSR; 1762 } 1763 break; 1764 case MISCREG_CURRENTEL: 1765 { 1766 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1767 cpsr.el = (uint8_t) ((CPSR) newVal).el; 1768 newVal = cpsr; 1769 misc_reg = MISCREG_CPSR; 1770 } 1771 break; 1772 case MISCREG_AT_S1E1R_Xt: 1773 case MISCREG_AT_S1E1W_Xt: 1774 case MISCREG_AT_S1E0R_Xt: 1775 case MISCREG_AT_S1E0W_Xt: 1776 case MISCREG_AT_S1E2R_Xt: 1777 case MISCREG_AT_S1E2W_Xt: 1778 case MISCREG_AT_S12E1R_Xt: 1779 case MISCREG_AT_S12E1W_Xt: 1780 case MISCREG_AT_S12E0R_Xt: 1781 case MISCREG_AT_S12E0W_Xt: 1782 case MISCREG_AT_S1E3R_Xt: 1783 case MISCREG_AT_S1E3W_Xt: 1784 { 1785 RequestPtr req = std::make_shared<Request>(); 1786 Request::Flags flags = 0; 1787 BaseTLB::Mode mode = BaseTLB::Read; 1788 TLB::ArmTranslationType tranType = TLB::NormalTran; 1789 Fault fault; 1790 switch(misc_reg) { 1791 case MISCREG_AT_S1E1R_Xt: 1792 flags = TLB::MustBeOne; 1793 tranType = TLB::S1E1Tran; 1794 mode = BaseTLB::Read; 1795 break; 1796 case MISCREG_AT_S1E1W_Xt: 1797 flags = TLB::MustBeOne; 1798 tranType = TLB::S1E1Tran; 1799 mode = BaseTLB::Write; 1800 break; 1801 case MISCREG_AT_S1E0R_Xt: 1802 flags = TLB::MustBeOne | TLB::UserMode; 1803 tranType = TLB::S1E0Tran; 1804 mode = BaseTLB::Read; 1805 break; 1806 case MISCREG_AT_S1E0W_Xt: 1807 flags = TLB::MustBeOne | TLB::UserMode; 1808 tranType = TLB::S1E0Tran; 1809 mode = BaseTLB::Write; 1810 break; 1811 case MISCREG_AT_S1E2R_Xt: 1812 flags = TLB::MustBeOne; 1813 tranType = TLB::S1E2Tran; 1814 mode = BaseTLB::Read; 1815 break; 1816 case MISCREG_AT_S1E2W_Xt: 1817 flags = TLB::MustBeOne; 1818 tranType = TLB::S1E2Tran; 1819 mode = BaseTLB::Write; 1820 break; 1821 case MISCREG_AT_S12E0R_Xt: 1822 flags = TLB::MustBeOne | TLB::UserMode; 1823 tranType = TLB::S12E0Tran; 1824 mode = BaseTLB::Read; 1825 break; 1826 case MISCREG_AT_S12E0W_Xt: 1827 flags = TLB::MustBeOne | TLB::UserMode; 1828 tranType = TLB::S12E0Tran; 1829 mode = BaseTLB::Write; 1830 break; 1831 case MISCREG_AT_S12E1R_Xt: 1832 flags = TLB::MustBeOne; 1833 tranType = TLB::S12E1Tran; 1834 mode = BaseTLB::Read; 1835 break; 1836 case MISCREG_AT_S12E1W_Xt: 1837 flags = TLB::MustBeOne; 1838 tranType = TLB::S12E1Tran; 1839 mode = BaseTLB::Write; 1840 break; 1841 case MISCREG_AT_S1E3R_Xt: 1842 flags = TLB::MustBeOne; 1843 tranType = TLB::S1E3Tran; 1844 mode = BaseTLB::Read; 1845 break; 1846 case MISCREG_AT_S1E3W_Xt: 1847 flags = TLB::MustBeOne; 1848 tranType = TLB::S1E3Tran; 1849 mode = BaseTLB::Write; 1850 break; 1851 } 1852 // If we're in timing mode then doing the translation in 1853 // functional mode then we're slightly distorting performance 1854 // results obtained from simulations. The translation should be 1855 // done in the same mode the core is running in. NOTE: This 1856 // can't be an atomic translation because that causes problems 1857 // with unexpected atomic snoop requests. 1858 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1859 req->setVirt(0, val, 0, flags, Request::funcMasterId, 1860 tc->pcState().pc()); 1861 req->setContext(tc->contextId()); 1862 fault = getDTBPtr(tc)->translateFunctional(req, tc, mode, 1863 tranType); 1864 1865 MiscReg newVal; 1866 if (fault == NoFault) { 1867 Addr paddr = req->getPaddr(); 1868 uint64_t attr = getDTBPtr(tc)->getAttr(); 1869 uint64_t attr1 = attr >> 56; 1870 if (!attr1 || attr1 ==0x44) { 1871 attr |= 0x100; 1872 attr &= ~ uint64_t(0x80); 1873 } 1874 newVal = (paddr & mask(47, 12)) | attr; 1875 DPRINTF(MiscRegs, 1876 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 1877 val, newVal); 1878 } else { 1879 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1880 armFault->update(tc); 1881 // Set fault bit and FSR 1882 FSR fsr = armFault->getFsr(tc); 1883 1884 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1885 if (cpsr.width) { // AArch32 1886 newVal = ((fsr >> 9) & 1) << 11; 1887 // rearrange fault status 1888 newVal |= ((fsr >> 0) & 0x3f) << 1; 1889 newVal |= 0x1; // F bit 1890 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1891 newVal |= armFault->isStage2() ? 0x200 : 0; 1892 } else { // AArch64 1893 newVal = 1; // F bit 1894 newVal |= fsr << 1; // FST 1895 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit. 1896 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 1897 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 1898 newVal |= 1 << 11; // RES1 1899 } 1900 DPRINTF(MiscRegs, 1901 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 1902 val, fsr, newVal); 1903 } 1904 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 1905 return; 1906 } 1907 case MISCREG_SPSR_EL3: 1908 case MISCREG_SPSR_EL2: 1909 case MISCREG_SPSR_EL1: 1910 // Force bits 23:21 to 0 1911 newVal = val & ~(0x7 << 21); 1912 break; 1913 case MISCREG_L2CTLR: 1914 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 1915 miscRegName[misc_reg], uint32_t(val)); 1916 break; 1917 1918 // Generic Timer registers 1919 case MISCREG_CNTHV_CTL_EL2: 1920 case MISCREG_CNTHV_CVAL_EL2: 1921 case MISCREG_CNTHV_TVAL_EL2: 1922 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 1923 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 1924 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 1925 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 1926 getGenericTimer(tc).setMiscReg(misc_reg, newVal); 1927 break; 1928 } 1929 } 1930 setMiscRegNoEffect(misc_reg, newVal); 1931} 1932 1933BaseISADevice & 1934ISA::getGenericTimer(ThreadContext *tc) 1935{ 1936 // We only need to create an ISA interface the first time we try 1937 // to access the timer. 1938 if (timer) 1939 return *timer.get(); 1940 1941 assert(system); 1942 GenericTimer *generic_timer(system->getGenericTimer()); 1943 if (!generic_timer) { 1944 panic("Trying to get a generic timer from a system that hasn't " 1945 "been configured to use a generic timer.\n"); 1946 } 1947 1948 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 1949 return *timer.get(); 1950} 1951 1952} 1953 1954ArmISA::ISA * 1955ArmISAParams::create() 1956{ 1957 return new ArmISA::ISA(this); 1958} 1959