isa.cc revision 12763:37c243ed1112
17405SAli.Saidi@ARM.com/* 210844Sandreas.sandberg@arm.com * Copyright (c) 2010-2018 ARM Limited 37405SAli.Saidi@ARM.com * All rights reserved 47405SAli.Saidi@ARM.com * 57405SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67405SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77405SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87405SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97405SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107405SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117405SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127405SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137405SAli.Saidi@ARM.com * 147405SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157405SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167405SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187405SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207405SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217405SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227405SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237405SAli.Saidi@ARM.com * this software without specific prior written permission. 247405SAli.Saidi@ARM.com * 257405SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267405SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277405SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287405SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297405SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307405SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317405SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327405SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337405SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347405SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357405SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367405SAli.Saidi@ARM.com * 377405SAli.Saidi@ARM.com * Authors: Gabe Black 387405SAli.Saidi@ARM.com * Ali Saidi 397405SAli.Saidi@ARM.com */ 407405SAli.Saidi@ARM.com 417405SAli.Saidi@ARM.com#include "arch/arm/isa.hh" 4210461SAndreas.Sandberg@ARM.com#include "arch/arm/pmu.hh" 439050Schander.sudanthi@arm.com#include "arch/arm/system.hh" 448887Sgeoffrey.blake@arm.com#include "arch/arm/tlb.hh" 4510461SAndreas.Sandberg@ARM.com#include "arch/arm/tlbi_op.hh" 468232Snate@binkert.org#include "cpu/base.hh" 478232Snate@binkert.org#include "cpu/checker/cpu.hh" 4810844Sandreas.sandberg@arm.com#include "debug/Arm.hh" 499384SAndreas.Sandberg@arm.com#include "debug/MiscRegs.hh" 507678Sgblack@eecs.umich.edu#include "dev/arm/generic_timer.hh" 518059SAli.Saidi@ARM.com#include "params/ArmISA.hh" 528284SAli.Saidi@ARM.com#include "sim/faults.hh" 537405SAli.Saidi@ARM.com#include "sim/stat_control.hh" 547405SAli.Saidi@ARM.com#include "sim/system.hh" 557405SAli.Saidi@ARM.com 567405SAli.Saidi@ARM.comnamespace ArmISA 5710037SARM gem5 Developers{ 5810037SARM gem5 Developers 5910037SARM gem5 DevelopersISA::ISA(Params *p) 6010037SARM gem5 Developers : SimObject(p), 6110037SARM gem5 Developers system(NULL), 6210037SARM gem5 Developers _decoderFlavour(p->decoderFlavour), 6310037SARM gem5 Developers _vecRegRenameMode(p->vecRegRenameMode), 6410037SARM gem5 Developers pmu(p->pmu), 6510037SARM gem5 Developers impdefAsNop(p->impdef_nop) 6610037SARM gem5 Developers{ 6710037SARM gem5 Developers miscRegs[MISCREG_SCTLR_RST] = 0; 6810037SARM gem5 Developers 6910037SARM gem5 Developers // Hook up a dummy device if we haven't been configured with a 7010037SARM gem5 Developers // real PMU. By using a dummy device, we don't need to check that 7110037SARM gem5 Developers // the PMU exist every time we try to access a PMU register. 7210037SARM gem5 Developers if (!pmu) 7310037SARM gem5 Developers pmu = &dummyDevice; 7410037SARM gem5 Developers 7510037SARM gem5 Developers // Give all ISA devices a pointer to this ISA 7610037SARM gem5 Developers pmu->setISA(this); 7710037SARM gem5 Developers 7810037SARM gem5 Developers system = dynamic_cast<ArmSystem *>(p->system); 7910037SARM gem5 Developers 8010037SARM gem5 Developers // Cache system-level properties 8110037SARM gem5 Developers if (FullSystem && system) { 8210037SARM gem5 Developers highestELIs64 = system->highestELIs64(); 8310037SARM gem5 Developers haveSecurity = system->haveSecurity(); 8410037SARM gem5 Developers haveLPAE = system->haveLPAE(); 8510037SARM gem5 Developers haveVirtualization = system->haveVirtualization(); 8610037SARM gem5 Developers haveLargeAsid64 = system->haveLargeAsid64(); 8710037SARM gem5 Developers physAddrRange64 = system->physAddrRange64(); 8810037SARM gem5 Developers } else { 8910037SARM gem5 Developers highestELIs64 = true; // ArmSystem::highestELIs64 does the same 9010037SARM gem5 Developers haveSecurity = haveLPAE = haveVirtualization = false; 9110037SARM gem5 Developers haveLargeAsid64 = false; 9210037SARM gem5 Developers physAddrRange64 = 32; // dummy value 9310037SARM gem5 Developers } 9410037SARM gem5 Developers 9510037SARM gem5 Developers initializeMiscRegMetadata(); 9610037SARM gem5 Developers preUnflattenMiscReg(); 9710037SARM gem5 Developers 9810037SARM gem5 Developers clear(); 9910037SARM gem5 Developers} 10010037SARM gem5 Developers 10110037SARM gem5 Developersstd::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS); 10210037SARM gem5 Developers 10310037SARM gem5 Developersconst ArmISAParams * 10410037SARM gem5 DevelopersISA::params() const 10510037SARM gem5 Developers{ 10610037SARM gem5 Developers return dynamic_cast<const Params *>(_params); 10710037SARM gem5 Developers} 10810037SARM gem5 Developers 10910037SARM gem5 Developersvoid 11010037SARM gem5 DevelopersISA::clear() 11110037SARM gem5 Developers{ 11210037SARM gem5 Developers const Params *p(params()); 11310037SARM gem5 Developers 11410037SARM gem5 Developers SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 11510037SARM gem5 Developers memset(miscRegs, 0, sizeof(miscRegs)); 11610037SARM gem5 Developers 11710037SARM gem5 Developers // Initialize configurable default values 11810037SARM gem5 Developers miscRegs[MISCREG_MIDR] = p->midr; 11910037SARM gem5 Developers miscRegs[MISCREG_MIDR_EL1] = p->midr; 12010037SARM gem5 Developers miscRegs[MISCREG_VPIDR] = p->midr; 12110037SARM gem5 Developers 12210037SARM gem5 Developers miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 12310037SARM gem5 Developers miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 12410037SARM gem5 Developers miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 12510037SARM gem5 Developers miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 12610037SARM gem5 Developers miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 1279384SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 12810461SAndreas.Sandberg@ARM.com 12910461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 13011165SRekai.GonzalezAlberquilla@arm.com miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 13110461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 13210461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 1339384SAndreas.Sandberg@arm.com 1349384SAndreas.Sandberg@arm.com if (FullSystem && system->highestELIs64()) { 1359384SAndreas.Sandberg@arm.com // Initialize AArch64 state 1369384SAndreas.Sandberg@arm.com clear64(p); 13710037SARM gem5 Developers return; 13810461SAndreas.Sandberg@ARM.com } 13910461SAndreas.Sandberg@ARM.com 14010461SAndreas.Sandberg@ARM.com // Initialize AArch32 state... 14110461SAndreas.Sandberg@ARM.com 14210461SAndreas.Sandberg@ARM.com CPSR cpsr = 0; 14310461SAndreas.Sandberg@ARM.com cpsr.mode = MODE_USER; 14410609Sandreas.sandberg@arm.com miscRegs[MISCREG_CPSR] = cpsr; 14510609Sandreas.sandberg@arm.com updateRegMap(cpsr); 14610609Sandreas.sandberg@arm.com 14710037SARM gem5 Developers SCTLR sctlr = 0; 14810037SARM gem5 Developers sctlr.te = (bool) sctlr_rst.te; 14910037SARM gem5 Developers sctlr.nmfi = (bool) sctlr_rst.nmfi; 15010037SARM gem5 Developers sctlr.v = (bool) sctlr_rst.v; 15110037SARM gem5 Developers sctlr.u = 1; 15210037SARM gem5 Developers sctlr.xp = 1; 15310037SARM gem5 Developers sctlr.rao2 = 1; 15410037SARM gem5 Developers sctlr.rao3 = 1; 15510037SARM gem5 Developers sctlr.rao4 = 0xf; // SCTLR[6:3] 15610037SARM gem5 Developers sctlr.uci = 1; 15710037SARM gem5 Developers sctlr.dze = 1; 15810037SARM gem5 Developers miscRegs[MISCREG_SCTLR_NS] = sctlr; 15910037SARM gem5 Developers miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 16010037SARM gem5 Developers miscRegs[MISCREG_HCPTR] = 0; 16110037SARM gem5 Developers 16210037SARM gem5 Developers // Start with an event in the mailbox 16310037SARM gem5 Developers miscRegs[MISCREG_SEV_MAILBOX] = 1; 16410037SARM gem5 Developers 16510037SARM gem5 Developers // Separate Instruction and Data TLBs 16610037SARM gem5 Developers miscRegs[MISCREG_TLBTR] = 1; 16710037SARM gem5 Developers 16810037SARM gem5 Developers MVFR0 mvfr0 = 0; 16910037SARM gem5 Developers mvfr0.advSimdRegisters = 2; 17010037SARM gem5 Developers mvfr0.singlePrecision = 2; 17110037SARM gem5 Developers mvfr0.doublePrecision = 2; 17210037SARM gem5 Developers mvfr0.vfpExceptionTrapping = 0; 17310037SARM gem5 Developers mvfr0.divide = 1; 1749384SAndreas.Sandberg@arm.com mvfr0.squareRoot = 1; 1759384SAndreas.Sandberg@arm.com mvfr0.shortVectors = 1; 1769384SAndreas.Sandberg@arm.com mvfr0.roundingModes = 1; 1779384SAndreas.Sandberg@arm.com miscRegs[MISCREG_MVFR0] = mvfr0; 1789384SAndreas.Sandberg@arm.com 1799384SAndreas.Sandberg@arm.com MVFR1 mvfr1 = 0; 1809384SAndreas.Sandberg@arm.com mvfr1.flushToZero = 1; 1819384SAndreas.Sandberg@arm.com mvfr1.defaultNaN = 1; 1829384SAndreas.Sandberg@arm.com mvfr1.advSimdLoadStore = 1; 1837427Sgblack@eecs.umich.edu mvfr1.advSimdInteger = 1; 1847427Sgblack@eecs.umich.edu mvfr1.advSimdSinglePrecision = 1; 1857427Sgblack@eecs.umich.edu mvfr1.advSimdHalfPrecision = 1; 1869385SAndreas.Sandberg@arm.com mvfr1.vfpHalfPrecision = 1; 1879385SAndreas.Sandberg@arm.com miscRegs[MISCREG_MVFR1] = mvfr1; 1887427Sgblack@eecs.umich.edu 1897427Sgblack@eecs.umich.edu // Reset values of PRRR and NMRR are implementation dependent 19010037SARM gem5 Developers 19110037SARM gem5 Developers // @todo: PRRR and NMRR in secure state? 19210037SARM gem5 Developers miscRegs[MISCREG_PRRR_NS] = 19310037SARM gem5 Developers (1 << 19) | // 19 19410037SARM gem5 Developers (0 << 18) | // 18 19510037SARM gem5 Developers (0 << 17) | // 17 19610037SARM gem5 Developers (1 << 16) | // 16 19710037SARM gem5 Developers (2 << 14) | // 15:14 19810037SARM gem5 Developers (0 << 12) | // 13:12 19910037SARM gem5 Developers (2 << 10) | // 11:10 20010037SARM gem5 Developers (2 << 8) | // 9:8 20110037SARM gem5 Developers (2 << 6) | // 7:6 20210037SARM gem5 Developers (2 << 4) | // 5:4 20310037SARM gem5 Developers (1 << 2) | // 3:2 2047427Sgblack@eecs.umich.edu 0; // 1:0 2057427Sgblack@eecs.umich.edu miscRegs[MISCREG_NMRR_NS] = 2067427Sgblack@eecs.umich.edu (1 << 30) | // 31:30 2077427Sgblack@eecs.umich.edu (0 << 26) | // 27:26 2087427Sgblack@eecs.umich.edu (0 << 24) | // 25:24 2097427Sgblack@eecs.umich.edu (3 << 22) | // 23:22 21010037SARM gem5 Developers (2 << 20) | // 21:20 21110037SARM gem5 Developers (0 << 18) | // 19:18 21210037SARM gem5 Developers (0 << 16) | // 17:16 21310037SARM gem5 Developers (1 << 14) | // 15:14 2147427Sgblack@eecs.umich.edu (0 << 12) | // 13:12 2157427Sgblack@eecs.umich.edu (2 << 10) | // 11:10 2167427Sgblack@eecs.umich.edu (0 << 8) | // 9:8 21710037SARM gem5 Developers (3 << 6) | // 7:6 21810204SAli.Saidi@ARM.com (2 << 4) | // 5:4 21910204SAli.Saidi@ARM.com (0 << 2) | // 3:2 22010037SARM gem5 Developers 0; // 1:0 2217427Sgblack@eecs.umich.edu 22210037SARM gem5 Developers miscRegs[MISCREG_CPACR] = 0; 2237427Sgblack@eecs.umich.edu 22410037SARM gem5 Developers miscRegs[MISCREG_FPSID] = p->fpsid; 2257427Sgblack@eecs.umich.edu 2267427Sgblack@eecs.umich.edu if (haveLPAE) { 22710037SARM gem5 Developers TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 2287427Sgblack@eecs.umich.edu ttbcr.eae = 0; 2297427Sgblack@eecs.umich.edu miscRegs[MISCREG_TTBCR_NS] = ttbcr; 2307427Sgblack@eecs.umich.edu // Enforce consistency with system-level settings 2317427Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 2327427Sgblack@eecs.umich.edu } 2337427Sgblack@eecs.umich.edu 2347427Sgblack@eecs.umich.edu if (haveSecurity) { 2357427Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR_S] = sctlr; 2367427Sgblack@eecs.umich.edu miscRegs[MISCREG_SCR] = 0; 2377427Sgblack@eecs.umich.edu miscRegs[MISCREG_VBAR_S] = 0; 2387427Sgblack@eecs.umich.edu } else { 2397427Sgblack@eecs.umich.edu // we're always non-secure 2407427Sgblack@eecs.umich.edu miscRegs[MISCREG_SCR] = 1; 2417427Sgblack@eecs.umich.edu } 2427427Sgblack@eecs.umich.edu 2437427Sgblack@eecs.umich.edu //XXX We need to initialize the rest of the state. 2447427Sgblack@eecs.umich.edu} 2457427Sgblack@eecs.umich.edu 2467427Sgblack@eecs.umich.eduvoid 2477427Sgblack@eecs.umich.eduISA::clear64(const ArmISAParams *p) 2487427Sgblack@eecs.umich.edu{ 2497427Sgblack@eecs.umich.edu CPSR cpsr = 0; 2507427Sgblack@eecs.umich.edu Addr rvbar = system->resetAddr64(); 2517436Sdam.sunwoo@arm.com switch (system->highestEL()) { 2527436Sdam.sunwoo@arm.com // Set initial EL to highest implemented EL using associated stack 25310037SARM gem5 Developers // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 25410037SARM gem5 Developers // value 2557436Sdam.sunwoo@arm.com case EL3: 2567436Sdam.sunwoo@arm.com cpsr.mode = MODE_EL3H; 2577436Sdam.sunwoo@arm.com miscRegs[MISCREG_RVBAR_EL3] = rvbar; 2587436Sdam.sunwoo@arm.com break; 2597436Sdam.sunwoo@arm.com case EL2: 2607436Sdam.sunwoo@arm.com cpsr.mode = MODE_EL2H; 2617436Sdam.sunwoo@arm.com miscRegs[MISCREG_RVBAR_EL2] = rvbar; 2627436Sdam.sunwoo@arm.com break; 2637436Sdam.sunwoo@arm.com case EL1: 2647436Sdam.sunwoo@arm.com cpsr.mode = MODE_EL1H; 2657436Sdam.sunwoo@arm.com miscRegs[MISCREG_RVBAR_EL1] = rvbar; 2667436Sdam.sunwoo@arm.com break; 26710037SARM gem5 Developers default: 2687436Sdam.sunwoo@arm.com panic("Invalid highest implemented exception level"); 2697436Sdam.sunwoo@arm.com break; 2707436Sdam.sunwoo@arm.com } 2717436Sdam.sunwoo@arm.com 2727436Sdam.sunwoo@arm.com // Initialize rest of CPSR 2737436Sdam.sunwoo@arm.com cpsr.daif = 0xf; // Mask all interrupts 2747436Sdam.sunwoo@arm.com cpsr.ss = 0; 2757436Sdam.sunwoo@arm.com cpsr.il = 0; 2767436Sdam.sunwoo@arm.com miscRegs[MISCREG_CPSR] = cpsr; 2777436Sdam.sunwoo@arm.com updateRegMap(cpsr); 2787436Sdam.sunwoo@arm.com 2797436Sdam.sunwoo@arm.com // Initialize other control registers 2807436Sdam.sunwoo@arm.com miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 2817436Sdam.sunwoo@arm.com if (haveSecurity) { 2827436Sdam.sunwoo@arm.com miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830; 2837436Sdam.sunwoo@arm.com miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 2847644Sali.saidi@arm.com } else if (haveVirtualization) { 2858147SAli.Saidi@ARM.com // also MISCREG_SCTLR_EL2 (by mapping) 2869385SAndreas.Sandberg@arm.com miscRegs[MISCREG_HSCTLR] = 0x30c50830; 2879385SAndreas.Sandberg@arm.com } else { 2889385SAndreas.Sandberg@arm.com // also MISCREG_SCTLR_EL1 (by mapping) 2899385SAndreas.Sandberg@arm.com miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init 2909385SAndreas.Sandberg@arm.com // Always non-secure 2919385SAndreas.Sandberg@arm.com miscRegs[MISCREG_SCR_EL3] = 1; 2929385SAndreas.Sandberg@arm.com } 2939385SAndreas.Sandberg@arm.com 2949385SAndreas.Sandberg@arm.com // Initialize configurable id registers 2959385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 2969385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 2979385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_AA64DFR0_EL1] = 2989385SAndreas.Sandberg@arm.com (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 2999385SAndreas.Sandberg@arm.com (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 3009385SAndreas.Sandberg@arm.com 3019385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 3029385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 3039385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 30410037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 30510037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 30610037SARM gem5 Developers 30710037SARM gem5 Developers miscRegs[MISCREG_ID_DFR0_EL1] = 30810037SARM gem5 Developers (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 30910037SARM gem5 Developers 31010037SARM gem5 Developers miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 31110037SARM gem5 Developers 31210037SARM gem5 Developers // Enforce consistency with system-level settings... 31310037SARM gem5 Developers 31410037SARM gem5 Developers // EL3 31510037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 31610037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 31710037SARM gem5 Developers haveSecurity ? 0x2 : 0x0); 31810037SARM gem5 Developers // EL2 31910037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 3208147SAli.Saidi@ARM.com miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 3217427Sgblack@eecs.umich.edu haveVirtualization ? 0x2 : 0x0); 3227427Sgblack@eecs.umich.edu // Large ASID support 3237427Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 32410037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 32510037SARM gem5 Developers haveLargeAsid64 ? 0x2 : 0x0); 32610037SARM gem5 Developers // Physical address size 32710037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 32810037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 32910037SARM gem5 Developers encodePhysAddrRange64(physAddrRange64)); 33010037SARM gem5 Developers} 33110037SARM gem5 Developers 33210037SARM gem5 DevelopersMiscReg 33310037SARM gem5 DevelopersISA::readMiscRegNoEffect(int misc_reg) const 33410037SARM gem5 Developers{ 33510037SARM gem5 Developers assert(misc_reg < NumMiscRegs); 33610037SARM gem5 Developers 33710037SARM gem5 Developers const auto ® = lookUpMiscReg[misc_reg]; // bit masks 33810037SARM gem5 Developers const auto &map = getMiscIndices(misc_reg); 33910037SARM gem5 Developers int lower = map.first, upper = map.second; 34010037SARM gem5 Developers // NB!: apply architectural masks according to desired register, 34110037SARM gem5 Developers // despite possibly getting value from different (mapped) register. 34210037SARM gem5 Developers auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32)) 34310037SARM gem5 Developers |(miscRegs[upper] << 32)); 34410037SARM gem5 Developers if (val & reg.res0()) { 34510037SARM gem5 Developers DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n", 34610037SARM gem5 Developers miscRegName[misc_reg], val & reg.res0()); 34710037SARM gem5 Developers } 34810037SARM gem5 Developers if ((val & reg.res1()) != reg.res1()) { 34910037SARM gem5 Developers DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n", 35010037SARM gem5 Developers miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1()); 35110037SARM gem5 Developers } 35210037SARM gem5 Developers return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao 35310037SARM gem5 Developers} 35410037SARM gem5 Developers 35510037SARM gem5 Developers 35610037SARM gem5 DevelopersMiscReg 35710037SARM gem5 DevelopersISA::readMiscReg(int misc_reg, ThreadContext *tc) 35810037SARM gem5 Developers{ 35910037SARM gem5 Developers CPSR cpsr = 0; 36010037SARM gem5 Developers PCState pc = 0; 36110037SARM gem5 Developers SCR scr = 0; 36210037SARM gem5 Developers 36310037SARM gem5 Developers if (misc_reg == MISCREG_CPSR) { 36410037SARM gem5 Developers cpsr = miscRegs[misc_reg]; 36510037SARM gem5 Developers pc = tc->pcState(); 36610037SARM gem5 Developers cpsr.j = pc.jazelle() ? 1 : 0; 36710037SARM gem5 Developers cpsr.t = pc.thumb() ? 1 : 0; 36810037SARM gem5 Developers return cpsr; 36910037SARM gem5 Developers } 37010037SARM gem5 Developers 37110037SARM gem5 Developers#ifndef NDEBUG 37210037SARM gem5 Developers if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 37310037SARM gem5 Developers if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 37410461SAndreas.Sandberg@ARM.com warn("Unimplemented system register %s read.\n", 37510461SAndreas.Sandberg@ARM.com miscRegName[misc_reg]); 37610461SAndreas.Sandberg@ARM.com else 37710461SAndreas.Sandberg@ARM.com panic("Unimplemented system register %s read.\n", 37810037SARM gem5 Developers miscRegName[misc_reg]); 37910037SARM gem5 Developers } 38010037SARM gem5 Developers#endif 38110037SARM gem5 Developers 38210037SARM gem5 Developers switch (unflattenMiscReg(misc_reg)) { 38310037SARM gem5 Developers case MISCREG_HCR: 38410037SARM gem5 Developers { 38510037SARM gem5 Developers if (!haveVirtualization) 38610461SAndreas.Sandberg@ARM.com return 0; 38710461SAndreas.Sandberg@ARM.com else 38810461SAndreas.Sandberg@ARM.com return readMiscRegNoEffect(MISCREG_HCR); 38910461SAndreas.Sandberg@ARM.com } 39010461SAndreas.Sandberg@ARM.com case MISCREG_CPACR: 39110037SARM gem5 Developers { 39210037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 39310037SARM gem5 Developers CPACR cpacrMask = 0; 39410037SARM gem5 Developers // Only cp10, cp11, and ase are implemented, nothing else should 39510037SARM gem5 Developers // be readable? (straight copy from the write code) 39610037SARM gem5 Developers cpacrMask.cp10 = ones; 39710037SARM gem5 Developers cpacrMask.cp11 = ones; 39810037SARM gem5 Developers cpacrMask.asedis = ones; 39910037SARM gem5 Developers 40010037SARM gem5 Developers // Security Extensions may limit the readability of CPACR 40110037SARM gem5 Developers if (haveSecurity) { 40210037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 40310037SARM gem5 Developers cpsr = readMiscRegNoEffect(MISCREG_CPSR); 40410037SARM gem5 Developers if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 40510037SARM gem5 Developers NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 40610037SARM gem5 Developers // NB: Skipping the full loop, here 40710037SARM gem5 Developers if (!nsacr.cp10) cpacrMask.cp10 = 0; 40810037SARM gem5 Developers if (!nsacr.cp11) cpacrMask.cp11 = 0; 40910037SARM gem5 Developers } 41010037SARM gem5 Developers } 41110037SARM gem5 Developers MiscReg val = readMiscRegNoEffect(MISCREG_CPACR); 41210037SARM gem5 Developers val &= cpacrMask; 4137405SAli.Saidi@ARM.com DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 41410035Sandreas.hansson@arm.com miscRegName[misc_reg], val); 4157405SAli.Saidi@ARM.com return val; 4167405SAli.Saidi@ARM.com } 4177614Sminkyu.jeong@arm.com case MISCREG_MPIDR: 41810037SARM gem5 Developers cpsr = readMiscRegNoEffect(MISCREG_CPSR); 41910037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 42010037SARM gem5 Developers if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 4217614Sminkyu.jeong@arm.com return getMPIDR(system, tc); 42210037SARM gem5 Developers } else { 42310037SARM gem5 Developers return readMiscReg(MISCREG_VMPIDR, tc); 42410037SARM gem5 Developers } 42510037SARM gem5 Developers break; 42610037SARM gem5 Developers case MISCREG_MPIDR_EL1: 42710037SARM gem5 Developers // @todo in the absence of v8 virtualization support just return MPIDR_EL1 42810037SARM gem5 Developers return getMPIDR(system, tc) & 0xffffffff; 42910037SARM gem5 Developers case MISCREG_VMPIDR: 43010037SARM gem5 Developers // top bit defined as RES1 43110037SARM gem5 Developers return readMiscRegNoEffect(misc_reg) | 0x80000000; 43210037SARM gem5 Developers case MISCREG_ID_AFR0: // not implemented, so alias MIDR 43310037SARM gem5 Developers case MISCREG_REVIDR: // not implemented, so alias MIDR 43410037SARM gem5 Developers case MISCREG_MIDR: 43510037SARM gem5 Developers cpsr = readMiscRegNoEffect(MISCREG_CPSR); 4367614Sminkyu.jeong@arm.com scr = readMiscRegNoEffect(MISCREG_SCR); 4377405SAli.Saidi@ARM.com if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 4387405SAli.Saidi@ARM.com return readMiscRegNoEffect(misc_reg); 4397405SAli.Saidi@ARM.com } else { 4407405SAli.Saidi@ARM.com return readMiscRegNoEffect(MISCREG_VPIDR); 4417405SAli.Saidi@ARM.com } 4427405SAli.Saidi@ARM.com break; 44310037SARM gem5 Developers case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 44410037SARM gem5 Developers case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 44510037SARM gem5 Developers case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 4469050Schander.sudanthi@arm.com case MISCREG_AIDR: // AUX ID set to 0 4477405SAli.Saidi@ARM.com case MISCREG_TCMTR: // No TCM's 44810037SARM gem5 Developers return 0; 44910037SARM gem5 Developers 4507720Sgblack@eecs.umich.edu case MISCREG_CLIDR: 4517720Sgblack@eecs.umich.edu warn_once("The clidr register always reports 0 caches.\n"); 4527405SAli.Saidi@ARM.com warn_once("clidr LoUIS field of 0b001 to match current " 4537405SAli.Saidi@ARM.com "ARM implementations.\n"); 4547757SAli.Saidi@ARM.com return 0x00200000; 45510037SARM gem5 Developers case MISCREG_CCSIDR: 45610037SARM gem5 Developers warn_once("The ccsidr register isn't implemented and " 45710037SARM gem5 Developers "always reads as 0.\n"); 45810037SARM gem5 Developers break; 45910037SARM gem5 Developers case MISCREG_CTR: // AArch32, ARMv7, top bit set 46010037SARM gem5 Developers case MISCREG_CTR_EL0: // AArch64 46110037SARM gem5 Developers { 46210037SARM gem5 Developers //all caches have the same line size in gem5 46310037SARM gem5 Developers //4 byte words in ARM 46410037SARM gem5 Developers unsigned lineSizeWords = 46510037SARM gem5 Developers tc->getSystemPtr()->cacheLineSize() / 4; 46610037SARM gem5 Developers unsigned log2LineSizeWords = 0; 46710037SARM gem5 Developers 46810037SARM gem5 Developers while (lineSizeWords >>= 1) { 46910037SARM gem5 Developers ++log2LineSizeWords; 47010037SARM gem5 Developers } 47110037SARM gem5 Developers 47210037SARM gem5 Developers CTR ctr = 0; 47310037SARM gem5 Developers //log2 of minimun i-cache line size (words) 47410037SARM gem5 Developers ctr.iCacheLineSize = log2LineSizeWords; 47510037SARM gem5 Developers //b11 - gem5 uses pipt 47610037SARM gem5 Developers ctr.l1IndexPolicy = 0x3; 47710037SARM gem5 Developers //log2 of minimum d-cache line size (words) 47810037SARM gem5 Developers ctr.dCacheLineSize = log2LineSizeWords; 47910037SARM gem5 Developers //log2 of max reservation size (words) 48010037SARM gem5 Developers ctr.erg = log2LineSizeWords; 48110037SARM gem5 Developers //log2 of max writeback size (words) 48210037SARM gem5 Developers ctr.cwg = log2LineSizeWords; 48310037SARM gem5 Developers //b100 - gem5 format is ARMv7 48410037SARM gem5 Developers ctr.format = 0x4; 48510037SARM gem5 Developers 48610037SARM gem5 Developers return ctr; 48710037SARM gem5 Developers } 48810037SARM gem5 Developers case MISCREG_ACTLR: 48910037SARM gem5 Developers warn("Not doing anything for miscreg ACTLR\n"); 49010037SARM gem5 Developers break; 49110037SARM gem5 Developers 49210037SARM gem5 Developers case MISCREG_PMXEVTYPER_PMCCFILTR: 49310037SARM gem5 Developers case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 49410037SARM gem5 Developers case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 49510037SARM gem5 Developers case MISCREG_PMCR ... MISCREG_PMOVSSET: 49610037SARM gem5 Developers return pmu->readMiscReg(misc_reg); 49710037SARM gem5 Developers 49810037SARM gem5 Developers case MISCREG_CPSR_Q: 49910037SARM gem5 Developers panic("shouldn't be reading this register seperately\n"); 50010037SARM gem5 Developers case MISCREG_FPSCR_QC: 5018284SAli.Saidi@ARM.com return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 50210037SARM gem5 Developers case MISCREG_FPSCR_EXC: 50310037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 50410037SARM gem5 Developers case MISCREG_FPSR: 50510037SARM gem5 Developers { 5069050Schander.sudanthi@arm.com const uint32_t ones = (uint32_t)(-1); 50710037SARM gem5 Developers FPSCR fpscrMask = 0; 50810037SARM gem5 Developers fpscrMask.ioc = ones; 50910037SARM gem5 Developers fpscrMask.dzc = ones; 51010037SARM gem5 Developers fpscrMask.ofc = ones; 51110037SARM gem5 Developers fpscrMask.ufc = ones; 51210037SARM gem5 Developers fpscrMask.ixc = ones; 51310037SARM gem5 Developers fpscrMask.idc = ones; 51410037SARM gem5 Developers fpscrMask.qc = ones; 51510037SARM gem5 Developers fpscrMask.v = ones; 51610037SARM gem5 Developers fpscrMask.c = ones; 51710037SARM gem5 Developers fpscrMask.z = ones; 51810037SARM gem5 Developers fpscrMask.n = ones; 51910037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 52010037SARM gem5 Developers } 52110037SARM gem5 Developers case MISCREG_FPCR: 52210037SARM gem5 Developers { 52310037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 52410037SARM gem5 Developers FPSCR fpscrMask = 0; 5259050Schander.sudanthi@arm.com fpscrMask.len = ones; 5268284SAli.Saidi@ARM.com fpscrMask.stride = ones; 52710037SARM gem5 Developers fpscrMask.rMode = ones; 52810037SARM gem5 Developers fpscrMask.fz = ones; 52910037SARM gem5 Developers fpscrMask.dn = ones; 53010037SARM gem5 Developers fpscrMask.ahp = ones; 53110037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 53210037SARM gem5 Developers } 53310037SARM gem5 Developers case MISCREG_NZCV: 5347405SAli.Saidi@ARM.com { 5357731SAli.Saidi@ARM.com CPSR cpsr = 0; 5368468Swade.walker@arm.com cpsr.nz = tc->readCCReg(CCREG_NZ); 5378468Swade.walker@arm.com cpsr.c = tc->readCCReg(CCREG_C); 5388468Swade.walker@arm.com cpsr.v = tc->readCCReg(CCREG_V); 5397405SAli.Saidi@ARM.com return cpsr; 5407731SAli.Saidi@ARM.com } 5417405SAli.Saidi@ARM.com case MISCREG_DAIF: 5427405SAli.Saidi@ARM.com { 5437583SAli.Saidi@arm.com CPSR cpsr = 0; 5449130Satgutier@umich.edu cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 5459130Satgutier@umich.edu return cpsr; 5469130Satgutier@umich.edu } 5479130Satgutier@umich.edu case MISCREG_SP_EL0: 5489814Sandreas.hansson@arm.com { 5499130Satgutier@umich.edu return tc->readIntReg(INTREG_SP0); 5509130Satgutier@umich.edu } 5519130Satgutier@umich.edu case MISCREG_SP_EL1: 5529130Satgutier@umich.edu { 5539130Satgutier@umich.edu return tc->readIntReg(INTREG_SP1); 5549130Satgutier@umich.edu } 5559130Satgutier@umich.edu case MISCREG_SP_EL2: 5569130Satgutier@umich.edu { 5579130Satgutier@umich.edu return tc->readIntReg(INTREG_SP2); 5589130Satgutier@umich.edu } 5599130Satgutier@umich.edu case MISCREG_SPSEL: 5609130Satgutier@umich.edu { 5619130Satgutier@umich.edu return miscRegs[MISCREG_CPSR] & 0x1; 5629130Satgutier@umich.edu } 5639130Satgutier@umich.edu case MISCREG_CURRENTEL: 5649130Satgutier@umich.edu { 5659130Satgutier@umich.edu return miscRegs[MISCREG_CPSR] & 0xc; 5669130Satgutier@umich.edu } 5679130Satgutier@umich.edu case MISCREG_L2CTLR: 5689130Satgutier@umich.edu { 5699130Satgutier@umich.edu // mostly unimplemented, just set NumCPUs field from sim and return 5709130Satgutier@umich.edu L2CTLR l2ctlr = 0; 5717583SAli.Saidi@arm.com // b00:1CPU to b11:4CPUs 5727583SAli.Saidi@arm.com l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 5737583SAli.Saidi@arm.com return l2ctlr; 57410461SAndreas.Sandberg@ARM.com } 57510461SAndreas.Sandberg@ARM.com case MISCREG_DBGDIDR: 57610461SAndreas.Sandberg@ARM.com /* For now just implement the version number. 57710461SAndreas.Sandberg@ARM.com * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 57810461SAndreas.Sandberg@ARM.com */ 57910461SAndreas.Sandberg@ARM.com return 0x5 << 16; 58010461SAndreas.Sandberg@ARM.com case MISCREG_DBGDSCRint: 5818302SAli.Saidi@ARM.com return 0; 5828302SAli.Saidi@ARM.com case MISCREG_ISR: 5837783SGiacomo.Gabrielli@arm.com return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 5847783SGiacomo.Gabrielli@arm.com readMiscRegNoEffect(MISCREG_HCR), 5857783SGiacomo.Gabrielli@arm.com readMiscRegNoEffect(MISCREG_CPSR), 5867783SGiacomo.Gabrielli@arm.com readMiscRegNoEffect(MISCREG_SCR)); 58710037SARM gem5 Developers case MISCREG_ISR_EL1: 58810037SARM gem5 Developers return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 58910037SARM gem5 Developers readMiscRegNoEffect(MISCREG_HCR_EL2), 59010037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR), 59110037SARM gem5 Developers readMiscRegNoEffect(MISCREG_SCR_EL3)); 59210037SARM gem5 Developers case MISCREG_DCZID_EL0: 59310037SARM gem5 Developers return 0x04; // DC ZVA clear 64-byte chunks 59410037SARM gem5 Developers case MISCREG_HCPTR: 59510037SARM gem5 Developers { 59610037SARM gem5 Developers MiscReg val = readMiscRegNoEffect(misc_reg); 59710037SARM gem5 Developers // The trap bit associated with CP14 is defined as RAZ 59810037SARM gem5 Developers val &= ~(1 << 14); 59910037SARM gem5 Developers // If a CP bit in NSACR is 0 then the corresponding bit in 60010037SARM gem5 Developers // HCPTR is RAO/WI 60110037SARM gem5 Developers bool secure_lookup = haveSecurity && 60210037SARM gem5 Developers inSecureState(readMiscRegNoEffect(MISCREG_SCR), 60310037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR)); 60410037SARM gem5 Developers if (!secure_lookup) { 60510037SARM gem5 Developers MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR); 60610037SARM gem5 Developers val |= (mask ^ 0x7FFF) & 0xBFFF; 60710037SARM gem5 Developers } 60810037SARM gem5 Developers // Set the bits for unimplemented coprocessors to RAO/WI 60910037SARM gem5 Developers val |= 0x33FF; 61010037SARM gem5 Developers return (val); 61110037SARM gem5 Developers } 61210037SARM gem5 Developers case MISCREG_HDFAR: // alias for secure DFAR 61310037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_DFAR_S); 61410037SARM gem5 Developers case MISCREG_HIFAR: // alias for secure IFAR 61510037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_IFAR_S); 61610037SARM gem5 Developers case MISCREG_HVBAR: // bottom bits reserved 61710037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0; 61810037SARM gem5 Developers case MISCREG_SCTLR: 61910037SARM gem5 Developers return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818; 62010037SARM gem5 Developers case MISCREG_SCTLR_EL1: 62110037SARM gem5 Developers return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800; 62210037SARM gem5 Developers case MISCREG_SCTLR_EL2: 62310037SARM gem5 Developers case MISCREG_SCTLR_EL3: 62410037SARM gem5 Developers case MISCREG_HSCTLR: 62510338SCurtis.Dunham@arm.com return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; 62610338SCurtis.Dunham@arm.com 62710338SCurtis.Dunham@arm.com case MISCREG_ID_PFR0: 62810037SARM gem5 Developers // !ThumbEE | !Jazelle | Thumb | ARM 62910037SARM gem5 Developers return 0x00000031; 63010037SARM gem5 Developers case MISCREG_ID_PFR1: 63110037SARM gem5 Developers { // Timer | Virti | !M Profile | TrustZone | ARMv4 63210037SARM gem5 Developers bool haveTimer = (system->getGenericTimer() != NULL); 63310037SARM gem5 Developers return 0x00000001 63410037SARM gem5 Developers | (haveSecurity ? 0x00000010 : 0x0) 63510037SARM gem5 Developers | (haveVirtualization ? 0x00001000 : 0x0) 63610037SARM gem5 Developers | (haveTimer ? 0x00010000 : 0x0); 63710037SARM gem5 Developers } 63810037SARM gem5 Developers case MISCREG_ID_AA64PFR0_EL1: 63910037SARM gem5 Developers return 0x0000000000000002 // AArch{64,32} supported at EL0 64010037SARM gem5 Developers | 0x0000000000000020 // EL1 64110037SARM gem5 Developers | (haveVirtualization ? 0x0000000000000200 : 0) // EL2 64210037SARM gem5 Developers | (haveSecurity ? 0x0000000000002000 : 0); // EL3 64310037SARM gem5 Developers case MISCREG_ID_AA64PFR1_EL1: 64410037SARM gem5 Developers return 0; // bits [63:0] RES0 (reserved for future use) 64510037SARM gem5 Developers 64610037SARM gem5 Developers // Generic Timer registers 64710037SARM gem5 Developers case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 64810037SARM gem5 Developers case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 64910037SARM gem5 Developers case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 65010037SARM gem5 Developers case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 65110037SARM gem5 Developers return getGenericTimer(tc).readMiscReg(misc_reg); 65210037SARM gem5 Developers 65310037SARM gem5 Developers default: 65410037SARM gem5 Developers break; 65510037SARM gem5 Developers 6568549Sdaniel.johnson@arm.com } 6578868SMatt.Horsnell@arm.com return readMiscRegNoEffect(misc_reg); 6588868SMatt.Horsnell@arm.com} 6598868SMatt.Horsnell@arm.com 6608868SMatt.Horsnell@arm.comvoid 6618868SMatt.Horsnell@arm.comISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 6628868SMatt.Horsnell@arm.com{ 6638868SMatt.Horsnell@arm.com assert(misc_reg < NumMiscRegs); 6648868SMatt.Horsnell@arm.com 6658868SMatt.Horsnell@arm.com const auto ® = lookUpMiscReg[misc_reg]; // bit masks 66610461SAndreas.Sandberg@ARM.com const auto &map = getMiscIndices(misc_reg); 6678868SMatt.Horsnell@arm.com int lower = map.first, upper = map.second; 66810461SAndreas.Sandberg@ARM.com 66910037SARM gem5 Developers auto v = (val & ~reg.wi()) | reg.rao(); 6708868SMatt.Horsnell@arm.com if (upper > 0) { 67110037SARM gem5 Developers miscRegs[lower] = bits(v, 31, 0); 67211150Smitch.hayenga@arm.com miscRegs[upper] = bits(v, 63, 32); 67310037SARM gem5 Developers DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 67410037SARM gem5 Developers misc_reg, lower, upper, v); 67510037SARM gem5 Developers } else { 67610037SARM gem5 Developers miscRegs[lower] = v; 67711150Smitch.hayenga@arm.com DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 67810037SARM gem5 Developers misc_reg, lower, v); 67910037SARM gem5 Developers } 68010037SARM gem5 Developers} 68110037SARM gem5 Developers 68210037SARM gem5 Developersvoid 68310037SARM gem5 DevelopersISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 68410037SARM gem5 Developers{ 68510037SARM gem5 Developers 68610037SARM gem5 Developers MiscReg newVal = val; 68710037SARM gem5 Developers bool secure_lookup; 68810037SARM gem5 Developers SCR scr; 68910037SARM gem5 Developers 69010037SARM gem5 Developers if (misc_reg == MISCREG_CPSR) { 69110037SARM gem5 Developers updateRegMap(val); 69210037SARM gem5 Developers 69310037SARM gem5 Developers 69410037SARM gem5 Developers CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 69510037SARM gem5 Developers int old_mode = old_cpsr.mode; 69610037SARM gem5 Developers CPSR cpsr = val; 69710037SARM gem5 Developers if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) { 69810037SARM gem5 Developers getITBPtr(tc)->invalidateMiscReg(); 69910037SARM gem5 Developers getDTBPtr(tc)->invalidateMiscReg(); 70010037SARM gem5 Developers } 70110037SARM gem5 Developers 70210037SARM gem5 Developers DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 70310037SARM gem5 Developers miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 70410037SARM gem5 Developers PCState pc = tc->pcState(); 70510037SARM gem5 Developers pc.nextThumb(cpsr.t); 70610037SARM gem5 Developers pc.nextJazelle(cpsr.j); 70710037SARM gem5 Developers pc.illegalExec(cpsr.il == 1); 70810037SARM gem5 Developers 70910037SARM gem5 Developers // Follow slightly different semantics if a CheckerCPU object 71010037SARM gem5 Developers // is connected 71110037SARM gem5 Developers CheckerCPU *checker = tc->getCheckerCpuPtr(); 71210037SARM gem5 Developers if (checker) { 71310037SARM gem5 Developers tc->pcStateNoRecord(pc); 71410037SARM gem5 Developers } else { 71510037SARM gem5 Developers tc->pcState(pc); 71610037SARM gem5 Developers } 71710037SARM gem5 Developers } else { 71810037SARM gem5 Developers#ifndef NDEBUG 71910037SARM gem5 Developers if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 72010037SARM gem5 Developers if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 72110037SARM gem5 Developers warn("Unimplemented system register %s write with %#x.\n", 72210037SARM gem5 Developers miscRegName[misc_reg], val); 72310037SARM gem5 Developers else 72410037SARM gem5 Developers panic("Unimplemented system register %s write with %#x.\n", 72510037SARM gem5 Developers miscRegName[misc_reg], val); 72610037SARM gem5 Developers } 72710037SARM gem5 Developers#endif 72810037SARM gem5 Developers switch (unflattenMiscReg(misc_reg)) { 72910037SARM gem5 Developers case MISCREG_CPACR: 73010037SARM gem5 Developers { 73110037SARM gem5 Developers 73210037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 73310037SARM gem5 Developers CPACR cpacrMask = 0; 73410844Sandreas.sandberg@arm.com // Only cp10, cp11, and ase are implemented, nothing else should 73510037SARM gem5 Developers // be writable 73610844Sandreas.sandberg@arm.com cpacrMask.cp10 = ones; 73710844Sandreas.sandberg@arm.com cpacrMask.cp11 = ones; 73810844Sandreas.sandberg@arm.com cpacrMask.asedis = ones; 73910844Sandreas.sandberg@arm.com 74010844Sandreas.sandberg@arm.com // Security Extensions may limit the writability of CPACR 74110844Sandreas.sandberg@arm.com if (haveSecurity) { 74210188Sgeoffrey.blake@arm.com scr = readMiscRegNoEffect(MISCREG_SCR); 74310037SARM gem5 Developers CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 74410037SARM gem5 Developers if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 7457405SAli.Saidi@ARM.com NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 7467405SAli.Saidi@ARM.com // NB: Skipping the full loop, here 7477405SAli.Saidi@ARM.com if (!nsacr.cp10) cpacrMask.cp10 = 0; 7487405SAli.Saidi@ARM.com if (!nsacr.cp11) cpacrMask.cp11 = 0; 7497405SAli.Saidi@ARM.com } 7507405SAli.Saidi@ARM.com } 7517405SAli.Saidi@ARM.com 7527405SAli.Saidi@ARM.com MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR); 7537614Sminkyu.jeong@arm.com newVal &= cpacrMask; 75410037SARM gem5 Developers newVal |= old_val & ~cpacrMask; 75510037SARM gem5 Developers DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 7567614Sminkyu.jeong@arm.com miscRegName[misc_reg], newVal); 75710037SARM gem5 Developers } 75810037SARM gem5 Developers break; 75910037SARM gem5 Developers case MISCREG_CPTR_EL2: 76010037SARM gem5 Developers { 76110037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 76210037SARM gem5 Developers CPTR cptrMask = 0; 76310037SARM gem5 Developers cptrMask.tcpac = ones; 76410037SARM gem5 Developers cptrMask.tta = ones; 76510037SARM gem5 Developers cptrMask.tfp = ones; 76610037SARM gem5 Developers newVal &= cptrMask; 76710037SARM gem5 Developers cptrMask = 0; 76810037SARM gem5 Developers cptrMask.res1_13_12_el2 = ones; 76910037SARM gem5 Developers cptrMask.res1_9_0_el2 = ones; 77010037SARM gem5 Developers newVal |= cptrMask; 77110037SARM gem5 Developers DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 77210037SARM gem5 Developers miscRegName[misc_reg], newVal); 77310037SARM gem5 Developers } 77410037SARM gem5 Developers break; 77510037SARM gem5 Developers case MISCREG_CPTR_EL3: 7767405SAli.Saidi@ARM.com { 7777405SAli.Saidi@ARM.com const uint32_t ones = (uint32_t)(-1); 7787405SAli.Saidi@ARM.com CPTR cptrMask = 0; 7797405SAli.Saidi@ARM.com cptrMask.tcpac = ones; 7807405SAli.Saidi@ARM.com cptrMask.tta = ones; 7817749SAli.Saidi@ARM.com cptrMask.tfp = ones; 7827405SAli.Saidi@ARM.com newVal &= cptrMask; 7838284SAli.Saidi@ARM.com DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 78410037SARM gem5 Developers miscRegName[misc_reg], newVal); 78510037SARM gem5 Developers } 7868284SAli.Saidi@ARM.com break; 7878284SAli.Saidi@ARM.com case MISCREG_CSSELR: 78810037SARM gem5 Developers warn_once("The csselr register isn't implemented.\n"); 78910037SARM gem5 Developers return; 79010037SARM gem5 Developers 7918284SAli.Saidi@ARM.com case MISCREG_DC_ZVA_Xt: 7927405SAli.Saidi@ARM.com warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 7937405SAli.Saidi@ARM.com return; 7947749SAli.Saidi@ARM.com 7957749SAli.Saidi@ARM.com case MISCREG_FPSCR: 7967749SAli.Saidi@ARM.com { 7977749SAli.Saidi@ARM.com const uint32_t ones = (uint32_t)(-1); 7987405SAli.Saidi@ARM.com FPSCR fpscrMask = 0; 7997749SAli.Saidi@ARM.com fpscrMask.ioc = ones; 8007749SAli.Saidi@ARM.com fpscrMask.dzc = ones; 8017749SAli.Saidi@ARM.com fpscrMask.ofc = ones; 8027749SAli.Saidi@ARM.com fpscrMask.ufc = ones; 8037749SAli.Saidi@ARM.com fpscrMask.ixc = ones; 8047614Sminkyu.jeong@arm.com fpscrMask.idc = ones; 8057614Sminkyu.jeong@arm.com fpscrMask.ioe = ones; 8067720Sgblack@eecs.umich.edu fpscrMask.dze = ones; 8077720Sgblack@eecs.umich.edu fpscrMask.ofe = ones; 8087720Sgblack@eecs.umich.edu fpscrMask.ufe = ones; 8098887Sgeoffrey.blake@arm.com fpscrMask.ixe = ones; 8108887Sgeoffrey.blake@arm.com fpscrMask.ide = ones; 8118887Sgeoffrey.blake@arm.com fpscrMask.len = ones; 8128887Sgeoffrey.blake@arm.com fpscrMask.stride = ones; 8138887Sgeoffrey.blake@arm.com fpscrMask.rMode = ones; 8148887Sgeoffrey.blake@arm.com fpscrMask.fz = ones; 8158887Sgeoffrey.blake@arm.com fpscrMask.dn = ones; 8168887Sgeoffrey.blake@arm.com fpscrMask.ahp = ones; 8178887Sgeoffrey.blake@arm.com fpscrMask.qc = ones; 8187408Sgblack@eecs.umich.edu fpscrMask.v = ones; 81910037SARM gem5 Developers fpscrMask.c = ones; 82010037SARM gem5 Developers fpscrMask.z = ones; 82110037SARM gem5 Developers fpscrMask.n = ones; 82210037SARM gem5 Developers newVal = (newVal & (uint32_t)fpscrMask) | 82310037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPSCR) & 82410037SARM gem5 Developers ~(uint32_t)fpscrMask); 82510037SARM gem5 Developers tc->getDecoderPtr()->setContext(newVal); 82610037SARM gem5 Developers } 82710037SARM gem5 Developers break; 82810037SARM gem5 Developers case MISCREG_FPSR: 82910037SARM gem5 Developers { 8307408Sgblack@eecs.umich.edu const uint32_t ones = (uint32_t)(-1); 8317408Sgblack@eecs.umich.edu FPSCR fpscrMask = 0; 8328206SWilliam.Wang@arm.com fpscrMask.ioc = ones; 8338206SWilliam.Wang@arm.com fpscrMask.dzc = ones; 8348206SWilliam.Wang@arm.com fpscrMask.ofc = ones; 8358206SWilliam.Wang@arm.com fpscrMask.ufc = ones; 8368206SWilliam.Wang@arm.com fpscrMask.ixc = ones; 8378206SWilliam.Wang@arm.com fpscrMask.idc = ones; 8388206SWilliam.Wang@arm.com fpscrMask.qc = ones; 8398206SWilliam.Wang@arm.com fpscrMask.v = ones; 84010037SARM gem5 Developers fpscrMask.c = ones; 84110037SARM gem5 Developers fpscrMask.z = ones; 84210037SARM gem5 Developers fpscrMask.n = ones; 84310037SARM gem5 Developers newVal = (newVal & (uint32_t)fpscrMask) | 84410037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPSCR) & 84510037SARM gem5 Developers ~(uint32_t)fpscrMask); 84610037SARM gem5 Developers misc_reg = MISCREG_FPSCR; 84710037SARM gem5 Developers } 84810037SARM gem5 Developers break; 84910037SARM gem5 Developers case MISCREG_FPCR: 85010037SARM gem5 Developers { 85110037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 85210037SARM gem5 Developers FPSCR fpscrMask = 0; 85310037SARM gem5 Developers fpscrMask.len = ones; 8548206SWilliam.Wang@arm.com fpscrMask.stride = ones; 85510037SARM gem5 Developers fpscrMask.rMode = ones; 85610037SARM gem5 Developers fpscrMask.fz = ones; 85710037SARM gem5 Developers fpscrMask.dn = ones; 85810037SARM gem5 Developers fpscrMask.ahp = ones; 85910037SARM gem5 Developers newVal = (newVal & (uint32_t)fpscrMask) | 86010037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPSCR) & 86110037SARM gem5 Developers ~(uint32_t)fpscrMask); 86210037SARM gem5 Developers misc_reg = MISCREG_FPSCR; 86310037SARM gem5 Developers } 86410037SARM gem5 Developers break; 86510037SARM gem5 Developers case MISCREG_CPSR_Q: 86610037SARM gem5 Developers { 86710037SARM gem5 Developers assert(!(newVal & ~CpsrMaskQ)); 86810037SARM gem5 Developers newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 86910037SARM gem5 Developers misc_reg = MISCREG_CPSR; 87010037SARM gem5 Developers } 87110037SARM gem5 Developers break; 87210037SARM gem5 Developers case MISCREG_FPSCR_QC: 87310037SARM gem5 Developers { 87410037SARM gem5 Developers newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 87510037SARM gem5 Developers (newVal & FpscrQcMask); 87610037SARM gem5 Developers misc_reg = MISCREG_FPSCR; 87710037SARM gem5 Developers } 87810037SARM gem5 Developers break; 87910037SARM gem5 Developers case MISCREG_FPSCR_EXC: 88010037SARM gem5 Developers { 88110037SARM gem5 Developers newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 88210037SARM gem5 Developers (newVal & FpscrExcMask); 88310037SARM gem5 Developers misc_reg = MISCREG_FPSCR; 88410037SARM gem5 Developers } 88510037SARM gem5 Developers break; 88610037SARM gem5 Developers case MISCREG_FPEXC: 88710037SARM gem5 Developers { 88810037SARM gem5 Developers // vfpv3 architecture, section B.6.1 of DDI04068 88910037SARM gem5 Developers // bit 29 - valid only if fpexc[31] is 0 89010037SARM gem5 Developers const uint32_t fpexcMask = 0x60000000; 89110037SARM gem5 Developers newVal = (newVal & fpexcMask) | 89210037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 89310037SARM gem5 Developers } 89410037SARM gem5 Developers break; 8958206SWilliam.Wang@arm.com case MISCREG_HCR: 8968206SWilliam.Wang@arm.com { 8977408Sgblack@eecs.umich.edu if (!haveVirtualization) 8987408Sgblack@eecs.umich.edu return; 8997408Sgblack@eecs.umich.edu } 9007731SAli.Saidi@ARM.com break; 9018206SWilliam.Wang@arm.com case MISCREG_IFSR: 90210037SARM gem5 Developers { 90310037SARM gem5 Developers // ARM ARM (ARM DDI 0406C.b) B4.1.96 90410037SARM gem5 Developers const uint32_t ifsrMask = 90510037SARM gem5 Developers mask(31, 13) | mask(11, 11) | mask(8, 6); 90610037SARM gem5 Developers newVal = newVal & ~ifsrMask; 9077408Sgblack@eecs.umich.edu } 9087408Sgblack@eecs.umich.edu break; 9097408Sgblack@eecs.umich.edu case MISCREG_DFSR: 9107408Sgblack@eecs.umich.edu { 9117408Sgblack@eecs.umich.edu // ARM ARM (ARM DDI 0406C.b) B4.1.52 9127408Sgblack@eecs.umich.edu const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 9137408Sgblack@eecs.umich.edu newVal = newVal & ~dfsrMask; 9147408Sgblack@eecs.umich.edu } 9157408Sgblack@eecs.umich.edu break; 9167408Sgblack@eecs.umich.edu case MISCREG_AMAIR0: 91710037SARM gem5 Developers case MISCREG_AMAIR1: 91810037SARM gem5 Developers { 91910037SARM gem5 Developers // ARM ARM (ARM DDI 0406C.b) B4.1.5 92010037SARM gem5 Developers // Valid only with LPAE 92110037SARM gem5 Developers if (!haveLPAE) 92210037SARM gem5 Developers return; 9237408Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 9247408Sgblack@eecs.umich.edu } 9257408Sgblack@eecs.umich.edu break; 9267408Sgblack@eecs.umich.edu case MISCREG_SCR: 9277408Sgblack@eecs.umich.edu getITBPtr(tc)->invalidateMiscReg(); 9287408Sgblack@eecs.umich.edu getDTBPtr(tc)->invalidateMiscReg(); 9297408Sgblack@eecs.umich.edu break; 9307408Sgblack@eecs.umich.edu case MISCREG_SCTLR: 9317408Sgblack@eecs.umich.edu { 9327408Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 9337408Sgblack@eecs.umich.edu scr = readMiscRegNoEffect(MISCREG_SCR); 9347408Sgblack@eecs.umich.edu 93510037SARM gem5 Developers MiscRegIndex sctlr_idx; 93610037SARM gem5 Developers if (haveSecurity && !highestELIs64 && !scr.ns) { 9379377Sgblack@eecs.umich.edu sctlr_idx = MISCREG_SCTLR_S; 9387408Sgblack@eecs.umich.edu } else { 9397408Sgblack@eecs.umich.edu sctlr_idx = MISCREG_SCTLR_NS; 94010037SARM gem5 Developers } 94110037SARM gem5 Developers 94210037SARM gem5 Developers SCTLR sctlr = miscRegs[sctlr_idx]; 94310037SARM gem5 Developers SCTLR new_sctlr = newVal; 94410037SARM gem5 Developers new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 94510037SARM gem5 Developers miscRegs[sctlr_idx] = (MiscReg)new_sctlr; 94610037SARM gem5 Developers getITBPtr(tc)->invalidateMiscReg(); 94710037SARM gem5 Developers getDTBPtr(tc)->invalidateMiscReg(); 94810037SARM gem5 Developers } 94910037SARM gem5 Developers case MISCREG_MIDR: 95010037SARM gem5 Developers case MISCREG_ID_PFR0: 95110037SARM gem5 Developers case MISCREG_ID_PFR1: 95210037SARM gem5 Developers case MISCREG_ID_DFR0: 95310037SARM gem5 Developers case MISCREG_ID_MMFR0: 95410037SARM gem5 Developers case MISCREG_ID_MMFR1: 95510037SARM gem5 Developers case MISCREG_ID_MMFR2: 95610037SARM gem5 Developers case MISCREG_ID_MMFR3: 95710037SARM gem5 Developers case MISCREG_ID_ISAR0: 95810037SARM gem5 Developers case MISCREG_ID_ISAR1: 95910037SARM gem5 Developers case MISCREG_ID_ISAR2: 96010037SARM gem5 Developers case MISCREG_ID_ISAR3: 96110037SARM gem5 Developers case MISCREG_ID_ISAR4: 96210037SARM gem5 Developers case MISCREG_ID_ISAR5: 96310037SARM gem5 Developers 96410037SARM gem5 Developers case MISCREG_MPIDR: 96510037SARM gem5 Developers case MISCREG_FPSID: 96610037SARM gem5 Developers case MISCREG_TLBTR: 96710037SARM gem5 Developers case MISCREG_MVFR0: 96810037SARM gem5 Developers case MISCREG_MVFR1: 96910037SARM gem5 Developers 97010037SARM gem5 Developers case MISCREG_ID_AA64AFR0_EL1: 97110037SARM gem5 Developers case MISCREG_ID_AA64AFR1_EL1: 97210037SARM gem5 Developers case MISCREG_ID_AA64DFR0_EL1: 97310037SARM gem5 Developers case MISCREG_ID_AA64DFR1_EL1: 97410037SARM gem5 Developers case MISCREG_ID_AA64ISAR0_EL1: 97510037SARM gem5 Developers case MISCREG_ID_AA64ISAR1_EL1: 97610037SARM gem5 Developers case MISCREG_ID_AA64MMFR0_EL1: 97710037SARM gem5 Developers case MISCREG_ID_AA64MMFR1_EL1: 97810037SARM gem5 Developers case MISCREG_ID_AA64PFR0_EL1: 97910037SARM gem5 Developers case MISCREG_ID_AA64PFR1_EL1: 98010037SARM gem5 Developers // ID registers are constants. 98110037SARM gem5 Developers return; 98210037SARM gem5 Developers 9838302SAli.Saidi@ARM.com // TLB Invalidate All 9848302SAli.Saidi@ARM.com case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 9858302SAli.Saidi@ARM.com { 98610037SARM gem5 Developers assert32(tc); 9878302SAli.Saidi@ARM.com scr = readMiscReg(MISCREG_SCR, tc); 9888302SAli.Saidi@ARM.com 9898302SAli.Saidi@ARM.com TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 9907783SGiacomo.Gabrielli@arm.com tlbiOp(tc); 9917783SGiacomo.Gabrielli@arm.com return; 99210037SARM gem5 Developers } 99310037SARM gem5 Developers // TLB Invalidate All, Inner Shareable 9947783SGiacomo.Gabrielli@arm.com case MISCREG_TLBIALLIS: 9957783SGiacomo.Gabrielli@arm.com { 9967783SGiacomo.Gabrielli@arm.com assert32(tc); 9977783SGiacomo.Gabrielli@arm.com scr = readMiscReg(MISCREG_SCR, tc); 9987783SGiacomo.Gabrielli@arm.com 99910037SARM gem5 Developers TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 100010037SARM gem5 Developers tlbiOp.broadcast(tc); 10017783SGiacomo.Gabrielli@arm.com return; 10027783SGiacomo.Gabrielli@arm.com } 10037783SGiacomo.Gabrielli@arm.com // Instruction TLB Invalidate All 10047408Sgblack@eecs.umich.edu case MISCREG_ITLBIALL: 10057408Sgblack@eecs.umich.edu { 10068206SWilliam.Wang@arm.com assert32(tc); 10078206SWilliam.Wang@arm.com scr = readMiscReg(MISCREG_SCR, tc); 10087408Sgblack@eecs.umich.edu 10097408Sgblack@eecs.umich.edu ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 101010037SARM gem5 Developers tlbiOp(tc); 10117408Sgblack@eecs.umich.edu return; 10127408Sgblack@eecs.umich.edu } 101310037SARM gem5 Developers // Data TLB Invalidate All 101410037SARM gem5 Developers case MISCREG_DTLBIALL: 101510037SARM gem5 Developers { 101610037SARM gem5 Developers assert32(tc); 101710037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 101810037SARM gem5 Developers 101910037SARM gem5 Developers DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 102010037SARM gem5 Developers tlbiOp(tc); 102110037SARM gem5 Developers return; 102210037SARM gem5 Developers } 102310037SARM gem5 Developers // TLB Invalidate by VA 102410037SARM gem5 Developers // mcr tlbimval(is) is invalidating all matching entries 102510037SARM gem5 Developers // regardless of the level of lookup, since in gem5 we cache 102610037SARM gem5 Developers // in the tlb the last level of lookup only. 102710037SARM gem5 Developers case MISCREG_TLBIMVA: 102810037SARM gem5 Developers case MISCREG_TLBIMVAL: 102910037SARM gem5 Developers { 103010037SARM gem5 Developers assert32(tc); 103110037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 103210037SARM gem5 Developers 103310037SARM gem5 Developers TLBIMVA tlbiOp(EL1, 103410037SARM gem5 Developers haveSecurity && !scr.ns, 103510037SARM gem5 Developers mbits(newVal, 31, 12), 103610037SARM gem5 Developers bits(newVal, 7,0)); 103710037SARM gem5 Developers 103810037SARM gem5 Developers tlbiOp(tc); 103910037SARM gem5 Developers return; 104010037SARM gem5 Developers } 104110037SARM gem5 Developers // TLB Invalidate by VA, Inner Shareable 104210037SARM gem5 Developers case MISCREG_TLBIMVAIS: 104310037SARM gem5 Developers case MISCREG_TLBIMVALIS: 104410037SARM gem5 Developers { 104510037SARM gem5 Developers assert32(tc); 104610037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 104710037SARM gem5 Developers 10487408Sgblack@eecs.umich.edu TLBIMVA tlbiOp(EL1, 10497408Sgblack@eecs.umich.edu haveSecurity && !scr.ns, 10507408Sgblack@eecs.umich.edu mbits(newVal, 31, 12), 105110037SARM gem5 Developers bits(newVal, 7,0)); 105210037SARM gem5 Developers 105310037SARM gem5 Developers tlbiOp.broadcast(tc); 105410037SARM gem5 Developers return; 105510037SARM gem5 Developers } 105610037SARM gem5 Developers // TLB Invalidate by ASID match 105710037SARM gem5 Developers case MISCREG_TLBIASID: 105810037SARM gem5 Developers { 105910037SARM gem5 Developers assert32(tc); 106010037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 106110037SARM gem5 Developers 106210037SARM gem5 Developers TLBIASID tlbiOp(EL1, 106310037SARM gem5 Developers haveSecurity && !scr.ns, 10647408Sgblack@eecs.umich.edu bits(newVal, 7,0)); 106510037SARM gem5 Developers 106610037SARM gem5 Developers tlbiOp(tc); 10677749SAli.Saidi@ARM.com return; 10687749SAli.Saidi@ARM.com } 10697408Sgblack@eecs.umich.edu // TLB Invalidate by ASID match, Inner Shareable 10709385SAndreas.Sandberg@arm.com case MISCREG_TLBIASIDIS: 10719385SAndreas.Sandberg@arm.com { 10729385SAndreas.Sandberg@arm.com assert32(tc); 107310461SAndreas.Sandberg@ARM.com scr = readMiscReg(MISCREG_SCR, tc); 10749385SAndreas.Sandberg@arm.com 10759385SAndreas.Sandberg@arm.com TLBIASID tlbiOp(EL1, 10769385SAndreas.Sandberg@arm.com haveSecurity && !scr.ns, 10779385SAndreas.Sandberg@arm.com bits(newVal, 7,0)); 10789385SAndreas.Sandberg@arm.com 10799385SAndreas.Sandberg@arm.com tlbiOp.broadcast(tc); 10809385SAndreas.Sandberg@arm.com return; 10819385SAndreas.Sandberg@arm.com } 10829385SAndreas.Sandberg@arm.com // mcr tlbimvaal(is) is invalidating all matching entries 10839385SAndreas.Sandberg@arm.com // regardless of the level of lookup, since in gem5 we cache 10849385SAndreas.Sandberg@arm.com // in the tlb the last level of lookup only. 10859385SAndreas.Sandberg@arm.com // TLB Invalidate by VA, All ASID 10869385SAndreas.Sandberg@arm.com case MISCREG_TLBIMVAA: 10877408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAAL: 10887408Sgblack@eecs.umich.edu { 10897408Sgblack@eecs.umich.edu assert32(tc); 109010037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 109110037SARM gem5 Developers 109210037SARM gem5 Developers TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 109310037SARM gem5 Developers mbits(newVal, 31,12), false); 109410037SARM gem5 Developers 109510037SARM gem5 Developers tlbiOp(tc); 109610037SARM gem5 Developers return; 109710037SARM gem5 Developers } 109810037SARM gem5 Developers // TLB Invalidate by VA, All ASID, Inner Shareable 109910037SARM gem5 Developers case MISCREG_TLBIMVAAIS: 110010037SARM gem5 Developers case MISCREG_TLBIMVAALIS: 11019385SAndreas.Sandberg@arm.com { 11027408Sgblack@eecs.umich.edu assert32(tc); 11039385SAndreas.Sandberg@arm.com scr = readMiscReg(MISCREG_SCR, tc); 110410037SARM gem5 Developers 11057408Sgblack@eecs.umich.edu TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 110610037SARM gem5 Developers mbits(newVal, 31,12), false); 110710037SARM gem5 Developers 110810037SARM gem5 Developers tlbiOp.broadcast(tc); 110910037SARM gem5 Developers return; 111010037SARM gem5 Developers } 11118284SAli.Saidi@ARM.com // mcr tlbimvalh(is) is invalidating all matching entries 11128284SAli.Saidi@ARM.com // regardless of the level of lookup, since in gem5 we cache 11138284SAli.Saidi@ARM.com // in the tlb the last level of lookup only. 11148284SAli.Saidi@ARM.com // TLB Invalidate by VA, Hyp mode 111510037SARM gem5 Developers case MISCREG_TLBIMVAH: 111610037SARM gem5 Developers case MISCREG_TLBIMVALH: 11178887Sgeoffrey.blake@arm.com { 11188887Sgeoffrey.blake@arm.com assert32(tc); 11198887Sgeoffrey.blake@arm.com scr = readMiscReg(MISCREG_SCR, tc); 11208733Sgeoffrey.blake@arm.com 112110037SARM gem5 Developers TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 112210037SARM gem5 Developers mbits(newVal, 31,12), true); 112310037SARM gem5 Developers 112410037SARM gem5 Developers tlbiOp(tc); 11258733Sgeoffrey.blake@arm.com return; 11268284SAli.Saidi@ARM.com } 11277408Sgblack@eecs.umich.edu // TLB Invalidate by VA, Hyp mode, Inner Shareable 112810037SARM gem5 Developers case MISCREG_TLBIMVAHIS: 11297408Sgblack@eecs.umich.edu case MISCREG_TLBIMVALHIS: 113010037SARM gem5 Developers { 113110037SARM gem5 Developers assert32(tc); 113210037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 113310037SARM gem5 Developers 113410037SARM gem5 Developers TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 11357408Sgblack@eecs.umich.edu mbits(newVal, 31,12), true); 113610037SARM gem5 Developers 11377408Sgblack@eecs.umich.edu tlbiOp.broadcast(tc); 113810037SARM gem5 Developers return; 113910037SARM gem5 Developers } 114010037SARM gem5 Developers // mcr tlbiipas2l(is) is invalidating all matching entries 114110037SARM gem5 Developers // regardless of the level of lookup, since in gem5 we cache 114210037SARM gem5 Developers // in the tlb the last level of lookup only. 11437408Sgblack@eecs.umich.edu // TLB Invalidate by Intermediate Physical Address, Stage 2 114410037SARM gem5 Developers case MISCREG_TLBIIPAS2: 11457408Sgblack@eecs.umich.edu case MISCREG_TLBIIPAS2L: 11467408Sgblack@eecs.umich.edu { 114710037SARM gem5 Developers assert32(tc); 114810037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 114910037SARM gem5 Developers 115010037SARM gem5 Developers TLBIIPA tlbiOp(EL1, 11518284SAli.Saidi@ARM.com haveSecurity && !scr.ns, 11528284SAli.Saidi@ARM.com static_cast<Addr>(bits(newVal, 35, 0)) << 12); 11538284SAli.Saidi@ARM.com 11548284SAli.Saidi@ARM.com tlbiOp(tc); 11558284SAli.Saidi@ARM.com return; 115610037SARM gem5 Developers } 115710037SARM gem5 Developers // TLB Invalidate by Intermediate Physical Address, Stage 2, 11588284SAli.Saidi@ARM.com // Inner Shareable 115910037SARM gem5 Developers case MISCREG_TLBIIPAS2IS: 116010037SARM gem5 Developers case MISCREG_TLBIIPAS2LIS: 11618887Sgeoffrey.blake@arm.com { 11628887Sgeoffrey.blake@arm.com assert32(tc); 11638733Sgeoffrey.blake@arm.com scr = readMiscReg(MISCREG_SCR, tc); 11648733Sgeoffrey.blake@arm.com 116510037SARM gem5 Developers TLBIIPA tlbiOp(EL1, 11668733Sgeoffrey.blake@arm.com haveSecurity && !scr.ns, 116710037SARM gem5 Developers static_cast<Addr>(bits(newVal, 35, 0)) << 12); 11688733Sgeoffrey.blake@arm.com 11698284SAli.Saidi@ARM.com tlbiOp.broadcast(tc); 11707408Sgblack@eecs.umich.edu return; 117110037SARM gem5 Developers } 11727408Sgblack@eecs.umich.edu // Instruction TLB Invalidate by VA 11737408Sgblack@eecs.umich.edu case MISCREG_ITLBIMVA: 117410037SARM gem5 Developers { 117510037SARM gem5 Developers assert32(tc); 117610037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 117710037SARM gem5 Developers 11788284SAli.Saidi@ARM.com ITLBIMVA tlbiOp(EL1, 11798284SAli.Saidi@ARM.com haveSecurity && !scr.ns, 11808284SAli.Saidi@ARM.com mbits(newVal, 31, 12), 11818284SAli.Saidi@ARM.com bits(newVal, 7,0)); 118210037SARM gem5 Developers 118310037SARM gem5 Developers tlbiOp(tc); 118410037SARM gem5 Developers return; 118510037SARM gem5 Developers } 11868887Sgeoffrey.blake@arm.com // Data TLB Invalidate by VA 11878733Sgeoffrey.blake@arm.com case MISCREG_DTLBIMVA: 118810037SARM gem5 Developers { 118910037SARM gem5 Developers assert32(tc); 119010037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 119110037SARM gem5 Developers 11928733Sgeoffrey.blake@arm.com DTLBIMVA tlbiOp(EL1, 11938284SAli.Saidi@ARM.com haveSecurity && !scr.ns, 11947408Sgblack@eecs.umich.edu mbits(newVal, 31, 12), 119510037SARM gem5 Developers bits(newVal, 7,0)); 11967408Sgblack@eecs.umich.edu 11977408Sgblack@eecs.umich.edu tlbiOp(tc); 119810037SARM gem5 Developers return; 119910037SARM gem5 Developers } 120010037SARM gem5 Developers // Instruction TLB Invalidate by ASID match 120110037SARM gem5 Developers case MISCREG_ITLBIASID: 120210037SARM gem5 Developers { 120310037SARM gem5 Developers assert32(tc); 120410037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 120510037SARM gem5 Developers 120610037SARM gem5 Developers ITLBIASID tlbiOp(EL1, 120710037SARM gem5 Developers haveSecurity && !scr.ns, 120810037SARM gem5 Developers bits(newVal, 7,0)); 120910037SARM gem5 Developers 121010037SARM gem5 Developers tlbiOp(tc); 121110037SARM gem5 Developers return; 121210037SARM gem5 Developers } 121310037SARM gem5 Developers // Data TLB Invalidate by ASID match 121410037SARM gem5 Developers case MISCREG_DTLBIASID: 121510037SARM gem5 Developers { 121610037SARM gem5 Developers assert32(tc); 121710037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 121810037SARM gem5 Developers 121910037SARM gem5 Developers DTLBIASID tlbiOp(EL1, 122010037SARM gem5 Developers haveSecurity && !scr.ns, 122110037SARM gem5 Developers bits(newVal, 7,0)); 122210037SARM gem5 Developers 122310037SARM gem5 Developers tlbiOp(tc); 122410037SARM gem5 Developers return; 122510037SARM gem5 Developers } 122610037SARM gem5 Developers // TLB Invalidate All, Non-Secure Non-Hyp 122710037SARM gem5 Developers case MISCREG_TLBIALLNSNH: 122810037SARM gem5 Developers { 122910037SARM gem5 Developers assert32(tc); 123010037SARM gem5 Developers 123110037SARM gem5 Developers TLBIALLN tlbiOp(EL1, false); 123210037SARM gem5 Developers tlbiOp(tc); 123310037SARM gem5 Developers return; 123410037SARM gem5 Developers } 123510037SARM gem5 Developers // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable 123610037SARM gem5 Developers case MISCREG_TLBIALLNSNHIS: 123710037SARM gem5 Developers { 123810037SARM gem5 Developers assert32(tc); 123910037SARM gem5 Developers 124010037SARM gem5 Developers TLBIALLN tlbiOp(EL1, false); 124110037SARM gem5 Developers tlbiOp.broadcast(tc); 124210037SARM gem5 Developers return; 124310037SARM gem5 Developers } 124410037SARM gem5 Developers // TLB Invalidate All, Hyp mode 124510037SARM gem5 Developers case MISCREG_TLBIALLH: 124610037SARM gem5 Developers { 124710037SARM gem5 Developers assert32(tc); 124810037SARM gem5 Developers 124910037SARM gem5 Developers TLBIALLN tlbiOp(EL1, true); 125010037SARM gem5 Developers tlbiOp(tc); 125110037SARM gem5 Developers return; 125210037SARM gem5 Developers } 125310037SARM gem5 Developers // TLB Invalidate All, Hyp mode, Inner Shareable 125410037SARM gem5 Developers case MISCREG_TLBIALLHIS: 125510037SARM gem5 Developers { 125610037SARM gem5 Developers assert32(tc); 125710037SARM gem5 Developers 125810037SARM gem5 Developers TLBIALLN tlbiOp(EL1, true); 125910037SARM gem5 Developers tlbiOp.broadcast(tc); 126010037SARM gem5 Developers return; 126110037SARM gem5 Developers } 126210037SARM gem5 Developers // AArch64 TLB Invalidate All, EL3 126310037SARM gem5 Developers case MISCREG_TLBI_ALLE3: 126410037SARM gem5 Developers { 126510037SARM gem5 Developers assert64(tc); 126610037SARM gem5 Developers 126710037SARM gem5 Developers TLBIALL tlbiOp(EL3, true); 126810037SARM gem5 Developers tlbiOp(tc); 126910037SARM gem5 Developers return; 127010037SARM gem5 Developers } 127110037SARM gem5 Developers // AArch64 TLB Invalidate All, EL3, Inner Shareable 127210037SARM gem5 Developers case MISCREG_TLBI_ALLE3IS: 127310037SARM gem5 Developers { 127410037SARM gem5 Developers assert64(tc); 127510037SARM gem5 Developers 127610037SARM gem5 Developers TLBIALL tlbiOp(EL3, true); 127710037SARM gem5 Developers tlbiOp.broadcast(tc); 127810037SARM gem5 Developers return; 127910037SARM gem5 Developers } 128010037SARM gem5 Developers // @todo: uncomment this to enable Virtualization 128110037SARM gem5 Developers // case MISCREG_TLBI_ALLE2IS: 128210037SARM gem5 Developers // case MISCREG_TLBI_ALLE2: 128310037SARM gem5 Developers // AArch64 TLB Invalidate All, EL1 128410037SARM gem5 Developers case MISCREG_TLBI_ALLE1: 128510037SARM gem5 Developers case MISCREG_TLBI_VMALLE1: 128610037SARM gem5 Developers case MISCREG_TLBI_VMALLS12E1: 128710037SARM gem5 Developers // @todo: handle VMID and stage 2 to enable Virtualization 128810037SARM gem5 Developers { 128910037SARM gem5 Developers assert64(tc); 129010037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 129110037SARM gem5 Developers 129210037SARM gem5 Developers TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 129310037SARM gem5 Developers tlbiOp(tc); 129410037SARM gem5 Developers return; 129510037SARM gem5 Developers } 129610037SARM gem5 Developers // AArch64 TLB Invalidate All, EL1, Inner Shareable 129710037SARM gem5 Developers case MISCREG_TLBI_ALLE1IS: 129810037SARM gem5 Developers case MISCREG_TLBI_VMALLE1IS: 129910037SARM gem5 Developers case MISCREG_TLBI_VMALLS12E1IS: 130010037SARM gem5 Developers // @todo: handle VMID and stage 2 to enable Virtualization 130110037SARM gem5 Developers { 130210037SARM gem5 Developers assert64(tc); 130310037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 130410037SARM gem5 Developers 130510037SARM gem5 Developers TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 130610037SARM gem5 Developers tlbiOp.broadcast(tc); 130710037SARM gem5 Developers return; 130810037SARM gem5 Developers } 130910037SARM gem5 Developers // VAEx(IS) and VALEx(IS) are the same because TLBs 131010037SARM gem5 Developers // only store entries 131110037SARM gem5 Developers // from the last level of translation table walks 131210037SARM gem5 Developers // @todo: handle VMID to enable Virtualization 131310037SARM gem5 Developers // AArch64 TLB Invalidate by VA, EL3 131410037SARM gem5 Developers case MISCREG_TLBI_VAE3_Xt: 131510037SARM gem5 Developers case MISCREG_TLBI_VALE3_Xt: 131610037SARM gem5 Developers { 131710037SARM gem5 Developers assert64(tc); 131810037SARM gem5 Developers 131910037SARM gem5 Developers TLBIMVA tlbiOp(EL3, true, 132010037SARM gem5 Developers static_cast<Addr>(bits(newVal, 43, 0)) << 12, 132110037SARM gem5 Developers 0xbeef); 132210037SARM gem5 Developers tlbiOp(tc); 132310037SARM gem5 Developers return; 132410037SARM gem5 Developers } 132510037SARM gem5 Developers // AArch64 TLB Invalidate by VA, EL3, Inner Shareable 132610037SARM gem5 Developers case MISCREG_TLBI_VAE3IS_Xt: 132710037SARM gem5 Developers case MISCREG_TLBI_VALE3IS_Xt: 132810037SARM gem5 Developers { 132910037SARM gem5 Developers assert64(tc); 133010037SARM gem5 Developers 133110037SARM gem5 Developers TLBIMVA tlbiOp(EL3, true, 133210037SARM gem5 Developers static_cast<Addr>(bits(newVal, 43, 0)) << 12, 133310037SARM gem5 Developers 0xbeef); 133410037SARM gem5 Developers 133510037SARM gem5 Developers tlbiOp.broadcast(tc); 133610037SARM gem5 Developers return; 133710037SARM gem5 Developers } 133810037SARM gem5 Developers // AArch64 TLB Invalidate by VA, EL2 133910037SARM gem5 Developers case MISCREG_TLBI_VAE2_Xt: 134010037SARM gem5 Developers case MISCREG_TLBI_VALE2_Xt: 134110037SARM gem5 Developers { 134210037SARM gem5 Developers assert64(tc); 13438284SAli.Saidi@ARM.com scr = readMiscReg(MISCREG_SCR, tc); 13448284SAli.Saidi@ARM.com 13458284SAli.Saidi@ARM.com TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 13468284SAli.Saidi@ARM.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, 134710037SARM gem5 Developers 0xbeef); 134810709SAndreas.Sandberg@ARM.com tlbiOp(tc); 134910037SARM gem5 Developers return; 135010037SARM gem5 Developers } 135110037SARM gem5 Developers // AArch64 TLB Invalidate by VA, EL2, Inner Shareable 135210037SARM gem5 Developers case MISCREG_TLBI_VAE2IS_Xt: 135310037SARM gem5 Developers case MISCREG_TLBI_VALE2IS_Xt: 135410037SARM gem5 Developers { 135510037SARM gem5 Developers assert64(tc); 135610037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 135710037SARM gem5 Developers 135810037SARM gem5 Developers TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 135910037SARM gem5 Developers static_cast<Addr>(bits(newVal, 43, 0)) << 12, 136010037SARM gem5 Developers 0xbeef); 136110037SARM gem5 Developers 136210037SARM gem5 Developers tlbiOp.broadcast(tc); 136310037SARM gem5 Developers return; 136410037SARM gem5 Developers } 136510037SARM gem5 Developers // AArch64 TLB Invalidate by VA, EL1 136610037SARM gem5 Developers case MISCREG_TLBI_VAE1_Xt: 136710037SARM gem5 Developers case MISCREG_TLBI_VALE1_Xt: 136810037SARM gem5 Developers { 136910037SARM gem5 Developers assert64(tc); 137010037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 137110037SARM gem5 Developers auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 137210037SARM gem5 Developers bits(newVal, 55, 48); 137310037SARM gem5 Developers 137410037SARM gem5 Developers TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 137510037SARM gem5 Developers static_cast<Addr>(bits(newVal, 43, 0)) << 12, 137610037SARM gem5 Developers asid); 137710037SARM gem5 Developers 137810037SARM gem5 Developers tlbiOp(tc); 137910037SARM gem5 Developers return; 138010037SARM gem5 Developers } 138110037SARM gem5 Developers // AArch64 TLB Invalidate by VA, EL1, Inner Shareable 138210037SARM gem5 Developers case MISCREG_TLBI_VAE1IS_Xt: 13838887Sgeoffrey.blake@arm.com case MISCREG_TLBI_VALE1IS_Xt: 13848887Sgeoffrey.blake@arm.com { 13858733Sgeoffrey.blake@arm.com assert64(tc); 138610037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 138710037SARM gem5 Developers auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 138810037SARM gem5 Developers bits(newVal, 55, 48); 138910037SARM gem5 Developers 13908733Sgeoffrey.blake@arm.com TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 13918284SAli.Saidi@ARM.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, 13927408Sgblack@eecs.umich.edu asid); 139310037SARM gem5 Developers 139410037SARM gem5 Developers tlbiOp.broadcast(tc); 139510037SARM gem5 Developers return; 139610037SARM gem5 Developers } 139710037SARM gem5 Developers // AArch64 TLB Invalidate by ASID, EL1 139810037SARM gem5 Developers // @todo: handle VMID to enable Virtualization 139910037SARM gem5 Developers case MISCREG_TLBI_ASIDE1_Xt: 140010037SARM gem5 Developers { 14017405SAli.Saidi@ARM.com assert64(tc); 14027583SAli.Saidi@arm.com scr = readMiscReg(MISCREG_SCR, tc); 14037583SAli.Saidi@arm.com auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 14047583SAli.Saidi@arm.com bits(newVal, 55, 48); 140510461SAndreas.Sandberg@ARM.com 140610461SAndreas.Sandberg@ARM.com TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 140710461SAndreas.Sandberg@ARM.com tlbiOp(tc); 140810461SAndreas.Sandberg@ARM.com return; 140910461SAndreas.Sandberg@ARM.com } 141010461SAndreas.Sandberg@ARM.com // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable 14117583SAli.Saidi@arm.com case MISCREG_TLBI_ASIDE1IS_Xt: 141210461SAndreas.Sandberg@ARM.com { 141310461SAndreas.Sandberg@ARM.com assert64(tc); 141410037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 141510037SARM gem5 Developers auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 141610037SARM gem5 Developers bits(newVal, 55, 48); 141710037SARM gem5 Developers 141810037SARM gem5 Developers TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 141910037SARM gem5 Developers tlbiOp.broadcast(tc); 142010037SARM gem5 Developers return; 142110037SARM gem5 Developers } 142210037SARM gem5 Developers // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 142310037SARM gem5 Developers // entries from the last level of translation table walks 142410037SARM gem5 Developers // AArch64 TLB Invalidate by VA, All ASID, EL1 142510037SARM gem5 Developers case MISCREG_TLBI_VAAE1_Xt: 142610037SARM gem5 Developers case MISCREG_TLBI_VAALE1_Xt: 142710037SARM gem5 Developers { 142810037SARM gem5 Developers assert64(tc); 142910037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 143010037SARM gem5 Developers 143110037SARM gem5 Developers TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 143210037SARM gem5 Developers static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 143310037SARM gem5 Developers 143410037SARM gem5 Developers tlbiOp(tc); 143510037SARM gem5 Developers return; 143610037SARM gem5 Developers } 143710037SARM gem5 Developers // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable 143810037SARM gem5 Developers case MISCREG_TLBI_VAAE1IS_Xt: 143910037SARM gem5 Developers case MISCREG_TLBI_VAALE1IS_Xt: 144010037SARM gem5 Developers { 144110037SARM gem5 Developers assert64(tc); 144210037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 144310037SARM gem5 Developers 144410037SARM gem5 Developers TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 144510037SARM gem5 Developers static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 144610037SARM gem5 Developers 144710037SARM gem5 Developers tlbiOp.broadcast(tc); 144810037SARM gem5 Developers return; 144910037SARM gem5 Developers } 145010037SARM gem5 Developers // AArch64 TLB Invalidate by Intermediate Physical Address, 14517436Sdam.sunwoo@arm.com // Stage 2, EL1 145210037SARM gem5 Developers case MISCREG_TLBI_IPAS2E1_Xt: 145310037SARM gem5 Developers case MISCREG_TLBI_IPAS2LE1_Xt: 145410037SARM gem5 Developers { 14557436Sdam.sunwoo@arm.com assert64(tc); 14567436Sdam.sunwoo@arm.com scr = readMiscReg(MISCREG_SCR, tc); 145710037SARM gem5 Developers 145810037SARM gem5 Developers TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 145910037SARM gem5 Developers static_cast<Addr>(bits(newVal, 35, 0)) << 12); 146010037SARM gem5 Developers 146110037SARM gem5 Developers tlbiOp(tc); 146210037SARM gem5 Developers return; 146310037SARM gem5 Developers } 146410037SARM gem5 Developers // AArch64 TLB Invalidate by Intermediate Physical Address, 146510037SARM gem5 Developers // Stage 2, EL1, Inner Shareable 146610037SARM gem5 Developers case MISCREG_TLBI_IPAS2E1IS_Xt: 146710037SARM gem5 Developers case MISCREG_TLBI_IPAS2LE1IS_Xt: 146810037SARM gem5 Developers { 146910037SARM gem5 Developers assert64(tc); 147010037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 147110037SARM gem5 Developers 147210037SARM gem5 Developers TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 147310037SARM gem5 Developers static_cast<Addr>(bits(newVal, 35, 0)) << 12); 147410037SARM gem5 Developers 147510037SARM gem5 Developers tlbiOp.broadcast(tc); 147610037SARM gem5 Developers return; 147710037SARM gem5 Developers } 147810037SARM gem5 Developers case MISCREG_ACTLR: 147910037SARM gem5 Developers warn("Not doing anything for write of miscreg ACTLR\n"); 148010037SARM gem5 Developers break; 148110037SARM gem5 Developers 148210037SARM gem5 Developers case MISCREG_PMXEVTYPER_PMCCFILTR: 148310037SARM gem5 Developers case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 148410037SARM gem5 Developers case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 148510037SARM gem5 Developers case MISCREG_PMCR ... MISCREG_PMOVSSET: 148610037SARM gem5 Developers pmu->setMiscReg(misc_reg, newVal); 148710037SARM gem5 Developers break; 148810037SARM gem5 Developers 148910037SARM gem5 Developers 149010037SARM gem5 Developers case MISCREG_HSTR: // TJDBX, now redifined to be RES0 149110037SARM gem5 Developers { 149210037SARM gem5 Developers HSTR hstrMask = 0; 149310037SARM gem5 Developers hstrMask.tjdbx = 1; 149410037SARM gem5 Developers newVal &= ~((uint32_t) hstrMask); 149510037SARM gem5 Developers break; 149610037SARM gem5 Developers } 149710037SARM gem5 Developers case MISCREG_HCPTR: 149810037SARM gem5 Developers { 149910037SARM gem5 Developers // If a CP bit in NSACR is 0 then the corresponding bit in 150010037SARM gem5 Developers // HCPTR is RAO/WI. Same applies to NSASEDIS 150110037SARM gem5 Developers secure_lookup = haveSecurity && 150210037SARM gem5 Developers inSecureState(readMiscRegNoEffect(MISCREG_SCR), 150310037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR)); 150410037SARM gem5 Developers if (!secure_lookup) { 150510037SARM gem5 Developers MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 150610037SARM gem5 Developers MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 150710037SARM gem5 Developers newVal = (newVal & ~mask) | (oldValue & mask); 150810037SARM gem5 Developers } 150910037SARM gem5 Developers break; 151010037SARM gem5 Developers } 151110037SARM gem5 Developers case MISCREG_HDFAR: // alias for secure DFAR 151210037SARM gem5 Developers misc_reg = MISCREG_DFAR_S; 151310037SARM gem5 Developers break; 151410037SARM gem5 Developers case MISCREG_HIFAR: // alias for secure IFAR 15157436Sdam.sunwoo@arm.com misc_reg = MISCREG_IFAR_S; 151610037SARM gem5 Developers break; 151710037SARM gem5 Developers case MISCREG_ATS1CPR: 151810037SARM gem5 Developers case MISCREG_ATS1CPW: 151910037SARM gem5 Developers case MISCREG_ATS1CUR: 152010037SARM gem5 Developers case MISCREG_ATS1CUW: 152110037SARM gem5 Developers case MISCREG_ATS12NSOPR: 152210037SARM gem5 Developers case MISCREG_ATS12NSOPW: 152311560Sandreas.sandberg@arm.com case MISCREG_ATS12NSOUR: 152411435Smitch.hayenga@arm.com case MISCREG_ATS12NSOUW: 152510653Sandreas.hansson@arm.com case MISCREG_ATS1HR: 152610037SARM gem5 Developers case MISCREG_ATS1HW: 152710037SARM gem5 Developers { 152810037SARM gem5 Developers Request::Flags flags = 0; 152910037SARM gem5 Developers BaseTLB::Mode mode = BaseTLB::Read; 15307436Sdam.sunwoo@arm.com TLB::ArmTranslationType tranType = TLB::NormalTran; 153110653Sandreas.hansson@arm.com Fault fault; 153210037SARM gem5 Developers switch(misc_reg) { 153310037SARM gem5 Developers case MISCREG_ATS1CPR: 153410037SARM gem5 Developers flags = TLB::MustBeOne; 153510037SARM gem5 Developers tranType = TLB::S1CTran; 153610037SARM gem5 Developers mode = BaseTLB::Read; 153710037SARM gem5 Developers break; 153810037SARM gem5 Developers case MISCREG_ATS1CPW: 153910037SARM gem5 Developers flags = TLB::MustBeOne; 15407436Sdam.sunwoo@arm.com tranType = TLB::S1CTran; 15417436Sdam.sunwoo@arm.com mode = BaseTLB::Write; 154210037SARM gem5 Developers break; 154310037SARM gem5 Developers case MISCREG_ATS1CUR: 154410037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 154510037SARM gem5 Developers tranType = TLB::S1CTran; 154610037SARM gem5 Developers mode = BaseTLB::Read; 154710037SARM gem5 Developers break; 154810037SARM gem5 Developers case MISCREG_ATS1CUW: 154910037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 155010037SARM gem5 Developers tranType = TLB::S1CTran; 155110037SARM gem5 Developers mode = BaseTLB::Write; 155210037SARM gem5 Developers break; 155310037SARM gem5 Developers case MISCREG_ATS12NSOPR: 155410037SARM gem5 Developers if (!haveSecurity) 155510037SARM gem5 Developers panic("Security Extensions required for ATS12NSOPR"); 155610037SARM gem5 Developers flags = TLB::MustBeOne; 155710037SARM gem5 Developers tranType = TLB::S1S2NsTran; 155810037SARM gem5 Developers mode = BaseTLB::Read; 155910037SARM gem5 Developers break; 156010037SARM gem5 Developers case MISCREG_ATS12NSOPW: 156110037SARM gem5 Developers if (!haveSecurity) 156210037SARM gem5 Developers panic("Security Extensions required for ATS12NSOPW"); 156310037SARM gem5 Developers flags = TLB::MustBeOne; 15647436Sdam.sunwoo@arm.com tranType = TLB::S1S2NsTran; 156510037SARM gem5 Developers mode = BaseTLB::Write; 15667436Sdam.sunwoo@arm.com break; 15677436Sdam.sunwoo@arm.com case MISCREG_ATS12NSOUR: 156810037SARM gem5 Developers if (!haveSecurity) 156910037SARM gem5 Developers panic("Security Extensions required for ATS12NSOUR"); 157010037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 157110037SARM gem5 Developers tranType = TLB::S1S2NsTran; 157210037SARM gem5 Developers mode = BaseTLB::Read; 157310037SARM gem5 Developers break; 157410037SARM gem5 Developers case MISCREG_ATS12NSOUW: 157510037SARM gem5 Developers if (!haveSecurity) 157610037SARM gem5 Developers panic("Security Extensions required for ATS12NSOUW"); 157710037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 157810037SARM gem5 Developers tranType = TLB::S1S2NsTran; 157910037SARM gem5 Developers mode = BaseTLB::Write; 158010037SARM gem5 Developers break; 158110037SARM gem5 Developers case MISCREG_ATS1HR: // only really useful from secure mode. 158210037SARM gem5 Developers flags = TLB::MustBeOne; 158310037SARM gem5 Developers tranType = TLB::HypMode; 158410037SARM gem5 Developers mode = BaseTLB::Read; 158510037SARM gem5 Developers break; 158610037SARM gem5 Developers case MISCREG_ATS1HW: 158710037SARM gem5 Developers flags = TLB::MustBeOne; 158810037SARM gem5 Developers tranType = TLB::HypMode; 158910037SARM gem5 Developers mode = BaseTLB::Write; 159010037SARM gem5 Developers break; 159110037SARM gem5 Developers } 159210037SARM gem5 Developers // If we're in timing mode then doing the translation in 159310037SARM gem5 Developers // functional mode then we're slightly distorting performance 159410037SARM gem5 Developers // results obtained from simulations. The translation should be 159510037SARM gem5 Developers // done in the same mode the core is running in. NOTE: This 159610037SARM gem5 Developers // can't be an atomic translation because that causes problems 159710037SARM gem5 Developers // with unexpected atomic snoop requests. 159810037SARM gem5 Developers warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 159910037SARM gem5 Developers 160010037SARM gem5 Developers auto req = std::make_shared<Request>( 160110037SARM gem5 Developers 0, val, 0, flags, Request::funcMasterId, 160210037SARM gem5 Developers tc->pcState().pc(), tc->contextId()); 160310037SARM gem5 Developers 160410037SARM gem5 Developers fault = getDTBPtr(tc)->translateFunctional( 160510037SARM gem5 Developers req, tc, mode, tranType); 160610037SARM gem5 Developers 160710037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 160810037SARM gem5 Developers HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 160910037SARM gem5 Developers 161010037SARM gem5 Developers MiscReg newVal; 161110037SARM gem5 Developers if (fault == NoFault) { 161210037SARM gem5 Developers Addr paddr = req->getPaddr(); 161310508SAli.Saidi@ARM.com if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 161410508SAli.Saidi@ARM.com ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 161510508SAli.Saidi@ARM.com newVal = (paddr & mask(39, 12)) | 161610508SAli.Saidi@ARM.com (getDTBPtr(tc)->getAttr()); 161710508SAli.Saidi@ARM.com } else { 161810508SAli.Saidi@ARM.com newVal = (paddr & 0xfffff000) | 16197749SAli.Saidi@ARM.com (getDTBPtr(tc)->getAttr()); 16207749SAli.Saidi@ARM.com } 16217749SAli.Saidi@ARM.com DPRINTF(MiscRegs, 162210037SARM gem5 Developers "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 162310037SARM gem5 Developers val, newVal); 16247749SAli.Saidi@ARM.com } else { 162510037SARM gem5 Developers ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 162610037SARM gem5 Developers armFault->update(tc); 162710037SARM gem5 Developers // Set fault bit and FSR 162810037SARM gem5 Developers FSR fsr = armFault->getFsr(tc); 162910037SARM gem5 Developers 163010508SAli.Saidi@ARM.com newVal = ((fsr >> 9) & 1) << 11; 163110508SAli.Saidi@ARM.com if (newVal) { 163210037SARM gem5 Developers // LPAE - rearange fault status 163310037SARM gem5 Developers newVal |= ((fsr >> 0) & 0x3f) << 1; 163410037SARM gem5 Developers } else { 163510037SARM gem5 Developers // VMSA - rearange fault status 16367749SAli.Saidi@ARM.com newVal |= ((fsr >> 0) & 0xf) << 1; 16377749SAli.Saidi@ARM.com newVal |= ((fsr >> 10) & 0x1) << 5; 16387749SAli.Saidi@ARM.com newVal |= ((fsr >> 12) & 0x1) << 6; 163910037SARM gem5 Developers } 164010037SARM gem5 Developers newVal |= 0x1; // F bit 164110037SARM gem5 Developers newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 164210037SARM gem5 Developers newVal |= armFault->isStage2() ? 0x200 : 0; 164310338SCurtis.Dunham@arm.com DPRINTF(MiscRegs, 164410338SCurtis.Dunham@arm.com "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 164510338SCurtis.Dunham@arm.com val, fsr, newVal); 164610037SARM gem5 Developers } 164710037SARM gem5 Developers setMiscRegNoEffect(MISCREG_PAR, newVal); 164810037SARM gem5 Developers return; 164910037SARM gem5 Developers } 165010037SARM gem5 Developers case MISCREG_TTBCR: 165110037SARM gem5 Developers { 165210037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 165310037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 165410037SARM gem5 Developers TTBCR ttbcrMask = 0; 165510037SARM gem5 Developers TTBCR ttbcrNew = newVal; 165610037SARM gem5 Developers 165710037SARM gem5 Developers // ARM DDI 0406C.b, ARMv7-32 165810037SARM gem5 Developers ttbcrMask.n = ones; // T0SZ 165910037SARM gem5 Developers if (haveSecurity) { 166010037SARM gem5 Developers ttbcrMask.pd0 = ones; 166110037SARM gem5 Developers ttbcrMask.pd1 = ones; 166210037SARM gem5 Developers } 166310037SARM gem5 Developers ttbcrMask.epd0 = ones; 166410037SARM gem5 Developers ttbcrMask.irgn0 = ones; 166510037SARM gem5 Developers ttbcrMask.orgn0 = ones; 166610037SARM gem5 Developers ttbcrMask.sh0 = ones; 166710037SARM gem5 Developers ttbcrMask.ps = ones; // T1SZ 166810037SARM gem5 Developers ttbcrMask.a1 = ones; 166910037SARM gem5 Developers ttbcrMask.epd1 = ones; 167010037SARM gem5 Developers ttbcrMask.irgn1 = ones; 167110037SARM gem5 Developers ttbcrMask.orgn1 = ones; 167210037SARM gem5 Developers ttbcrMask.sh1 = ones; 167310037SARM gem5 Developers if (haveLPAE) 167410037SARM gem5 Developers ttbcrMask.eae = ones; 167510037SARM gem5 Developers 167610037SARM gem5 Developers if (haveLPAE && ttbcrNew.eae) { 167710037SARM gem5 Developers newVal = newVal & ttbcrMask; 167810037SARM gem5 Developers } else { 167910037SARM gem5 Developers newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 168010037SARM gem5 Developers } 168110037SARM gem5 Developers // Invalidate TLB MiscReg 168210037SARM gem5 Developers getITBPtr(tc)->invalidateMiscReg(); 168310037SARM gem5 Developers getDTBPtr(tc)->invalidateMiscReg(); 168410037SARM gem5 Developers break; 168510037SARM gem5 Developers } 168610037SARM gem5 Developers case MISCREG_TTBR0: 168710037SARM gem5 Developers case MISCREG_TTBR1: 168810037SARM gem5 Developers { 168910037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 169010037SARM gem5 Developers if (haveLPAE) { 169110037SARM gem5 Developers if (ttbcr.eae) { 169210037SARM gem5 Developers // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 169310037SARM gem5 Developers // ARMv8 AArch32 bit 63-56 only 169410037SARM gem5 Developers uint64_t ttbrMask = mask(63,56) | mask(47,40); 169510037SARM gem5 Developers newVal = (newVal & (~ttbrMask)); 169610037SARM gem5 Developers } 169710037SARM gem5 Developers } 169810037SARM gem5 Developers // Invalidate TLB MiscReg 169910037SARM gem5 Developers getITBPtr(tc)->invalidateMiscReg(); 170010037SARM gem5 Developers getDTBPtr(tc)->invalidateMiscReg(); 170110037SARM gem5 Developers break; 170210037SARM gem5 Developers } 170310037SARM gem5 Developers case MISCREG_SCTLR_EL1: 170410037SARM gem5 Developers case MISCREG_CONTEXTIDR: 170510037SARM gem5 Developers case MISCREG_PRRR: 170610037SARM gem5 Developers case MISCREG_NMRR: 170710037SARM gem5 Developers case MISCREG_MAIR0: 170810037SARM gem5 Developers case MISCREG_MAIR1: 170910037SARM gem5 Developers case MISCREG_DACR: 171010037SARM gem5 Developers case MISCREG_VTTBR: 171110037SARM gem5 Developers case MISCREG_SCR_EL3: 171210037SARM gem5 Developers case MISCREG_HCR_EL2: 171310037SARM gem5 Developers case MISCREG_TCR_EL1: 171410037SARM gem5 Developers case MISCREG_TCR_EL2: 171510037SARM gem5 Developers case MISCREG_TCR_EL3: 171610037SARM gem5 Developers case MISCREG_SCTLR_EL2: 171710037SARM gem5 Developers case MISCREG_SCTLR_EL3: 171810037SARM gem5 Developers case MISCREG_HSCTLR: 171910037SARM gem5 Developers case MISCREG_TTBR0_EL1: 172010037SARM gem5 Developers case MISCREG_TTBR1_EL1: 172110037SARM gem5 Developers case MISCREG_TTBR0_EL2: 172210037SARM gem5 Developers case MISCREG_TTBR1_EL2: 172310037SARM gem5 Developers case MISCREG_TTBR0_EL3: 172410037SARM gem5 Developers getITBPtr(tc)->invalidateMiscReg(); 172510037SARM gem5 Developers getDTBPtr(tc)->invalidateMiscReg(); 172610037SARM gem5 Developers break; 172710037SARM gem5 Developers case MISCREG_NZCV: 172810037SARM gem5 Developers { 172910037SARM gem5 Developers CPSR cpsr = val; 173010037SARM gem5 Developers 173110037SARM gem5 Developers tc->setCCReg(CCREG_NZ, cpsr.nz); 173210037SARM gem5 Developers tc->setCCReg(CCREG_C, cpsr.c); 173310037SARM gem5 Developers tc->setCCReg(CCREG_V, cpsr.v); 173410037SARM gem5 Developers } 173510037SARM gem5 Developers break; 173610037SARM gem5 Developers case MISCREG_DAIF: 173710037SARM gem5 Developers { 173810037SARM gem5 Developers CPSR cpsr = miscRegs[MISCREG_CPSR]; 173910037SARM gem5 Developers cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 174010037SARM gem5 Developers newVal = cpsr; 174110037SARM gem5 Developers misc_reg = MISCREG_CPSR; 174210037SARM gem5 Developers } 174310037SARM gem5 Developers break; 174410037SARM gem5 Developers case MISCREG_SP_EL0: 174510037SARM gem5 Developers tc->setIntReg(INTREG_SP0, newVal); 174610037SARM gem5 Developers break; 174710037SARM gem5 Developers case MISCREG_SP_EL1: 174810037SARM gem5 Developers tc->setIntReg(INTREG_SP1, newVal); 174910037SARM gem5 Developers break; 175010037SARM gem5 Developers case MISCREG_SP_EL2: 175110037SARM gem5 Developers tc->setIntReg(INTREG_SP2, newVal); 175210037SARM gem5 Developers break; 175310037SARM gem5 Developers case MISCREG_SPSEL: 175410037SARM gem5 Developers { 175510037SARM gem5 Developers CPSR cpsr = miscRegs[MISCREG_CPSR]; 175610037SARM gem5 Developers cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 175710037SARM gem5 Developers newVal = cpsr; 175810037SARM gem5 Developers misc_reg = MISCREG_CPSR; 175910037SARM gem5 Developers } 176010037SARM gem5 Developers break; 176110037SARM gem5 Developers case MISCREG_CURRENTEL: 176210037SARM gem5 Developers { 176310037SARM gem5 Developers CPSR cpsr = miscRegs[MISCREG_CPSR]; 176410037SARM gem5 Developers cpsr.el = (uint8_t) ((CPSR) newVal).el; 176510037SARM gem5 Developers newVal = cpsr; 176610037SARM gem5 Developers misc_reg = MISCREG_CPSR; 176710037SARM gem5 Developers } 176811560Sandreas.sandberg@arm.com break; 176910037SARM gem5 Developers case MISCREG_AT_S1E1R_Xt: 177011435Smitch.hayenga@arm.com case MISCREG_AT_S1E1W_Xt: 177110037SARM gem5 Developers case MISCREG_AT_S1E0R_Xt: 177210037SARM gem5 Developers case MISCREG_AT_S1E0W_Xt: 177310037SARM gem5 Developers case MISCREG_AT_S1E2R_Xt: 177410037SARM gem5 Developers case MISCREG_AT_S1E2W_Xt: 177510037SARM gem5 Developers case MISCREG_AT_S12E1R_Xt: 177610037SARM gem5 Developers case MISCREG_AT_S12E1W_Xt: 177710037SARM gem5 Developers case MISCREG_AT_S12E0R_Xt: 177810037SARM gem5 Developers case MISCREG_AT_S12E0W_Xt: 177910037SARM gem5 Developers case MISCREG_AT_S1E3R_Xt: 178010037SARM gem5 Developers case MISCREG_AT_S1E3W_Xt: 178110037SARM gem5 Developers { 178210037SARM gem5 Developers RequestPtr req = std::make_shared<Request>(); 178310037SARM gem5 Developers Request::Flags flags = 0; 178410037SARM gem5 Developers BaseTLB::Mode mode = BaseTLB::Read; 178510037SARM gem5 Developers TLB::ArmTranslationType tranType = TLB::NormalTran; 178610037SARM gem5 Developers Fault fault; 178710037SARM gem5 Developers switch(misc_reg) { 178810037SARM gem5 Developers case MISCREG_AT_S1E1R_Xt: 178910037SARM gem5 Developers flags = TLB::MustBeOne; 179010037SARM gem5 Developers tranType = TLB::S1E1Tran; 179110037SARM gem5 Developers mode = BaseTLB::Read; 179210037SARM gem5 Developers break; 179310037SARM gem5 Developers case MISCREG_AT_S1E1W_Xt: 179410037SARM gem5 Developers flags = TLB::MustBeOne; 179510037SARM gem5 Developers tranType = TLB::S1E1Tran; 179610037SARM gem5 Developers mode = BaseTLB::Write; 179710037SARM gem5 Developers break; 179810037SARM gem5 Developers case MISCREG_AT_S1E0R_Xt: 179910037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 180010037SARM gem5 Developers tranType = TLB::S1E0Tran; 180110037SARM gem5 Developers mode = BaseTLB::Read; 180210037SARM gem5 Developers break; 180310037SARM gem5 Developers case MISCREG_AT_S1E0W_Xt: 180410037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 180510037SARM gem5 Developers tranType = TLB::S1E0Tran; 180610037SARM gem5 Developers mode = BaseTLB::Write; 180710037SARM gem5 Developers break; 180810037SARM gem5 Developers case MISCREG_AT_S1E2R_Xt: 180910037SARM gem5 Developers flags = TLB::MustBeOne; 181010037SARM gem5 Developers tranType = TLB::S1E2Tran; 181110037SARM gem5 Developers mode = BaseTLB::Read; 18128549Sdaniel.johnson@arm.com break; 18138549Sdaniel.johnson@arm.com case MISCREG_AT_S1E2W_Xt: 18148549Sdaniel.johnson@arm.com flags = TLB::MustBeOne; 181510037SARM gem5 Developers tranType = TLB::S1E2Tran; 181610037SARM gem5 Developers mode = BaseTLB::Write; 181710037SARM gem5 Developers break; 181810844Sandreas.sandberg@arm.com case MISCREG_AT_S12E0R_Xt: 181910844Sandreas.sandberg@arm.com flags = TLB::MustBeOne | TLB::UserMode; 182010844Sandreas.sandberg@arm.com tranType = TLB::S12E0Tran; 182110844Sandreas.sandberg@arm.com mode = BaseTLB::Read; 182210844Sandreas.sandberg@arm.com break; 182310037SARM gem5 Developers case MISCREG_AT_S12E0W_Xt: 18247405SAli.Saidi@ARM.com flags = TLB::MustBeOne | TLB::UserMode; 18257405SAli.Saidi@ARM.com tranType = TLB::S12E0Tran; 18267405SAli.Saidi@ARM.com mode = BaseTLB::Write; 18277405SAli.Saidi@ARM.com break; 18287405SAli.Saidi@ARM.com case MISCREG_AT_S12E1R_Xt: 182910037SARM gem5 Developers flags = TLB::MustBeOne; 183010709SAndreas.Sandberg@ARM.com tranType = TLB::S12E1Tran; 183110709SAndreas.Sandberg@ARM.com mode = BaseTLB::Read; 183210037SARM gem5 Developers break; 183310709SAndreas.Sandberg@ARM.com case MISCREG_AT_S12E1W_Xt: 183410037SARM gem5 Developers flags = TLB::MustBeOne; 183510037SARM gem5 Developers tranType = TLB::S12E1Tran; 183610037SARM gem5 Developers mode = BaseTLB::Write; 183710037SARM gem5 Developers break; 183810037SARM gem5 Developers case MISCREG_AT_S1E3R_Xt: 183910037SARM gem5 Developers flags = TLB::MustBeOne; 184010037SARM gem5 Developers tranType = TLB::S1E3Tran; 184110037SARM gem5 Developers mode = BaseTLB::Read; 184210037SARM gem5 Developers break; 184310037SARM gem5 Developers case MISCREG_AT_S1E3W_Xt: 184410037SARM gem5 Developers flags = TLB::MustBeOne; 184510037SARM gem5 Developers tranType = TLB::S1E3Tran; 184610037SARM gem5 Developers mode = BaseTLB::Write; 184710037SARM gem5 Developers break; 184810037SARM gem5 Developers } 184910037SARM gem5 Developers // If we're in timing mode then doing the translation in 185010037SARM gem5 Developers // functional mode then we're slightly distorting performance 185110037SARM gem5 Developers // results obtained from simulations. The translation should be 185210037SARM gem5 Developers // done in the same mode the core is running in. NOTE: This 185310037SARM gem5 Developers // can't be an atomic translation because that causes problems 185410037SARM gem5 Developers // with unexpected atomic snoop requests. 185510037SARM gem5 Developers warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 185610037SARM gem5 Developers req->setVirt(0, val, 0, flags, Request::funcMasterId, 185710037SARM gem5 Developers tc->pcState().pc()); 185810037SARM gem5 Developers req->setContext(tc->contextId()); 185910037SARM gem5 Developers fault = getDTBPtr(tc)->translateFunctional(req, tc, mode, 186010037SARM gem5 Developers tranType); 186110037SARM gem5 Developers 186210037SARM gem5 Developers MiscReg newVal; 186310037SARM gem5 Developers if (fault == NoFault) { 186410037SARM gem5 Developers Addr paddr = req->getPaddr(); 186510037SARM gem5 Developers uint64_t attr = getDTBPtr(tc)->getAttr(); 186610037SARM gem5 Developers uint64_t attr1 = attr >> 56; 186710037SARM gem5 Developers if (!attr1 || attr1 ==0x44) { 186810037SARM gem5 Developers attr |= 0x100; 186910037SARM gem5 Developers attr &= ~ uint64_t(0x80); 187010037SARM gem5 Developers } 187110037SARM gem5 Developers newVal = (paddr & mask(47, 12)) | attr; 187210037SARM gem5 Developers DPRINTF(MiscRegs, 187310037SARM gem5 Developers "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 187410037SARM gem5 Developers val, newVal); 187510037SARM gem5 Developers } else { 187610037SARM gem5 Developers ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 187710037SARM gem5 Developers armFault->update(tc); 187810037SARM gem5 Developers // Set fault bit and FSR 187910037SARM gem5 Developers FSR fsr = armFault->getFsr(tc); 188010037SARM gem5 Developers 188110037SARM gem5 Developers CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 188210037SARM gem5 Developers if (cpsr.width) { // AArch32 188310037SARM gem5 Developers newVal = ((fsr >> 9) & 1) << 11; 188410037SARM gem5 Developers // rearrange fault status 188510037SARM gem5 Developers newVal |= ((fsr >> 0) & 0x3f) << 1; 188610037SARM gem5 Developers newVal |= 0x1; // F bit 188710037SARM gem5 Developers newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 188810037SARM gem5 Developers newVal |= armFault->isStage2() ? 0x200 : 0; 188910037SARM gem5 Developers } else { // AArch64 189010037SARM gem5 Developers newVal = 1; // F bit 189110037SARM gem5 Developers newVal |= fsr << 1; // FST 189210037SARM gem5 Developers // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit. 189310037SARM gem5 Developers newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 189410037SARM gem5 Developers newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 189510037SARM gem5 Developers newVal |= 1 << 11; // RES1 189610037SARM gem5 Developers } 189710037SARM gem5 Developers DPRINTF(MiscRegs, 189810037SARM gem5 Developers "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 189910037SARM gem5 Developers val, fsr, newVal); 190010037SARM gem5 Developers } 190110037SARM gem5 Developers setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 190210037SARM gem5 Developers return; 190310037SARM gem5 Developers } 190410037SARM gem5 Developers case MISCREG_SPSR_EL3: 190510037SARM gem5 Developers case MISCREG_SPSR_EL2: 190610037SARM gem5 Developers case MISCREG_SPSR_EL1: 190710037SARM gem5 Developers // Force bits 23:21 to 0 190810037SARM gem5 Developers newVal = val & ~(0x7 << 21); 190910037SARM gem5 Developers break; 191010037SARM gem5 Developers case MISCREG_L2CTLR: 191110037SARM gem5 Developers warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 191210037SARM gem5 Developers miscRegName[misc_reg], uint32_t(val)); 191310037SARM gem5 Developers break; 191410037SARM gem5 Developers 191510037SARM gem5 Developers // Generic Timer registers 191610037SARM gem5 Developers case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 191710844Sandreas.sandberg@arm.com case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 191810844Sandreas.sandberg@arm.com case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 191910037SARM gem5 Developers case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 192010844Sandreas.sandberg@arm.com getGenericTimer(tc).setMiscReg(misc_reg, newVal); 192110844Sandreas.sandberg@arm.com break; 192210844Sandreas.sandberg@arm.com } 192310844Sandreas.sandberg@arm.com } 192410844Sandreas.sandberg@arm.com setMiscRegNoEffect(misc_reg, newVal); 192510844Sandreas.sandberg@arm.com} 192610844Sandreas.sandberg@arm.com 192710844Sandreas.sandberg@arm.comBaseISADevice & 192810844Sandreas.sandberg@arm.comISA::getGenericTimer(ThreadContext *tc) 192910844Sandreas.sandberg@arm.com{ 193010037SARM gem5 Developers // We only need to create an ISA interface the first time we try 193110037SARM gem5 Developers // to access the timer. 193211150Smitch.hayenga@arm.com if (timer) 193310844Sandreas.sandberg@arm.com return *timer.get(); 193410037SARM gem5 Developers 193510037SARM gem5 Developers assert(system); 19367405SAli.Saidi@ARM.com GenericTimer *generic_timer(system->getGenericTimer()); 19379384SAndreas.Sandberg@arm.com if (!generic_timer) { 19389384SAndreas.Sandberg@arm.com panic("Trying to get a generic timer from a system that hasn't " 19399384SAndreas.Sandberg@arm.com "been configured to use a generic timer.\n"); 19409384SAndreas.Sandberg@arm.com } 19419384SAndreas.Sandberg@arm.com 19429384SAndreas.Sandberg@arm.com timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 1943 return *timer.get(); 1944} 1945 1946} 1947 1948ArmISA::ISA * 1949ArmISAParams::create() 1950{ 1951 return new ArmISA::ISA(this); 1952} 1953