isa.cc revision 12749:223c83ed9979
1/* 2 * Copyright (c) 2010-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 */ 40 41#include "arch/arm/isa.hh" 42#include "arch/arm/pmu.hh" 43#include "arch/arm/system.hh" 44#include "arch/arm/tlb.hh" 45#include "arch/arm/tlbi_op.hh" 46#include "cpu/base.hh" 47#include "cpu/checker/cpu.hh" 48#include "debug/Arm.hh" 49#include "debug/MiscRegs.hh" 50#include "dev/arm/generic_timer.hh" 51#include "params/ArmISA.hh" 52#include "sim/faults.hh" 53#include "sim/stat_control.hh" 54#include "sim/system.hh" 55 56namespace ArmISA 57{ 58 59ISA::ISA(Params *p) 60 : SimObject(p), 61 system(NULL), 62 _decoderFlavour(p->decoderFlavour), 63 _vecRegRenameMode(p->vecRegRenameMode), 64 pmu(p->pmu), 65 impdefAsNop(p->impdef_nop) 66{ 67 miscRegs[MISCREG_SCTLR_RST] = 0; 68 69 // Hook up a dummy device if we haven't been configured with a 70 // real PMU. By using a dummy device, we don't need to check that 71 // the PMU exist every time we try to access a PMU register. 72 if (!pmu) 73 pmu = &dummyDevice; 74 75 // Give all ISA devices a pointer to this ISA 76 pmu->setISA(this); 77 78 system = dynamic_cast<ArmSystem *>(p->system); 79 80 // Cache system-level properties 81 if (FullSystem && system) { 82 highestELIs64 = system->highestELIs64(); 83 haveSecurity = system->haveSecurity(); 84 haveLPAE = system->haveLPAE(); 85 haveVirtualization = system->haveVirtualization(); 86 haveLargeAsid64 = system->haveLargeAsid64(); 87 physAddrRange64 = system->physAddrRange64(); 88 } else { 89 highestELIs64 = true; // ArmSystem::highestELIs64 does the same 90 haveSecurity = haveLPAE = haveVirtualization = false; 91 haveLargeAsid64 = false; 92 physAddrRange64 = 32; // dummy value 93 } 94 95 initializeMiscRegMetadata(); 96 preUnflattenMiscReg(); 97 98 clear(); 99} 100 101std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS); 102 103const ArmISAParams * 104ISA::params() const 105{ 106 return dynamic_cast<const Params *>(_params); 107} 108 109void 110ISA::clear() 111{ 112 const Params *p(params()); 113 114 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 115 memset(miscRegs, 0, sizeof(miscRegs)); 116 117 // Initialize configurable default values 118 miscRegs[MISCREG_MIDR] = p->midr; 119 miscRegs[MISCREG_MIDR_EL1] = p->midr; 120 miscRegs[MISCREG_VPIDR] = p->midr; 121 122 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 123 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 124 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 125 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 126 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 127 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 128 129 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 130 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 131 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 132 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 133 134 if (FullSystem && system->highestELIs64()) { 135 // Initialize AArch64 state 136 clear64(p); 137 return; 138 } 139 140 // Initialize AArch32 state... 141 142 CPSR cpsr = 0; 143 cpsr.mode = MODE_USER; 144 miscRegs[MISCREG_CPSR] = cpsr; 145 updateRegMap(cpsr); 146 147 SCTLR sctlr = 0; 148 sctlr.te = (bool) sctlr_rst.te; 149 sctlr.nmfi = (bool) sctlr_rst.nmfi; 150 sctlr.v = (bool) sctlr_rst.v; 151 sctlr.u = 1; 152 sctlr.xp = 1; 153 sctlr.rao2 = 1; 154 sctlr.rao3 = 1; 155 sctlr.rao4 = 0xf; // SCTLR[6:3] 156 sctlr.uci = 1; 157 sctlr.dze = 1; 158 miscRegs[MISCREG_SCTLR_NS] = sctlr; 159 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 160 miscRegs[MISCREG_HCPTR] = 0; 161 162 // Start with an event in the mailbox 163 miscRegs[MISCREG_SEV_MAILBOX] = 1; 164 165 // Separate Instruction and Data TLBs 166 miscRegs[MISCREG_TLBTR] = 1; 167 168 MVFR0 mvfr0 = 0; 169 mvfr0.advSimdRegisters = 2; 170 mvfr0.singlePrecision = 2; 171 mvfr0.doublePrecision = 2; 172 mvfr0.vfpExceptionTrapping = 0; 173 mvfr0.divide = 1; 174 mvfr0.squareRoot = 1; 175 mvfr0.shortVectors = 1; 176 mvfr0.roundingModes = 1; 177 miscRegs[MISCREG_MVFR0] = mvfr0; 178 179 MVFR1 mvfr1 = 0; 180 mvfr1.flushToZero = 1; 181 mvfr1.defaultNaN = 1; 182 mvfr1.advSimdLoadStore = 1; 183 mvfr1.advSimdInteger = 1; 184 mvfr1.advSimdSinglePrecision = 1; 185 mvfr1.advSimdHalfPrecision = 1; 186 mvfr1.vfpHalfPrecision = 1; 187 miscRegs[MISCREG_MVFR1] = mvfr1; 188 189 // Reset values of PRRR and NMRR are implementation dependent 190 191 // @todo: PRRR and NMRR in secure state? 192 miscRegs[MISCREG_PRRR_NS] = 193 (1 << 19) | // 19 194 (0 << 18) | // 18 195 (0 << 17) | // 17 196 (1 << 16) | // 16 197 (2 << 14) | // 15:14 198 (0 << 12) | // 13:12 199 (2 << 10) | // 11:10 200 (2 << 8) | // 9:8 201 (2 << 6) | // 7:6 202 (2 << 4) | // 5:4 203 (1 << 2) | // 3:2 204 0; // 1:0 205 miscRegs[MISCREG_NMRR_NS] = 206 (1 << 30) | // 31:30 207 (0 << 26) | // 27:26 208 (0 << 24) | // 25:24 209 (3 << 22) | // 23:22 210 (2 << 20) | // 21:20 211 (0 << 18) | // 19:18 212 (0 << 16) | // 17:16 213 (1 << 14) | // 15:14 214 (0 << 12) | // 13:12 215 (2 << 10) | // 11:10 216 (0 << 8) | // 9:8 217 (3 << 6) | // 7:6 218 (2 << 4) | // 5:4 219 (0 << 2) | // 3:2 220 0; // 1:0 221 222 miscRegs[MISCREG_CPACR] = 0; 223 224 miscRegs[MISCREG_FPSID] = p->fpsid; 225 226 if (haveLPAE) { 227 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 228 ttbcr.eae = 0; 229 miscRegs[MISCREG_TTBCR_NS] = ttbcr; 230 // Enforce consistency with system-level settings 231 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 232 } 233 234 if (haveSecurity) { 235 miscRegs[MISCREG_SCTLR_S] = sctlr; 236 miscRegs[MISCREG_SCR] = 0; 237 miscRegs[MISCREG_VBAR_S] = 0; 238 } else { 239 // we're always non-secure 240 miscRegs[MISCREG_SCR] = 1; 241 } 242 243 //XXX We need to initialize the rest of the state. 244} 245 246void 247ISA::clear64(const ArmISAParams *p) 248{ 249 CPSR cpsr = 0; 250 Addr rvbar = system->resetAddr64(); 251 switch (system->highestEL()) { 252 // Set initial EL to highest implemented EL using associated stack 253 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 254 // value 255 case EL3: 256 cpsr.mode = MODE_EL3H; 257 miscRegs[MISCREG_RVBAR_EL3] = rvbar; 258 break; 259 case EL2: 260 cpsr.mode = MODE_EL2H; 261 miscRegs[MISCREG_RVBAR_EL2] = rvbar; 262 break; 263 case EL1: 264 cpsr.mode = MODE_EL1H; 265 miscRegs[MISCREG_RVBAR_EL1] = rvbar; 266 break; 267 default: 268 panic("Invalid highest implemented exception level"); 269 break; 270 } 271 272 // Initialize rest of CPSR 273 cpsr.daif = 0xf; // Mask all interrupts 274 cpsr.ss = 0; 275 cpsr.il = 0; 276 miscRegs[MISCREG_CPSR] = cpsr; 277 updateRegMap(cpsr); 278 279 // Initialize other control registers 280 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 281 if (haveSecurity) { 282 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830; 283 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 284 } else if (haveVirtualization) { 285 // also MISCREG_SCTLR_EL2 (by mapping) 286 miscRegs[MISCREG_HSCTLR] = 0x30c50830; 287 } else { 288 // also MISCREG_SCTLR_EL1 (by mapping) 289 miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init 290 // Always non-secure 291 miscRegs[MISCREG_SCR_EL3] = 1; 292 } 293 294 // Initialize configurable id registers 295 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 296 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 297 miscRegs[MISCREG_ID_AA64DFR0_EL1] = 298 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 299 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 300 301 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 302 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 303 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 304 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 305 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 306 307 miscRegs[MISCREG_ID_DFR0_EL1] = 308 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 309 310 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 311 312 // Enforce consistency with system-level settings... 313 314 // EL3 315 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 316 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 317 haveSecurity ? 0x2 : 0x0); 318 // EL2 319 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 320 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 321 haveVirtualization ? 0x2 : 0x0); 322 // Large ASID support 323 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 324 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 325 haveLargeAsid64 ? 0x2 : 0x0); 326 // Physical address size 327 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 328 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 329 encodePhysAddrRange64(physAddrRange64)); 330} 331 332MiscReg 333ISA::readMiscRegNoEffect(int misc_reg) const 334{ 335 assert(misc_reg < NumMiscRegs); 336 337 const auto ® = lookUpMiscReg[misc_reg]; // bit masks 338 const auto &map = getMiscIndices(misc_reg); 339 int lower = map.first, upper = map.second; 340 // NB!: apply architectural masks according to desired register, 341 // despite possibly getting value from different (mapped) register. 342 auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32)) 343 |(miscRegs[upper] << 32)); 344 if (val & reg.res0()) { 345 DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n", 346 miscRegName[misc_reg], val & reg.res0()); 347 } 348 if ((val & reg.res1()) != reg.res1()) { 349 DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n", 350 miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1()); 351 } 352 return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao 353} 354 355 356MiscReg 357ISA::readMiscReg(int misc_reg, ThreadContext *tc) 358{ 359 CPSR cpsr = 0; 360 PCState pc = 0; 361 SCR scr = 0; 362 363 if (misc_reg == MISCREG_CPSR) { 364 cpsr = miscRegs[misc_reg]; 365 pc = tc->pcState(); 366 cpsr.j = pc.jazelle() ? 1 : 0; 367 cpsr.t = pc.thumb() ? 1 : 0; 368 return cpsr; 369 } 370 371#ifndef NDEBUG 372 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 373 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 374 warn("Unimplemented system register %s read.\n", 375 miscRegName[misc_reg]); 376 else 377 panic("Unimplemented system register %s read.\n", 378 miscRegName[misc_reg]); 379 } 380#endif 381 382 switch (unflattenMiscReg(misc_reg)) { 383 case MISCREG_HCR: 384 { 385 if (!haveVirtualization) 386 return 0; 387 else 388 return readMiscRegNoEffect(MISCREG_HCR); 389 } 390 case MISCREG_CPACR: 391 { 392 const uint32_t ones = (uint32_t)(-1); 393 CPACR cpacrMask = 0; 394 // Only cp10, cp11, and ase are implemented, nothing else should 395 // be readable? (straight copy from the write code) 396 cpacrMask.cp10 = ones; 397 cpacrMask.cp11 = ones; 398 cpacrMask.asedis = ones; 399 400 // Security Extensions may limit the readability of CPACR 401 if (haveSecurity) { 402 scr = readMiscRegNoEffect(MISCREG_SCR); 403 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 404 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 405 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 406 // NB: Skipping the full loop, here 407 if (!nsacr.cp10) cpacrMask.cp10 = 0; 408 if (!nsacr.cp11) cpacrMask.cp11 = 0; 409 } 410 } 411 MiscReg val = readMiscRegNoEffect(MISCREG_CPACR); 412 val &= cpacrMask; 413 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 414 miscRegName[misc_reg], val); 415 return val; 416 } 417 case MISCREG_MPIDR: 418 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 419 scr = readMiscRegNoEffect(MISCREG_SCR); 420 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 421 return getMPIDR(system, tc); 422 } else { 423 return readMiscReg(MISCREG_VMPIDR, tc); 424 } 425 break; 426 case MISCREG_MPIDR_EL1: 427 // @todo in the absence of v8 virtualization support just return MPIDR_EL1 428 return getMPIDR(system, tc) & 0xffffffff; 429 case MISCREG_VMPIDR: 430 // top bit defined as RES1 431 return readMiscRegNoEffect(misc_reg) | 0x80000000; 432 case MISCREG_ID_AFR0: // not implemented, so alias MIDR 433 case MISCREG_REVIDR: // not implemented, so alias MIDR 434 case MISCREG_MIDR: 435 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 436 scr = readMiscRegNoEffect(MISCREG_SCR); 437 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 438 return readMiscRegNoEffect(misc_reg); 439 } else { 440 return readMiscRegNoEffect(MISCREG_VPIDR); 441 } 442 break; 443 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 444 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 445 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 446 case MISCREG_AIDR: // AUX ID set to 0 447 case MISCREG_TCMTR: // No TCM's 448 return 0; 449 450 case MISCREG_CLIDR: 451 warn_once("The clidr register always reports 0 caches.\n"); 452 warn_once("clidr LoUIS field of 0b001 to match current " 453 "ARM implementations.\n"); 454 return 0x00200000; 455 case MISCREG_CCSIDR: 456 warn_once("The ccsidr register isn't implemented and " 457 "always reads as 0.\n"); 458 break; 459 case MISCREG_CTR: // AArch32, ARMv7, top bit set 460 case MISCREG_CTR_EL0: // AArch64 461 { 462 //all caches have the same line size in gem5 463 //4 byte words in ARM 464 unsigned lineSizeWords = 465 tc->getSystemPtr()->cacheLineSize() / 4; 466 unsigned log2LineSizeWords = 0; 467 468 while (lineSizeWords >>= 1) { 469 ++log2LineSizeWords; 470 } 471 472 CTR ctr = 0; 473 //log2 of minimun i-cache line size (words) 474 ctr.iCacheLineSize = log2LineSizeWords; 475 //b11 - gem5 uses pipt 476 ctr.l1IndexPolicy = 0x3; 477 //log2 of minimum d-cache line size (words) 478 ctr.dCacheLineSize = log2LineSizeWords; 479 //log2 of max reservation size (words) 480 ctr.erg = log2LineSizeWords; 481 //log2 of max writeback size (words) 482 ctr.cwg = log2LineSizeWords; 483 //b100 - gem5 format is ARMv7 484 ctr.format = 0x4; 485 486 return ctr; 487 } 488 case MISCREG_ACTLR: 489 warn("Not doing anything for miscreg ACTLR\n"); 490 break; 491 492 case MISCREG_PMXEVTYPER_PMCCFILTR: 493 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 494 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 495 case MISCREG_PMCR ... MISCREG_PMOVSSET: 496 return pmu->readMiscReg(misc_reg); 497 498 case MISCREG_CPSR_Q: 499 panic("shouldn't be reading this register seperately\n"); 500 case MISCREG_FPSCR_QC: 501 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 502 case MISCREG_FPSCR_EXC: 503 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 504 case MISCREG_FPSR: 505 { 506 const uint32_t ones = (uint32_t)(-1); 507 FPSCR fpscrMask = 0; 508 fpscrMask.ioc = ones; 509 fpscrMask.dzc = ones; 510 fpscrMask.ofc = ones; 511 fpscrMask.ufc = ones; 512 fpscrMask.ixc = ones; 513 fpscrMask.idc = ones; 514 fpscrMask.qc = ones; 515 fpscrMask.v = ones; 516 fpscrMask.c = ones; 517 fpscrMask.z = ones; 518 fpscrMask.n = ones; 519 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 520 } 521 case MISCREG_FPCR: 522 { 523 const uint32_t ones = (uint32_t)(-1); 524 FPSCR fpscrMask = 0; 525 fpscrMask.len = ones; 526 fpscrMask.stride = ones; 527 fpscrMask.rMode = ones; 528 fpscrMask.fz = ones; 529 fpscrMask.dn = ones; 530 fpscrMask.ahp = ones; 531 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 532 } 533 case MISCREG_NZCV: 534 { 535 CPSR cpsr = 0; 536 cpsr.nz = tc->readCCReg(CCREG_NZ); 537 cpsr.c = tc->readCCReg(CCREG_C); 538 cpsr.v = tc->readCCReg(CCREG_V); 539 return cpsr; 540 } 541 case MISCREG_DAIF: 542 { 543 CPSR cpsr = 0; 544 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 545 return cpsr; 546 } 547 case MISCREG_SP_EL0: 548 { 549 return tc->readIntReg(INTREG_SP0); 550 } 551 case MISCREG_SP_EL1: 552 { 553 return tc->readIntReg(INTREG_SP1); 554 } 555 case MISCREG_SP_EL2: 556 { 557 return tc->readIntReg(INTREG_SP2); 558 } 559 case MISCREG_SPSEL: 560 { 561 return miscRegs[MISCREG_CPSR] & 0x1; 562 } 563 case MISCREG_CURRENTEL: 564 { 565 return miscRegs[MISCREG_CPSR] & 0xc; 566 } 567 case MISCREG_L2CTLR: 568 { 569 // mostly unimplemented, just set NumCPUs field from sim and return 570 L2CTLR l2ctlr = 0; 571 // b00:1CPU to b11:4CPUs 572 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 573 return l2ctlr; 574 } 575 case MISCREG_DBGDIDR: 576 /* For now just implement the version number. 577 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 578 */ 579 return 0x5 << 16; 580 case MISCREG_DBGDSCRint: 581 return 0; 582 case MISCREG_ISR: 583 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 584 readMiscRegNoEffect(MISCREG_HCR), 585 readMiscRegNoEffect(MISCREG_CPSR), 586 readMiscRegNoEffect(MISCREG_SCR)); 587 case MISCREG_ISR_EL1: 588 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 589 readMiscRegNoEffect(MISCREG_HCR_EL2), 590 readMiscRegNoEffect(MISCREG_CPSR), 591 readMiscRegNoEffect(MISCREG_SCR_EL3)); 592 case MISCREG_DCZID_EL0: 593 return 0x04; // DC ZVA clear 64-byte chunks 594 case MISCREG_HCPTR: 595 { 596 MiscReg val = readMiscRegNoEffect(misc_reg); 597 // The trap bit associated with CP14 is defined as RAZ 598 val &= ~(1 << 14); 599 // If a CP bit in NSACR is 0 then the corresponding bit in 600 // HCPTR is RAO/WI 601 bool secure_lookup = haveSecurity && 602 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 603 readMiscRegNoEffect(MISCREG_CPSR)); 604 if (!secure_lookup) { 605 MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR); 606 val |= (mask ^ 0x7FFF) & 0xBFFF; 607 } 608 // Set the bits for unimplemented coprocessors to RAO/WI 609 val |= 0x33FF; 610 return (val); 611 } 612 case MISCREG_HDFAR: // alias for secure DFAR 613 return readMiscRegNoEffect(MISCREG_DFAR_S); 614 case MISCREG_HIFAR: // alias for secure IFAR 615 return readMiscRegNoEffect(MISCREG_IFAR_S); 616 case MISCREG_HVBAR: // bottom bits reserved 617 return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0; 618 case MISCREG_SCTLR: 619 return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818; 620 case MISCREG_SCTLR_EL1: 621 return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800; 622 case MISCREG_SCTLR_EL2: 623 case MISCREG_SCTLR_EL3: 624 case MISCREG_HSCTLR: 625 return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; 626 627 case MISCREG_ID_PFR0: 628 // !ThumbEE | !Jazelle | Thumb | ARM 629 return 0x00000031; 630 case MISCREG_ID_PFR1: 631 { // Timer | Virti | !M Profile | TrustZone | ARMv4 632 bool haveTimer = (system->getGenericTimer() != NULL); 633 return 0x00000001 634 | (haveSecurity ? 0x00000010 : 0x0) 635 | (haveVirtualization ? 0x00001000 : 0x0) 636 | (haveTimer ? 0x00010000 : 0x0); 637 } 638 case MISCREG_ID_AA64PFR0_EL1: 639 return 0x0000000000000002 // AArch{64,32} supported at EL0 640 | 0x0000000000000020 // EL1 641 | (haveVirtualization ? 0x0000000000000200 : 0) // EL2 642 | (haveSecurity ? 0x0000000000002000 : 0); // EL3 643 case MISCREG_ID_AA64PFR1_EL1: 644 return 0; // bits [63:0] RES0 (reserved for future use) 645 646 // Generic Timer registers 647 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 648 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 649 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 650 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 651 return getGenericTimer(tc).readMiscReg(misc_reg); 652 653 default: 654 break; 655 656 } 657 return readMiscRegNoEffect(misc_reg); 658} 659 660void 661ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 662{ 663 assert(misc_reg < NumMiscRegs); 664 665 const auto ® = lookUpMiscReg[misc_reg]; // bit masks 666 const auto &map = getMiscIndices(misc_reg); 667 int lower = map.first, upper = map.second; 668 669 auto v = (val & ~reg.wi()) | reg.rao(); 670 if (upper > 0) { 671 miscRegs[lower] = bits(v, 31, 0); 672 miscRegs[upper] = bits(v, 63, 32); 673 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 674 misc_reg, lower, upper, v); 675 } else { 676 miscRegs[lower] = v; 677 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 678 misc_reg, lower, v); 679 } 680} 681 682void 683ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 684{ 685 686 MiscReg newVal = val; 687 bool secure_lookup; 688 SCR scr; 689 690 if (misc_reg == MISCREG_CPSR) { 691 updateRegMap(val); 692 693 694 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 695 int old_mode = old_cpsr.mode; 696 CPSR cpsr = val; 697 if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) { 698 getITBPtr(tc)->invalidateMiscReg(); 699 getDTBPtr(tc)->invalidateMiscReg(); 700 } 701 702 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 703 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 704 PCState pc = tc->pcState(); 705 pc.nextThumb(cpsr.t); 706 pc.nextJazelle(cpsr.j); 707 708 // Follow slightly different semantics if a CheckerCPU object 709 // is connected 710 CheckerCPU *checker = tc->getCheckerCpuPtr(); 711 if (checker) { 712 tc->pcStateNoRecord(pc); 713 } else { 714 tc->pcState(pc); 715 } 716 } else { 717#ifndef NDEBUG 718 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 719 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 720 warn("Unimplemented system register %s write with %#x.\n", 721 miscRegName[misc_reg], val); 722 else 723 panic("Unimplemented system register %s write with %#x.\n", 724 miscRegName[misc_reg], val); 725 } 726#endif 727 switch (unflattenMiscReg(misc_reg)) { 728 case MISCREG_CPACR: 729 { 730 731 const uint32_t ones = (uint32_t)(-1); 732 CPACR cpacrMask = 0; 733 // Only cp10, cp11, and ase are implemented, nothing else should 734 // be writable 735 cpacrMask.cp10 = ones; 736 cpacrMask.cp11 = ones; 737 cpacrMask.asedis = ones; 738 739 // Security Extensions may limit the writability of CPACR 740 if (haveSecurity) { 741 scr = readMiscRegNoEffect(MISCREG_SCR); 742 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 743 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 744 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 745 // NB: Skipping the full loop, here 746 if (!nsacr.cp10) cpacrMask.cp10 = 0; 747 if (!nsacr.cp11) cpacrMask.cp11 = 0; 748 } 749 } 750 751 MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR); 752 newVal &= cpacrMask; 753 newVal |= old_val & ~cpacrMask; 754 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 755 miscRegName[misc_reg], newVal); 756 } 757 break; 758 case MISCREG_CPTR_EL2: 759 { 760 const uint32_t ones = (uint32_t)(-1); 761 CPTR cptrMask = 0; 762 cptrMask.tcpac = ones; 763 cptrMask.tta = ones; 764 cptrMask.tfp = ones; 765 newVal &= cptrMask; 766 cptrMask = 0; 767 cptrMask.res1_13_12_el2 = ones; 768 cptrMask.res1_9_0_el2 = ones; 769 newVal |= cptrMask; 770 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 771 miscRegName[misc_reg], newVal); 772 } 773 break; 774 case MISCREG_CPTR_EL3: 775 { 776 const uint32_t ones = (uint32_t)(-1); 777 CPTR cptrMask = 0; 778 cptrMask.tcpac = ones; 779 cptrMask.tta = ones; 780 cptrMask.tfp = ones; 781 newVal &= cptrMask; 782 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 783 miscRegName[misc_reg], newVal); 784 } 785 break; 786 case MISCREG_CSSELR: 787 warn_once("The csselr register isn't implemented.\n"); 788 return; 789 790 case MISCREG_DC_ZVA_Xt: 791 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 792 return; 793 794 case MISCREG_FPSCR: 795 { 796 const uint32_t ones = (uint32_t)(-1); 797 FPSCR fpscrMask = 0; 798 fpscrMask.ioc = ones; 799 fpscrMask.dzc = ones; 800 fpscrMask.ofc = ones; 801 fpscrMask.ufc = ones; 802 fpscrMask.ixc = ones; 803 fpscrMask.idc = ones; 804 fpscrMask.ioe = ones; 805 fpscrMask.dze = ones; 806 fpscrMask.ofe = ones; 807 fpscrMask.ufe = ones; 808 fpscrMask.ixe = ones; 809 fpscrMask.ide = ones; 810 fpscrMask.len = ones; 811 fpscrMask.stride = ones; 812 fpscrMask.rMode = ones; 813 fpscrMask.fz = ones; 814 fpscrMask.dn = ones; 815 fpscrMask.ahp = ones; 816 fpscrMask.qc = ones; 817 fpscrMask.v = ones; 818 fpscrMask.c = ones; 819 fpscrMask.z = ones; 820 fpscrMask.n = ones; 821 newVal = (newVal & (uint32_t)fpscrMask) | 822 (readMiscRegNoEffect(MISCREG_FPSCR) & 823 ~(uint32_t)fpscrMask); 824 tc->getDecoderPtr()->setContext(newVal); 825 } 826 break; 827 case MISCREG_FPSR: 828 { 829 const uint32_t ones = (uint32_t)(-1); 830 FPSCR fpscrMask = 0; 831 fpscrMask.ioc = ones; 832 fpscrMask.dzc = ones; 833 fpscrMask.ofc = ones; 834 fpscrMask.ufc = ones; 835 fpscrMask.ixc = ones; 836 fpscrMask.idc = ones; 837 fpscrMask.qc = ones; 838 fpscrMask.v = ones; 839 fpscrMask.c = ones; 840 fpscrMask.z = ones; 841 fpscrMask.n = ones; 842 newVal = (newVal & (uint32_t)fpscrMask) | 843 (readMiscRegNoEffect(MISCREG_FPSCR) & 844 ~(uint32_t)fpscrMask); 845 misc_reg = MISCREG_FPSCR; 846 } 847 break; 848 case MISCREG_FPCR: 849 { 850 const uint32_t ones = (uint32_t)(-1); 851 FPSCR fpscrMask = 0; 852 fpscrMask.len = ones; 853 fpscrMask.stride = ones; 854 fpscrMask.rMode = ones; 855 fpscrMask.fz = ones; 856 fpscrMask.dn = ones; 857 fpscrMask.ahp = ones; 858 newVal = (newVal & (uint32_t)fpscrMask) | 859 (readMiscRegNoEffect(MISCREG_FPSCR) & 860 ~(uint32_t)fpscrMask); 861 misc_reg = MISCREG_FPSCR; 862 } 863 break; 864 case MISCREG_CPSR_Q: 865 { 866 assert(!(newVal & ~CpsrMaskQ)); 867 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 868 misc_reg = MISCREG_CPSR; 869 } 870 break; 871 case MISCREG_FPSCR_QC: 872 { 873 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 874 (newVal & FpscrQcMask); 875 misc_reg = MISCREG_FPSCR; 876 } 877 break; 878 case MISCREG_FPSCR_EXC: 879 { 880 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 881 (newVal & FpscrExcMask); 882 misc_reg = MISCREG_FPSCR; 883 } 884 break; 885 case MISCREG_FPEXC: 886 { 887 // vfpv3 architecture, section B.6.1 of DDI04068 888 // bit 29 - valid only if fpexc[31] is 0 889 const uint32_t fpexcMask = 0x60000000; 890 newVal = (newVal & fpexcMask) | 891 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 892 } 893 break; 894 case MISCREG_HCR: 895 { 896 if (!haveVirtualization) 897 return; 898 } 899 break; 900 case MISCREG_IFSR: 901 { 902 // ARM ARM (ARM DDI 0406C.b) B4.1.96 903 const uint32_t ifsrMask = 904 mask(31, 13) | mask(11, 11) | mask(8, 6); 905 newVal = newVal & ~ifsrMask; 906 } 907 break; 908 case MISCREG_DFSR: 909 { 910 // ARM ARM (ARM DDI 0406C.b) B4.1.52 911 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 912 newVal = newVal & ~dfsrMask; 913 } 914 break; 915 case MISCREG_AMAIR0: 916 case MISCREG_AMAIR1: 917 { 918 // ARM ARM (ARM DDI 0406C.b) B4.1.5 919 // Valid only with LPAE 920 if (!haveLPAE) 921 return; 922 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 923 } 924 break; 925 case MISCREG_SCR: 926 getITBPtr(tc)->invalidateMiscReg(); 927 getDTBPtr(tc)->invalidateMiscReg(); 928 break; 929 case MISCREG_SCTLR: 930 { 931 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 932 scr = readMiscRegNoEffect(MISCREG_SCR); 933 934 MiscRegIndex sctlr_idx; 935 if (haveSecurity && !highestELIs64 && !scr.ns) { 936 sctlr_idx = MISCREG_SCTLR_S; 937 } else { 938 sctlr_idx = MISCREG_SCTLR_NS; 939 } 940 941 SCTLR sctlr = miscRegs[sctlr_idx]; 942 SCTLR new_sctlr = newVal; 943 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 944 miscRegs[sctlr_idx] = (MiscReg)new_sctlr; 945 getITBPtr(tc)->invalidateMiscReg(); 946 getDTBPtr(tc)->invalidateMiscReg(); 947 } 948 case MISCREG_MIDR: 949 case MISCREG_ID_PFR0: 950 case MISCREG_ID_PFR1: 951 case MISCREG_ID_DFR0: 952 case MISCREG_ID_MMFR0: 953 case MISCREG_ID_MMFR1: 954 case MISCREG_ID_MMFR2: 955 case MISCREG_ID_MMFR3: 956 case MISCREG_ID_ISAR0: 957 case MISCREG_ID_ISAR1: 958 case MISCREG_ID_ISAR2: 959 case MISCREG_ID_ISAR3: 960 case MISCREG_ID_ISAR4: 961 case MISCREG_ID_ISAR5: 962 963 case MISCREG_MPIDR: 964 case MISCREG_FPSID: 965 case MISCREG_TLBTR: 966 case MISCREG_MVFR0: 967 case MISCREG_MVFR1: 968 969 case MISCREG_ID_AA64AFR0_EL1: 970 case MISCREG_ID_AA64AFR1_EL1: 971 case MISCREG_ID_AA64DFR0_EL1: 972 case MISCREG_ID_AA64DFR1_EL1: 973 case MISCREG_ID_AA64ISAR0_EL1: 974 case MISCREG_ID_AA64ISAR1_EL1: 975 case MISCREG_ID_AA64MMFR0_EL1: 976 case MISCREG_ID_AA64MMFR1_EL1: 977 case MISCREG_ID_AA64PFR0_EL1: 978 case MISCREG_ID_AA64PFR1_EL1: 979 // ID registers are constants. 980 return; 981 982 // TLB Invalidate All 983 case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 984 { 985 assert32(tc); 986 scr = readMiscReg(MISCREG_SCR, tc); 987 988 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 989 tlbiOp(tc); 990 return; 991 } 992 // TLB Invalidate All, Inner Shareable 993 case MISCREG_TLBIALLIS: 994 { 995 assert32(tc); 996 scr = readMiscReg(MISCREG_SCR, tc); 997 998 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 999 tlbiOp.broadcast(tc); 1000 return; 1001 } 1002 // Instruction TLB Invalidate All 1003 case MISCREG_ITLBIALL: 1004 { 1005 assert32(tc); 1006 scr = readMiscReg(MISCREG_SCR, tc); 1007 1008 ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1009 tlbiOp(tc); 1010 return; 1011 } 1012 // Data TLB Invalidate All 1013 case MISCREG_DTLBIALL: 1014 { 1015 assert32(tc); 1016 scr = readMiscReg(MISCREG_SCR, tc); 1017 1018 DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1019 tlbiOp(tc); 1020 return; 1021 } 1022 // TLB Invalidate by VA 1023 // mcr tlbimval(is) is invalidating all matching entries 1024 // regardless of the level of lookup, since in gem5 we cache 1025 // in the tlb the last level of lookup only. 1026 case MISCREG_TLBIMVA: 1027 case MISCREG_TLBIMVAL: 1028 { 1029 assert32(tc); 1030 scr = readMiscReg(MISCREG_SCR, tc); 1031 1032 TLBIMVA tlbiOp(EL1, 1033 haveSecurity && !scr.ns, 1034 mbits(newVal, 31, 12), 1035 bits(newVal, 7,0)); 1036 1037 tlbiOp(tc); 1038 return; 1039 } 1040 // TLB Invalidate by VA, Inner Shareable 1041 case MISCREG_TLBIMVAIS: 1042 case MISCREG_TLBIMVALIS: 1043 { 1044 assert32(tc); 1045 scr = readMiscReg(MISCREG_SCR, tc); 1046 1047 TLBIMVA tlbiOp(EL1, 1048 haveSecurity && !scr.ns, 1049 mbits(newVal, 31, 12), 1050 bits(newVal, 7,0)); 1051 1052 tlbiOp.broadcast(tc); 1053 return; 1054 } 1055 // TLB Invalidate by ASID match 1056 case MISCREG_TLBIASID: 1057 { 1058 assert32(tc); 1059 scr = readMiscReg(MISCREG_SCR, tc); 1060 1061 TLBIASID tlbiOp(EL1, 1062 haveSecurity && !scr.ns, 1063 bits(newVal, 7,0)); 1064 1065 tlbiOp(tc); 1066 return; 1067 } 1068 // TLB Invalidate by ASID match, Inner Shareable 1069 case MISCREG_TLBIASIDIS: 1070 { 1071 assert32(tc); 1072 scr = readMiscReg(MISCREG_SCR, tc); 1073 1074 TLBIASID tlbiOp(EL1, 1075 haveSecurity && !scr.ns, 1076 bits(newVal, 7,0)); 1077 1078 tlbiOp.broadcast(tc); 1079 return; 1080 } 1081 // mcr tlbimvaal(is) is invalidating all matching entries 1082 // regardless of the level of lookup, since in gem5 we cache 1083 // in the tlb the last level of lookup only. 1084 // TLB Invalidate by VA, All ASID 1085 case MISCREG_TLBIMVAA: 1086 case MISCREG_TLBIMVAAL: 1087 { 1088 assert32(tc); 1089 scr = readMiscReg(MISCREG_SCR, tc); 1090 1091 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1092 mbits(newVal, 31,12), false); 1093 1094 tlbiOp(tc); 1095 return; 1096 } 1097 // TLB Invalidate by VA, All ASID, Inner Shareable 1098 case MISCREG_TLBIMVAAIS: 1099 case MISCREG_TLBIMVAALIS: 1100 { 1101 assert32(tc); 1102 scr = readMiscReg(MISCREG_SCR, tc); 1103 1104 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1105 mbits(newVal, 31,12), false); 1106 1107 tlbiOp.broadcast(tc); 1108 return; 1109 } 1110 // mcr tlbimvalh(is) is invalidating all matching entries 1111 // regardless of the level of lookup, since in gem5 we cache 1112 // in the tlb the last level of lookup only. 1113 // TLB Invalidate by VA, Hyp mode 1114 case MISCREG_TLBIMVAH: 1115 case MISCREG_TLBIMVALH: 1116 { 1117 assert32(tc); 1118 scr = readMiscReg(MISCREG_SCR, tc); 1119 1120 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1121 mbits(newVal, 31,12), true); 1122 1123 tlbiOp(tc); 1124 return; 1125 } 1126 // TLB Invalidate by VA, Hyp mode, Inner Shareable 1127 case MISCREG_TLBIMVAHIS: 1128 case MISCREG_TLBIMVALHIS: 1129 { 1130 assert32(tc); 1131 scr = readMiscReg(MISCREG_SCR, tc); 1132 1133 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1134 mbits(newVal, 31,12), true); 1135 1136 tlbiOp.broadcast(tc); 1137 return; 1138 } 1139 // mcr tlbiipas2l(is) is invalidating all matching entries 1140 // regardless of the level of lookup, since in gem5 we cache 1141 // in the tlb the last level of lookup only. 1142 // TLB Invalidate by Intermediate Physical Address, Stage 2 1143 case MISCREG_TLBIIPAS2: 1144 case MISCREG_TLBIIPAS2L: 1145 { 1146 assert32(tc); 1147 scr = readMiscReg(MISCREG_SCR, tc); 1148 1149 TLBIIPA tlbiOp(EL1, 1150 haveSecurity && !scr.ns, 1151 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1152 1153 tlbiOp(tc); 1154 return; 1155 } 1156 // TLB Invalidate by Intermediate Physical Address, Stage 2, 1157 // Inner Shareable 1158 case MISCREG_TLBIIPAS2IS: 1159 case MISCREG_TLBIIPAS2LIS: 1160 { 1161 assert32(tc); 1162 scr = readMiscReg(MISCREG_SCR, tc); 1163 1164 TLBIIPA tlbiOp(EL1, 1165 haveSecurity && !scr.ns, 1166 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1167 1168 tlbiOp.broadcast(tc); 1169 return; 1170 } 1171 // Instruction TLB Invalidate by VA 1172 case MISCREG_ITLBIMVA: 1173 { 1174 assert32(tc); 1175 scr = readMiscReg(MISCREG_SCR, tc); 1176 1177 ITLBIMVA tlbiOp(EL1, 1178 haveSecurity && !scr.ns, 1179 mbits(newVal, 31, 12), 1180 bits(newVal, 7,0)); 1181 1182 tlbiOp(tc); 1183 return; 1184 } 1185 // Data TLB Invalidate by VA 1186 case MISCREG_DTLBIMVA: 1187 { 1188 assert32(tc); 1189 scr = readMiscReg(MISCREG_SCR, tc); 1190 1191 DTLBIMVA tlbiOp(EL1, 1192 haveSecurity && !scr.ns, 1193 mbits(newVal, 31, 12), 1194 bits(newVal, 7,0)); 1195 1196 tlbiOp(tc); 1197 return; 1198 } 1199 // Instruction TLB Invalidate by ASID match 1200 case MISCREG_ITLBIASID: 1201 { 1202 assert32(tc); 1203 scr = readMiscReg(MISCREG_SCR, tc); 1204 1205 ITLBIASID tlbiOp(EL1, 1206 haveSecurity && !scr.ns, 1207 bits(newVal, 7,0)); 1208 1209 tlbiOp(tc); 1210 return; 1211 } 1212 // Data TLB Invalidate by ASID match 1213 case MISCREG_DTLBIASID: 1214 { 1215 assert32(tc); 1216 scr = readMiscReg(MISCREG_SCR, tc); 1217 1218 DTLBIASID tlbiOp(EL1, 1219 haveSecurity && !scr.ns, 1220 bits(newVal, 7,0)); 1221 1222 tlbiOp(tc); 1223 return; 1224 } 1225 // TLB Invalidate All, Non-Secure Non-Hyp 1226 case MISCREG_TLBIALLNSNH: 1227 { 1228 assert32(tc); 1229 1230 TLBIALLN tlbiOp(EL1, false); 1231 tlbiOp(tc); 1232 return; 1233 } 1234 // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable 1235 case MISCREG_TLBIALLNSNHIS: 1236 { 1237 assert32(tc); 1238 1239 TLBIALLN tlbiOp(EL1, false); 1240 tlbiOp.broadcast(tc); 1241 return; 1242 } 1243 // TLB Invalidate All, Hyp mode 1244 case MISCREG_TLBIALLH: 1245 { 1246 assert32(tc); 1247 1248 TLBIALLN tlbiOp(EL1, true); 1249 tlbiOp(tc); 1250 return; 1251 } 1252 // TLB Invalidate All, Hyp mode, Inner Shareable 1253 case MISCREG_TLBIALLHIS: 1254 { 1255 assert32(tc); 1256 1257 TLBIALLN tlbiOp(EL1, true); 1258 tlbiOp.broadcast(tc); 1259 return; 1260 } 1261 // AArch64 TLB Invalidate All, EL3 1262 case MISCREG_TLBI_ALLE3: 1263 { 1264 assert64(tc); 1265 1266 TLBIALL tlbiOp(EL3, true); 1267 tlbiOp(tc); 1268 return; 1269 } 1270 // AArch64 TLB Invalidate All, EL3, Inner Shareable 1271 case MISCREG_TLBI_ALLE3IS: 1272 { 1273 assert64(tc); 1274 1275 TLBIALL tlbiOp(EL3, true); 1276 tlbiOp.broadcast(tc); 1277 return; 1278 } 1279 // @todo: uncomment this to enable Virtualization 1280 // case MISCREG_TLBI_ALLE2IS: 1281 // case MISCREG_TLBI_ALLE2: 1282 // AArch64 TLB Invalidate All, EL1 1283 case MISCREG_TLBI_ALLE1: 1284 case MISCREG_TLBI_VMALLE1: 1285 case MISCREG_TLBI_VMALLS12E1: 1286 // @todo: handle VMID and stage 2 to enable Virtualization 1287 { 1288 assert64(tc); 1289 scr = readMiscReg(MISCREG_SCR, tc); 1290 1291 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1292 tlbiOp(tc); 1293 return; 1294 } 1295 // AArch64 TLB Invalidate All, EL1, Inner Shareable 1296 case MISCREG_TLBI_ALLE1IS: 1297 case MISCREG_TLBI_VMALLE1IS: 1298 case MISCREG_TLBI_VMALLS12E1IS: 1299 // @todo: handle VMID and stage 2 to enable Virtualization 1300 { 1301 assert64(tc); 1302 scr = readMiscReg(MISCREG_SCR, tc); 1303 1304 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1305 tlbiOp.broadcast(tc); 1306 return; 1307 } 1308 // VAEx(IS) and VALEx(IS) are the same because TLBs 1309 // only store entries 1310 // from the last level of translation table walks 1311 // @todo: handle VMID to enable Virtualization 1312 // AArch64 TLB Invalidate by VA, EL3 1313 case MISCREG_TLBI_VAE3_Xt: 1314 case MISCREG_TLBI_VALE3_Xt: 1315 { 1316 assert64(tc); 1317 1318 TLBIMVA tlbiOp(EL3, true, 1319 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1320 0xbeef); 1321 tlbiOp(tc); 1322 return; 1323 } 1324 // AArch64 TLB Invalidate by VA, EL3, Inner Shareable 1325 case MISCREG_TLBI_VAE3IS_Xt: 1326 case MISCREG_TLBI_VALE3IS_Xt: 1327 { 1328 assert64(tc); 1329 1330 TLBIMVA tlbiOp(EL3, true, 1331 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1332 0xbeef); 1333 1334 tlbiOp.broadcast(tc); 1335 return; 1336 } 1337 // AArch64 TLB Invalidate by VA, EL2 1338 case MISCREG_TLBI_VAE2_Xt: 1339 case MISCREG_TLBI_VALE2_Xt: 1340 { 1341 assert64(tc); 1342 scr = readMiscReg(MISCREG_SCR, tc); 1343 1344 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1345 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1346 0xbeef); 1347 tlbiOp(tc); 1348 return; 1349 } 1350 // AArch64 TLB Invalidate by VA, EL2, Inner Shareable 1351 case MISCREG_TLBI_VAE2IS_Xt: 1352 case MISCREG_TLBI_VALE2IS_Xt: 1353 { 1354 assert64(tc); 1355 scr = readMiscReg(MISCREG_SCR, tc); 1356 1357 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1358 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1359 0xbeef); 1360 1361 tlbiOp.broadcast(tc); 1362 return; 1363 } 1364 // AArch64 TLB Invalidate by VA, EL1 1365 case MISCREG_TLBI_VAE1_Xt: 1366 case MISCREG_TLBI_VALE1_Xt: 1367 { 1368 assert64(tc); 1369 scr = readMiscReg(MISCREG_SCR, tc); 1370 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1371 bits(newVal, 55, 48); 1372 1373 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1374 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1375 asid); 1376 1377 tlbiOp(tc); 1378 return; 1379 } 1380 // AArch64 TLB Invalidate by VA, EL1, Inner Shareable 1381 case MISCREG_TLBI_VAE1IS_Xt: 1382 case MISCREG_TLBI_VALE1IS_Xt: 1383 { 1384 assert64(tc); 1385 scr = readMiscReg(MISCREG_SCR, tc); 1386 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1387 bits(newVal, 55, 48); 1388 1389 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1390 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1391 asid); 1392 1393 tlbiOp.broadcast(tc); 1394 return; 1395 } 1396 // AArch64 TLB Invalidate by ASID, EL1 1397 // @todo: handle VMID to enable Virtualization 1398 case MISCREG_TLBI_ASIDE1_Xt: 1399 { 1400 assert64(tc); 1401 scr = readMiscReg(MISCREG_SCR, tc); 1402 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1403 bits(newVal, 55, 48); 1404 1405 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1406 tlbiOp(tc); 1407 return; 1408 } 1409 // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable 1410 case MISCREG_TLBI_ASIDE1IS_Xt: 1411 { 1412 assert64(tc); 1413 scr = readMiscReg(MISCREG_SCR, tc); 1414 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1415 bits(newVal, 55, 48); 1416 1417 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1418 tlbiOp.broadcast(tc); 1419 return; 1420 } 1421 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 1422 // entries from the last level of translation table walks 1423 // AArch64 TLB Invalidate by VA, All ASID, EL1 1424 case MISCREG_TLBI_VAAE1_Xt: 1425 case MISCREG_TLBI_VAALE1_Xt: 1426 { 1427 assert64(tc); 1428 scr = readMiscReg(MISCREG_SCR, tc); 1429 1430 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1431 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 1432 1433 tlbiOp(tc); 1434 return; 1435 } 1436 // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable 1437 case MISCREG_TLBI_VAAE1IS_Xt: 1438 case MISCREG_TLBI_VAALE1IS_Xt: 1439 { 1440 assert64(tc); 1441 scr = readMiscReg(MISCREG_SCR, tc); 1442 1443 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1444 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 1445 1446 tlbiOp.broadcast(tc); 1447 return; 1448 } 1449 // AArch64 TLB Invalidate by Intermediate Physical Address, 1450 // Stage 2, EL1 1451 case MISCREG_TLBI_IPAS2E1_Xt: 1452 case MISCREG_TLBI_IPAS2LE1_Xt: 1453 { 1454 assert64(tc); 1455 scr = readMiscReg(MISCREG_SCR, tc); 1456 1457 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1458 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1459 1460 tlbiOp(tc); 1461 return; 1462 } 1463 // AArch64 TLB Invalidate by Intermediate Physical Address, 1464 // Stage 2, EL1, Inner Shareable 1465 case MISCREG_TLBI_IPAS2E1IS_Xt: 1466 case MISCREG_TLBI_IPAS2LE1IS_Xt: 1467 { 1468 assert64(tc); 1469 scr = readMiscReg(MISCREG_SCR, tc); 1470 1471 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1472 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1473 1474 tlbiOp.broadcast(tc); 1475 return; 1476 } 1477 case MISCREG_ACTLR: 1478 warn("Not doing anything for write of miscreg ACTLR\n"); 1479 break; 1480 1481 case MISCREG_PMXEVTYPER_PMCCFILTR: 1482 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 1483 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 1484 case MISCREG_PMCR ... MISCREG_PMOVSSET: 1485 pmu->setMiscReg(misc_reg, newVal); 1486 break; 1487 1488 1489 case MISCREG_HSTR: // TJDBX, now redifined to be RES0 1490 { 1491 HSTR hstrMask = 0; 1492 hstrMask.tjdbx = 1; 1493 newVal &= ~((uint32_t) hstrMask); 1494 break; 1495 } 1496 case MISCREG_HCPTR: 1497 { 1498 // If a CP bit in NSACR is 0 then the corresponding bit in 1499 // HCPTR is RAO/WI. Same applies to NSASEDIS 1500 secure_lookup = haveSecurity && 1501 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 1502 readMiscRegNoEffect(MISCREG_CPSR)); 1503 if (!secure_lookup) { 1504 MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 1505 MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 1506 newVal = (newVal & ~mask) | (oldValue & mask); 1507 } 1508 break; 1509 } 1510 case MISCREG_HDFAR: // alias for secure DFAR 1511 misc_reg = MISCREG_DFAR_S; 1512 break; 1513 case MISCREG_HIFAR: // alias for secure IFAR 1514 misc_reg = MISCREG_IFAR_S; 1515 break; 1516 case MISCREG_ATS1CPR: 1517 case MISCREG_ATS1CPW: 1518 case MISCREG_ATS1CUR: 1519 case MISCREG_ATS1CUW: 1520 case MISCREG_ATS12NSOPR: 1521 case MISCREG_ATS12NSOPW: 1522 case MISCREG_ATS12NSOUR: 1523 case MISCREG_ATS12NSOUW: 1524 case MISCREG_ATS1HR: 1525 case MISCREG_ATS1HW: 1526 { 1527 Request::Flags flags = 0; 1528 BaseTLB::Mode mode = BaseTLB::Read; 1529 TLB::ArmTranslationType tranType = TLB::NormalTran; 1530 Fault fault; 1531 switch(misc_reg) { 1532 case MISCREG_ATS1CPR: 1533 flags = TLB::MustBeOne; 1534 tranType = TLB::S1CTran; 1535 mode = BaseTLB::Read; 1536 break; 1537 case MISCREG_ATS1CPW: 1538 flags = TLB::MustBeOne; 1539 tranType = TLB::S1CTran; 1540 mode = BaseTLB::Write; 1541 break; 1542 case MISCREG_ATS1CUR: 1543 flags = TLB::MustBeOne | TLB::UserMode; 1544 tranType = TLB::S1CTran; 1545 mode = BaseTLB::Read; 1546 break; 1547 case MISCREG_ATS1CUW: 1548 flags = TLB::MustBeOne | TLB::UserMode; 1549 tranType = TLB::S1CTran; 1550 mode = BaseTLB::Write; 1551 break; 1552 case MISCREG_ATS12NSOPR: 1553 if (!haveSecurity) 1554 panic("Security Extensions required for ATS12NSOPR"); 1555 flags = TLB::MustBeOne; 1556 tranType = TLB::S1S2NsTran; 1557 mode = BaseTLB::Read; 1558 break; 1559 case MISCREG_ATS12NSOPW: 1560 if (!haveSecurity) 1561 panic("Security Extensions required for ATS12NSOPW"); 1562 flags = TLB::MustBeOne; 1563 tranType = TLB::S1S2NsTran; 1564 mode = BaseTLB::Write; 1565 break; 1566 case MISCREG_ATS12NSOUR: 1567 if (!haveSecurity) 1568 panic("Security Extensions required for ATS12NSOUR"); 1569 flags = TLB::MustBeOne | TLB::UserMode; 1570 tranType = TLB::S1S2NsTran; 1571 mode = BaseTLB::Read; 1572 break; 1573 case MISCREG_ATS12NSOUW: 1574 if (!haveSecurity) 1575 panic("Security Extensions required for ATS12NSOUW"); 1576 flags = TLB::MustBeOne | TLB::UserMode; 1577 tranType = TLB::S1S2NsTran; 1578 mode = BaseTLB::Write; 1579 break; 1580 case MISCREG_ATS1HR: // only really useful from secure mode. 1581 flags = TLB::MustBeOne; 1582 tranType = TLB::HypMode; 1583 mode = BaseTLB::Read; 1584 break; 1585 case MISCREG_ATS1HW: 1586 flags = TLB::MustBeOne; 1587 tranType = TLB::HypMode; 1588 mode = BaseTLB::Write; 1589 break; 1590 } 1591 // If we're in timing mode then doing the translation in 1592 // functional mode then we're slightly distorting performance 1593 // results obtained from simulations. The translation should be 1594 // done in the same mode the core is running in. NOTE: This 1595 // can't be an atomic translation because that causes problems 1596 // with unexpected atomic snoop requests. 1597 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1598 1599 auto req = std::make_shared<Request>( 1600 0, val, 0, flags, Request::funcMasterId, 1601 tc->pcState().pc(), tc->contextId()); 1602 1603 fault = getDTBPtr(tc)->translateFunctional( 1604 req, tc, mode, tranType); 1605 1606 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1607 HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 1608 1609 MiscReg newVal; 1610 if (fault == NoFault) { 1611 Addr paddr = req->getPaddr(); 1612 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 1613 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 1614 newVal = (paddr & mask(39, 12)) | 1615 (getDTBPtr(tc)->getAttr()); 1616 } else { 1617 newVal = (paddr & 0xfffff000) | 1618 (getDTBPtr(tc)->getAttr()); 1619 } 1620 DPRINTF(MiscRegs, 1621 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 1622 val, newVal); 1623 } else { 1624 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1625 armFault->update(tc); 1626 // Set fault bit and FSR 1627 FSR fsr = armFault->getFsr(tc); 1628 1629 newVal = ((fsr >> 9) & 1) << 11; 1630 if (newVal) { 1631 // LPAE - rearange fault status 1632 newVal |= ((fsr >> 0) & 0x3f) << 1; 1633 } else { 1634 // VMSA - rearange fault status 1635 newVal |= ((fsr >> 0) & 0xf) << 1; 1636 newVal |= ((fsr >> 10) & 0x1) << 5; 1637 newVal |= ((fsr >> 12) & 0x1) << 6; 1638 } 1639 newVal |= 0x1; // F bit 1640 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1641 newVal |= armFault->isStage2() ? 0x200 : 0; 1642 DPRINTF(MiscRegs, 1643 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 1644 val, fsr, newVal); 1645 } 1646 setMiscRegNoEffect(MISCREG_PAR, newVal); 1647 return; 1648 } 1649 case MISCREG_TTBCR: 1650 { 1651 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1652 const uint32_t ones = (uint32_t)(-1); 1653 TTBCR ttbcrMask = 0; 1654 TTBCR ttbcrNew = newVal; 1655 1656 // ARM DDI 0406C.b, ARMv7-32 1657 ttbcrMask.n = ones; // T0SZ 1658 if (haveSecurity) { 1659 ttbcrMask.pd0 = ones; 1660 ttbcrMask.pd1 = ones; 1661 } 1662 ttbcrMask.epd0 = ones; 1663 ttbcrMask.irgn0 = ones; 1664 ttbcrMask.orgn0 = ones; 1665 ttbcrMask.sh0 = ones; 1666 ttbcrMask.ps = ones; // T1SZ 1667 ttbcrMask.a1 = ones; 1668 ttbcrMask.epd1 = ones; 1669 ttbcrMask.irgn1 = ones; 1670 ttbcrMask.orgn1 = ones; 1671 ttbcrMask.sh1 = ones; 1672 if (haveLPAE) 1673 ttbcrMask.eae = ones; 1674 1675 if (haveLPAE && ttbcrNew.eae) { 1676 newVal = newVal & ttbcrMask; 1677 } else { 1678 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 1679 } 1680 // Invalidate TLB MiscReg 1681 getITBPtr(tc)->invalidateMiscReg(); 1682 getDTBPtr(tc)->invalidateMiscReg(); 1683 break; 1684 } 1685 case MISCREG_TTBR0: 1686 case MISCREG_TTBR1: 1687 { 1688 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1689 if (haveLPAE) { 1690 if (ttbcr.eae) { 1691 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 1692 // ARMv8 AArch32 bit 63-56 only 1693 uint64_t ttbrMask = mask(63,56) | mask(47,40); 1694 newVal = (newVal & (~ttbrMask)); 1695 } 1696 } 1697 // Invalidate TLB MiscReg 1698 getITBPtr(tc)->invalidateMiscReg(); 1699 getDTBPtr(tc)->invalidateMiscReg(); 1700 break; 1701 } 1702 case MISCREG_SCTLR_EL1: 1703 case MISCREG_CONTEXTIDR: 1704 case MISCREG_PRRR: 1705 case MISCREG_NMRR: 1706 case MISCREG_MAIR0: 1707 case MISCREG_MAIR1: 1708 case MISCREG_DACR: 1709 case MISCREG_VTTBR: 1710 case MISCREG_SCR_EL3: 1711 case MISCREG_HCR_EL2: 1712 case MISCREG_TCR_EL1: 1713 case MISCREG_TCR_EL2: 1714 case MISCREG_TCR_EL3: 1715 case MISCREG_SCTLR_EL2: 1716 case MISCREG_SCTLR_EL3: 1717 case MISCREG_HSCTLR: 1718 case MISCREG_TTBR0_EL1: 1719 case MISCREG_TTBR1_EL1: 1720 case MISCREG_TTBR0_EL2: 1721 case MISCREG_TTBR1_EL2: 1722 case MISCREG_TTBR0_EL3: 1723 getITBPtr(tc)->invalidateMiscReg(); 1724 getDTBPtr(tc)->invalidateMiscReg(); 1725 break; 1726 case MISCREG_NZCV: 1727 { 1728 CPSR cpsr = val; 1729 1730 tc->setCCReg(CCREG_NZ, cpsr.nz); 1731 tc->setCCReg(CCREG_C, cpsr.c); 1732 tc->setCCReg(CCREG_V, cpsr.v); 1733 } 1734 break; 1735 case MISCREG_DAIF: 1736 { 1737 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1738 cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 1739 newVal = cpsr; 1740 misc_reg = MISCREG_CPSR; 1741 } 1742 break; 1743 case MISCREG_SP_EL0: 1744 tc->setIntReg(INTREG_SP0, newVal); 1745 break; 1746 case MISCREG_SP_EL1: 1747 tc->setIntReg(INTREG_SP1, newVal); 1748 break; 1749 case MISCREG_SP_EL2: 1750 tc->setIntReg(INTREG_SP2, newVal); 1751 break; 1752 case MISCREG_SPSEL: 1753 { 1754 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1755 cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 1756 newVal = cpsr; 1757 misc_reg = MISCREG_CPSR; 1758 } 1759 break; 1760 case MISCREG_CURRENTEL: 1761 { 1762 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1763 cpsr.el = (uint8_t) ((CPSR) newVal).el; 1764 newVal = cpsr; 1765 misc_reg = MISCREG_CPSR; 1766 } 1767 break; 1768 case MISCREG_AT_S1E1R_Xt: 1769 case MISCREG_AT_S1E1W_Xt: 1770 case MISCREG_AT_S1E0R_Xt: 1771 case MISCREG_AT_S1E0W_Xt: 1772 case MISCREG_AT_S1E2R_Xt: 1773 case MISCREG_AT_S1E2W_Xt: 1774 case MISCREG_AT_S12E1R_Xt: 1775 case MISCREG_AT_S12E1W_Xt: 1776 case MISCREG_AT_S12E0R_Xt: 1777 case MISCREG_AT_S12E0W_Xt: 1778 case MISCREG_AT_S1E3R_Xt: 1779 case MISCREG_AT_S1E3W_Xt: 1780 { 1781 RequestPtr req = std::make_shared<Request>(); 1782 Request::Flags flags = 0; 1783 BaseTLB::Mode mode = BaseTLB::Read; 1784 TLB::ArmTranslationType tranType = TLB::NormalTran; 1785 Fault fault; 1786 switch(misc_reg) { 1787 case MISCREG_AT_S1E1R_Xt: 1788 flags = TLB::MustBeOne; 1789 tranType = TLB::S1E1Tran; 1790 mode = BaseTLB::Read; 1791 break; 1792 case MISCREG_AT_S1E1W_Xt: 1793 flags = TLB::MustBeOne; 1794 tranType = TLB::S1E1Tran; 1795 mode = BaseTLB::Write; 1796 break; 1797 case MISCREG_AT_S1E0R_Xt: 1798 flags = TLB::MustBeOne | TLB::UserMode; 1799 tranType = TLB::S1E0Tran; 1800 mode = BaseTLB::Read; 1801 break; 1802 case MISCREG_AT_S1E0W_Xt: 1803 flags = TLB::MustBeOne | TLB::UserMode; 1804 tranType = TLB::S1E0Tran; 1805 mode = BaseTLB::Write; 1806 break; 1807 case MISCREG_AT_S1E2R_Xt: 1808 flags = TLB::MustBeOne; 1809 tranType = TLB::S1E2Tran; 1810 mode = BaseTLB::Read; 1811 break; 1812 case MISCREG_AT_S1E2W_Xt: 1813 flags = TLB::MustBeOne; 1814 tranType = TLB::S1E2Tran; 1815 mode = BaseTLB::Write; 1816 break; 1817 case MISCREG_AT_S12E0R_Xt: 1818 flags = TLB::MustBeOne | TLB::UserMode; 1819 tranType = TLB::S12E0Tran; 1820 mode = BaseTLB::Read; 1821 break; 1822 case MISCREG_AT_S12E0W_Xt: 1823 flags = TLB::MustBeOne | TLB::UserMode; 1824 tranType = TLB::S12E0Tran; 1825 mode = BaseTLB::Write; 1826 break; 1827 case MISCREG_AT_S12E1R_Xt: 1828 flags = TLB::MustBeOne; 1829 tranType = TLB::S12E1Tran; 1830 mode = BaseTLB::Read; 1831 break; 1832 case MISCREG_AT_S12E1W_Xt: 1833 flags = TLB::MustBeOne; 1834 tranType = TLB::S12E1Tran; 1835 mode = BaseTLB::Write; 1836 break; 1837 case MISCREG_AT_S1E3R_Xt: 1838 flags = TLB::MustBeOne; 1839 tranType = TLB::S1E3Tran; 1840 mode = BaseTLB::Read; 1841 break; 1842 case MISCREG_AT_S1E3W_Xt: 1843 flags = TLB::MustBeOne; 1844 tranType = TLB::S1E3Tran; 1845 mode = BaseTLB::Write; 1846 break; 1847 } 1848 // If we're in timing mode then doing the translation in 1849 // functional mode then we're slightly distorting performance 1850 // results obtained from simulations. The translation should be 1851 // done in the same mode the core is running in. NOTE: This 1852 // can't be an atomic translation because that causes problems 1853 // with unexpected atomic snoop requests. 1854 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1855 req->setVirt(0, val, 0, flags, Request::funcMasterId, 1856 tc->pcState().pc()); 1857 req->setContext(tc->contextId()); 1858 fault = getDTBPtr(tc)->translateFunctional(req, tc, mode, 1859 tranType); 1860 1861 MiscReg newVal; 1862 if (fault == NoFault) { 1863 Addr paddr = req->getPaddr(); 1864 uint64_t attr = getDTBPtr(tc)->getAttr(); 1865 uint64_t attr1 = attr >> 56; 1866 if (!attr1 || attr1 ==0x44) { 1867 attr |= 0x100; 1868 attr &= ~ uint64_t(0x80); 1869 } 1870 newVal = (paddr & mask(47, 12)) | attr; 1871 DPRINTF(MiscRegs, 1872 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 1873 val, newVal); 1874 } else { 1875 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1876 armFault->update(tc); 1877 // Set fault bit and FSR 1878 FSR fsr = armFault->getFsr(tc); 1879 1880 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1881 if (cpsr.width) { // AArch32 1882 newVal = ((fsr >> 9) & 1) << 11; 1883 // rearrange fault status 1884 newVal |= ((fsr >> 0) & 0x3f) << 1; 1885 newVal |= 0x1; // F bit 1886 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1887 newVal |= armFault->isStage2() ? 0x200 : 0; 1888 } else { // AArch64 1889 newVal = 1; // F bit 1890 newVal |= fsr << 1; // FST 1891 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit. 1892 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 1893 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 1894 newVal |= 1 << 11; // RES1 1895 } 1896 DPRINTF(MiscRegs, 1897 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 1898 val, fsr, newVal); 1899 } 1900 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 1901 return; 1902 } 1903 case MISCREG_SPSR_EL3: 1904 case MISCREG_SPSR_EL2: 1905 case MISCREG_SPSR_EL1: 1906 // Force bits 23:21 to 0 1907 newVal = val & ~(0x7 << 21); 1908 break; 1909 case MISCREG_L2CTLR: 1910 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 1911 miscRegName[misc_reg], uint32_t(val)); 1912 break; 1913 1914 // Generic Timer registers 1915 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 1916 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 1917 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 1918 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 1919 getGenericTimer(tc).setMiscReg(misc_reg, newVal); 1920 break; 1921 } 1922 } 1923 setMiscRegNoEffect(misc_reg, newVal); 1924} 1925 1926BaseISADevice & 1927ISA::getGenericTimer(ThreadContext *tc) 1928{ 1929 // We only need to create an ISA interface the first time we try 1930 // to access the timer. 1931 if (timer) 1932 return *timer.get(); 1933 1934 assert(system); 1935 GenericTimer *generic_timer(system->getGenericTimer()); 1936 if (!generic_timer) { 1937 panic("Trying to get a generic timer from a system that hasn't " 1938 "been configured to use a generic timer.\n"); 1939 } 1940 1941 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 1942 return *timer.get(); 1943} 1944 1945} 1946 1947ArmISA::ISA * 1948ArmISAParams::create() 1949{ 1950 return new ArmISA::ISA(this); 1951} 1952