isa.cc revision 12671:2a9f13f15e91
1/* 2 * Copyright (c) 2010-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 */ 40 41#include "arch/arm/isa.hh" 42#include "arch/arm/pmu.hh" 43#include "arch/arm/system.hh" 44#include "arch/arm/tlb.hh" 45#include "arch/arm/tlbi_op.hh" 46#include "cpu/base.hh" 47#include "cpu/checker/cpu.hh" 48#include "debug/Arm.hh" 49#include "debug/MiscRegs.hh" 50#include "dev/arm/generic_timer.hh" 51#include "params/ArmISA.hh" 52#include "sim/faults.hh" 53#include "sim/stat_control.hh" 54#include "sim/system.hh" 55 56namespace ArmISA 57{ 58 59ISA::ISA(Params *p) 60 : SimObject(p), 61 system(NULL), 62 _decoderFlavour(p->decoderFlavour), 63 _vecRegRenameMode(p->vecRegRenameMode), 64 pmu(p->pmu) 65{ 66 miscRegs[MISCREG_SCTLR_RST] = 0; 67 68 // Hook up a dummy device if we haven't been configured with a 69 // real PMU. By using a dummy device, we don't need to check that 70 // the PMU exist every time we try to access a PMU register. 71 if (!pmu) 72 pmu = &dummyDevice; 73 74 // Give all ISA devices a pointer to this ISA 75 pmu->setISA(this); 76 77 system = dynamic_cast<ArmSystem *>(p->system); 78 79 // Cache system-level properties 80 if (FullSystem && system) { 81 highestELIs64 = system->highestELIs64(); 82 haveSecurity = system->haveSecurity(); 83 haveLPAE = system->haveLPAE(); 84 haveVirtualization = system->haveVirtualization(); 85 haveLargeAsid64 = system->haveLargeAsid64(); 86 physAddrRange64 = system->physAddrRange64(); 87 } else { 88 highestELIs64 = true; // ArmSystem::highestELIs64 does the same 89 haveSecurity = haveLPAE = haveVirtualization = false; 90 haveLargeAsid64 = false; 91 physAddrRange64 = 32; // dummy value 92 } 93 94 initializeMiscRegMetadata(); 95 preUnflattenMiscReg(); 96 97 clear(); 98} 99 100std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS); 101 102const ArmISAParams * 103ISA::params() const 104{ 105 return dynamic_cast<const Params *>(_params); 106} 107 108void 109ISA::clear() 110{ 111 const Params *p(params()); 112 113 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 114 memset(miscRegs, 0, sizeof(miscRegs)); 115 116 // Initialize configurable default values 117 miscRegs[MISCREG_MIDR] = p->midr; 118 miscRegs[MISCREG_MIDR_EL1] = p->midr; 119 miscRegs[MISCREG_VPIDR] = p->midr; 120 121 if (FullSystem && system->highestELIs64()) { 122 // Initialize AArch64 state 123 clear64(p); 124 return; 125 } 126 127 // Initialize AArch32 state... 128 129 CPSR cpsr = 0; 130 cpsr.mode = MODE_USER; 131 miscRegs[MISCREG_CPSR] = cpsr; 132 updateRegMap(cpsr); 133 134 SCTLR sctlr = 0; 135 sctlr.te = (bool) sctlr_rst.te; 136 sctlr.nmfi = (bool) sctlr_rst.nmfi; 137 sctlr.v = (bool) sctlr_rst.v; 138 sctlr.u = 1; 139 sctlr.xp = 1; 140 sctlr.rao2 = 1; 141 sctlr.rao3 = 1; 142 sctlr.rao4 = 0xf; // SCTLR[6:3] 143 sctlr.uci = 1; 144 sctlr.dze = 1; 145 miscRegs[MISCREG_SCTLR_NS] = sctlr; 146 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 147 miscRegs[MISCREG_HCPTR] = 0; 148 149 // Start with an event in the mailbox 150 miscRegs[MISCREG_SEV_MAILBOX] = 1; 151 152 // Separate Instruction and Data TLBs 153 miscRegs[MISCREG_TLBTR] = 1; 154 155 MVFR0 mvfr0 = 0; 156 mvfr0.advSimdRegisters = 2; 157 mvfr0.singlePrecision = 2; 158 mvfr0.doublePrecision = 2; 159 mvfr0.vfpExceptionTrapping = 0; 160 mvfr0.divide = 1; 161 mvfr0.squareRoot = 1; 162 mvfr0.shortVectors = 1; 163 mvfr0.roundingModes = 1; 164 miscRegs[MISCREG_MVFR0] = mvfr0; 165 166 MVFR1 mvfr1 = 0; 167 mvfr1.flushToZero = 1; 168 mvfr1.defaultNaN = 1; 169 mvfr1.advSimdLoadStore = 1; 170 mvfr1.advSimdInteger = 1; 171 mvfr1.advSimdSinglePrecision = 1; 172 mvfr1.advSimdHalfPrecision = 1; 173 mvfr1.vfpHalfPrecision = 1; 174 miscRegs[MISCREG_MVFR1] = mvfr1; 175 176 // Reset values of PRRR and NMRR are implementation dependent 177 178 // @todo: PRRR and NMRR in secure state? 179 miscRegs[MISCREG_PRRR_NS] = 180 (1 << 19) | // 19 181 (0 << 18) | // 18 182 (0 << 17) | // 17 183 (1 << 16) | // 16 184 (2 << 14) | // 15:14 185 (0 << 12) | // 13:12 186 (2 << 10) | // 11:10 187 (2 << 8) | // 9:8 188 (2 << 6) | // 7:6 189 (2 << 4) | // 5:4 190 (1 << 2) | // 3:2 191 0; // 1:0 192 miscRegs[MISCREG_NMRR_NS] = 193 (1 << 30) | // 31:30 194 (0 << 26) | // 27:26 195 (0 << 24) | // 25:24 196 (3 << 22) | // 23:22 197 (2 << 20) | // 21:20 198 (0 << 18) | // 19:18 199 (0 << 16) | // 17:16 200 (1 << 14) | // 15:14 201 (0 << 12) | // 13:12 202 (2 << 10) | // 11:10 203 (0 << 8) | // 9:8 204 (3 << 6) | // 7:6 205 (2 << 4) | // 5:4 206 (0 << 2) | // 3:2 207 0; // 1:0 208 209 miscRegs[MISCREG_CPACR] = 0; 210 211 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 212 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 213 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 214 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 215 216 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 217 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 218 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 219 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 220 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 221 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 222 223 miscRegs[MISCREG_FPSID] = p->fpsid; 224 225 if (haveLPAE) { 226 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 227 ttbcr.eae = 0; 228 miscRegs[MISCREG_TTBCR_NS] = ttbcr; 229 // Enforce consistency with system-level settings 230 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 231 } 232 233 if (haveSecurity) { 234 miscRegs[MISCREG_SCTLR_S] = sctlr; 235 miscRegs[MISCREG_SCR] = 0; 236 miscRegs[MISCREG_VBAR_S] = 0; 237 } else { 238 // we're always non-secure 239 miscRegs[MISCREG_SCR] = 1; 240 } 241 242 //XXX We need to initialize the rest of the state. 243} 244 245void 246ISA::clear64(const ArmISAParams *p) 247{ 248 CPSR cpsr = 0; 249 Addr rvbar = system->resetAddr64(); 250 switch (system->highestEL()) { 251 // Set initial EL to highest implemented EL using associated stack 252 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 253 // value 254 case EL3: 255 cpsr.mode = MODE_EL3H; 256 miscRegs[MISCREG_RVBAR_EL3] = rvbar; 257 break; 258 case EL2: 259 cpsr.mode = MODE_EL2H; 260 miscRegs[MISCREG_RVBAR_EL2] = rvbar; 261 break; 262 case EL1: 263 cpsr.mode = MODE_EL1H; 264 miscRegs[MISCREG_RVBAR_EL1] = rvbar; 265 break; 266 default: 267 panic("Invalid highest implemented exception level"); 268 break; 269 } 270 271 // Initialize rest of CPSR 272 cpsr.daif = 0xf; // Mask all interrupts 273 cpsr.ss = 0; 274 cpsr.il = 0; 275 miscRegs[MISCREG_CPSR] = cpsr; 276 updateRegMap(cpsr); 277 278 // Initialize other control registers 279 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 280 if (haveSecurity) { 281 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830; 282 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 283 } else if (haveVirtualization) { 284 // also MISCREG_SCTLR_EL2 (by mapping) 285 miscRegs[MISCREG_HSCTLR] = 0x30c50830; 286 } else { 287 // also MISCREG_SCTLR_EL1 (by mapping) 288 miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init 289 // Always non-secure 290 miscRegs[MISCREG_SCR_EL3] = 1; 291 } 292 293 // Initialize configurable id registers 294 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 295 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 296 miscRegs[MISCREG_ID_AA64DFR0_EL1] = 297 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 298 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 299 300 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 301 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 302 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 303 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 304 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 305 306 miscRegs[MISCREG_ID_DFR0_EL1] = 307 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 308 309 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 310 311 // Enforce consistency with system-level settings... 312 313 // EL3 314 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 315 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 316 haveSecurity ? 0x2 : 0x0); 317 // EL2 318 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 319 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 320 haveVirtualization ? 0x2 : 0x0); 321 // Large ASID support 322 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 323 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 324 haveLargeAsid64 ? 0x2 : 0x0); 325 // Physical address size 326 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 327 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 328 encodePhysAddrRange64(physAddrRange64)); 329} 330 331MiscReg 332ISA::readMiscRegNoEffect(int misc_reg) const 333{ 334 assert(misc_reg < NumMiscRegs); 335 336 const auto ® = lookUpMiscReg[misc_reg]; // bit masks 337 const auto &map = getMiscIndices(misc_reg); 338 int lower = map.first, upper = map.second; 339 // NB!: apply architectural masks according to desired register, 340 // despite possibly getting value from different (mapped) register. 341 auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32)) 342 |(miscRegs[upper] << 32)); 343 if (val & reg.res0()) { 344 DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n", 345 miscRegName[misc_reg], val & reg.res0()); 346 } 347 if ((val & reg.res1()) != reg.res1()) { 348 DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n", 349 miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1()); 350 } 351 return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao 352} 353 354 355MiscReg 356ISA::readMiscReg(int misc_reg, ThreadContext *tc) 357{ 358 CPSR cpsr = 0; 359 PCState pc = 0; 360 SCR scr = 0; 361 362 if (misc_reg == MISCREG_CPSR) { 363 cpsr = miscRegs[misc_reg]; 364 pc = tc->pcState(); 365 cpsr.j = pc.jazelle() ? 1 : 0; 366 cpsr.t = pc.thumb() ? 1 : 0; 367 return cpsr; 368 } 369 370#ifndef NDEBUG 371 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 372 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 373 warn("Unimplemented system register %s read.\n", 374 miscRegName[misc_reg]); 375 else 376 panic("Unimplemented system register %s read.\n", 377 miscRegName[misc_reg]); 378 } 379#endif 380 381 switch (unflattenMiscReg(misc_reg)) { 382 case MISCREG_HCR: 383 { 384 if (!haveVirtualization) 385 return 0; 386 else 387 return readMiscRegNoEffect(MISCREG_HCR); 388 } 389 case MISCREG_CPACR: 390 { 391 const uint32_t ones = (uint32_t)(-1); 392 CPACR cpacrMask = 0; 393 // Only cp10, cp11, and ase are implemented, nothing else should 394 // be readable? (straight copy from the write code) 395 cpacrMask.cp10 = ones; 396 cpacrMask.cp11 = ones; 397 cpacrMask.asedis = ones; 398 399 // Security Extensions may limit the readability of CPACR 400 if (haveSecurity) { 401 scr = readMiscRegNoEffect(MISCREG_SCR); 402 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 403 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 404 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 405 // NB: Skipping the full loop, here 406 if (!nsacr.cp10) cpacrMask.cp10 = 0; 407 if (!nsacr.cp11) cpacrMask.cp11 = 0; 408 } 409 } 410 MiscReg val = readMiscRegNoEffect(MISCREG_CPACR); 411 val &= cpacrMask; 412 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 413 miscRegName[misc_reg], val); 414 return val; 415 } 416 case MISCREG_MPIDR: 417 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 418 scr = readMiscRegNoEffect(MISCREG_SCR); 419 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 420 return getMPIDR(system, tc); 421 } else { 422 return readMiscReg(MISCREG_VMPIDR, tc); 423 } 424 break; 425 case MISCREG_MPIDR_EL1: 426 // @todo in the absence of v8 virtualization support just return MPIDR_EL1 427 return getMPIDR(system, tc) & 0xffffffff; 428 case MISCREG_VMPIDR: 429 // top bit defined as RES1 430 return readMiscRegNoEffect(misc_reg) | 0x80000000; 431 case MISCREG_ID_AFR0: // not implemented, so alias MIDR 432 case MISCREG_REVIDR: // not implemented, so alias MIDR 433 case MISCREG_MIDR: 434 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 435 scr = readMiscRegNoEffect(MISCREG_SCR); 436 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 437 return readMiscRegNoEffect(misc_reg); 438 } else { 439 return readMiscRegNoEffect(MISCREG_VPIDR); 440 } 441 break; 442 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 443 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 444 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 445 case MISCREG_AIDR: // AUX ID set to 0 446 case MISCREG_TCMTR: // No TCM's 447 return 0; 448 449 case MISCREG_CLIDR: 450 warn_once("The clidr register always reports 0 caches.\n"); 451 warn_once("clidr LoUIS field of 0b001 to match current " 452 "ARM implementations.\n"); 453 return 0x00200000; 454 case MISCREG_CCSIDR: 455 warn_once("The ccsidr register isn't implemented and " 456 "always reads as 0.\n"); 457 break; 458 case MISCREG_CTR: // AArch32, ARMv7, top bit set 459 case MISCREG_CTR_EL0: // AArch64 460 { 461 //all caches have the same line size in gem5 462 //4 byte words in ARM 463 unsigned lineSizeWords = 464 tc->getSystemPtr()->cacheLineSize() / 4; 465 unsigned log2LineSizeWords = 0; 466 467 while (lineSizeWords >>= 1) { 468 ++log2LineSizeWords; 469 } 470 471 CTR ctr = 0; 472 //log2 of minimun i-cache line size (words) 473 ctr.iCacheLineSize = log2LineSizeWords; 474 //b11 - gem5 uses pipt 475 ctr.l1IndexPolicy = 0x3; 476 //log2 of minimum d-cache line size (words) 477 ctr.dCacheLineSize = log2LineSizeWords; 478 //log2 of max reservation size (words) 479 ctr.erg = log2LineSizeWords; 480 //log2 of max writeback size (words) 481 ctr.cwg = log2LineSizeWords; 482 //b100 - gem5 format is ARMv7 483 ctr.format = 0x4; 484 485 return ctr; 486 } 487 case MISCREG_ACTLR: 488 warn("Not doing anything for miscreg ACTLR\n"); 489 break; 490 491 case MISCREG_PMXEVTYPER_PMCCFILTR: 492 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 493 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 494 case MISCREG_PMCR ... MISCREG_PMOVSSET: 495 return pmu->readMiscReg(misc_reg); 496 497 case MISCREG_CPSR_Q: 498 panic("shouldn't be reading this register seperately\n"); 499 case MISCREG_FPSCR_QC: 500 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 501 case MISCREG_FPSCR_EXC: 502 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 503 case MISCREG_FPSR: 504 { 505 const uint32_t ones = (uint32_t)(-1); 506 FPSCR fpscrMask = 0; 507 fpscrMask.ioc = ones; 508 fpscrMask.dzc = ones; 509 fpscrMask.ofc = ones; 510 fpscrMask.ufc = ones; 511 fpscrMask.ixc = ones; 512 fpscrMask.idc = ones; 513 fpscrMask.qc = ones; 514 fpscrMask.v = ones; 515 fpscrMask.c = ones; 516 fpscrMask.z = ones; 517 fpscrMask.n = ones; 518 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 519 } 520 case MISCREG_FPCR: 521 { 522 const uint32_t ones = (uint32_t)(-1); 523 FPSCR fpscrMask = 0; 524 fpscrMask.len = ones; 525 fpscrMask.stride = ones; 526 fpscrMask.rMode = ones; 527 fpscrMask.fz = ones; 528 fpscrMask.dn = ones; 529 fpscrMask.ahp = ones; 530 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 531 } 532 case MISCREG_NZCV: 533 { 534 CPSR cpsr = 0; 535 cpsr.nz = tc->readCCReg(CCREG_NZ); 536 cpsr.c = tc->readCCReg(CCREG_C); 537 cpsr.v = tc->readCCReg(CCREG_V); 538 return cpsr; 539 } 540 case MISCREG_DAIF: 541 { 542 CPSR cpsr = 0; 543 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 544 return cpsr; 545 } 546 case MISCREG_SP_EL0: 547 { 548 return tc->readIntReg(INTREG_SP0); 549 } 550 case MISCREG_SP_EL1: 551 { 552 return tc->readIntReg(INTREG_SP1); 553 } 554 case MISCREG_SP_EL2: 555 { 556 return tc->readIntReg(INTREG_SP2); 557 } 558 case MISCREG_SPSEL: 559 { 560 return miscRegs[MISCREG_CPSR] & 0x1; 561 } 562 case MISCREG_CURRENTEL: 563 { 564 return miscRegs[MISCREG_CPSR] & 0xc; 565 } 566 case MISCREG_L2CTLR: 567 { 568 // mostly unimplemented, just set NumCPUs field from sim and return 569 L2CTLR l2ctlr = 0; 570 // b00:1CPU to b11:4CPUs 571 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 572 return l2ctlr; 573 } 574 case MISCREG_DBGDIDR: 575 /* For now just implement the version number. 576 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 577 */ 578 return 0x5 << 16; 579 case MISCREG_DBGDSCRint: 580 return 0; 581 case MISCREG_ISR: 582 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 583 readMiscRegNoEffect(MISCREG_HCR), 584 readMiscRegNoEffect(MISCREG_CPSR), 585 readMiscRegNoEffect(MISCREG_SCR)); 586 case MISCREG_ISR_EL1: 587 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 588 readMiscRegNoEffect(MISCREG_HCR_EL2), 589 readMiscRegNoEffect(MISCREG_CPSR), 590 readMiscRegNoEffect(MISCREG_SCR_EL3)); 591 case MISCREG_DCZID_EL0: 592 return 0x04; // DC ZVA clear 64-byte chunks 593 case MISCREG_HCPTR: 594 { 595 MiscReg val = readMiscRegNoEffect(misc_reg); 596 // The trap bit associated with CP14 is defined as RAZ 597 val &= ~(1 << 14); 598 // If a CP bit in NSACR is 0 then the corresponding bit in 599 // HCPTR is RAO/WI 600 bool secure_lookup = haveSecurity && 601 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 602 readMiscRegNoEffect(MISCREG_CPSR)); 603 if (!secure_lookup) { 604 MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR); 605 val |= (mask ^ 0x7FFF) & 0xBFFF; 606 } 607 // Set the bits for unimplemented coprocessors to RAO/WI 608 val |= 0x33FF; 609 return (val); 610 } 611 case MISCREG_HDFAR: // alias for secure DFAR 612 return readMiscRegNoEffect(MISCREG_DFAR_S); 613 case MISCREG_HIFAR: // alias for secure IFAR 614 return readMiscRegNoEffect(MISCREG_IFAR_S); 615 case MISCREG_HVBAR: // bottom bits reserved 616 return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0; 617 case MISCREG_SCTLR: 618 return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818; 619 case MISCREG_SCTLR_EL1: 620 return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800; 621 case MISCREG_SCTLR_EL2: 622 case MISCREG_SCTLR_EL3: 623 case MISCREG_HSCTLR: 624 return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; 625 626 case MISCREG_ID_PFR0: 627 // !ThumbEE | !Jazelle | Thumb | ARM 628 return 0x00000031; 629 case MISCREG_ID_PFR1: 630 { // Timer | Virti | !M Profile | TrustZone | ARMv4 631 bool haveTimer = (system->getGenericTimer() != NULL); 632 return 0x00000001 633 | (haveSecurity ? 0x00000010 : 0x0) 634 | (haveVirtualization ? 0x00001000 : 0x0) 635 | (haveTimer ? 0x00010000 : 0x0); 636 } 637 case MISCREG_ID_AA64PFR0_EL1: 638 return 0x0000000000000002 // AArch{64,32} supported at EL0 639 | 0x0000000000000020 // EL1 640 | (haveVirtualization ? 0x0000000000000200 : 0) // EL2 641 | (haveSecurity ? 0x0000000000002000 : 0); // EL3 642 case MISCREG_ID_AA64PFR1_EL1: 643 return 0; // bits [63:0] RES0 (reserved for future use) 644 645 // Generic Timer registers 646 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 647 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 648 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 649 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 650 return getGenericTimer(tc).readMiscReg(misc_reg); 651 652 default: 653 break; 654 655 } 656 return readMiscRegNoEffect(misc_reg); 657} 658 659void 660ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 661{ 662 assert(misc_reg < NumMiscRegs); 663 664 const auto ® = lookUpMiscReg[misc_reg]; // bit masks 665 const auto &map = getMiscIndices(misc_reg); 666 int lower = map.first, upper = map.second; 667 668 auto v = (val & ~reg.wi()) | reg.rao(); 669 if (upper > 0) { 670 miscRegs[lower] = bits(v, 31, 0); 671 miscRegs[upper] = bits(v, 63, 32); 672 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 673 misc_reg, lower, upper, v); 674 } else { 675 miscRegs[lower] = v; 676 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 677 misc_reg, lower, v); 678 } 679} 680 681void 682ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 683{ 684 685 MiscReg newVal = val; 686 bool secure_lookup; 687 SCR scr; 688 689 if (misc_reg == MISCREG_CPSR) { 690 updateRegMap(val); 691 692 693 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 694 int old_mode = old_cpsr.mode; 695 CPSR cpsr = val; 696 if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) { 697 getITBPtr(tc)->invalidateMiscReg(); 698 getDTBPtr(tc)->invalidateMiscReg(); 699 } 700 701 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 702 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 703 PCState pc = tc->pcState(); 704 pc.nextThumb(cpsr.t); 705 pc.nextJazelle(cpsr.j); 706 707 // Follow slightly different semantics if a CheckerCPU object 708 // is connected 709 CheckerCPU *checker = tc->getCheckerCpuPtr(); 710 if (checker) { 711 tc->pcStateNoRecord(pc); 712 } else { 713 tc->pcState(pc); 714 } 715 } else { 716#ifndef NDEBUG 717 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 718 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 719 warn("Unimplemented system register %s write with %#x.\n", 720 miscRegName[misc_reg], val); 721 else 722 panic("Unimplemented system register %s write with %#x.\n", 723 miscRegName[misc_reg], val); 724 } 725#endif 726 switch (unflattenMiscReg(misc_reg)) { 727 case MISCREG_CPACR: 728 { 729 730 const uint32_t ones = (uint32_t)(-1); 731 CPACR cpacrMask = 0; 732 // Only cp10, cp11, and ase are implemented, nothing else should 733 // be writable 734 cpacrMask.cp10 = ones; 735 cpacrMask.cp11 = ones; 736 cpacrMask.asedis = ones; 737 738 // Security Extensions may limit the writability of CPACR 739 if (haveSecurity) { 740 scr = readMiscRegNoEffect(MISCREG_SCR); 741 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 742 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 743 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 744 // NB: Skipping the full loop, here 745 if (!nsacr.cp10) cpacrMask.cp10 = 0; 746 if (!nsacr.cp11) cpacrMask.cp11 = 0; 747 } 748 } 749 750 MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR); 751 newVal &= cpacrMask; 752 newVal |= old_val & ~cpacrMask; 753 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 754 miscRegName[misc_reg], newVal); 755 } 756 break; 757 case MISCREG_CPTR_EL2: 758 { 759 const uint32_t ones = (uint32_t)(-1); 760 CPTR cptrMask = 0; 761 cptrMask.tcpac = ones; 762 cptrMask.tta = ones; 763 cptrMask.tfp = ones; 764 newVal &= cptrMask; 765 cptrMask = 0; 766 cptrMask.res1_13_12_el2 = ones; 767 cptrMask.res1_9_0_el2 = ones; 768 newVal |= cptrMask; 769 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 770 miscRegName[misc_reg], newVal); 771 } 772 break; 773 case MISCREG_CPTR_EL3: 774 { 775 const uint32_t ones = (uint32_t)(-1); 776 CPTR cptrMask = 0; 777 cptrMask.tcpac = ones; 778 cptrMask.tta = ones; 779 cptrMask.tfp = ones; 780 newVal &= cptrMask; 781 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 782 miscRegName[misc_reg], newVal); 783 } 784 break; 785 case MISCREG_CSSELR: 786 warn_once("The csselr register isn't implemented.\n"); 787 return; 788 789 case MISCREG_DC_ZVA_Xt: 790 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 791 return; 792 793 case MISCREG_FPSCR: 794 { 795 const uint32_t ones = (uint32_t)(-1); 796 FPSCR fpscrMask = 0; 797 fpscrMask.ioc = ones; 798 fpscrMask.dzc = ones; 799 fpscrMask.ofc = ones; 800 fpscrMask.ufc = ones; 801 fpscrMask.ixc = ones; 802 fpscrMask.idc = ones; 803 fpscrMask.ioe = ones; 804 fpscrMask.dze = ones; 805 fpscrMask.ofe = ones; 806 fpscrMask.ufe = ones; 807 fpscrMask.ixe = ones; 808 fpscrMask.ide = ones; 809 fpscrMask.len = ones; 810 fpscrMask.stride = ones; 811 fpscrMask.rMode = ones; 812 fpscrMask.fz = ones; 813 fpscrMask.dn = ones; 814 fpscrMask.ahp = ones; 815 fpscrMask.qc = ones; 816 fpscrMask.v = ones; 817 fpscrMask.c = ones; 818 fpscrMask.z = ones; 819 fpscrMask.n = ones; 820 newVal = (newVal & (uint32_t)fpscrMask) | 821 (readMiscRegNoEffect(MISCREG_FPSCR) & 822 ~(uint32_t)fpscrMask); 823 tc->getDecoderPtr()->setContext(newVal); 824 } 825 break; 826 case MISCREG_FPSR: 827 { 828 const uint32_t ones = (uint32_t)(-1); 829 FPSCR fpscrMask = 0; 830 fpscrMask.ioc = ones; 831 fpscrMask.dzc = ones; 832 fpscrMask.ofc = ones; 833 fpscrMask.ufc = ones; 834 fpscrMask.ixc = ones; 835 fpscrMask.idc = ones; 836 fpscrMask.qc = ones; 837 fpscrMask.v = ones; 838 fpscrMask.c = ones; 839 fpscrMask.z = ones; 840 fpscrMask.n = ones; 841 newVal = (newVal & (uint32_t)fpscrMask) | 842 (readMiscRegNoEffect(MISCREG_FPSCR) & 843 ~(uint32_t)fpscrMask); 844 misc_reg = MISCREG_FPSCR; 845 } 846 break; 847 case MISCREG_FPCR: 848 { 849 const uint32_t ones = (uint32_t)(-1); 850 FPSCR fpscrMask = 0; 851 fpscrMask.len = ones; 852 fpscrMask.stride = ones; 853 fpscrMask.rMode = ones; 854 fpscrMask.fz = ones; 855 fpscrMask.dn = ones; 856 fpscrMask.ahp = ones; 857 newVal = (newVal & (uint32_t)fpscrMask) | 858 (readMiscRegNoEffect(MISCREG_FPSCR) & 859 ~(uint32_t)fpscrMask); 860 misc_reg = MISCREG_FPSCR; 861 } 862 break; 863 case MISCREG_CPSR_Q: 864 { 865 assert(!(newVal & ~CpsrMaskQ)); 866 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 867 misc_reg = MISCREG_CPSR; 868 } 869 break; 870 case MISCREG_FPSCR_QC: 871 { 872 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 873 (newVal & FpscrQcMask); 874 misc_reg = MISCREG_FPSCR; 875 } 876 break; 877 case MISCREG_FPSCR_EXC: 878 { 879 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 880 (newVal & FpscrExcMask); 881 misc_reg = MISCREG_FPSCR; 882 } 883 break; 884 case MISCREG_FPEXC: 885 { 886 // vfpv3 architecture, section B.6.1 of DDI04068 887 // bit 29 - valid only if fpexc[31] is 0 888 const uint32_t fpexcMask = 0x60000000; 889 newVal = (newVal & fpexcMask) | 890 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 891 } 892 break; 893 case MISCREG_HCR: 894 { 895 if (!haveVirtualization) 896 return; 897 } 898 break; 899 case MISCREG_IFSR: 900 { 901 // ARM ARM (ARM DDI 0406C.b) B4.1.96 902 const uint32_t ifsrMask = 903 mask(31, 13) | mask(11, 11) | mask(8, 6); 904 newVal = newVal & ~ifsrMask; 905 } 906 break; 907 case MISCREG_DFSR: 908 { 909 // ARM ARM (ARM DDI 0406C.b) B4.1.52 910 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 911 newVal = newVal & ~dfsrMask; 912 } 913 break; 914 case MISCREG_AMAIR0: 915 case MISCREG_AMAIR1: 916 { 917 // ARM ARM (ARM DDI 0406C.b) B4.1.5 918 // Valid only with LPAE 919 if (!haveLPAE) 920 return; 921 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 922 } 923 break; 924 case MISCREG_SCR: 925 getITBPtr(tc)->invalidateMiscReg(); 926 getDTBPtr(tc)->invalidateMiscReg(); 927 break; 928 case MISCREG_SCTLR: 929 { 930 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 931 scr = readMiscRegNoEffect(MISCREG_SCR); 932 933 MiscRegIndex sctlr_idx; 934 if (haveSecurity && !highestELIs64 && !scr.ns) { 935 sctlr_idx = MISCREG_SCTLR_S; 936 } else { 937 sctlr_idx = MISCREG_SCTLR_NS; 938 } 939 940 SCTLR sctlr = miscRegs[sctlr_idx]; 941 SCTLR new_sctlr = newVal; 942 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 943 miscRegs[sctlr_idx] = (MiscReg)new_sctlr; 944 getITBPtr(tc)->invalidateMiscReg(); 945 getDTBPtr(tc)->invalidateMiscReg(); 946 } 947 case MISCREG_MIDR: 948 case MISCREG_ID_PFR0: 949 case MISCREG_ID_PFR1: 950 case MISCREG_ID_DFR0: 951 case MISCREG_ID_MMFR0: 952 case MISCREG_ID_MMFR1: 953 case MISCREG_ID_MMFR2: 954 case MISCREG_ID_MMFR3: 955 case MISCREG_ID_ISAR0: 956 case MISCREG_ID_ISAR1: 957 case MISCREG_ID_ISAR2: 958 case MISCREG_ID_ISAR3: 959 case MISCREG_ID_ISAR4: 960 case MISCREG_ID_ISAR5: 961 962 case MISCREG_MPIDR: 963 case MISCREG_FPSID: 964 case MISCREG_TLBTR: 965 case MISCREG_MVFR0: 966 case MISCREG_MVFR1: 967 968 case MISCREG_ID_AA64AFR0_EL1: 969 case MISCREG_ID_AA64AFR1_EL1: 970 case MISCREG_ID_AA64DFR0_EL1: 971 case MISCREG_ID_AA64DFR1_EL1: 972 case MISCREG_ID_AA64ISAR0_EL1: 973 case MISCREG_ID_AA64ISAR1_EL1: 974 case MISCREG_ID_AA64MMFR0_EL1: 975 case MISCREG_ID_AA64MMFR1_EL1: 976 case MISCREG_ID_AA64PFR0_EL1: 977 case MISCREG_ID_AA64PFR1_EL1: 978 // ID registers are constants. 979 return; 980 981 // TLB Invalidate All 982 case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 983 { 984 assert32(tc); 985 scr = readMiscReg(MISCREG_SCR, tc); 986 987 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 988 tlbiOp(tc); 989 return; 990 } 991 // TLB Invalidate All, Inner Shareable 992 case MISCREG_TLBIALLIS: 993 { 994 assert32(tc); 995 scr = readMiscReg(MISCREG_SCR, tc); 996 997 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 998 tlbiOp.broadcast(tc); 999 return; 1000 } 1001 // Instruction TLB Invalidate All 1002 case MISCREG_ITLBIALL: 1003 { 1004 assert32(tc); 1005 scr = readMiscReg(MISCREG_SCR, tc); 1006 1007 ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1008 tlbiOp(tc); 1009 return; 1010 } 1011 // Data TLB Invalidate All 1012 case MISCREG_DTLBIALL: 1013 { 1014 assert32(tc); 1015 scr = readMiscReg(MISCREG_SCR, tc); 1016 1017 DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1018 tlbiOp(tc); 1019 return; 1020 } 1021 // TLB Invalidate by VA 1022 // mcr tlbimval(is) is invalidating all matching entries 1023 // regardless of the level of lookup, since in gem5 we cache 1024 // in the tlb the last level of lookup only. 1025 case MISCREG_TLBIMVA: 1026 case MISCREG_TLBIMVAL: 1027 { 1028 assert32(tc); 1029 scr = readMiscReg(MISCREG_SCR, tc); 1030 1031 TLBIMVA tlbiOp(EL1, 1032 haveSecurity && !scr.ns, 1033 mbits(newVal, 31, 12), 1034 bits(newVal, 7,0)); 1035 1036 tlbiOp(tc); 1037 return; 1038 } 1039 // TLB Invalidate by VA, Inner Shareable 1040 case MISCREG_TLBIMVAIS: 1041 case MISCREG_TLBIMVALIS: 1042 { 1043 assert32(tc); 1044 scr = readMiscReg(MISCREG_SCR, tc); 1045 1046 TLBIMVA tlbiOp(EL1, 1047 haveSecurity && !scr.ns, 1048 mbits(newVal, 31, 12), 1049 bits(newVal, 7,0)); 1050 1051 tlbiOp.broadcast(tc); 1052 return; 1053 } 1054 // TLB Invalidate by ASID match 1055 case MISCREG_TLBIASID: 1056 { 1057 assert32(tc); 1058 scr = readMiscReg(MISCREG_SCR, tc); 1059 1060 TLBIASID tlbiOp(EL1, 1061 haveSecurity && !scr.ns, 1062 bits(newVal, 7,0)); 1063 1064 tlbiOp(tc); 1065 return; 1066 } 1067 // TLB Invalidate by ASID match, Inner Shareable 1068 case MISCREG_TLBIASIDIS: 1069 { 1070 assert32(tc); 1071 scr = readMiscReg(MISCREG_SCR, tc); 1072 1073 TLBIASID tlbiOp(EL1, 1074 haveSecurity && !scr.ns, 1075 bits(newVal, 7,0)); 1076 1077 tlbiOp.broadcast(tc); 1078 return; 1079 } 1080 // mcr tlbimvaal(is) is invalidating all matching entries 1081 // regardless of the level of lookup, since in gem5 we cache 1082 // in the tlb the last level of lookup only. 1083 // TLB Invalidate by VA, All ASID 1084 case MISCREG_TLBIMVAA: 1085 case MISCREG_TLBIMVAAL: 1086 { 1087 assert32(tc); 1088 scr = readMiscReg(MISCREG_SCR, tc); 1089 1090 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1091 mbits(newVal, 31,12), false); 1092 1093 tlbiOp(tc); 1094 return; 1095 } 1096 // TLB Invalidate by VA, All ASID, Inner Shareable 1097 case MISCREG_TLBIMVAAIS: 1098 case MISCREG_TLBIMVAALIS: 1099 { 1100 assert32(tc); 1101 scr = readMiscReg(MISCREG_SCR, tc); 1102 1103 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1104 mbits(newVal, 31,12), false); 1105 1106 tlbiOp.broadcast(tc); 1107 return; 1108 } 1109 // mcr tlbimvalh(is) is invalidating all matching entries 1110 // regardless of the level of lookup, since in gem5 we cache 1111 // in the tlb the last level of lookup only. 1112 // TLB Invalidate by VA, Hyp mode 1113 case MISCREG_TLBIMVAH: 1114 case MISCREG_TLBIMVALH: 1115 { 1116 assert32(tc); 1117 scr = readMiscReg(MISCREG_SCR, tc); 1118 1119 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1120 mbits(newVal, 31,12), true); 1121 1122 tlbiOp(tc); 1123 return; 1124 } 1125 // TLB Invalidate by VA, Hyp mode, Inner Shareable 1126 case MISCREG_TLBIMVAHIS: 1127 case MISCREG_TLBIMVALHIS: 1128 { 1129 assert32(tc); 1130 scr = readMiscReg(MISCREG_SCR, tc); 1131 1132 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1133 mbits(newVal, 31,12), true); 1134 1135 tlbiOp.broadcast(tc); 1136 return; 1137 } 1138 // mcr tlbiipas2l(is) is invalidating all matching entries 1139 // regardless of the level of lookup, since in gem5 we cache 1140 // in the tlb the last level of lookup only. 1141 // TLB Invalidate by Intermediate Physical Address, Stage 2 1142 case MISCREG_TLBIIPAS2: 1143 case MISCREG_TLBIIPAS2L: 1144 { 1145 assert32(tc); 1146 scr = readMiscReg(MISCREG_SCR, tc); 1147 1148 TLBIIPA tlbiOp(EL1, 1149 haveSecurity && !scr.ns, 1150 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1151 1152 tlbiOp(tc); 1153 return; 1154 } 1155 // TLB Invalidate by Intermediate Physical Address, Stage 2, 1156 // Inner Shareable 1157 case MISCREG_TLBIIPAS2IS: 1158 case MISCREG_TLBIIPAS2LIS: 1159 { 1160 assert32(tc); 1161 scr = readMiscReg(MISCREG_SCR, tc); 1162 1163 TLBIIPA tlbiOp(EL1, 1164 haveSecurity && !scr.ns, 1165 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1166 1167 tlbiOp.broadcast(tc); 1168 return; 1169 } 1170 // Instruction TLB Invalidate by VA 1171 case MISCREG_ITLBIMVA: 1172 { 1173 assert32(tc); 1174 scr = readMiscReg(MISCREG_SCR, tc); 1175 1176 ITLBIMVA tlbiOp(EL1, 1177 haveSecurity && !scr.ns, 1178 mbits(newVal, 31, 12), 1179 bits(newVal, 7,0)); 1180 1181 tlbiOp(tc); 1182 return; 1183 } 1184 // Data TLB Invalidate by VA 1185 case MISCREG_DTLBIMVA: 1186 { 1187 assert32(tc); 1188 scr = readMiscReg(MISCREG_SCR, tc); 1189 1190 DTLBIMVA tlbiOp(EL1, 1191 haveSecurity && !scr.ns, 1192 mbits(newVal, 31, 12), 1193 bits(newVal, 7,0)); 1194 1195 tlbiOp(tc); 1196 return; 1197 } 1198 // Instruction TLB Invalidate by ASID match 1199 case MISCREG_ITLBIASID: 1200 { 1201 assert32(tc); 1202 scr = readMiscReg(MISCREG_SCR, tc); 1203 1204 ITLBIASID tlbiOp(EL1, 1205 haveSecurity && !scr.ns, 1206 bits(newVal, 7,0)); 1207 1208 tlbiOp(tc); 1209 return; 1210 } 1211 // Data TLB Invalidate by ASID match 1212 case MISCREG_DTLBIASID: 1213 { 1214 assert32(tc); 1215 scr = readMiscReg(MISCREG_SCR, tc); 1216 1217 DTLBIASID tlbiOp(EL1, 1218 haveSecurity && !scr.ns, 1219 bits(newVal, 7,0)); 1220 1221 tlbiOp(tc); 1222 return; 1223 } 1224 // TLB Invalidate All, Non-Secure Non-Hyp 1225 case MISCREG_TLBIALLNSNH: 1226 { 1227 assert32(tc); 1228 1229 TLBIALLN tlbiOp(EL1, false); 1230 tlbiOp(tc); 1231 return; 1232 } 1233 // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable 1234 case MISCREG_TLBIALLNSNHIS: 1235 { 1236 assert32(tc); 1237 1238 TLBIALLN tlbiOp(EL1, false); 1239 tlbiOp.broadcast(tc); 1240 return; 1241 } 1242 // TLB Invalidate All, Hyp mode 1243 case MISCREG_TLBIALLH: 1244 { 1245 assert32(tc); 1246 1247 TLBIALLN tlbiOp(EL1, true); 1248 tlbiOp(tc); 1249 return; 1250 } 1251 // TLB Invalidate All, Hyp mode, Inner Shareable 1252 case MISCREG_TLBIALLHIS: 1253 { 1254 assert32(tc); 1255 1256 TLBIALLN tlbiOp(EL1, true); 1257 tlbiOp.broadcast(tc); 1258 return; 1259 } 1260 // AArch64 TLB Invalidate All, EL3 1261 case MISCREG_TLBI_ALLE3: 1262 { 1263 assert64(tc); 1264 1265 TLBIALL tlbiOp(EL3, true); 1266 tlbiOp(tc); 1267 return; 1268 } 1269 // AArch64 TLB Invalidate All, EL3, Inner Shareable 1270 case MISCREG_TLBI_ALLE3IS: 1271 { 1272 assert64(tc); 1273 1274 TLBIALL tlbiOp(EL3, true); 1275 tlbiOp.broadcast(tc); 1276 return; 1277 } 1278 // @todo: uncomment this to enable Virtualization 1279 // case MISCREG_TLBI_ALLE2IS: 1280 // case MISCREG_TLBI_ALLE2: 1281 // AArch64 TLB Invalidate All, EL1 1282 case MISCREG_TLBI_ALLE1: 1283 case MISCREG_TLBI_VMALLE1: 1284 case MISCREG_TLBI_VMALLS12E1: 1285 // @todo: handle VMID and stage 2 to enable Virtualization 1286 { 1287 assert64(tc); 1288 scr = readMiscReg(MISCREG_SCR, tc); 1289 1290 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1291 tlbiOp(tc); 1292 return; 1293 } 1294 // AArch64 TLB Invalidate All, EL1, Inner Shareable 1295 case MISCREG_TLBI_ALLE1IS: 1296 case MISCREG_TLBI_VMALLE1IS: 1297 case MISCREG_TLBI_VMALLS12E1IS: 1298 // @todo: handle VMID and stage 2 to enable Virtualization 1299 { 1300 assert64(tc); 1301 scr = readMiscReg(MISCREG_SCR, tc); 1302 1303 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1304 tlbiOp.broadcast(tc); 1305 return; 1306 } 1307 // VAEx(IS) and VALEx(IS) are the same because TLBs 1308 // only store entries 1309 // from the last level of translation table walks 1310 // @todo: handle VMID to enable Virtualization 1311 // AArch64 TLB Invalidate by VA, EL3 1312 case MISCREG_TLBI_VAE3_Xt: 1313 case MISCREG_TLBI_VALE3_Xt: 1314 { 1315 assert64(tc); 1316 1317 TLBIMVA tlbiOp(EL3, true, 1318 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1319 0xbeef); 1320 tlbiOp(tc); 1321 return; 1322 } 1323 // AArch64 TLB Invalidate by VA, EL3, Inner Shareable 1324 case MISCREG_TLBI_VAE3IS_Xt: 1325 case MISCREG_TLBI_VALE3IS_Xt: 1326 { 1327 assert64(tc); 1328 1329 TLBIMVA tlbiOp(EL3, true, 1330 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1331 0xbeef); 1332 1333 tlbiOp.broadcast(tc); 1334 return; 1335 } 1336 // AArch64 TLB Invalidate by VA, EL2 1337 case MISCREG_TLBI_VAE2_Xt: 1338 case MISCREG_TLBI_VALE2_Xt: 1339 { 1340 assert64(tc); 1341 scr = readMiscReg(MISCREG_SCR, tc); 1342 1343 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1344 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1345 0xbeef); 1346 tlbiOp(tc); 1347 return; 1348 } 1349 // AArch64 TLB Invalidate by VA, EL2, Inner Shareable 1350 case MISCREG_TLBI_VAE2IS_Xt: 1351 case MISCREG_TLBI_VALE2IS_Xt: 1352 { 1353 assert64(tc); 1354 scr = readMiscReg(MISCREG_SCR, tc); 1355 1356 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1357 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1358 0xbeef); 1359 1360 tlbiOp.broadcast(tc); 1361 return; 1362 } 1363 // AArch64 TLB Invalidate by VA, EL1 1364 case MISCREG_TLBI_VAE1_Xt: 1365 case MISCREG_TLBI_VALE1_Xt: 1366 { 1367 assert64(tc); 1368 scr = readMiscReg(MISCREG_SCR, tc); 1369 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1370 bits(newVal, 55, 48); 1371 1372 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1373 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1374 asid); 1375 1376 tlbiOp(tc); 1377 return; 1378 } 1379 // AArch64 TLB Invalidate by VA, EL1, Inner Shareable 1380 case MISCREG_TLBI_VAE1IS_Xt: 1381 case MISCREG_TLBI_VALE1IS_Xt: 1382 { 1383 assert64(tc); 1384 scr = readMiscReg(MISCREG_SCR, tc); 1385 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1386 bits(newVal, 55, 48); 1387 1388 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1389 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1390 asid); 1391 1392 tlbiOp.broadcast(tc); 1393 return; 1394 } 1395 // AArch64 TLB Invalidate by ASID, EL1 1396 // @todo: handle VMID to enable Virtualization 1397 case MISCREG_TLBI_ASIDE1_Xt: 1398 { 1399 assert64(tc); 1400 scr = readMiscReg(MISCREG_SCR, tc); 1401 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1402 bits(newVal, 55, 48); 1403 1404 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1405 tlbiOp(tc); 1406 return; 1407 } 1408 // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable 1409 case MISCREG_TLBI_ASIDE1IS_Xt: 1410 { 1411 assert64(tc); 1412 scr = readMiscReg(MISCREG_SCR, tc); 1413 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1414 bits(newVal, 55, 48); 1415 1416 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1417 tlbiOp.broadcast(tc); 1418 return; 1419 } 1420 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 1421 // entries from the last level of translation table walks 1422 // AArch64 TLB Invalidate by VA, All ASID, EL1 1423 case MISCREG_TLBI_VAAE1_Xt: 1424 case MISCREG_TLBI_VAALE1_Xt: 1425 { 1426 assert64(tc); 1427 scr = readMiscReg(MISCREG_SCR, tc); 1428 1429 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1430 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 1431 1432 tlbiOp(tc); 1433 return; 1434 } 1435 // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable 1436 case MISCREG_TLBI_VAAE1IS_Xt: 1437 case MISCREG_TLBI_VAALE1IS_Xt: 1438 { 1439 assert64(tc); 1440 scr = readMiscReg(MISCREG_SCR, tc); 1441 1442 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1443 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 1444 1445 tlbiOp.broadcast(tc); 1446 return; 1447 } 1448 // AArch64 TLB Invalidate by Intermediate Physical Address, 1449 // Stage 2, EL1 1450 case MISCREG_TLBI_IPAS2E1_Xt: 1451 case MISCREG_TLBI_IPAS2LE1_Xt: 1452 { 1453 assert64(tc); 1454 scr = readMiscReg(MISCREG_SCR, tc); 1455 1456 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1457 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1458 1459 tlbiOp(tc); 1460 return; 1461 } 1462 // AArch64 TLB Invalidate by Intermediate Physical Address, 1463 // Stage 2, EL1, Inner Shareable 1464 case MISCREG_TLBI_IPAS2E1IS_Xt: 1465 case MISCREG_TLBI_IPAS2LE1IS_Xt: 1466 { 1467 assert64(tc); 1468 scr = readMiscReg(MISCREG_SCR, tc); 1469 1470 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1471 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1472 1473 tlbiOp.broadcast(tc); 1474 return; 1475 } 1476 case MISCREG_ACTLR: 1477 warn("Not doing anything for write of miscreg ACTLR\n"); 1478 break; 1479 1480 case MISCREG_PMXEVTYPER_PMCCFILTR: 1481 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 1482 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 1483 case MISCREG_PMCR ... MISCREG_PMOVSSET: 1484 pmu->setMiscReg(misc_reg, newVal); 1485 break; 1486 1487 1488 case MISCREG_HSTR: // TJDBX, now redifined to be RES0 1489 { 1490 HSTR hstrMask = 0; 1491 hstrMask.tjdbx = 1; 1492 newVal &= ~((uint32_t) hstrMask); 1493 break; 1494 } 1495 case MISCREG_HCPTR: 1496 { 1497 // If a CP bit in NSACR is 0 then the corresponding bit in 1498 // HCPTR is RAO/WI. Same applies to NSASEDIS 1499 secure_lookup = haveSecurity && 1500 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 1501 readMiscRegNoEffect(MISCREG_CPSR)); 1502 if (!secure_lookup) { 1503 MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 1504 MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 1505 newVal = (newVal & ~mask) | (oldValue & mask); 1506 } 1507 break; 1508 } 1509 case MISCREG_HDFAR: // alias for secure DFAR 1510 misc_reg = MISCREG_DFAR_S; 1511 break; 1512 case MISCREG_HIFAR: // alias for secure IFAR 1513 misc_reg = MISCREG_IFAR_S; 1514 break; 1515 case MISCREG_ATS1CPR: 1516 case MISCREG_ATS1CPW: 1517 case MISCREG_ATS1CUR: 1518 case MISCREG_ATS1CUW: 1519 case MISCREG_ATS12NSOPR: 1520 case MISCREG_ATS12NSOPW: 1521 case MISCREG_ATS12NSOUR: 1522 case MISCREG_ATS12NSOUW: 1523 case MISCREG_ATS1HR: 1524 case MISCREG_ATS1HW: 1525 { 1526 Request::Flags flags = 0; 1527 BaseTLB::Mode mode = BaseTLB::Read; 1528 TLB::ArmTranslationType tranType = TLB::NormalTran; 1529 Fault fault; 1530 switch(misc_reg) { 1531 case MISCREG_ATS1CPR: 1532 flags = TLB::MustBeOne; 1533 tranType = TLB::S1CTran; 1534 mode = BaseTLB::Read; 1535 break; 1536 case MISCREG_ATS1CPW: 1537 flags = TLB::MustBeOne; 1538 tranType = TLB::S1CTran; 1539 mode = BaseTLB::Write; 1540 break; 1541 case MISCREG_ATS1CUR: 1542 flags = TLB::MustBeOne | TLB::UserMode; 1543 tranType = TLB::S1CTran; 1544 mode = BaseTLB::Read; 1545 break; 1546 case MISCREG_ATS1CUW: 1547 flags = TLB::MustBeOne | TLB::UserMode; 1548 tranType = TLB::S1CTran; 1549 mode = BaseTLB::Write; 1550 break; 1551 case MISCREG_ATS12NSOPR: 1552 if (!haveSecurity) 1553 panic("Security Extensions required for ATS12NSOPR"); 1554 flags = TLB::MustBeOne; 1555 tranType = TLB::S1S2NsTran; 1556 mode = BaseTLB::Read; 1557 break; 1558 case MISCREG_ATS12NSOPW: 1559 if (!haveSecurity) 1560 panic("Security Extensions required for ATS12NSOPW"); 1561 flags = TLB::MustBeOne; 1562 tranType = TLB::S1S2NsTran; 1563 mode = BaseTLB::Write; 1564 break; 1565 case MISCREG_ATS12NSOUR: 1566 if (!haveSecurity) 1567 panic("Security Extensions required for ATS12NSOUR"); 1568 flags = TLB::MustBeOne | TLB::UserMode; 1569 tranType = TLB::S1S2NsTran; 1570 mode = BaseTLB::Read; 1571 break; 1572 case MISCREG_ATS12NSOUW: 1573 if (!haveSecurity) 1574 panic("Security Extensions required for ATS12NSOUW"); 1575 flags = TLB::MustBeOne | TLB::UserMode; 1576 tranType = TLB::S1S2NsTran; 1577 mode = BaseTLB::Write; 1578 break; 1579 case MISCREG_ATS1HR: // only really useful from secure mode. 1580 flags = TLB::MustBeOne; 1581 tranType = TLB::HypMode; 1582 mode = BaseTLB::Read; 1583 break; 1584 case MISCREG_ATS1HW: 1585 flags = TLB::MustBeOne; 1586 tranType = TLB::HypMode; 1587 mode = BaseTLB::Write; 1588 break; 1589 } 1590 // If we're in timing mode then doing the translation in 1591 // functional mode then we're slightly distorting performance 1592 // results obtained from simulations. The translation should be 1593 // done in the same mode the core is running in. NOTE: This 1594 // can't be an atomic translation because that causes problems 1595 // with unexpected atomic snoop requests. 1596 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1597 Request req(0, val, 0, flags, Request::funcMasterId, 1598 tc->pcState().pc(), tc->contextId()); 1599 fault = getDTBPtr(tc)->translateFunctional( 1600 &req, tc, mode, tranType); 1601 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1602 HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 1603 1604 MiscReg newVal; 1605 if (fault == NoFault) { 1606 Addr paddr = req.getPaddr(); 1607 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 1608 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 1609 newVal = (paddr & mask(39, 12)) | 1610 (getDTBPtr(tc)->getAttr()); 1611 } else { 1612 newVal = (paddr & 0xfffff000) | 1613 (getDTBPtr(tc)->getAttr()); 1614 } 1615 DPRINTF(MiscRegs, 1616 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 1617 val, newVal); 1618 } else { 1619 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1620 armFault->update(tc); 1621 // Set fault bit and FSR 1622 FSR fsr = armFault->getFsr(tc); 1623 1624 newVal = ((fsr >> 9) & 1) << 11; 1625 if (newVal) { 1626 // LPAE - rearange fault status 1627 newVal |= ((fsr >> 0) & 0x3f) << 1; 1628 } else { 1629 // VMSA - rearange fault status 1630 newVal |= ((fsr >> 0) & 0xf) << 1; 1631 newVal |= ((fsr >> 10) & 0x1) << 5; 1632 newVal |= ((fsr >> 12) & 0x1) << 6; 1633 } 1634 newVal |= 0x1; // F bit 1635 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1636 newVal |= armFault->isStage2() ? 0x200 : 0; 1637 DPRINTF(MiscRegs, 1638 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 1639 val, fsr, newVal); 1640 } 1641 setMiscRegNoEffect(MISCREG_PAR, newVal); 1642 return; 1643 } 1644 case MISCREG_TTBCR: 1645 { 1646 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1647 const uint32_t ones = (uint32_t)(-1); 1648 TTBCR ttbcrMask = 0; 1649 TTBCR ttbcrNew = newVal; 1650 1651 // ARM DDI 0406C.b, ARMv7-32 1652 ttbcrMask.n = ones; // T0SZ 1653 if (haveSecurity) { 1654 ttbcrMask.pd0 = ones; 1655 ttbcrMask.pd1 = ones; 1656 } 1657 ttbcrMask.epd0 = ones; 1658 ttbcrMask.irgn0 = ones; 1659 ttbcrMask.orgn0 = ones; 1660 ttbcrMask.sh0 = ones; 1661 ttbcrMask.ps = ones; // T1SZ 1662 ttbcrMask.a1 = ones; 1663 ttbcrMask.epd1 = ones; 1664 ttbcrMask.irgn1 = ones; 1665 ttbcrMask.orgn1 = ones; 1666 ttbcrMask.sh1 = ones; 1667 if (haveLPAE) 1668 ttbcrMask.eae = ones; 1669 1670 if (haveLPAE && ttbcrNew.eae) { 1671 newVal = newVal & ttbcrMask; 1672 } else { 1673 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 1674 } 1675 // Invalidate TLB MiscReg 1676 getITBPtr(tc)->invalidateMiscReg(); 1677 getDTBPtr(tc)->invalidateMiscReg(); 1678 break; 1679 } 1680 case MISCREG_TTBR0: 1681 case MISCREG_TTBR1: 1682 { 1683 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1684 if (haveLPAE) { 1685 if (ttbcr.eae) { 1686 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 1687 // ARMv8 AArch32 bit 63-56 only 1688 uint64_t ttbrMask = mask(63,56) | mask(47,40); 1689 newVal = (newVal & (~ttbrMask)); 1690 } 1691 } 1692 // Invalidate TLB MiscReg 1693 getITBPtr(tc)->invalidateMiscReg(); 1694 getDTBPtr(tc)->invalidateMiscReg(); 1695 break; 1696 } 1697 case MISCREG_SCTLR_EL1: 1698 case MISCREG_CONTEXTIDR: 1699 case MISCREG_PRRR: 1700 case MISCREG_NMRR: 1701 case MISCREG_MAIR0: 1702 case MISCREG_MAIR1: 1703 case MISCREG_DACR: 1704 case MISCREG_VTTBR: 1705 case MISCREG_SCR_EL3: 1706 case MISCREG_HCR_EL2: 1707 case MISCREG_TCR_EL1: 1708 case MISCREG_TCR_EL2: 1709 case MISCREG_TCR_EL3: 1710 case MISCREG_SCTLR_EL2: 1711 case MISCREG_SCTLR_EL3: 1712 case MISCREG_HSCTLR: 1713 case MISCREG_TTBR0_EL1: 1714 case MISCREG_TTBR1_EL1: 1715 case MISCREG_TTBR0_EL2: 1716 case MISCREG_TTBR0_EL3: 1717 getITBPtr(tc)->invalidateMiscReg(); 1718 getDTBPtr(tc)->invalidateMiscReg(); 1719 break; 1720 case MISCREG_NZCV: 1721 { 1722 CPSR cpsr = val; 1723 1724 tc->setCCReg(CCREG_NZ, cpsr.nz); 1725 tc->setCCReg(CCREG_C, cpsr.c); 1726 tc->setCCReg(CCREG_V, cpsr.v); 1727 } 1728 break; 1729 case MISCREG_DAIF: 1730 { 1731 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1732 cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 1733 newVal = cpsr; 1734 misc_reg = MISCREG_CPSR; 1735 } 1736 break; 1737 case MISCREG_SP_EL0: 1738 tc->setIntReg(INTREG_SP0, newVal); 1739 break; 1740 case MISCREG_SP_EL1: 1741 tc->setIntReg(INTREG_SP1, newVal); 1742 break; 1743 case MISCREG_SP_EL2: 1744 tc->setIntReg(INTREG_SP2, newVal); 1745 break; 1746 case MISCREG_SPSEL: 1747 { 1748 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1749 cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 1750 newVal = cpsr; 1751 misc_reg = MISCREG_CPSR; 1752 } 1753 break; 1754 case MISCREG_CURRENTEL: 1755 { 1756 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1757 cpsr.el = (uint8_t) ((CPSR) newVal).el; 1758 newVal = cpsr; 1759 misc_reg = MISCREG_CPSR; 1760 } 1761 break; 1762 case MISCREG_AT_S1E1R_Xt: 1763 case MISCREG_AT_S1E1W_Xt: 1764 case MISCREG_AT_S1E0R_Xt: 1765 case MISCREG_AT_S1E0W_Xt: 1766 case MISCREG_AT_S1E2R_Xt: 1767 case MISCREG_AT_S1E2W_Xt: 1768 case MISCREG_AT_S12E1R_Xt: 1769 case MISCREG_AT_S12E1W_Xt: 1770 case MISCREG_AT_S12E0R_Xt: 1771 case MISCREG_AT_S12E0W_Xt: 1772 case MISCREG_AT_S1E3R_Xt: 1773 case MISCREG_AT_S1E3W_Xt: 1774 { 1775 RequestPtr req = new Request; 1776 Request::Flags flags = 0; 1777 BaseTLB::Mode mode = BaseTLB::Read; 1778 TLB::ArmTranslationType tranType = TLB::NormalTran; 1779 Fault fault; 1780 switch(misc_reg) { 1781 case MISCREG_AT_S1E1R_Xt: 1782 flags = TLB::MustBeOne; 1783 tranType = TLB::S1E1Tran; 1784 mode = BaseTLB::Read; 1785 break; 1786 case MISCREG_AT_S1E1W_Xt: 1787 flags = TLB::MustBeOne; 1788 tranType = TLB::S1E1Tran; 1789 mode = BaseTLB::Write; 1790 break; 1791 case MISCREG_AT_S1E0R_Xt: 1792 flags = TLB::MustBeOne | TLB::UserMode; 1793 tranType = TLB::S1E0Tran; 1794 mode = BaseTLB::Read; 1795 break; 1796 case MISCREG_AT_S1E0W_Xt: 1797 flags = TLB::MustBeOne | TLB::UserMode; 1798 tranType = TLB::S1E0Tran; 1799 mode = BaseTLB::Write; 1800 break; 1801 case MISCREG_AT_S1E2R_Xt: 1802 flags = TLB::MustBeOne; 1803 tranType = TLB::S1E2Tran; 1804 mode = BaseTLB::Read; 1805 break; 1806 case MISCREG_AT_S1E2W_Xt: 1807 flags = TLB::MustBeOne; 1808 tranType = TLB::S1E2Tran; 1809 mode = BaseTLB::Write; 1810 break; 1811 case MISCREG_AT_S12E0R_Xt: 1812 flags = TLB::MustBeOne | TLB::UserMode; 1813 tranType = TLB::S12E0Tran; 1814 mode = BaseTLB::Read; 1815 break; 1816 case MISCREG_AT_S12E0W_Xt: 1817 flags = TLB::MustBeOne | TLB::UserMode; 1818 tranType = TLB::S12E0Tran; 1819 mode = BaseTLB::Write; 1820 break; 1821 case MISCREG_AT_S12E1R_Xt: 1822 flags = TLB::MustBeOne; 1823 tranType = TLB::S12E1Tran; 1824 mode = BaseTLB::Read; 1825 break; 1826 case MISCREG_AT_S12E1W_Xt: 1827 flags = TLB::MustBeOne; 1828 tranType = TLB::S12E1Tran; 1829 mode = BaseTLB::Write; 1830 break; 1831 case MISCREG_AT_S1E3R_Xt: 1832 flags = TLB::MustBeOne; 1833 tranType = TLB::S1E3Tran; 1834 mode = BaseTLB::Read; 1835 break; 1836 case MISCREG_AT_S1E3W_Xt: 1837 flags = TLB::MustBeOne; 1838 tranType = TLB::S1E3Tran; 1839 mode = BaseTLB::Write; 1840 break; 1841 } 1842 // If we're in timing mode then doing the translation in 1843 // functional mode then we're slightly distorting performance 1844 // results obtained from simulations. The translation should be 1845 // done in the same mode the core is running in. NOTE: This 1846 // can't be an atomic translation because that causes problems 1847 // with unexpected atomic snoop requests. 1848 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1849 req->setVirt(0, val, 0, flags, Request::funcMasterId, 1850 tc->pcState().pc()); 1851 req->setContext(tc->contextId()); 1852 fault = getDTBPtr(tc)->translateFunctional(req, tc, mode, 1853 tranType); 1854 1855 MiscReg newVal; 1856 if (fault == NoFault) { 1857 Addr paddr = req->getPaddr(); 1858 uint64_t attr = getDTBPtr(tc)->getAttr(); 1859 uint64_t attr1 = attr >> 56; 1860 if (!attr1 || attr1 ==0x44) { 1861 attr |= 0x100; 1862 attr &= ~ uint64_t(0x80); 1863 } 1864 newVal = (paddr & mask(47, 12)) | attr; 1865 DPRINTF(MiscRegs, 1866 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 1867 val, newVal); 1868 } else { 1869 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1870 armFault->update(tc); 1871 // Set fault bit and FSR 1872 FSR fsr = armFault->getFsr(tc); 1873 1874 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1875 if (cpsr.width) { // AArch32 1876 newVal = ((fsr >> 9) & 1) << 11; 1877 // rearrange fault status 1878 newVal |= ((fsr >> 0) & 0x3f) << 1; 1879 newVal |= 0x1; // F bit 1880 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1881 newVal |= armFault->isStage2() ? 0x200 : 0; 1882 } else { // AArch64 1883 newVal = 1; // F bit 1884 newVal |= fsr << 1; // FST 1885 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit. 1886 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 1887 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 1888 newVal |= 1 << 11; // RES1 1889 } 1890 DPRINTF(MiscRegs, 1891 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 1892 val, fsr, newVal); 1893 } 1894 delete req; 1895 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 1896 return; 1897 } 1898 case MISCREG_SPSR_EL3: 1899 case MISCREG_SPSR_EL2: 1900 case MISCREG_SPSR_EL1: 1901 // Force bits 23:21 to 0 1902 newVal = val & ~(0x7 << 21); 1903 break; 1904 case MISCREG_L2CTLR: 1905 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 1906 miscRegName[misc_reg], uint32_t(val)); 1907 break; 1908 1909 // Generic Timer registers 1910 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 1911 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 1912 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 1913 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 1914 getGenericTimer(tc).setMiscReg(misc_reg, newVal); 1915 break; 1916 } 1917 } 1918 setMiscRegNoEffect(misc_reg, newVal); 1919} 1920 1921BaseISADevice & 1922ISA::getGenericTimer(ThreadContext *tc) 1923{ 1924 // We only need to create an ISA interface the first time we try 1925 // to access the timer. 1926 if (timer) 1927 return *timer.get(); 1928 1929 assert(system); 1930 GenericTimer *generic_timer(system->getGenericTimer()); 1931 if (!generic_timer) { 1932 panic("Trying to get a generic timer from a system that hasn't " 1933 "been configured to use a generic timer.\n"); 1934 } 1935 1936 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 1937 return *timer.get(); 1938} 1939 1940} 1941 1942ArmISA::ISA * 1943ArmISAParams::create() 1944{ 1945 return new ArmISA::ISA(this); 1946} 1947