isa.cc revision 12670:d662ee5a095a
1/* 2 * Copyright (c) 2010-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 */ 40 41#include "arch/arm/isa.hh" 42#include "arch/arm/pmu.hh" 43#include "arch/arm/system.hh" 44#include "arch/arm/tlb.hh" 45#include "arch/arm/tlbi_op.hh" 46#include "cpu/base.hh" 47#include "cpu/checker/cpu.hh" 48#include "debug/Arm.hh" 49#include "debug/MiscRegs.hh" 50#include "dev/arm/generic_timer.hh" 51#include "params/ArmISA.hh" 52#include "sim/faults.hh" 53#include "sim/stat_control.hh" 54#include "sim/system.hh" 55 56namespace ArmISA 57{ 58 59ISA::ISA(Params *p) 60 : SimObject(p), 61 system(NULL), 62 _decoderFlavour(p->decoderFlavour), 63 _vecRegRenameMode(p->vecRegRenameMode), 64 pmu(p->pmu) 65{ 66 miscRegs[MISCREG_SCTLR_RST] = 0; 67 68 // Hook up a dummy device if we haven't been configured with a 69 // real PMU. By using a dummy device, we don't need to check that 70 // the PMU exist every time we try to access a PMU register. 71 if (!pmu) 72 pmu = &dummyDevice; 73 74 // Give all ISA devices a pointer to this ISA 75 pmu->setISA(this); 76 77 system = dynamic_cast<ArmSystem *>(p->system); 78 79 // Cache system-level properties 80 if (FullSystem && system) { 81 highestELIs64 = system->highestELIs64(); 82 haveSecurity = system->haveSecurity(); 83 haveLPAE = system->haveLPAE(); 84 haveVirtualization = system->haveVirtualization(); 85 haveLargeAsid64 = system->haveLargeAsid64(); 86 physAddrRange64 = system->physAddrRange64(); 87 } else { 88 highestELIs64 = true; // ArmSystem::highestELIs64 does the same 89 haveSecurity = haveLPAE = haveVirtualization = false; 90 haveLargeAsid64 = false; 91 physAddrRange64 = 32; // dummy value 92 } 93 94 initializeMiscRegMetadata(); 95 preUnflattenMiscReg(); 96 97 clear(); 98} 99 100std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS); 101 102const ArmISAParams * 103ISA::params() const 104{ 105 return dynamic_cast<const Params *>(_params); 106} 107 108void 109ISA::clear() 110{ 111 const Params *p(params()); 112 113 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 114 memset(miscRegs, 0, sizeof(miscRegs)); 115 116 // Initialize configurable default values 117 miscRegs[MISCREG_MIDR] = p->midr; 118 miscRegs[MISCREG_MIDR_EL1] = p->midr; 119 miscRegs[MISCREG_VPIDR] = p->midr; 120 121 if (FullSystem && system->highestELIs64()) { 122 // Initialize AArch64 state 123 clear64(p); 124 return; 125 } 126 127 // Initialize AArch32 state... 128 129 CPSR cpsr = 0; 130 cpsr.mode = MODE_USER; 131 miscRegs[MISCREG_CPSR] = cpsr; 132 updateRegMap(cpsr); 133 134 SCTLR sctlr = 0; 135 sctlr.te = (bool) sctlr_rst.te; 136 sctlr.nmfi = (bool) sctlr_rst.nmfi; 137 sctlr.v = (bool) sctlr_rst.v; 138 sctlr.u = 1; 139 sctlr.xp = 1; 140 sctlr.rao2 = 1; 141 sctlr.rao3 = 1; 142 sctlr.rao4 = 0xf; // SCTLR[6:3] 143 sctlr.uci = 1; 144 sctlr.dze = 1; 145 miscRegs[MISCREG_SCTLR_NS] = sctlr; 146 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 147 miscRegs[MISCREG_HCPTR] = 0; 148 149 // Start with an event in the mailbox 150 miscRegs[MISCREG_SEV_MAILBOX] = 1; 151 152 // Separate Instruction and Data TLBs 153 miscRegs[MISCREG_TLBTR] = 1; 154 155 MVFR0 mvfr0 = 0; 156 mvfr0.advSimdRegisters = 2; 157 mvfr0.singlePrecision = 2; 158 mvfr0.doublePrecision = 2; 159 mvfr0.vfpExceptionTrapping = 0; 160 mvfr0.divide = 1; 161 mvfr0.squareRoot = 1; 162 mvfr0.shortVectors = 1; 163 mvfr0.roundingModes = 1; 164 miscRegs[MISCREG_MVFR0] = mvfr0; 165 166 MVFR1 mvfr1 = 0; 167 mvfr1.flushToZero = 1; 168 mvfr1.defaultNaN = 1; 169 mvfr1.advSimdLoadStore = 1; 170 mvfr1.advSimdInteger = 1; 171 mvfr1.advSimdSinglePrecision = 1; 172 mvfr1.advSimdHalfPrecision = 1; 173 mvfr1.vfpHalfPrecision = 1; 174 miscRegs[MISCREG_MVFR1] = mvfr1; 175 176 // Reset values of PRRR and NMRR are implementation dependent 177 178 // @todo: PRRR and NMRR in secure state? 179 miscRegs[MISCREG_PRRR_NS] = 180 (1 << 19) | // 19 181 (0 << 18) | // 18 182 (0 << 17) | // 17 183 (1 << 16) | // 16 184 (2 << 14) | // 15:14 185 (0 << 12) | // 13:12 186 (2 << 10) | // 11:10 187 (2 << 8) | // 9:8 188 (2 << 6) | // 7:6 189 (2 << 4) | // 5:4 190 (1 << 2) | // 3:2 191 0; // 1:0 192 miscRegs[MISCREG_NMRR_NS] = 193 (1 << 30) | // 31:30 194 (0 << 26) | // 27:26 195 (0 << 24) | // 25:24 196 (3 << 22) | // 23:22 197 (2 << 20) | // 21:20 198 (0 << 18) | // 19:18 199 (0 << 16) | // 17:16 200 (1 << 14) | // 15:14 201 (0 << 12) | // 13:12 202 (2 << 10) | // 11:10 203 (0 << 8) | // 9:8 204 (3 << 6) | // 7:6 205 (2 << 4) | // 5:4 206 (0 << 2) | // 3:2 207 0; // 1:0 208 209 miscRegs[MISCREG_CPACR] = 0; 210 211 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 212 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 213 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 214 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 215 216 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 217 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 218 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 219 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 220 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 221 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 222 223 miscRegs[MISCREG_FPSID] = p->fpsid; 224 225 if (haveLPAE) { 226 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 227 ttbcr.eae = 0; 228 miscRegs[MISCREG_TTBCR_NS] = ttbcr; 229 // Enforce consistency with system-level settings 230 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 231 } 232 233 if (haveSecurity) { 234 miscRegs[MISCREG_SCTLR_S] = sctlr; 235 miscRegs[MISCREG_SCR] = 0; 236 miscRegs[MISCREG_VBAR_S] = 0; 237 } else { 238 // we're always non-secure 239 miscRegs[MISCREG_SCR] = 1; 240 } 241 242 //XXX We need to initialize the rest of the state. 243} 244 245void 246ISA::clear64(const ArmISAParams *p) 247{ 248 CPSR cpsr = 0; 249 Addr rvbar = system->resetAddr64(); 250 switch (system->highestEL()) { 251 // Set initial EL to highest implemented EL using associated stack 252 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 253 // value 254 case EL3: 255 cpsr.mode = MODE_EL3H; 256 miscRegs[MISCREG_RVBAR_EL3] = rvbar; 257 break; 258 case EL2: 259 cpsr.mode = MODE_EL2H; 260 miscRegs[MISCREG_RVBAR_EL2] = rvbar; 261 break; 262 case EL1: 263 cpsr.mode = MODE_EL1H; 264 miscRegs[MISCREG_RVBAR_EL1] = rvbar; 265 break; 266 default: 267 panic("Invalid highest implemented exception level"); 268 break; 269 } 270 271 // Initialize rest of CPSR 272 cpsr.daif = 0xf; // Mask all interrupts 273 cpsr.ss = 0; 274 cpsr.il = 0; 275 miscRegs[MISCREG_CPSR] = cpsr; 276 updateRegMap(cpsr); 277 278 // Initialize other control registers 279 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 280 if (haveSecurity) { 281 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830; 282 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 283 } else if (haveVirtualization) { 284 // also MISCREG_SCTLR_EL2 (by mapping) 285 miscRegs[MISCREG_HSCTLR] = 0x30c50830; 286 } else { 287 // also MISCREG_SCTLR_EL1 (by mapping) 288 miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init 289 // Always non-secure 290 miscRegs[MISCREG_SCR_EL3] = 1; 291 } 292 293 // Initialize configurable id registers 294 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 295 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 296 miscRegs[MISCREG_ID_AA64DFR0_EL1] = 297 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 298 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 299 300 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 301 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 302 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 303 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 304 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 305 306 miscRegs[MISCREG_ID_DFR0_EL1] = 307 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 308 309 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 310 311 // Enforce consistency with system-level settings... 312 313 // EL3 314 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 315 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 316 haveSecurity ? 0x2 : 0x0); 317 // EL2 318 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 319 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 320 haveVirtualization ? 0x2 : 0x0); 321 // Large ASID support 322 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 323 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 324 haveLargeAsid64 ? 0x2 : 0x0); 325 // Physical address size 326 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 327 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 328 encodePhysAddrRange64(physAddrRange64)); 329} 330 331MiscReg 332ISA::readMiscRegNoEffect(int misc_reg) const 333{ 334 assert(misc_reg < NumMiscRegs); 335 336 const auto ® = lookUpMiscReg[misc_reg]; // bit masks 337 const auto &map = getMiscIndices(misc_reg); 338 int lower = map.first, upper = map.second; 339 // NB!: apply architectural masks according to desired register, 340 // despite possibly getting value from different (mapped) register. 341 auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32)) 342 |(miscRegs[upper] << 32)); 343 if (val & reg.res0()) { 344 DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n", 345 miscRegName[misc_reg], val & reg.res0()); 346 } 347 if ((val & reg.res1()) != reg.res1()) { 348 DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n", 349 miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1()); 350 } 351 return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao 352} 353 354 355MiscReg 356ISA::readMiscReg(int misc_reg, ThreadContext *tc) 357{ 358 CPSR cpsr = 0; 359 PCState pc = 0; 360 SCR scr = 0; 361 362 if (misc_reg == MISCREG_CPSR) { 363 cpsr = miscRegs[misc_reg]; 364 pc = tc->pcState(); 365 cpsr.j = pc.jazelle() ? 1 : 0; 366 cpsr.t = pc.thumb() ? 1 : 0; 367 return cpsr; 368 } 369 370#ifndef NDEBUG 371 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 372 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 373 warn("Unimplemented system register %s read.\n", 374 miscRegName[misc_reg]); 375 else 376 panic("Unimplemented system register %s read.\n", 377 miscRegName[misc_reg]); 378 } 379#endif 380 381 switch (unflattenMiscReg(misc_reg)) { 382 case MISCREG_HCR: 383 { 384 if (!haveVirtualization) 385 return 0; 386 else 387 return readMiscRegNoEffect(MISCREG_HCR); 388 } 389 case MISCREG_CPACR: 390 { 391 const uint32_t ones = (uint32_t)(-1); 392 CPACR cpacrMask = 0; 393 // Only cp10, cp11, and ase are implemented, nothing else should 394 // be readable? (straight copy from the write code) 395 cpacrMask.cp10 = ones; 396 cpacrMask.cp11 = ones; 397 cpacrMask.asedis = ones; 398 399 // Security Extensions may limit the readability of CPACR 400 if (haveSecurity) { 401 scr = readMiscRegNoEffect(MISCREG_SCR); 402 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 403 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 404 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 405 // NB: Skipping the full loop, here 406 if (!nsacr.cp10) cpacrMask.cp10 = 0; 407 if (!nsacr.cp11) cpacrMask.cp11 = 0; 408 } 409 } 410 MiscReg val = readMiscRegNoEffect(MISCREG_CPACR); 411 val &= cpacrMask; 412 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 413 miscRegName[misc_reg], val); 414 return val; 415 } 416 case MISCREG_MPIDR: 417 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 418 scr = readMiscRegNoEffect(MISCREG_SCR); 419 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 420 return getMPIDR(system, tc); 421 } else { 422 return readMiscReg(MISCREG_VMPIDR, tc); 423 } 424 break; 425 case MISCREG_MPIDR_EL1: 426 // @todo in the absence of v8 virtualization support just return MPIDR_EL1 427 return getMPIDR(system, tc) & 0xffffffff; 428 case MISCREG_VMPIDR: 429 // top bit defined as RES1 430 return readMiscRegNoEffect(misc_reg) | 0x80000000; 431 case MISCREG_ID_AFR0: // not implemented, so alias MIDR 432 case MISCREG_REVIDR: // not implemented, so alias MIDR 433 case MISCREG_MIDR: 434 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 435 scr = readMiscRegNoEffect(MISCREG_SCR); 436 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 437 return readMiscRegNoEffect(misc_reg); 438 } else { 439 return readMiscRegNoEffect(MISCREG_VPIDR); 440 } 441 break; 442 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 443 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 444 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 445 case MISCREG_AIDR: // AUX ID set to 0 446 case MISCREG_TCMTR: // No TCM's 447 return 0; 448 449 case MISCREG_CLIDR: 450 warn_once("The clidr register always reports 0 caches.\n"); 451 warn_once("clidr LoUIS field of 0b001 to match current " 452 "ARM implementations.\n"); 453 return 0x00200000; 454 case MISCREG_CCSIDR: 455 warn_once("The ccsidr register isn't implemented and " 456 "always reads as 0.\n"); 457 break; 458 case MISCREG_CTR: // AArch32, ARMv7, top bit set 459 case MISCREG_CTR_EL0: // AArch64 460 { 461 //all caches have the same line size in gem5 462 //4 byte words in ARM 463 unsigned lineSizeWords = 464 tc->getSystemPtr()->cacheLineSize() / 4; 465 unsigned log2LineSizeWords = 0; 466 467 while (lineSizeWords >>= 1) { 468 ++log2LineSizeWords; 469 } 470 471 CTR ctr = 0; 472 //log2 of minimun i-cache line size (words) 473 ctr.iCacheLineSize = log2LineSizeWords; 474 //b11 - gem5 uses pipt 475 ctr.l1IndexPolicy = 0x3; 476 //log2 of minimum d-cache line size (words) 477 ctr.dCacheLineSize = log2LineSizeWords; 478 //log2 of max reservation size (words) 479 ctr.erg = log2LineSizeWords; 480 //log2 of max writeback size (words) 481 ctr.cwg = log2LineSizeWords; 482 //b100 - gem5 format is ARMv7 483 ctr.format = 0x4; 484 485 return ctr; 486 } 487 case MISCREG_ACTLR: 488 warn("Not doing anything for miscreg ACTLR\n"); 489 break; 490 491 case MISCREG_PMXEVTYPER_PMCCFILTR: 492 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 493 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 494 case MISCREG_PMCR ... MISCREG_PMOVSSET: 495 return pmu->readMiscReg(misc_reg); 496 497 case MISCREG_CPSR_Q: 498 panic("shouldn't be reading this register seperately\n"); 499 case MISCREG_FPSCR_QC: 500 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 501 case MISCREG_FPSCR_EXC: 502 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 503 case MISCREG_FPSR: 504 { 505 const uint32_t ones = (uint32_t)(-1); 506 FPSCR fpscrMask = 0; 507 fpscrMask.ioc = ones; 508 fpscrMask.dzc = ones; 509 fpscrMask.ofc = ones; 510 fpscrMask.ufc = ones; 511 fpscrMask.ixc = ones; 512 fpscrMask.idc = ones; 513 fpscrMask.qc = ones; 514 fpscrMask.v = ones; 515 fpscrMask.c = ones; 516 fpscrMask.z = ones; 517 fpscrMask.n = ones; 518 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 519 } 520 case MISCREG_FPCR: 521 { 522 const uint32_t ones = (uint32_t)(-1); 523 FPSCR fpscrMask = 0; 524 fpscrMask.len = ones; 525 fpscrMask.stride = ones; 526 fpscrMask.rMode = ones; 527 fpscrMask.fz = ones; 528 fpscrMask.dn = ones; 529 fpscrMask.ahp = ones; 530 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 531 } 532 case MISCREG_NZCV: 533 { 534 CPSR cpsr = 0; 535 cpsr.nz = tc->readCCReg(CCREG_NZ); 536 cpsr.c = tc->readCCReg(CCREG_C); 537 cpsr.v = tc->readCCReg(CCREG_V); 538 return cpsr; 539 } 540 case MISCREG_DAIF: 541 { 542 CPSR cpsr = 0; 543 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 544 return cpsr; 545 } 546 case MISCREG_SP_EL0: 547 { 548 return tc->readIntReg(INTREG_SP0); 549 } 550 case MISCREG_SP_EL1: 551 { 552 return tc->readIntReg(INTREG_SP1); 553 } 554 case MISCREG_SP_EL2: 555 { 556 return tc->readIntReg(INTREG_SP2); 557 } 558 case MISCREG_SPSEL: 559 { 560 return miscRegs[MISCREG_CPSR] & 0x1; 561 } 562 case MISCREG_CURRENTEL: 563 { 564 return miscRegs[MISCREG_CPSR] & 0xc; 565 } 566 case MISCREG_L2CTLR: 567 { 568 // mostly unimplemented, just set NumCPUs field from sim and return 569 L2CTLR l2ctlr = 0; 570 // b00:1CPU to b11:4CPUs 571 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 572 return l2ctlr; 573 } 574 case MISCREG_DBGDIDR: 575 /* For now just implement the version number. 576 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 577 */ 578 return 0x5 << 16; 579 case MISCREG_DBGDSCRint: 580 return 0; 581 case MISCREG_ISR: 582 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 583 readMiscRegNoEffect(MISCREG_HCR), 584 readMiscRegNoEffect(MISCREG_CPSR), 585 readMiscRegNoEffect(MISCREG_SCR)); 586 case MISCREG_ISR_EL1: 587 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 588 readMiscRegNoEffect(MISCREG_HCR_EL2), 589 readMiscRegNoEffect(MISCREG_CPSR), 590 readMiscRegNoEffect(MISCREG_SCR_EL3)); 591 case MISCREG_DCZID_EL0: 592 return 0x04; // DC ZVA clear 64-byte chunks 593 case MISCREG_HCPTR: 594 { 595 MiscReg val = readMiscRegNoEffect(misc_reg); 596 // The trap bit associated with CP14 is defined as RAZ 597 val &= ~(1 << 14); 598 // If a CP bit in NSACR is 0 then the corresponding bit in 599 // HCPTR is RAO/WI 600 bool secure_lookup = haveSecurity && 601 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 602 readMiscRegNoEffect(MISCREG_CPSR)); 603 if (!secure_lookup) { 604 MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR); 605 val |= (mask ^ 0x7FFF) & 0xBFFF; 606 } 607 // Set the bits for unimplemented coprocessors to RAO/WI 608 val |= 0x33FF; 609 return (val); 610 } 611 case MISCREG_HDFAR: // alias for secure DFAR 612 return readMiscRegNoEffect(MISCREG_DFAR_S); 613 case MISCREG_HIFAR: // alias for secure IFAR 614 return readMiscRegNoEffect(MISCREG_IFAR_S); 615 case MISCREG_HVBAR: // bottom bits reserved 616 return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0; 617 case MISCREG_SCTLR: 618 return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818; 619 case MISCREG_SCTLR_EL1: 620 return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800; 621 case MISCREG_SCTLR_EL2: 622 case MISCREG_SCTLR_EL3: 623 case MISCREG_HSCTLR: 624 return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; 625 626 case MISCREG_ID_PFR0: 627 // !ThumbEE | !Jazelle | Thumb | ARM 628 return 0x00000031; 629 case MISCREG_ID_PFR1: 630 { // Timer | Virti | !M Profile | TrustZone | ARMv4 631 bool haveTimer = (system->getGenericTimer() != NULL); 632 return 0x00000001 633 | (haveSecurity ? 0x00000010 : 0x0) 634 | (haveVirtualization ? 0x00001000 : 0x0) 635 | (haveTimer ? 0x00010000 : 0x0); 636 } 637 case MISCREG_ID_AA64PFR0_EL1: 638 return 0x0000000000000002 // AArch{64,32} supported at EL0 639 | 0x0000000000000020 // EL1 640 | (haveVirtualization ? 0x0000000000000200 : 0) // EL2 641 | (haveSecurity ? 0x0000000000002000 : 0); // EL3 642 case MISCREG_ID_AA64PFR1_EL1: 643 return 0; // bits [63:0] RES0 (reserved for future use) 644 645 // Generic Timer registers 646 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 647 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 648 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 649 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 650 return getGenericTimer(tc).readMiscReg(misc_reg); 651 652 default: 653 break; 654 655 } 656 return readMiscRegNoEffect(misc_reg); 657} 658 659void 660ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 661{ 662 assert(misc_reg < NumMiscRegs); 663 664 const auto ® = lookUpMiscReg[misc_reg]; // bit masks 665 const auto &map = getMiscIndices(misc_reg); 666 int lower = map.first, upper = map.second; 667 668 auto v = (val & ~reg.wi()) | reg.rao(); 669 if (upper > 0) { 670 miscRegs[lower] = bits(v, 31, 0); 671 miscRegs[upper] = bits(v, 63, 32); 672 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 673 misc_reg, lower, upper, v); 674 } else { 675 miscRegs[lower] = v; 676 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 677 misc_reg, lower, v); 678 } 679} 680 681void 682ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 683{ 684 685 MiscReg newVal = val; 686 bool secure_lookup; 687 SCR scr; 688 689 if (misc_reg == MISCREG_CPSR) { 690 updateRegMap(val); 691 692 693 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 694 int old_mode = old_cpsr.mode; 695 CPSR cpsr = val; 696 if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) { 697 getITBPtr(tc)->invalidateMiscReg(); 698 getDTBPtr(tc)->invalidateMiscReg(); 699 } 700 701 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 702 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 703 PCState pc = tc->pcState(); 704 pc.nextThumb(cpsr.t); 705 pc.nextJazelle(cpsr.j); 706 707 // Follow slightly different semantics if a CheckerCPU object 708 // is connected 709 CheckerCPU *checker = tc->getCheckerCpuPtr(); 710 if (checker) { 711 tc->pcStateNoRecord(pc); 712 } else { 713 tc->pcState(pc); 714 } 715 } else { 716#ifndef NDEBUG 717 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 718 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 719 warn("Unimplemented system register %s write with %#x.\n", 720 miscRegName[misc_reg], val); 721 else 722 panic("Unimplemented system register %s write with %#x.\n", 723 miscRegName[misc_reg], val); 724 } 725#endif 726 switch (unflattenMiscReg(misc_reg)) { 727 case MISCREG_CPACR: 728 { 729 730 const uint32_t ones = (uint32_t)(-1); 731 CPACR cpacrMask = 0; 732 // Only cp10, cp11, and ase are implemented, nothing else should 733 // be writable 734 cpacrMask.cp10 = ones; 735 cpacrMask.cp11 = ones; 736 cpacrMask.asedis = ones; 737 738 // Security Extensions may limit the writability of CPACR 739 if (haveSecurity) { 740 scr = readMiscRegNoEffect(MISCREG_SCR); 741 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 742 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 743 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 744 // NB: Skipping the full loop, here 745 if (!nsacr.cp10) cpacrMask.cp10 = 0; 746 if (!nsacr.cp11) cpacrMask.cp11 = 0; 747 } 748 } 749 750 MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR); 751 newVal &= cpacrMask; 752 newVal |= old_val & ~cpacrMask; 753 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 754 miscRegName[misc_reg], newVal); 755 } 756 break; 757 case MISCREG_CPACR_EL1: 758 { 759 const uint32_t ones = (uint32_t)(-1); 760 CPACR cpacrMask = 0; 761 cpacrMask.tta = ones; 762 cpacrMask.fpen = ones; 763 newVal &= cpacrMask; 764 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 765 miscRegName[misc_reg], newVal); 766 } 767 break; 768 case MISCREG_CPTR_EL2: 769 { 770 const uint32_t ones = (uint32_t)(-1); 771 CPTR cptrMask = 0; 772 cptrMask.tcpac = ones; 773 cptrMask.tta = ones; 774 cptrMask.tfp = ones; 775 newVal &= cptrMask; 776 cptrMask = 0; 777 cptrMask.res1_13_12_el2 = ones; 778 cptrMask.res1_9_0_el2 = ones; 779 newVal |= cptrMask; 780 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 781 miscRegName[misc_reg], newVal); 782 } 783 break; 784 case MISCREG_CPTR_EL3: 785 { 786 const uint32_t ones = (uint32_t)(-1); 787 CPTR cptrMask = 0; 788 cptrMask.tcpac = ones; 789 cptrMask.tta = ones; 790 cptrMask.tfp = ones; 791 newVal &= cptrMask; 792 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 793 miscRegName[misc_reg], newVal); 794 } 795 break; 796 case MISCREG_CSSELR: 797 warn_once("The csselr register isn't implemented.\n"); 798 return; 799 800 case MISCREG_DC_ZVA_Xt: 801 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 802 return; 803 804 case MISCREG_FPSCR: 805 { 806 const uint32_t ones = (uint32_t)(-1); 807 FPSCR fpscrMask = 0; 808 fpscrMask.ioc = ones; 809 fpscrMask.dzc = ones; 810 fpscrMask.ofc = ones; 811 fpscrMask.ufc = ones; 812 fpscrMask.ixc = ones; 813 fpscrMask.idc = ones; 814 fpscrMask.ioe = ones; 815 fpscrMask.dze = ones; 816 fpscrMask.ofe = ones; 817 fpscrMask.ufe = ones; 818 fpscrMask.ixe = ones; 819 fpscrMask.ide = ones; 820 fpscrMask.len = ones; 821 fpscrMask.stride = ones; 822 fpscrMask.rMode = ones; 823 fpscrMask.fz = ones; 824 fpscrMask.dn = ones; 825 fpscrMask.ahp = ones; 826 fpscrMask.qc = ones; 827 fpscrMask.v = ones; 828 fpscrMask.c = ones; 829 fpscrMask.z = ones; 830 fpscrMask.n = ones; 831 newVal = (newVal & (uint32_t)fpscrMask) | 832 (readMiscRegNoEffect(MISCREG_FPSCR) & 833 ~(uint32_t)fpscrMask); 834 tc->getDecoderPtr()->setContext(newVal); 835 } 836 break; 837 case MISCREG_FPSR: 838 { 839 const uint32_t ones = (uint32_t)(-1); 840 FPSCR fpscrMask = 0; 841 fpscrMask.ioc = ones; 842 fpscrMask.dzc = ones; 843 fpscrMask.ofc = ones; 844 fpscrMask.ufc = ones; 845 fpscrMask.ixc = ones; 846 fpscrMask.idc = ones; 847 fpscrMask.qc = ones; 848 fpscrMask.v = ones; 849 fpscrMask.c = ones; 850 fpscrMask.z = ones; 851 fpscrMask.n = ones; 852 newVal = (newVal & (uint32_t)fpscrMask) | 853 (readMiscRegNoEffect(MISCREG_FPSCR) & 854 ~(uint32_t)fpscrMask); 855 misc_reg = MISCREG_FPSCR; 856 } 857 break; 858 case MISCREG_FPCR: 859 { 860 const uint32_t ones = (uint32_t)(-1); 861 FPSCR fpscrMask = 0; 862 fpscrMask.len = ones; 863 fpscrMask.stride = ones; 864 fpscrMask.rMode = ones; 865 fpscrMask.fz = ones; 866 fpscrMask.dn = ones; 867 fpscrMask.ahp = ones; 868 newVal = (newVal & (uint32_t)fpscrMask) | 869 (readMiscRegNoEffect(MISCREG_FPSCR) & 870 ~(uint32_t)fpscrMask); 871 misc_reg = MISCREG_FPSCR; 872 } 873 break; 874 case MISCREG_CPSR_Q: 875 { 876 assert(!(newVal & ~CpsrMaskQ)); 877 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 878 misc_reg = MISCREG_CPSR; 879 } 880 break; 881 case MISCREG_FPSCR_QC: 882 { 883 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 884 (newVal & FpscrQcMask); 885 misc_reg = MISCREG_FPSCR; 886 } 887 break; 888 case MISCREG_FPSCR_EXC: 889 { 890 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 891 (newVal & FpscrExcMask); 892 misc_reg = MISCREG_FPSCR; 893 } 894 break; 895 case MISCREG_FPEXC: 896 { 897 // vfpv3 architecture, section B.6.1 of DDI04068 898 // bit 29 - valid only if fpexc[31] is 0 899 const uint32_t fpexcMask = 0x60000000; 900 newVal = (newVal & fpexcMask) | 901 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 902 } 903 break; 904 case MISCREG_HCR: 905 { 906 if (!haveVirtualization) 907 return; 908 } 909 break; 910 case MISCREG_IFSR: 911 { 912 // ARM ARM (ARM DDI 0406C.b) B4.1.96 913 const uint32_t ifsrMask = 914 mask(31, 13) | mask(11, 11) | mask(8, 6); 915 newVal = newVal & ~ifsrMask; 916 } 917 break; 918 case MISCREG_DFSR: 919 { 920 // ARM ARM (ARM DDI 0406C.b) B4.1.52 921 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 922 newVal = newVal & ~dfsrMask; 923 } 924 break; 925 case MISCREG_AMAIR0: 926 case MISCREG_AMAIR1: 927 { 928 // ARM ARM (ARM DDI 0406C.b) B4.1.5 929 // Valid only with LPAE 930 if (!haveLPAE) 931 return; 932 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 933 } 934 break; 935 case MISCREG_SCR: 936 getITBPtr(tc)->invalidateMiscReg(); 937 getDTBPtr(tc)->invalidateMiscReg(); 938 break; 939 case MISCREG_SCTLR: 940 { 941 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 942 scr = readMiscRegNoEffect(MISCREG_SCR); 943 944 MiscRegIndex sctlr_idx; 945 if (haveSecurity && !highestELIs64 && !scr.ns) { 946 sctlr_idx = MISCREG_SCTLR_S; 947 } else { 948 sctlr_idx = MISCREG_SCTLR_NS; 949 } 950 951 SCTLR sctlr = miscRegs[sctlr_idx]; 952 SCTLR new_sctlr = newVal; 953 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 954 miscRegs[sctlr_idx] = (MiscReg)new_sctlr; 955 getITBPtr(tc)->invalidateMiscReg(); 956 getDTBPtr(tc)->invalidateMiscReg(); 957 } 958 case MISCREG_MIDR: 959 case MISCREG_ID_PFR0: 960 case MISCREG_ID_PFR1: 961 case MISCREG_ID_DFR0: 962 case MISCREG_ID_MMFR0: 963 case MISCREG_ID_MMFR1: 964 case MISCREG_ID_MMFR2: 965 case MISCREG_ID_MMFR3: 966 case MISCREG_ID_ISAR0: 967 case MISCREG_ID_ISAR1: 968 case MISCREG_ID_ISAR2: 969 case MISCREG_ID_ISAR3: 970 case MISCREG_ID_ISAR4: 971 case MISCREG_ID_ISAR5: 972 973 case MISCREG_MPIDR: 974 case MISCREG_FPSID: 975 case MISCREG_TLBTR: 976 case MISCREG_MVFR0: 977 case MISCREG_MVFR1: 978 979 case MISCREG_ID_AA64AFR0_EL1: 980 case MISCREG_ID_AA64AFR1_EL1: 981 case MISCREG_ID_AA64DFR0_EL1: 982 case MISCREG_ID_AA64DFR1_EL1: 983 case MISCREG_ID_AA64ISAR0_EL1: 984 case MISCREG_ID_AA64ISAR1_EL1: 985 case MISCREG_ID_AA64MMFR0_EL1: 986 case MISCREG_ID_AA64MMFR1_EL1: 987 case MISCREG_ID_AA64PFR0_EL1: 988 case MISCREG_ID_AA64PFR1_EL1: 989 // ID registers are constants. 990 return; 991 992 // TLB Invalidate All 993 case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 994 { 995 assert32(tc); 996 scr = readMiscReg(MISCREG_SCR, tc); 997 998 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 999 tlbiOp(tc); 1000 return; 1001 } 1002 // TLB Invalidate All, Inner Shareable 1003 case MISCREG_TLBIALLIS: 1004 { 1005 assert32(tc); 1006 scr = readMiscReg(MISCREG_SCR, tc); 1007 1008 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1009 tlbiOp.broadcast(tc); 1010 return; 1011 } 1012 // Instruction TLB Invalidate All 1013 case MISCREG_ITLBIALL: 1014 { 1015 assert32(tc); 1016 scr = readMiscReg(MISCREG_SCR, tc); 1017 1018 ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1019 tlbiOp(tc); 1020 return; 1021 } 1022 // Data TLB Invalidate All 1023 case MISCREG_DTLBIALL: 1024 { 1025 assert32(tc); 1026 scr = readMiscReg(MISCREG_SCR, tc); 1027 1028 DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1029 tlbiOp(tc); 1030 return; 1031 } 1032 // TLB Invalidate by VA 1033 // mcr tlbimval(is) is invalidating all matching entries 1034 // regardless of the level of lookup, since in gem5 we cache 1035 // in the tlb the last level of lookup only. 1036 case MISCREG_TLBIMVA: 1037 case MISCREG_TLBIMVAL: 1038 { 1039 assert32(tc); 1040 scr = readMiscReg(MISCREG_SCR, tc); 1041 1042 TLBIMVA tlbiOp(EL1, 1043 haveSecurity && !scr.ns, 1044 mbits(newVal, 31, 12), 1045 bits(newVal, 7,0)); 1046 1047 tlbiOp(tc); 1048 return; 1049 } 1050 // TLB Invalidate by VA, Inner Shareable 1051 case MISCREG_TLBIMVAIS: 1052 case MISCREG_TLBIMVALIS: 1053 { 1054 assert32(tc); 1055 scr = readMiscReg(MISCREG_SCR, tc); 1056 1057 TLBIMVA tlbiOp(EL1, 1058 haveSecurity && !scr.ns, 1059 mbits(newVal, 31, 12), 1060 bits(newVal, 7,0)); 1061 1062 tlbiOp.broadcast(tc); 1063 return; 1064 } 1065 // TLB Invalidate by ASID match 1066 case MISCREG_TLBIASID: 1067 { 1068 assert32(tc); 1069 scr = readMiscReg(MISCREG_SCR, tc); 1070 1071 TLBIASID tlbiOp(EL1, 1072 haveSecurity && !scr.ns, 1073 bits(newVal, 7,0)); 1074 1075 tlbiOp(tc); 1076 return; 1077 } 1078 // TLB Invalidate by ASID match, Inner Shareable 1079 case MISCREG_TLBIASIDIS: 1080 { 1081 assert32(tc); 1082 scr = readMiscReg(MISCREG_SCR, tc); 1083 1084 TLBIASID tlbiOp(EL1, 1085 haveSecurity && !scr.ns, 1086 bits(newVal, 7,0)); 1087 1088 tlbiOp.broadcast(tc); 1089 return; 1090 } 1091 // mcr tlbimvaal(is) is invalidating all matching entries 1092 // regardless of the level of lookup, since in gem5 we cache 1093 // in the tlb the last level of lookup only. 1094 // TLB Invalidate by VA, All ASID 1095 case MISCREG_TLBIMVAA: 1096 case MISCREG_TLBIMVAAL: 1097 { 1098 assert32(tc); 1099 scr = readMiscReg(MISCREG_SCR, tc); 1100 1101 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1102 mbits(newVal, 31,12), false); 1103 1104 tlbiOp(tc); 1105 return; 1106 } 1107 // TLB Invalidate by VA, All ASID, Inner Shareable 1108 case MISCREG_TLBIMVAAIS: 1109 case MISCREG_TLBIMVAALIS: 1110 { 1111 assert32(tc); 1112 scr = readMiscReg(MISCREG_SCR, tc); 1113 1114 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1115 mbits(newVal, 31,12), false); 1116 1117 tlbiOp.broadcast(tc); 1118 return; 1119 } 1120 // mcr tlbimvalh(is) is invalidating all matching entries 1121 // regardless of the level of lookup, since in gem5 we cache 1122 // in the tlb the last level of lookup only. 1123 // TLB Invalidate by VA, Hyp mode 1124 case MISCREG_TLBIMVAH: 1125 case MISCREG_TLBIMVALH: 1126 { 1127 assert32(tc); 1128 scr = readMiscReg(MISCREG_SCR, tc); 1129 1130 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1131 mbits(newVal, 31,12), true); 1132 1133 tlbiOp(tc); 1134 return; 1135 } 1136 // TLB Invalidate by VA, Hyp mode, Inner Shareable 1137 case MISCREG_TLBIMVAHIS: 1138 case MISCREG_TLBIMVALHIS: 1139 { 1140 assert32(tc); 1141 scr = readMiscReg(MISCREG_SCR, tc); 1142 1143 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1144 mbits(newVal, 31,12), true); 1145 1146 tlbiOp.broadcast(tc); 1147 return; 1148 } 1149 // mcr tlbiipas2l(is) is invalidating all matching entries 1150 // regardless of the level of lookup, since in gem5 we cache 1151 // in the tlb the last level of lookup only. 1152 // TLB Invalidate by Intermediate Physical Address, Stage 2 1153 case MISCREG_TLBIIPAS2: 1154 case MISCREG_TLBIIPAS2L: 1155 { 1156 assert32(tc); 1157 scr = readMiscReg(MISCREG_SCR, tc); 1158 1159 TLBIIPA tlbiOp(EL1, 1160 haveSecurity && !scr.ns, 1161 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1162 1163 tlbiOp(tc); 1164 return; 1165 } 1166 // TLB Invalidate by Intermediate Physical Address, Stage 2, 1167 // Inner Shareable 1168 case MISCREG_TLBIIPAS2IS: 1169 case MISCREG_TLBIIPAS2LIS: 1170 { 1171 assert32(tc); 1172 scr = readMiscReg(MISCREG_SCR, tc); 1173 1174 TLBIIPA tlbiOp(EL1, 1175 haveSecurity && !scr.ns, 1176 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1177 1178 tlbiOp.broadcast(tc); 1179 return; 1180 } 1181 // Instruction TLB Invalidate by VA 1182 case MISCREG_ITLBIMVA: 1183 { 1184 assert32(tc); 1185 scr = readMiscReg(MISCREG_SCR, tc); 1186 1187 ITLBIMVA tlbiOp(EL1, 1188 haveSecurity && !scr.ns, 1189 mbits(newVal, 31, 12), 1190 bits(newVal, 7,0)); 1191 1192 tlbiOp(tc); 1193 return; 1194 } 1195 // Data TLB Invalidate by VA 1196 case MISCREG_DTLBIMVA: 1197 { 1198 assert32(tc); 1199 scr = readMiscReg(MISCREG_SCR, tc); 1200 1201 DTLBIMVA tlbiOp(EL1, 1202 haveSecurity && !scr.ns, 1203 mbits(newVal, 31, 12), 1204 bits(newVal, 7,0)); 1205 1206 tlbiOp(tc); 1207 return; 1208 } 1209 // Instruction TLB Invalidate by ASID match 1210 case MISCREG_ITLBIASID: 1211 { 1212 assert32(tc); 1213 scr = readMiscReg(MISCREG_SCR, tc); 1214 1215 ITLBIASID tlbiOp(EL1, 1216 haveSecurity && !scr.ns, 1217 bits(newVal, 7,0)); 1218 1219 tlbiOp(tc); 1220 return; 1221 } 1222 // Data TLB Invalidate by ASID match 1223 case MISCREG_DTLBIASID: 1224 { 1225 assert32(tc); 1226 scr = readMiscReg(MISCREG_SCR, tc); 1227 1228 DTLBIASID tlbiOp(EL1, 1229 haveSecurity && !scr.ns, 1230 bits(newVal, 7,0)); 1231 1232 tlbiOp(tc); 1233 return; 1234 } 1235 // TLB Invalidate All, Non-Secure Non-Hyp 1236 case MISCREG_TLBIALLNSNH: 1237 { 1238 assert32(tc); 1239 1240 TLBIALLN tlbiOp(EL1, false); 1241 tlbiOp(tc); 1242 return; 1243 } 1244 // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable 1245 case MISCREG_TLBIALLNSNHIS: 1246 { 1247 assert32(tc); 1248 1249 TLBIALLN tlbiOp(EL1, false); 1250 tlbiOp.broadcast(tc); 1251 return; 1252 } 1253 // TLB Invalidate All, Hyp mode 1254 case MISCREG_TLBIALLH: 1255 { 1256 assert32(tc); 1257 1258 TLBIALLN tlbiOp(EL1, true); 1259 tlbiOp(tc); 1260 return; 1261 } 1262 // TLB Invalidate All, Hyp mode, Inner Shareable 1263 case MISCREG_TLBIALLHIS: 1264 { 1265 assert32(tc); 1266 1267 TLBIALLN tlbiOp(EL1, true); 1268 tlbiOp.broadcast(tc); 1269 return; 1270 } 1271 // AArch64 TLB Invalidate All, EL3 1272 case MISCREG_TLBI_ALLE3: 1273 { 1274 assert64(tc); 1275 1276 TLBIALL tlbiOp(EL3, true); 1277 tlbiOp(tc); 1278 return; 1279 } 1280 // AArch64 TLB Invalidate All, EL3, Inner Shareable 1281 case MISCREG_TLBI_ALLE3IS: 1282 { 1283 assert64(tc); 1284 1285 TLBIALL tlbiOp(EL3, true); 1286 tlbiOp.broadcast(tc); 1287 return; 1288 } 1289 // @todo: uncomment this to enable Virtualization 1290 // case MISCREG_TLBI_ALLE2IS: 1291 // case MISCREG_TLBI_ALLE2: 1292 // AArch64 TLB Invalidate All, EL1 1293 case MISCREG_TLBI_ALLE1: 1294 case MISCREG_TLBI_VMALLE1: 1295 case MISCREG_TLBI_VMALLS12E1: 1296 // @todo: handle VMID and stage 2 to enable Virtualization 1297 { 1298 assert64(tc); 1299 scr = readMiscReg(MISCREG_SCR, tc); 1300 1301 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1302 tlbiOp(tc); 1303 return; 1304 } 1305 // AArch64 TLB Invalidate All, EL1, Inner Shareable 1306 case MISCREG_TLBI_ALLE1IS: 1307 case MISCREG_TLBI_VMALLE1IS: 1308 case MISCREG_TLBI_VMALLS12E1IS: 1309 // @todo: handle VMID and stage 2 to enable Virtualization 1310 { 1311 assert64(tc); 1312 scr = readMiscReg(MISCREG_SCR, tc); 1313 1314 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 1315 tlbiOp.broadcast(tc); 1316 return; 1317 } 1318 // VAEx(IS) and VALEx(IS) are the same because TLBs 1319 // only store entries 1320 // from the last level of translation table walks 1321 // @todo: handle VMID to enable Virtualization 1322 // AArch64 TLB Invalidate by VA, EL3 1323 case MISCREG_TLBI_VAE3_Xt: 1324 case MISCREG_TLBI_VALE3_Xt: 1325 { 1326 assert64(tc); 1327 1328 TLBIMVA tlbiOp(EL3, true, 1329 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1330 0xbeef); 1331 tlbiOp(tc); 1332 return; 1333 } 1334 // AArch64 TLB Invalidate by VA, EL3, Inner Shareable 1335 case MISCREG_TLBI_VAE3IS_Xt: 1336 case MISCREG_TLBI_VALE3IS_Xt: 1337 { 1338 assert64(tc); 1339 1340 TLBIMVA tlbiOp(EL3, true, 1341 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1342 0xbeef); 1343 1344 tlbiOp.broadcast(tc); 1345 return; 1346 } 1347 // AArch64 TLB Invalidate by VA, EL2 1348 case MISCREG_TLBI_VAE2_Xt: 1349 case MISCREG_TLBI_VALE2_Xt: 1350 { 1351 assert64(tc); 1352 scr = readMiscReg(MISCREG_SCR, tc); 1353 1354 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1355 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1356 0xbeef); 1357 tlbiOp(tc); 1358 return; 1359 } 1360 // AArch64 TLB Invalidate by VA, EL2, Inner Shareable 1361 case MISCREG_TLBI_VAE2IS_Xt: 1362 case MISCREG_TLBI_VALE2IS_Xt: 1363 { 1364 assert64(tc); 1365 scr = readMiscReg(MISCREG_SCR, tc); 1366 1367 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 1368 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1369 0xbeef); 1370 1371 tlbiOp.broadcast(tc); 1372 return; 1373 } 1374 // AArch64 TLB Invalidate by VA, EL1 1375 case MISCREG_TLBI_VAE1_Xt: 1376 case MISCREG_TLBI_VALE1_Xt: 1377 { 1378 assert64(tc); 1379 scr = readMiscReg(MISCREG_SCR, tc); 1380 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1381 bits(newVal, 55, 48); 1382 1383 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1384 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1385 asid); 1386 1387 tlbiOp(tc); 1388 return; 1389 } 1390 // AArch64 TLB Invalidate by VA, EL1, Inner Shareable 1391 case MISCREG_TLBI_VAE1IS_Xt: 1392 case MISCREG_TLBI_VALE1IS_Xt: 1393 { 1394 assert64(tc); 1395 scr = readMiscReg(MISCREG_SCR, tc); 1396 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1397 bits(newVal, 55, 48); 1398 1399 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 1400 static_cast<Addr>(bits(newVal, 43, 0)) << 12, 1401 asid); 1402 1403 tlbiOp.broadcast(tc); 1404 return; 1405 } 1406 // AArch64 TLB Invalidate by ASID, EL1 1407 // @todo: handle VMID to enable Virtualization 1408 case MISCREG_TLBI_ASIDE1_Xt: 1409 { 1410 assert64(tc); 1411 scr = readMiscReg(MISCREG_SCR, tc); 1412 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1413 bits(newVal, 55, 48); 1414 1415 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1416 tlbiOp(tc); 1417 return; 1418 } 1419 // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable 1420 case MISCREG_TLBI_ASIDE1IS_Xt: 1421 { 1422 assert64(tc); 1423 scr = readMiscReg(MISCREG_SCR, tc); 1424 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 1425 bits(newVal, 55, 48); 1426 1427 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 1428 tlbiOp.broadcast(tc); 1429 return; 1430 } 1431 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 1432 // entries from the last level of translation table walks 1433 // AArch64 TLB Invalidate by VA, All ASID, EL1 1434 case MISCREG_TLBI_VAAE1_Xt: 1435 case MISCREG_TLBI_VAALE1_Xt: 1436 { 1437 assert64(tc); 1438 scr = readMiscReg(MISCREG_SCR, tc); 1439 1440 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1441 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 1442 1443 tlbiOp(tc); 1444 return; 1445 } 1446 // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable 1447 case MISCREG_TLBI_VAAE1IS_Xt: 1448 case MISCREG_TLBI_VAALE1IS_Xt: 1449 { 1450 assert64(tc); 1451 scr = readMiscReg(MISCREG_SCR, tc); 1452 1453 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 1454 static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 1455 1456 tlbiOp.broadcast(tc); 1457 return; 1458 } 1459 // AArch64 TLB Invalidate by Intermediate Physical Address, 1460 // Stage 2, EL1 1461 case MISCREG_TLBI_IPAS2E1_Xt: 1462 case MISCREG_TLBI_IPAS2LE1_Xt: 1463 { 1464 assert64(tc); 1465 scr = readMiscReg(MISCREG_SCR, tc); 1466 1467 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1468 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1469 1470 tlbiOp(tc); 1471 return; 1472 } 1473 // AArch64 TLB Invalidate by Intermediate Physical Address, 1474 // Stage 2, EL1, Inner Shareable 1475 case MISCREG_TLBI_IPAS2E1IS_Xt: 1476 case MISCREG_TLBI_IPAS2LE1IS_Xt: 1477 { 1478 assert64(tc); 1479 scr = readMiscReg(MISCREG_SCR, tc); 1480 1481 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 1482 static_cast<Addr>(bits(newVal, 35, 0)) << 12); 1483 1484 tlbiOp.broadcast(tc); 1485 return; 1486 } 1487 case MISCREG_ACTLR: 1488 warn("Not doing anything for write of miscreg ACTLR\n"); 1489 break; 1490 1491 case MISCREG_PMXEVTYPER_PMCCFILTR: 1492 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 1493 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 1494 case MISCREG_PMCR ... MISCREG_PMOVSSET: 1495 pmu->setMiscReg(misc_reg, newVal); 1496 break; 1497 1498 1499 case MISCREG_HSTR: // TJDBX, now redifined to be RES0 1500 { 1501 HSTR hstrMask = 0; 1502 hstrMask.tjdbx = 1; 1503 newVal &= ~((uint32_t) hstrMask); 1504 break; 1505 } 1506 case MISCREG_HCPTR: 1507 { 1508 // If a CP bit in NSACR is 0 then the corresponding bit in 1509 // HCPTR is RAO/WI. Same applies to NSASEDIS 1510 secure_lookup = haveSecurity && 1511 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 1512 readMiscRegNoEffect(MISCREG_CPSR)); 1513 if (!secure_lookup) { 1514 MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 1515 MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 1516 newVal = (newVal & ~mask) | (oldValue & mask); 1517 } 1518 break; 1519 } 1520 case MISCREG_HDFAR: // alias for secure DFAR 1521 misc_reg = MISCREG_DFAR_S; 1522 break; 1523 case MISCREG_HIFAR: // alias for secure IFAR 1524 misc_reg = MISCREG_IFAR_S; 1525 break; 1526 case MISCREG_ATS1CPR: 1527 case MISCREG_ATS1CPW: 1528 case MISCREG_ATS1CUR: 1529 case MISCREG_ATS1CUW: 1530 case MISCREG_ATS12NSOPR: 1531 case MISCREG_ATS12NSOPW: 1532 case MISCREG_ATS12NSOUR: 1533 case MISCREG_ATS12NSOUW: 1534 case MISCREG_ATS1HR: 1535 case MISCREG_ATS1HW: 1536 { 1537 Request::Flags flags = 0; 1538 BaseTLB::Mode mode = BaseTLB::Read; 1539 TLB::ArmTranslationType tranType = TLB::NormalTran; 1540 Fault fault; 1541 switch(misc_reg) { 1542 case MISCREG_ATS1CPR: 1543 flags = TLB::MustBeOne; 1544 tranType = TLB::S1CTran; 1545 mode = BaseTLB::Read; 1546 break; 1547 case MISCREG_ATS1CPW: 1548 flags = TLB::MustBeOne; 1549 tranType = TLB::S1CTran; 1550 mode = BaseTLB::Write; 1551 break; 1552 case MISCREG_ATS1CUR: 1553 flags = TLB::MustBeOne | TLB::UserMode; 1554 tranType = TLB::S1CTran; 1555 mode = BaseTLB::Read; 1556 break; 1557 case MISCREG_ATS1CUW: 1558 flags = TLB::MustBeOne | TLB::UserMode; 1559 tranType = TLB::S1CTran; 1560 mode = BaseTLB::Write; 1561 break; 1562 case MISCREG_ATS12NSOPR: 1563 if (!haveSecurity) 1564 panic("Security Extensions required for ATS12NSOPR"); 1565 flags = TLB::MustBeOne; 1566 tranType = TLB::S1S2NsTran; 1567 mode = BaseTLB::Read; 1568 break; 1569 case MISCREG_ATS12NSOPW: 1570 if (!haveSecurity) 1571 panic("Security Extensions required for ATS12NSOPW"); 1572 flags = TLB::MustBeOne; 1573 tranType = TLB::S1S2NsTran; 1574 mode = BaseTLB::Write; 1575 break; 1576 case MISCREG_ATS12NSOUR: 1577 if (!haveSecurity) 1578 panic("Security Extensions required for ATS12NSOUR"); 1579 flags = TLB::MustBeOne | TLB::UserMode; 1580 tranType = TLB::S1S2NsTran; 1581 mode = BaseTLB::Read; 1582 break; 1583 case MISCREG_ATS12NSOUW: 1584 if (!haveSecurity) 1585 panic("Security Extensions required for ATS12NSOUW"); 1586 flags = TLB::MustBeOne | TLB::UserMode; 1587 tranType = TLB::S1S2NsTran; 1588 mode = BaseTLB::Write; 1589 break; 1590 case MISCREG_ATS1HR: // only really useful from secure mode. 1591 flags = TLB::MustBeOne; 1592 tranType = TLB::HypMode; 1593 mode = BaseTLB::Read; 1594 break; 1595 case MISCREG_ATS1HW: 1596 flags = TLB::MustBeOne; 1597 tranType = TLB::HypMode; 1598 mode = BaseTLB::Write; 1599 break; 1600 } 1601 // If we're in timing mode then doing the translation in 1602 // functional mode then we're slightly distorting performance 1603 // results obtained from simulations. The translation should be 1604 // done in the same mode the core is running in. NOTE: This 1605 // can't be an atomic translation because that causes problems 1606 // with unexpected atomic snoop requests. 1607 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1608 Request req(0, val, 0, flags, Request::funcMasterId, 1609 tc->pcState().pc(), tc->contextId()); 1610 fault = getDTBPtr(tc)->translateFunctional( 1611 &req, tc, mode, tranType); 1612 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1613 HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 1614 1615 MiscReg newVal; 1616 if (fault == NoFault) { 1617 Addr paddr = req.getPaddr(); 1618 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 1619 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 1620 newVal = (paddr & mask(39, 12)) | 1621 (getDTBPtr(tc)->getAttr()); 1622 } else { 1623 newVal = (paddr & 0xfffff000) | 1624 (getDTBPtr(tc)->getAttr()); 1625 } 1626 DPRINTF(MiscRegs, 1627 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 1628 val, newVal); 1629 } else { 1630 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1631 armFault->update(tc); 1632 // Set fault bit and FSR 1633 FSR fsr = armFault->getFsr(tc); 1634 1635 newVal = ((fsr >> 9) & 1) << 11; 1636 if (newVal) { 1637 // LPAE - rearange fault status 1638 newVal |= ((fsr >> 0) & 0x3f) << 1; 1639 } else { 1640 // VMSA - rearange fault status 1641 newVal |= ((fsr >> 0) & 0xf) << 1; 1642 newVal |= ((fsr >> 10) & 0x1) << 5; 1643 newVal |= ((fsr >> 12) & 0x1) << 6; 1644 } 1645 newVal |= 0x1; // F bit 1646 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1647 newVal |= armFault->isStage2() ? 0x200 : 0; 1648 DPRINTF(MiscRegs, 1649 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 1650 val, fsr, newVal); 1651 } 1652 setMiscRegNoEffect(MISCREG_PAR, newVal); 1653 return; 1654 } 1655 case MISCREG_TTBCR: 1656 { 1657 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1658 const uint32_t ones = (uint32_t)(-1); 1659 TTBCR ttbcrMask = 0; 1660 TTBCR ttbcrNew = newVal; 1661 1662 // ARM DDI 0406C.b, ARMv7-32 1663 ttbcrMask.n = ones; // T0SZ 1664 if (haveSecurity) { 1665 ttbcrMask.pd0 = ones; 1666 ttbcrMask.pd1 = ones; 1667 } 1668 ttbcrMask.epd0 = ones; 1669 ttbcrMask.irgn0 = ones; 1670 ttbcrMask.orgn0 = ones; 1671 ttbcrMask.sh0 = ones; 1672 ttbcrMask.ps = ones; // T1SZ 1673 ttbcrMask.a1 = ones; 1674 ttbcrMask.epd1 = ones; 1675 ttbcrMask.irgn1 = ones; 1676 ttbcrMask.orgn1 = ones; 1677 ttbcrMask.sh1 = ones; 1678 if (haveLPAE) 1679 ttbcrMask.eae = ones; 1680 1681 if (haveLPAE && ttbcrNew.eae) { 1682 newVal = newVal & ttbcrMask; 1683 } else { 1684 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 1685 } 1686 // Invalidate TLB MiscReg 1687 getITBPtr(tc)->invalidateMiscReg(); 1688 getDTBPtr(tc)->invalidateMiscReg(); 1689 break; 1690 } 1691 case MISCREG_TTBR0: 1692 case MISCREG_TTBR1: 1693 { 1694 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1695 if (haveLPAE) { 1696 if (ttbcr.eae) { 1697 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 1698 // ARMv8 AArch32 bit 63-56 only 1699 uint64_t ttbrMask = mask(63,56) | mask(47,40); 1700 newVal = (newVal & (~ttbrMask)); 1701 } 1702 } 1703 // Invalidate TLB MiscReg 1704 getITBPtr(tc)->invalidateMiscReg(); 1705 getDTBPtr(tc)->invalidateMiscReg(); 1706 break; 1707 } 1708 case MISCREG_SCTLR_EL1: 1709 case MISCREG_CONTEXTIDR: 1710 case MISCREG_PRRR: 1711 case MISCREG_NMRR: 1712 case MISCREG_MAIR0: 1713 case MISCREG_MAIR1: 1714 case MISCREG_DACR: 1715 case MISCREG_VTTBR: 1716 case MISCREG_SCR_EL3: 1717 case MISCREG_HCR_EL2: 1718 case MISCREG_TCR_EL1: 1719 case MISCREG_TCR_EL2: 1720 case MISCREG_TCR_EL3: 1721 case MISCREG_SCTLR_EL2: 1722 case MISCREG_SCTLR_EL3: 1723 case MISCREG_HSCTLR: 1724 case MISCREG_TTBR0_EL1: 1725 case MISCREG_TTBR1_EL1: 1726 case MISCREG_TTBR0_EL2: 1727 case MISCREG_TTBR0_EL3: 1728 getITBPtr(tc)->invalidateMiscReg(); 1729 getDTBPtr(tc)->invalidateMiscReg(); 1730 break; 1731 case MISCREG_NZCV: 1732 { 1733 CPSR cpsr = val; 1734 1735 tc->setCCReg(CCREG_NZ, cpsr.nz); 1736 tc->setCCReg(CCREG_C, cpsr.c); 1737 tc->setCCReg(CCREG_V, cpsr.v); 1738 } 1739 break; 1740 case MISCREG_DAIF: 1741 { 1742 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1743 cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 1744 newVal = cpsr; 1745 misc_reg = MISCREG_CPSR; 1746 } 1747 break; 1748 case MISCREG_SP_EL0: 1749 tc->setIntReg(INTREG_SP0, newVal); 1750 break; 1751 case MISCREG_SP_EL1: 1752 tc->setIntReg(INTREG_SP1, newVal); 1753 break; 1754 case MISCREG_SP_EL2: 1755 tc->setIntReg(INTREG_SP2, newVal); 1756 break; 1757 case MISCREG_SPSEL: 1758 { 1759 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1760 cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 1761 newVal = cpsr; 1762 misc_reg = MISCREG_CPSR; 1763 } 1764 break; 1765 case MISCREG_CURRENTEL: 1766 { 1767 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1768 cpsr.el = (uint8_t) ((CPSR) newVal).el; 1769 newVal = cpsr; 1770 misc_reg = MISCREG_CPSR; 1771 } 1772 break; 1773 case MISCREG_AT_S1E1R_Xt: 1774 case MISCREG_AT_S1E1W_Xt: 1775 case MISCREG_AT_S1E0R_Xt: 1776 case MISCREG_AT_S1E0W_Xt: 1777 case MISCREG_AT_S1E2R_Xt: 1778 case MISCREG_AT_S1E2W_Xt: 1779 case MISCREG_AT_S12E1R_Xt: 1780 case MISCREG_AT_S12E1W_Xt: 1781 case MISCREG_AT_S12E0R_Xt: 1782 case MISCREG_AT_S12E0W_Xt: 1783 case MISCREG_AT_S1E3R_Xt: 1784 case MISCREG_AT_S1E3W_Xt: 1785 { 1786 RequestPtr req = new Request; 1787 Request::Flags flags = 0; 1788 BaseTLB::Mode mode = BaseTLB::Read; 1789 TLB::ArmTranslationType tranType = TLB::NormalTran; 1790 Fault fault; 1791 switch(misc_reg) { 1792 case MISCREG_AT_S1E1R_Xt: 1793 flags = TLB::MustBeOne; 1794 tranType = TLB::S1E1Tran; 1795 mode = BaseTLB::Read; 1796 break; 1797 case MISCREG_AT_S1E1W_Xt: 1798 flags = TLB::MustBeOne; 1799 tranType = TLB::S1E1Tran; 1800 mode = BaseTLB::Write; 1801 break; 1802 case MISCREG_AT_S1E0R_Xt: 1803 flags = TLB::MustBeOne | TLB::UserMode; 1804 tranType = TLB::S1E0Tran; 1805 mode = BaseTLB::Read; 1806 break; 1807 case MISCREG_AT_S1E0W_Xt: 1808 flags = TLB::MustBeOne | TLB::UserMode; 1809 tranType = TLB::S1E0Tran; 1810 mode = BaseTLB::Write; 1811 break; 1812 case MISCREG_AT_S1E2R_Xt: 1813 flags = TLB::MustBeOne; 1814 tranType = TLB::S1E2Tran; 1815 mode = BaseTLB::Read; 1816 break; 1817 case MISCREG_AT_S1E2W_Xt: 1818 flags = TLB::MustBeOne; 1819 tranType = TLB::S1E2Tran; 1820 mode = BaseTLB::Write; 1821 break; 1822 case MISCREG_AT_S12E0R_Xt: 1823 flags = TLB::MustBeOne | TLB::UserMode; 1824 tranType = TLB::S12E0Tran; 1825 mode = BaseTLB::Read; 1826 break; 1827 case MISCREG_AT_S12E0W_Xt: 1828 flags = TLB::MustBeOne | TLB::UserMode; 1829 tranType = TLB::S12E0Tran; 1830 mode = BaseTLB::Write; 1831 break; 1832 case MISCREG_AT_S12E1R_Xt: 1833 flags = TLB::MustBeOne; 1834 tranType = TLB::S12E1Tran; 1835 mode = BaseTLB::Read; 1836 break; 1837 case MISCREG_AT_S12E1W_Xt: 1838 flags = TLB::MustBeOne; 1839 tranType = TLB::S12E1Tran; 1840 mode = BaseTLB::Write; 1841 break; 1842 case MISCREG_AT_S1E3R_Xt: 1843 flags = TLB::MustBeOne; 1844 tranType = TLB::S1E3Tran; 1845 mode = BaseTLB::Read; 1846 break; 1847 case MISCREG_AT_S1E3W_Xt: 1848 flags = TLB::MustBeOne; 1849 tranType = TLB::S1E3Tran; 1850 mode = BaseTLB::Write; 1851 break; 1852 } 1853 // If we're in timing mode then doing the translation in 1854 // functional mode then we're slightly distorting performance 1855 // results obtained from simulations. The translation should be 1856 // done in the same mode the core is running in. NOTE: This 1857 // can't be an atomic translation because that causes problems 1858 // with unexpected atomic snoop requests. 1859 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1860 req->setVirt(0, val, 0, flags, Request::funcMasterId, 1861 tc->pcState().pc()); 1862 req->setContext(tc->contextId()); 1863 fault = getDTBPtr(tc)->translateFunctional(req, tc, mode, 1864 tranType); 1865 1866 MiscReg newVal; 1867 if (fault == NoFault) { 1868 Addr paddr = req->getPaddr(); 1869 uint64_t attr = getDTBPtr(tc)->getAttr(); 1870 uint64_t attr1 = attr >> 56; 1871 if (!attr1 || attr1 ==0x44) { 1872 attr |= 0x100; 1873 attr &= ~ uint64_t(0x80); 1874 } 1875 newVal = (paddr & mask(47, 12)) | attr; 1876 DPRINTF(MiscRegs, 1877 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 1878 val, newVal); 1879 } else { 1880 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1881 armFault->update(tc); 1882 // Set fault bit and FSR 1883 FSR fsr = armFault->getFsr(tc); 1884 1885 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1886 if (cpsr.width) { // AArch32 1887 newVal = ((fsr >> 9) & 1) << 11; 1888 // rearrange fault status 1889 newVal |= ((fsr >> 0) & 0x3f) << 1; 1890 newVal |= 0x1; // F bit 1891 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1892 newVal |= armFault->isStage2() ? 0x200 : 0; 1893 } else { // AArch64 1894 newVal = 1; // F bit 1895 newVal |= fsr << 1; // FST 1896 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit. 1897 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 1898 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 1899 newVal |= 1 << 11; // RES1 1900 } 1901 DPRINTF(MiscRegs, 1902 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 1903 val, fsr, newVal); 1904 } 1905 delete req; 1906 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 1907 return; 1908 } 1909 case MISCREG_SPSR_EL3: 1910 case MISCREG_SPSR_EL2: 1911 case MISCREG_SPSR_EL1: 1912 // Force bits 23:21 to 0 1913 newVal = val & ~(0x7 << 21); 1914 break; 1915 case MISCREG_L2CTLR: 1916 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 1917 miscRegName[misc_reg], uint32_t(val)); 1918 break; 1919 1920 // Generic Timer registers 1921 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 1922 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 1923 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 1924 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 1925 getGenericTimer(tc).setMiscReg(misc_reg, newVal); 1926 break; 1927 } 1928 } 1929 setMiscRegNoEffect(misc_reg, newVal); 1930} 1931 1932BaseISADevice & 1933ISA::getGenericTimer(ThreadContext *tc) 1934{ 1935 // We only need to create an ISA interface the first time we try 1936 // to access the timer. 1937 if (timer) 1938 return *timer.get(); 1939 1940 assert(system); 1941 GenericTimer *generic_timer(system->getGenericTimer()); 1942 if (!generic_timer) { 1943 panic("Trying to get a generic timer from a system that hasn't " 1944 "been configured to use a generic timer.\n"); 1945 } 1946 1947 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 1948 return *timer.get(); 1949} 1950 1951} 1952 1953ArmISA::ISA * 1954ArmISAParams::create() 1955{ 1956 return new ArmISA::ISA(this); 1957} 1958