isa.cc revision 12392
1/*
2 * Copyright (c) 2010-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 *          Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42
43#include "arch/arm/pmu.hh"
44#include "arch/arm/system.hh"
45#include "cpu/base.hh"
46#include "cpu/checker/cpu.hh"
47#include "debug/Arm.hh"
48#include "debug/MiscRegs.hh"
49#include "dev/arm/generic_timer.hh"
50#include "params/ArmISA.hh"
51#include "sim/faults.hh"
52#include "sim/stat_control.hh"
53#include "sim/system.hh"
54
55namespace ArmISA
56{
57
58
59/**
60 * Some registers alias with others, and therefore need to be translated.
61 * For each entry:
62 * The first value is the misc register that is to be looked up
63 * the second value is the lower part of the translation
64 * the third the upper part
65 * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543
66 */
67const struct ISA::MiscRegInitializerEntry
68    ISA::MiscRegSwitch[] = {
69    {MISCREG_ACTLR_EL1, {MISCREG_ACTLR_NS, 0}},
70    {MISCREG_AFSR0_EL1, {MISCREG_ADFSR_NS, 0}},
71    {MISCREG_AFSR1_EL1, {MISCREG_AIFSR_NS, 0}},
72    {MISCREG_AMAIR_EL1, {MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS}},
73    {MISCREG_CONTEXTIDR_EL1, {MISCREG_CONTEXTIDR_NS, 0}},
74    {MISCREG_CPACR_EL1, {MISCREG_CPACR, 0}},
75    {MISCREG_CSSELR_EL1, {MISCREG_CSSELR_NS, 0}},
76    {MISCREG_DACR32_EL2, {MISCREG_DACR_NS, 0}},
77    {MISCREG_FAR_EL1, {MISCREG_DFAR_NS, MISCREG_IFAR_NS}},
78    // ESR_EL1 -> DFSR
79    {MISCREG_HACR_EL2, {MISCREG_HACR, 0}},
80    {MISCREG_ACTLR_EL2, {MISCREG_HACTLR, 0}},
81    {MISCREG_AFSR0_EL2, {MISCREG_HADFSR, 0}},
82    {MISCREG_AFSR1_EL2, {MISCREG_HAIFSR, 0}},
83    {MISCREG_AMAIR_EL2, {MISCREG_HAMAIR0, MISCREG_HAMAIR1}},
84    {MISCREG_CPTR_EL2, {MISCREG_HCPTR, 0}},
85    {MISCREG_HCR_EL2, {MISCREG_HCR, 0 /*MISCREG_HCR2*/}},
86    {MISCREG_MDCR_EL2, {MISCREG_HDCR, 0}},
87    {MISCREG_FAR_EL2, {MISCREG_HDFAR, MISCREG_HIFAR}},
88    {MISCREG_MAIR_EL2, {MISCREG_HMAIR0, MISCREG_HMAIR1}},
89    {MISCREG_HPFAR_EL2, {MISCREG_HPFAR, 0}},
90    {MISCREG_SCTLR_EL2, {MISCREG_HSCTLR, 0}},
91    {MISCREG_ESR_EL2, {MISCREG_HSR, 0}},
92    {MISCREG_HSTR_EL2, {MISCREG_HSTR, 0}},
93    {MISCREG_TCR_EL2, {MISCREG_HTCR, 0}},
94    {MISCREG_TPIDR_EL2, {MISCREG_HTPIDR, 0}},
95    {MISCREG_TTBR0_EL2, {MISCREG_HTTBR, 0}},
96    {MISCREG_VBAR_EL2, {MISCREG_HVBAR, 0}},
97    {MISCREG_IFSR32_EL2, {MISCREG_IFSR_NS, 0}},
98    {MISCREG_MAIR_EL1, {MISCREG_PRRR_NS, MISCREG_NMRR_NS}},
99    {MISCREG_PAR_EL1, {MISCREG_PAR_NS, 0}},
100    // RMR_EL1 -> RMR
101    // RMR_EL2 -> HRMR
102    {MISCREG_SCTLR_EL1, {MISCREG_SCTLR_NS, 0}},
103    {MISCREG_SDER32_EL3, {MISCREG_SDER, 0}},
104    {MISCREG_TPIDR_EL1, {MISCREG_TPIDRPRW_NS, 0}},
105    {MISCREG_TPIDRRO_EL0, {MISCREG_TPIDRURO_NS, 0}},
106    {MISCREG_TPIDR_EL0, {MISCREG_TPIDRURW_NS, 0}},
107    {MISCREG_TCR_EL1, {MISCREG_TTBCR_NS, 0}},
108    {MISCREG_TTBR0_EL1, {MISCREG_TTBR0_NS, 0}},
109    {MISCREG_TTBR1_EL1, {MISCREG_TTBR1_NS, 0}},
110    {MISCREG_VBAR_EL1, {MISCREG_VBAR_NS, 0}},
111    {MISCREG_VMPIDR_EL2, {MISCREG_VMPIDR, 0}},
112    {MISCREG_VPIDR_EL2, {MISCREG_VPIDR, 0}},
113    {MISCREG_VTCR_EL2, {MISCREG_VTCR, 0}},
114    {MISCREG_VTTBR_EL2, {MISCREG_VTTBR, 0}},
115    {MISCREG_CNTFRQ_EL0, {MISCREG_CNTFRQ, 0}},
116    {MISCREG_CNTHCTL_EL2, {MISCREG_CNTHCTL, 0}},
117    {MISCREG_CNTHP_CTL_EL2, {MISCREG_CNTHP_CTL, 0}},
118    {MISCREG_CNTHP_CVAL_EL2, {MISCREG_CNTHP_CVAL, 0}}, /* 64b */
119    {MISCREG_CNTHP_TVAL_EL2, {MISCREG_CNTHP_TVAL, 0}},
120    {MISCREG_CNTKCTL_EL1, {MISCREG_CNTKCTL, 0}},
121    {MISCREG_CNTP_CTL_EL0, {MISCREG_CNTP_CTL_NS, 0}},
122    {MISCREG_CNTP_CVAL_EL0, {MISCREG_CNTP_CVAL_NS, 0}}, /* 64b */
123    {MISCREG_CNTP_TVAL_EL0, {MISCREG_CNTP_TVAL_NS, 0}},
124    {MISCREG_CNTPCT_EL0, {MISCREG_CNTPCT, 0}}, /* 64b */
125    {MISCREG_CNTV_CTL_EL0, {MISCREG_CNTV_CTL, 0}},
126    {MISCREG_CNTV_CVAL_EL0, {MISCREG_CNTV_CVAL, 0}}, /* 64b */
127    {MISCREG_CNTV_TVAL_EL0, {MISCREG_CNTV_TVAL, 0}},
128    {MISCREG_CNTVCT_EL0, {MISCREG_CNTVCT, 0}}, /* 64b */
129    {MISCREG_CNTVOFF_EL2, {MISCREG_CNTVOFF, 0}}, /* 64b */
130    {MISCREG_DBGAUTHSTATUS_EL1, {MISCREG_DBGAUTHSTATUS, 0}},
131    {MISCREG_DBGBCR0_EL1, {MISCREG_DBGBCR0, 0}},
132    {MISCREG_DBGBCR1_EL1, {MISCREG_DBGBCR1, 0}},
133    {MISCREG_DBGBCR2_EL1, {MISCREG_DBGBCR2, 0}},
134    {MISCREG_DBGBCR3_EL1, {MISCREG_DBGBCR3, 0}},
135    {MISCREG_DBGBCR4_EL1, {MISCREG_DBGBCR4, 0}},
136    {MISCREG_DBGBCR5_EL1, {MISCREG_DBGBCR5, 0}},
137    {MISCREG_DBGBVR0_EL1, {MISCREG_DBGBVR0, 0 /* MISCREG_DBGBXVR0 */}},
138    {MISCREG_DBGBVR1_EL1, {MISCREG_DBGBVR1, 0 /* MISCREG_DBGBXVR1 */}},
139    {MISCREG_DBGBVR2_EL1, {MISCREG_DBGBVR2, 0 /* MISCREG_DBGBXVR2 */}},
140    {MISCREG_DBGBVR3_EL1, {MISCREG_DBGBVR3, 0 /* MISCREG_DBGBXVR3 */}},
141    {MISCREG_DBGBVR4_EL1, {MISCREG_DBGBVR4, MISCREG_DBGBXVR4}},
142    {MISCREG_DBGBVR5_EL1, {MISCREG_DBGBVR5, MISCREG_DBGBXVR5}},
143    {MISCREG_DBGCLAIMSET_EL1, {MISCREG_DBGCLAIMSET, 0}},
144    {MISCREG_DBGCLAIMCLR_EL1, {MISCREG_DBGCLAIMCLR, 0}},
145    // DBGDTR_EL0 -> DBGDTR{R or T}Xint
146    // DBGDTRRX_EL0 -> DBGDTRRXint
147    // DBGDTRTX_EL0 -> DBGDTRRXint
148    {MISCREG_DBGPRCR_EL1, {MISCREG_DBGPRCR, 0}},
149    {MISCREG_DBGVCR32_EL2, {MISCREG_DBGVCR, 0}},
150    {MISCREG_DBGWCR0_EL1, {MISCREG_DBGWCR0, 0}},
151    {MISCREG_DBGWCR1_EL1, {MISCREG_DBGWCR1, 0}},
152    {MISCREG_DBGWCR2_EL1, {MISCREG_DBGWCR2, 0}},
153    {MISCREG_DBGWCR3_EL1, {MISCREG_DBGWCR3, 0}},
154    {MISCREG_DBGWVR0_EL1, {MISCREG_DBGWVR0, 0}},
155    {MISCREG_DBGWVR1_EL1, {MISCREG_DBGWVR1, 0}},
156    {MISCREG_DBGWVR2_EL1, {MISCREG_DBGWVR2, 0}},
157    {MISCREG_DBGWVR3_EL1, {MISCREG_DBGWVR3, 0}},
158    {MISCREG_ID_DFR0_EL1, {MISCREG_ID_DFR0, 0}},
159    {MISCREG_MDCCSR_EL0, {MISCREG_DBGDSCRint, 0}},
160    {MISCREG_MDRAR_EL1, {MISCREG_DBGDRAR, 0}},
161    {MISCREG_MDSCR_EL1, {MISCREG_DBGDSCRext, 0}},
162    {MISCREG_OSDLR_EL1, {MISCREG_DBGOSDLR, 0}},
163    {MISCREG_OSDTRRX_EL1, {MISCREG_DBGDTRRXext, 0}},
164    {MISCREG_OSDTRTX_EL1, {MISCREG_DBGDTRTXext, 0}},
165    {MISCREG_OSECCR_EL1, {MISCREG_DBGOSECCR, 0}},
166    {MISCREG_OSLAR_EL1, {MISCREG_DBGOSLAR, 0}},
167    {MISCREG_OSLSR_EL1, {MISCREG_DBGOSLSR, 0}},
168    {MISCREG_PMCCNTR_EL0, {MISCREG_PMCCNTR, 0}},
169    {MISCREG_PMCEID0_EL0, {MISCREG_PMCEID0, 0}},
170    {MISCREG_PMCEID1_EL0, {MISCREG_PMCEID1, 0}},
171    {MISCREG_PMCNTENSET_EL0, {MISCREG_PMCNTENSET, 0}},
172    {MISCREG_PMCNTENCLR_EL0, {MISCREG_PMCNTENCLR, 0}},
173    {MISCREG_PMCR_EL0, {MISCREG_PMCR, 0}},
174/*  {MISCREG_PMEVCNTR0_EL0, {MISCREG_PMEVCNTR0, 0}},
175    {MISCREG_PMEVCNTR1_EL0, {MISCREG_PMEVCNTR1, 0}},
176    {MISCREG_PMEVCNTR2_EL0, {MISCREG_PMEVCNTR2, 0}},
177    {MISCREG_PMEVCNTR3_EL0, {MISCREG_PMEVCNTR3, 0}},
178    {MISCREG_PMEVCNTR4_EL0, {MISCREG_PMEVCNTR4, 0}},
179    {MISCREG_PMEVCNTR5_EL0, {MISCREG_PMEVCNTR5, 0}},
180    {MISCREG_PMEVTYPER0_EL0, {MISCREG_PMEVTYPER0, 0}},
181    {MISCREG_PMEVTYPER1_EL0, {MISCREG_PMEVTYPER1, 0}},
182    {MISCREG_PMEVTYPER2_EL0, {MISCREG_PMEVTYPER2, 0}},
183    {MISCREG_PMEVTYPER3_EL0, {MISCREG_PMEVTYPER3, 0}},
184    {MISCREG_PMEVTYPER4_EL0, {MISCREG_PMEVTYPER4, 0}},
185    {MISCREG_PMEVTYPER5_EL0, {MISCREG_PMEVTYPER5, 0}}, */
186    {MISCREG_PMINTENCLR_EL1, {MISCREG_PMINTENCLR, 0}},
187    {MISCREG_PMINTENSET_EL1, {MISCREG_PMINTENSET, 0}},
188//  {MISCREG_PMOVSCLR_EL0, {MISCREG_PMOVSCLR, 0}},
189    {MISCREG_PMOVSSET_EL0, {MISCREG_PMOVSSET, 0}},
190    {MISCREG_PMSELR_EL0, {MISCREG_PMSELR, 0}},
191    {MISCREG_PMSWINC_EL0, {MISCREG_PMSWINC, 0}},
192    {MISCREG_PMUSERENR_EL0, {MISCREG_PMUSERENR, 0}},
193    {MISCREG_PMXEVCNTR_EL0, {MISCREG_PMXEVCNTR, 0}},
194    {MISCREG_PMXEVTYPER_EL0, {MISCREG_PMXEVTYPER, 0}},
195
196    // from ARM DDI 0487A.i, template text
197    // "AArch64 System register ___ can be mapped to
198    //  AArch32 System register ___, but this is not
199    //  architecturally mandated."
200    {MISCREG_SCR_EL3, {MISCREG_SCR, 0}}, // D7-2005
201    // MDCR_EL3 -> SDCR, D7-2108 (the latter is unimpl. in gem5)
202    {MISCREG_SPSR_EL1, {MISCREG_SPSR_SVC, 0}}, // C5.2.17 SPSR_EL1
203    {MISCREG_SPSR_EL2, {MISCREG_SPSR_HYP, 0}}, // C5.2.18 SPSR_EL2
204    {MISCREG_SPSR_EL3, {MISCREG_SPSR_MON, 0}}, // C5.2.19 SPSR_EL3
205};
206
207
208ISA::ISA(Params *p)
209    : SimObject(p),
210      system(NULL),
211      _decoderFlavour(p->decoderFlavour),
212      _vecRegRenameMode(p->vecRegRenameMode),
213      pmu(p->pmu),
214      lookUpMiscReg(NUM_MISCREGS, {0,0})
215{
216    miscRegs[MISCREG_SCTLR_RST] = 0;
217
218    // Hook up a dummy device if we haven't been configured with a
219    // real PMU. By using a dummy device, we don't need to check that
220    // the PMU exist every time we try to access a PMU register.
221    if (!pmu)
222        pmu = &dummyDevice;
223
224    // Give all ISA devices a pointer to this ISA
225    pmu->setISA(this);
226
227    system = dynamic_cast<ArmSystem *>(p->system);
228
229    // Cache system-level properties
230    if (FullSystem && system) {
231        highestELIs64 = system->highestELIs64();
232        haveSecurity = system->haveSecurity();
233        haveLPAE = system->haveLPAE();
234        haveVirtualization = system->haveVirtualization();
235        haveLargeAsid64 = system->haveLargeAsid64();
236        physAddrRange64 = system->physAddrRange64();
237    } else {
238        highestELIs64 = true; // ArmSystem::highestELIs64 does the same
239        haveSecurity = haveLPAE = haveVirtualization = false;
240        haveLargeAsid64 = false;
241        physAddrRange64 = 32;  // dummy value
242    }
243
244    /** Fill in the miscReg translation table */
245    for (auto sw : MiscRegSwitch) {
246        lookUpMiscReg[sw.index] = sw.entry;
247    }
248
249    preUnflattenMiscReg();
250
251    clear();
252}
253
254const ArmISAParams *
255ISA::params() const
256{
257    return dynamic_cast<const Params *>(_params);
258}
259
260void
261ISA::clear()
262{
263    const Params *p(params());
264
265    SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
266    memset(miscRegs, 0, sizeof(miscRegs));
267
268    // Initialize configurable default values
269    miscRegs[MISCREG_MIDR] = p->midr;
270    miscRegs[MISCREG_MIDR_EL1] = p->midr;
271    miscRegs[MISCREG_VPIDR] = p->midr;
272
273    if (FullSystem && system->highestELIs64()) {
274        // Initialize AArch64 state
275        clear64(p);
276        return;
277    }
278
279    // Initialize AArch32 state...
280
281    CPSR cpsr = 0;
282    cpsr.mode = MODE_USER;
283    miscRegs[MISCREG_CPSR] = cpsr;
284    updateRegMap(cpsr);
285
286    SCTLR sctlr = 0;
287    sctlr.te = (bool) sctlr_rst.te;
288    sctlr.nmfi = (bool) sctlr_rst.nmfi;
289    sctlr.v = (bool) sctlr_rst.v;
290    sctlr.u = 1;
291    sctlr.xp = 1;
292    sctlr.rao2 = 1;
293    sctlr.rao3 = 1;
294    sctlr.rao4 = 0xf;  // SCTLR[6:3]
295    sctlr.uci = 1;
296    sctlr.dze = 1;
297    miscRegs[MISCREG_SCTLR_NS] = sctlr;
298    miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
299    miscRegs[MISCREG_HCPTR] = 0;
300
301    // Start with an event in the mailbox
302    miscRegs[MISCREG_SEV_MAILBOX] = 1;
303
304    // Separate Instruction and Data TLBs
305    miscRegs[MISCREG_TLBTR] = 1;
306
307    MVFR0 mvfr0 = 0;
308    mvfr0.advSimdRegisters = 2;
309    mvfr0.singlePrecision = 2;
310    mvfr0.doublePrecision = 2;
311    mvfr0.vfpExceptionTrapping = 0;
312    mvfr0.divide = 1;
313    mvfr0.squareRoot = 1;
314    mvfr0.shortVectors = 1;
315    mvfr0.roundingModes = 1;
316    miscRegs[MISCREG_MVFR0] = mvfr0;
317
318    MVFR1 mvfr1 = 0;
319    mvfr1.flushToZero = 1;
320    mvfr1.defaultNaN = 1;
321    mvfr1.advSimdLoadStore = 1;
322    mvfr1.advSimdInteger = 1;
323    mvfr1.advSimdSinglePrecision = 1;
324    mvfr1.advSimdHalfPrecision = 1;
325    mvfr1.vfpHalfPrecision = 1;
326    miscRegs[MISCREG_MVFR1] = mvfr1;
327
328    // Reset values of PRRR and NMRR are implementation dependent
329
330    // @todo: PRRR and NMRR in secure state?
331    miscRegs[MISCREG_PRRR_NS] =
332        (1 << 19) | // 19
333        (0 << 18) | // 18
334        (0 << 17) | // 17
335        (1 << 16) | // 16
336        (2 << 14) | // 15:14
337        (0 << 12) | // 13:12
338        (2 << 10) | // 11:10
339        (2 << 8)  | // 9:8
340        (2 << 6)  | // 7:6
341        (2 << 4)  | // 5:4
342        (1 << 2)  | // 3:2
343        0;          // 1:0
344    miscRegs[MISCREG_NMRR_NS] =
345        (1 << 30) | // 31:30
346        (0 << 26) | // 27:26
347        (0 << 24) | // 25:24
348        (3 << 22) | // 23:22
349        (2 << 20) | // 21:20
350        (0 << 18) | // 19:18
351        (0 << 16) | // 17:16
352        (1 << 14) | // 15:14
353        (0 << 12) | // 13:12
354        (2 << 10) | // 11:10
355        (0 << 8)  | // 9:8
356        (3 << 6)  | // 7:6
357        (2 << 4)  | // 5:4
358        (0 << 2)  | // 3:2
359        0;          // 1:0
360
361    miscRegs[MISCREG_CPACR] = 0;
362
363    miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
364    miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
365    miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
366    miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
367
368    miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
369    miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
370    miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
371    miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
372    miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
373    miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
374
375    miscRegs[MISCREG_FPSID] = p->fpsid;
376
377    if (haveLPAE) {
378        TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS];
379        ttbcr.eae = 0;
380        miscRegs[MISCREG_TTBCR_NS] = ttbcr;
381        // Enforce consistency with system-level settings
382        miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5;
383    }
384
385    if (haveSecurity) {
386        miscRegs[MISCREG_SCTLR_S] = sctlr;
387        miscRegs[MISCREG_SCR] = 0;
388        miscRegs[MISCREG_VBAR_S] = 0;
389    } else {
390        // we're always non-secure
391        miscRegs[MISCREG_SCR] = 1;
392    }
393
394    //XXX We need to initialize the rest of the state.
395}
396
397void
398ISA::clear64(const ArmISAParams *p)
399{
400    CPSR cpsr = 0;
401    Addr rvbar = system->resetAddr64();
402    switch (system->highestEL()) {
403        // Set initial EL to highest implemented EL using associated stack
404        // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
405        // value
406      case EL3:
407        cpsr.mode = MODE_EL3H;
408        miscRegs[MISCREG_RVBAR_EL3] = rvbar;
409        break;
410      case EL2:
411        cpsr.mode = MODE_EL2H;
412        miscRegs[MISCREG_RVBAR_EL2] = rvbar;
413        break;
414      case EL1:
415        cpsr.mode = MODE_EL1H;
416        miscRegs[MISCREG_RVBAR_EL1] = rvbar;
417        break;
418      default:
419        panic("Invalid highest implemented exception level");
420        break;
421    }
422
423    // Initialize rest of CPSR
424    cpsr.daif = 0xf;  // Mask all interrupts
425    cpsr.ss = 0;
426    cpsr.il = 0;
427    miscRegs[MISCREG_CPSR] = cpsr;
428    updateRegMap(cpsr);
429
430    // Initialize other control registers
431    miscRegs[MISCREG_MPIDR_EL1] = 0x80000000;
432    if (haveSecurity) {
433        miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830;
434        miscRegs[MISCREG_SCR_EL3]   = 0x00000030;  // RES1 fields
435    } else if (haveVirtualization) {
436        // also  MISCREG_SCTLR_EL2 (by mapping)
437        miscRegs[MISCREG_HSCTLR] = 0x30c50830;
438    } else {
439        // also  MISCREG_SCTLR_EL1 (by mapping)
440        miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init
441        // Always non-secure
442        miscRegs[MISCREG_SCR_EL3] = 1;
443    }
444
445    // Initialize configurable id registers
446    miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1;
447    miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1;
448    miscRegs[MISCREG_ID_AA64DFR0_EL1] =
449        (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) |
450        (p->pmu ?             0x0000000000000100ULL : 0); // Enable PMUv3
451
452    miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1;
453    miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1;
454    miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1;
455    miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1;
456    miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1;
457
458    miscRegs[MISCREG_ID_DFR0_EL1] =
459        (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3
460
461    miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1];
462
463    // Enforce consistency with system-level settings...
464
465    // EL3
466    miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
467        miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12,
468        haveSecurity ? 0x2 : 0x0);
469    // EL2
470    miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
471        miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8,
472        haveVirtualization ? 0x2 : 0x0);
473    // Large ASID support
474    miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
475        miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4,
476        haveLargeAsid64 ? 0x2 : 0x0);
477    // Physical address size
478    miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
479        miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0,
480        encodePhysAddrRange64(physAddrRange64));
481}
482
483MiscReg
484ISA::readMiscRegNoEffect(int misc_reg) const
485{
486    assert(misc_reg < NumMiscRegs);
487
488    auto regs = getMiscIndices(misc_reg);
489    int lower = regs.first, upper = regs.second;
490    return !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32))
491                                      |(miscRegs[upper] << 32));
492}
493
494
495MiscReg
496ISA::readMiscReg(int misc_reg, ThreadContext *tc)
497{
498    CPSR cpsr = 0;
499    PCState pc = 0;
500    SCR scr = 0;
501
502    if (misc_reg == MISCREG_CPSR) {
503        cpsr = miscRegs[misc_reg];
504        pc = tc->pcState();
505        cpsr.j = pc.jazelle() ? 1 : 0;
506        cpsr.t = pc.thumb() ? 1 : 0;
507        return cpsr;
508    }
509
510#ifndef NDEBUG
511    if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
512        if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
513            warn("Unimplemented system register %s read.\n",
514                 miscRegName[misc_reg]);
515        else
516            panic("Unimplemented system register %s read.\n",
517                  miscRegName[misc_reg]);
518    }
519#endif
520
521    switch (unflattenMiscReg(misc_reg)) {
522      case MISCREG_HCR:
523        {
524            if (!haveVirtualization)
525                return 0;
526            else
527                return readMiscRegNoEffect(MISCREG_HCR);
528        }
529      case MISCREG_CPACR:
530        {
531            const uint32_t ones = (uint32_t)(-1);
532            CPACR cpacrMask = 0;
533            // Only cp10, cp11, and ase are implemented, nothing else should
534            // be readable? (straight copy from the write code)
535            cpacrMask.cp10 = ones;
536            cpacrMask.cp11 = ones;
537            cpacrMask.asedis = ones;
538
539            // Security Extensions may limit the readability of CPACR
540            if (haveSecurity) {
541                scr = readMiscRegNoEffect(MISCREG_SCR);
542                cpsr = readMiscRegNoEffect(MISCREG_CPSR);
543                if (scr.ns && (cpsr.mode != MODE_MON)) {
544                    NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
545                    // NB: Skipping the full loop, here
546                    if (!nsacr.cp10) cpacrMask.cp10 = 0;
547                    if (!nsacr.cp11) cpacrMask.cp11 = 0;
548                }
549            }
550            MiscReg val = readMiscRegNoEffect(MISCREG_CPACR);
551            val &= cpacrMask;
552            DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n",
553                    miscRegName[misc_reg], val);
554            return val;
555        }
556      case MISCREG_MPIDR:
557        cpsr = readMiscRegNoEffect(MISCREG_CPSR);
558        scr  = readMiscRegNoEffect(MISCREG_SCR);
559        if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) {
560            return getMPIDR(system, tc);
561        } else {
562            return readMiscReg(MISCREG_VMPIDR, tc);
563        }
564            break;
565      case MISCREG_MPIDR_EL1:
566        // @todo in the absence of v8 virtualization support just return MPIDR_EL1
567        return getMPIDR(system, tc) & 0xffffffff;
568      case MISCREG_VMPIDR:
569        // top bit defined as RES1
570        return readMiscRegNoEffect(misc_reg) | 0x80000000;
571      case MISCREG_ID_AFR0: // not implemented, so alias MIDR
572      case MISCREG_REVIDR:  // not implemented, so alias MIDR
573      case MISCREG_MIDR:
574        cpsr = readMiscRegNoEffect(MISCREG_CPSR);
575        scr  = readMiscRegNoEffect(MISCREG_SCR);
576        if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) {
577            return readMiscRegNoEffect(misc_reg);
578        } else {
579            return readMiscRegNoEffect(MISCREG_VPIDR);
580        }
581        break;
582      case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI
583      case MISCREG_JMCR:  // Jazelle trivial implementation, RAZ/WI
584      case MISCREG_JIDR:  // Jazelle trivial implementation, RAZ/WI
585      case MISCREG_AIDR:  // AUX ID set to 0
586      case MISCREG_TCMTR: // No TCM's
587        return 0;
588
589      case MISCREG_CLIDR:
590        warn_once("The clidr register always reports 0 caches.\n");
591        warn_once("clidr LoUIS field of 0b001 to match current "
592                  "ARM implementations.\n");
593        return 0x00200000;
594      case MISCREG_CCSIDR:
595        warn_once("The ccsidr register isn't implemented and "
596                "always reads as 0.\n");
597        break;
598      case MISCREG_CTR:                 // AArch32, ARMv7, top bit set
599      case MISCREG_CTR_EL0:             // AArch64
600        {
601            //all caches have the same line size in gem5
602            //4 byte words in ARM
603            unsigned lineSizeWords =
604                tc->getSystemPtr()->cacheLineSize() / 4;
605            unsigned log2LineSizeWords = 0;
606
607            while (lineSizeWords >>= 1) {
608                ++log2LineSizeWords;
609            }
610
611            CTR ctr = 0;
612            //log2 of minimun i-cache line size (words)
613            ctr.iCacheLineSize = log2LineSizeWords;
614            //b11 - gem5 uses pipt
615            ctr.l1IndexPolicy = 0x3;
616            //log2 of minimum d-cache line size (words)
617            ctr.dCacheLineSize = log2LineSizeWords;
618            //log2 of max reservation size (words)
619            ctr.erg = log2LineSizeWords;
620            //log2 of max writeback size (words)
621            ctr.cwg = log2LineSizeWords;
622            //b100 - gem5 format is ARMv7
623            ctr.format = 0x4;
624
625            return ctr;
626        }
627      case MISCREG_ACTLR:
628        warn("Not doing anything for miscreg ACTLR\n");
629        break;
630
631      case MISCREG_PMXEVTYPER_PMCCFILTR:
632      case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
633      case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
634      case MISCREG_PMCR ... MISCREG_PMOVSSET:
635        return pmu->readMiscReg(misc_reg);
636
637      case MISCREG_CPSR_Q:
638        panic("shouldn't be reading this register seperately\n");
639      case MISCREG_FPSCR_QC:
640        return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
641      case MISCREG_FPSCR_EXC:
642        return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
643      case MISCREG_FPSR:
644        {
645            const uint32_t ones = (uint32_t)(-1);
646            FPSCR fpscrMask = 0;
647            fpscrMask.ioc = ones;
648            fpscrMask.dzc = ones;
649            fpscrMask.ofc = ones;
650            fpscrMask.ufc = ones;
651            fpscrMask.ixc = ones;
652            fpscrMask.idc = ones;
653            fpscrMask.qc = ones;
654            fpscrMask.v = ones;
655            fpscrMask.c = ones;
656            fpscrMask.z = ones;
657            fpscrMask.n = ones;
658            return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
659        }
660      case MISCREG_FPCR:
661        {
662            const uint32_t ones = (uint32_t)(-1);
663            FPSCR fpscrMask  = 0;
664            fpscrMask.ioe = ones;
665            fpscrMask.dze = ones;
666            fpscrMask.ofe = ones;
667            fpscrMask.ufe = ones;
668            fpscrMask.ixe = ones;
669            fpscrMask.ide = ones;
670            fpscrMask.len    = ones;
671            fpscrMask.stride = ones;
672            fpscrMask.rMode  = ones;
673            fpscrMask.fz     = ones;
674            fpscrMask.dn     = ones;
675            fpscrMask.ahp    = ones;
676            return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
677        }
678      case MISCREG_NZCV:
679        {
680            CPSR cpsr = 0;
681            cpsr.nz   = tc->readCCReg(CCREG_NZ);
682            cpsr.c    = tc->readCCReg(CCREG_C);
683            cpsr.v    = tc->readCCReg(CCREG_V);
684            return cpsr;
685        }
686      case MISCREG_DAIF:
687        {
688            CPSR cpsr = 0;
689            cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif;
690            return cpsr;
691        }
692      case MISCREG_SP_EL0:
693        {
694            return tc->readIntReg(INTREG_SP0);
695        }
696      case MISCREG_SP_EL1:
697        {
698            return tc->readIntReg(INTREG_SP1);
699        }
700      case MISCREG_SP_EL2:
701        {
702            return tc->readIntReg(INTREG_SP2);
703        }
704      case MISCREG_SPSEL:
705        {
706            return miscRegs[MISCREG_CPSR] & 0x1;
707        }
708      case MISCREG_CURRENTEL:
709        {
710            return miscRegs[MISCREG_CPSR] & 0xc;
711        }
712      case MISCREG_L2CTLR:
713        {
714            // mostly unimplemented, just set NumCPUs field from sim and return
715            L2CTLR l2ctlr = 0;
716            // b00:1CPU to b11:4CPUs
717            l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1;
718            return l2ctlr;
719        }
720      case MISCREG_DBGDIDR:
721        /* For now just implement the version number.
722         * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
723         */
724        return 0x5 << 16;
725      case MISCREG_DBGDSCRint:
726        return 0;
727      case MISCREG_ISR:
728        return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR(
729            readMiscRegNoEffect(MISCREG_HCR),
730            readMiscRegNoEffect(MISCREG_CPSR),
731            readMiscRegNoEffect(MISCREG_SCR));
732      case MISCREG_ISR_EL1:
733        return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR(
734            readMiscRegNoEffect(MISCREG_HCR_EL2),
735            readMiscRegNoEffect(MISCREG_CPSR),
736            readMiscRegNoEffect(MISCREG_SCR_EL3));
737      case MISCREG_DCZID_EL0:
738        return 0x04;  // DC ZVA clear 64-byte chunks
739      case MISCREG_HCPTR:
740        {
741            MiscReg val = readMiscRegNoEffect(misc_reg);
742            // The trap bit associated with CP14 is defined as RAZ
743            val &= ~(1 << 14);
744            // If a CP bit in NSACR is 0 then the corresponding bit in
745            // HCPTR is RAO/WI
746            bool secure_lookup = haveSecurity &&
747                inSecureState(readMiscRegNoEffect(MISCREG_SCR),
748                              readMiscRegNoEffect(MISCREG_CPSR));
749            if (!secure_lookup) {
750                MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR);
751                val |= (mask ^ 0x7FFF) & 0xBFFF;
752            }
753            // Set the bits for unimplemented coprocessors to RAO/WI
754            val |= 0x33FF;
755            return (val);
756        }
757      case MISCREG_HDFAR: // alias for secure DFAR
758        return readMiscRegNoEffect(MISCREG_DFAR_S);
759      case MISCREG_HIFAR: // alias for secure IFAR
760        return readMiscRegNoEffect(MISCREG_IFAR_S);
761      case MISCREG_HVBAR: // bottom bits reserved
762        return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0;
763      case MISCREG_SCTLR:
764        return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818;
765      case MISCREG_SCTLR_EL1:
766        return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800;
767      case MISCREG_SCTLR_EL2:
768      case MISCREG_SCTLR_EL3:
769      case MISCREG_HSCTLR:
770        return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830;
771
772      case MISCREG_ID_PFR0:
773        // !ThumbEE | !Jazelle | Thumb | ARM
774        return 0x00000031;
775      case MISCREG_ID_PFR1:
776        {   // Timer | Virti | !M Profile | TrustZone | ARMv4
777            bool haveTimer = (system->getGenericTimer() != NULL);
778            return 0x00000001
779                 | (haveSecurity       ? 0x00000010 : 0x0)
780                 | (haveVirtualization ? 0x00001000 : 0x0)
781                 | (haveTimer          ? 0x00010000 : 0x0);
782        }
783      case MISCREG_ID_AA64PFR0_EL1:
784        return 0x0000000000000002   // AArch{64,32} supported at EL0
785             | 0x0000000000000020                             // EL1
786             | (haveVirtualization ? 0x0000000000000200 : 0)  // EL2
787             | (haveSecurity       ? 0x0000000000002000 : 0); // EL3
788      case MISCREG_ID_AA64PFR1_EL1:
789        return 0; // bits [63:0] RES0 (reserved for future use)
790
791      // Generic Timer registers
792      case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
793      case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
794      case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:
795      case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1:
796        return getGenericTimer(tc).readMiscReg(misc_reg);
797
798      default:
799        break;
800
801    }
802    return readMiscRegNoEffect(misc_reg);
803}
804
805void
806ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
807{
808    assert(misc_reg < NumMiscRegs);
809
810    auto regs = getMiscIndices(misc_reg);
811    int lower = regs.first, upper = regs.second;
812    if (upper > 0) {
813        miscRegs[lower] = bits(val, 31, 0);
814        miscRegs[upper] = bits(val, 63, 32);
815        DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n",
816                misc_reg, lower, upper, val);
817    } else {
818        miscRegs[lower] = val;
819        DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n",
820                misc_reg, lower, val);
821    }
822}
823
824void
825ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
826{
827
828    MiscReg newVal = val;
829    int x;
830    bool secure_lookup;
831    bool hyp;
832    System *sys;
833    ThreadContext *oc;
834    uint8_t target_el;
835    uint16_t asid;
836    SCR scr;
837
838    if (misc_reg == MISCREG_CPSR) {
839        updateRegMap(val);
840
841
842        CPSR old_cpsr = miscRegs[MISCREG_CPSR];
843        int old_mode = old_cpsr.mode;
844        CPSR cpsr = val;
845        if (old_mode != cpsr.mode) {
846            tc->getITBPtr()->invalidateMiscReg();
847            tc->getDTBPtr()->invalidateMiscReg();
848        }
849
850        DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
851                miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
852        PCState pc = tc->pcState();
853        pc.nextThumb(cpsr.t);
854        pc.nextJazelle(cpsr.j);
855
856        // Follow slightly different semantics if a CheckerCPU object
857        // is connected
858        CheckerCPU *checker = tc->getCheckerCpuPtr();
859        if (checker) {
860            tc->pcStateNoRecord(pc);
861        } else {
862            tc->pcState(pc);
863        }
864    } else {
865#ifndef NDEBUG
866        if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
867            if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
868                warn("Unimplemented system register %s write with %#x.\n",
869                    miscRegName[misc_reg], val);
870            else
871                panic("Unimplemented system register %s write with %#x.\n",
872                    miscRegName[misc_reg], val);
873        }
874#endif
875        switch (unflattenMiscReg(misc_reg)) {
876          case MISCREG_CPACR:
877            {
878
879                const uint32_t ones = (uint32_t)(-1);
880                CPACR cpacrMask = 0;
881                // Only cp10, cp11, and ase are implemented, nothing else should
882                // be writable
883                cpacrMask.cp10 = ones;
884                cpacrMask.cp11 = ones;
885                cpacrMask.asedis = ones;
886
887                // Security Extensions may limit the writability of CPACR
888                if (haveSecurity) {
889                    scr = readMiscRegNoEffect(MISCREG_SCR);
890                    CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR);
891                    if (scr.ns && (cpsr.mode != MODE_MON)) {
892                        NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
893                        // NB: Skipping the full loop, here
894                        if (!nsacr.cp10) cpacrMask.cp10 = 0;
895                        if (!nsacr.cp11) cpacrMask.cp11 = 0;
896                    }
897                }
898
899                MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR);
900                newVal &= cpacrMask;
901                newVal |= old_val & ~cpacrMask;
902                DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
903                        miscRegName[misc_reg], newVal);
904            }
905            break;
906          case MISCREG_CPACR_EL1:
907            {
908                const uint32_t ones = (uint32_t)(-1);
909                CPACR cpacrMask = 0;
910                cpacrMask.tta = ones;
911                cpacrMask.fpen = ones;
912                newVal &= cpacrMask;
913                DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
914                        miscRegName[misc_reg], newVal);
915            }
916            break;
917          case MISCREG_CPTR_EL2:
918            {
919                const uint32_t ones = (uint32_t)(-1);
920                CPTR cptrMask = 0;
921                cptrMask.tcpac = ones;
922                cptrMask.tta = ones;
923                cptrMask.tfp = ones;
924                newVal &= cptrMask;
925                cptrMask = 0;
926                cptrMask.res1_13_12_el2 = ones;
927                cptrMask.res1_9_0_el2 = ones;
928                newVal |= cptrMask;
929                DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
930                        miscRegName[misc_reg], newVal);
931            }
932            break;
933          case MISCREG_CPTR_EL3:
934            {
935                const uint32_t ones = (uint32_t)(-1);
936                CPTR cptrMask = 0;
937                cptrMask.tcpac = ones;
938                cptrMask.tta = ones;
939                cptrMask.tfp = ones;
940                newVal &= cptrMask;
941                DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
942                        miscRegName[misc_reg], newVal);
943            }
944            break;
945          case MISCREG_CSSELR:
946            warn_once("The csselr register isn't implemented.\n");
947            return;
948
949          case MISCREG_DC_ZVA_Xt:
950            warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n");
951            return;
952
953          case MISCREG_FPSCR:
954            {
955                const uint32_t ones = (uint32_t)(-1);
956                FPSCR fpscrMask = 0;
957                fpscrMask.ioc = ones;
958                fpscrMask.dzc = ones;
959                fpscrMask.ofc = ones;
960                fpscrMask.ufc = ones;
961                fpscrMask.ixc = ones;
962                fpscrMask.idc = ones;
963                fpscrMask.ioe = ones;
964                fpscrMask.dze = ones;
965                fpscrMask.ofe = ones;
966                fpscrMask.ufe = ones;
967                fpscrMask.ixe = ones;
968                fpscrMask.ide = ones;
969                fpscrMask.len = ones;
970                fpscrMask.stride = ones;
971                fpscrMask.rMode = ones;
972                fpscrMask.fz = ones;
973                fpscrMask.dn = ones;
974                fpscrMask.ahp = ones;
975                fpscrMask.qc = ones;
976                fpscrMask.v = ones;
977                fpscrMask.c = ones;
978                fpscrMask.z = ones;
979                fpscrMask.n = ones;
980                newVal = (newVal & (uint32_t)fpscrMask) |
981                         (readMiscRegNoEffect(MISCREG_FPSCR) &
982                          ~(uint32_t)fpscrMask);
983                tc->getDecoderPtr()->setContext(newVal);
984            }
985            break;
986          case MISCREG_FPSR:
987            {
988                const uint32_t ones = (uint32_t)(-1);
989                FPSCR fpscrMask = 0;
990                fpscrMask.ioc = ones;
991                fpscrMask.dzc = ones;
992                fpscrMask.ofc = ones;
993                fpscrMask.ufc = ones;
994                fpscrMask.ixc = ones;
995                fpscrMask.idc = ones;
996                fpscrMask.qc = ones;
997                fpscrMask.v = ones;
998                fpscrMask.c = ones;
999                fpscrMask.z = ones;
1000                fpscrMask.n = ones;
1001                newVal = (newVal & (uint32_t)fpscrMask) |
1002                         (readMiscRegNoEffect(MISCREG_FPSCR) &
1003                          ~(uint32_t)fpscrMask);
1004                misc_reg = MISCREG_FPSCR;
1005            }
1006            break;
1007          case MISCREG_FPCR:
1008            {
1009                const uint32_t ones = (uint32_t)(-1);
1010                FPSCR fpscrMask  = 0;
1011                fpscrMask.ioe = ones;
1012                fpscrMask.dze = ones;
1013                fpscrMask.ofe = ones;
1014                fpscrMask.ufe = ones;
1015                fpscrMask.ixe = ones;
1016                fpscrMask.ide = ones;
1017                fpscrMask.len    = ones;
1018                fpscrMask.stride = ones;
1019                fpscrMask.rMode  = ones;
1020                fpscrMask.fz     = ones;
1021                fpscrMask.dn     = ones;
1022                fpscrMask.ahp    = ones;
1023                newVal = (newVal & (uint32_t)fpscrMask) |
1024                         (readMiscRegNoEffect(MISCREG_FPSCR) &
1025                          ~(uint32_t)fpscrMask);
1026                misc_reg = MISCREG_FPSCR;
1027            }
1028            break;
1029          case MISCREG_CPSR_Q:
1030            {
1031                assert(!(newVal & ~CpsrMaskQ));
1032                newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal;
1033                misc_reg = MISCREG_CPSR;
1034            }
1035            break;
1036          case MISCREG_FPSCR_QC:
1037            {
1038                newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
1039                         (newVal & FpscrQcMask);
1040                misc_reg = MISCREG_FPSCR;
1041            }
1042            break;
1043          case MISCREG_FPSCR_EXC:
1044            {
1045                newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
1046                         (newVal & FpscrExcMask);
1047                misc_reg = MISCREG_FPSCR;
1048            }
1049            break;
1050          case MISCREG_FPEXC:
1051            {
1052                // vfpv3 architecture, section B.6.1 of DDI04068
1053                // bit 29 - valid only if fpexc[31] is 0
1054                const uint32_t fpexcMask = 0x60000000;
1055                newVal = (newVal & fpexcMask) |
1056                         (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask);
1057            }
1058            break;
1059          case MISCREG_HCR:
1060            {
1061                if (!haveVirtualization)
1062                    return;
1063            }
1064            break;
1065          case MISCREG_IFSR:
1066            {
1067                // ARM ARM (ARM DDI 0406C.b) B4.1.96
1068                const uint32_t ifsrMask =
1069                    mask(31, 13) | mask(11, 11) | mask(8, 6);
1070                newVal = newVal & ~ifsrMask;
1071            }
1072            break;
1073          case MISCREG_DFSR:
1074            {
1075                // ARM ARM (ARM DDI 0406C.b) B4.1.52
1076                const uint32_t dfsrMask = mask(31, 14) | mask(8, 8);
1077                newVal = newVal & ~dfsrMask;
1078            }
1079            break;
1080          case MISCREG_AMAIR0:
1081          case MISCREG_AMAIR1:
1082            {
1083                // ARM ARM (ARM DDI 0406C.b) B4.1.5
1084                // Valid only with LPAE
1085                if (!haveLPAE)
1086                    return;
1087                DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal);
1088            }
1089            break;
1090          case MISCREG_SCR:
1091            tc->getITBPtr()->invalidateMiscReg();
1092            tc->getDTBPtr()->invalidateMiscReg();
1093            break;
1094          case MISCREG_SCTLR:
1095            {
1096                DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
1097                scr = readMiscRegNoEffect(MISCREG_SCR);
1098                MiscRegIndex sctlr_idx = (haveSecurity && !scr.ns)
1099                                         ? MISCREG_SCTLR_S : MISCREG_SCTLR_NS;
1100                SCTLR sctlr = miscRegs[sctlr_idx];
1101                SCTLR new_sctlr = newVal;
1102                new_sctlr.nmfi =  ((bool)sctlr.nmfi) && !haveVirtualization;
1103                miscRegs[sctlr_idx] = (MiscReg)new_sctlr;
1104                tc->getITBPtr()->invalidateMiscReg();
1105                tc->getDTBPtr()->invalidateMiscReg();
1106            }
1107          case MISCREG_MIDR:
1108          case MISCREG_ID_PFR0:
1109          case MISCREG_ID_PFR1:
1110          case MISCREG_ID_DFR0:
1111          case MISCREG_ID_MMFR0:
1112          case MISCREG_ID_MMFR1:
1113          case MISCREG_ID_MMFR2:
1114          case MISCREG_ID_MMFR3:
1115          case MISCREG_ID_ISAR0:
1116          case MISCREG_ID_ISAR1:
1117          case MISCREG_ID_ISAR2:
1118          case MISCREG_ID_ISAR3:
1119          case MISCREG_ID_ISAR4:
1120          case MISCREG_ID_ISAR5:
1121
1122          case MISCREG_MPIDR:
1123          case MISCREG_FPSID:
1124          case MISCREG_TLBTR:
1125          case MISCREG_MVFR0:
1126          case MISCREG_MVFR1:
1127
1128          case MISCREG_ID_AA64AFR0_EL1:
1129          case MISCREG_ID_AA64AFR1_EL1:
1130          case MISCREG_ID_AA64DFR0_EL1:
1131          case MISCREG_ID_AA64DFR1_EL1:
1132          case MISCREG_ID_AA64ISAR0_EL1:
1133          case MISCREG_ID_AA64ISAR1_EL1:
1134          case MISCREG_ID_AA64MMFR0_EL1:
1135          case MISCREG_ID_AA64MMFR1_EL1:
1136          case MISCREG_ID_AA64PFR0_EL1:
1137          case MISCREG_ID_AA64PFR1_EL1:
1138            // ID registers are constants.
1139            return;
1140
1141          // TLBI all entries, EL0&1 inner sharable (ignored)
1142          case MISCREG_TLBIALLIS:
1143          case MISCREG_TLBIALL: // TLBI all entries, EL0&1,
1144            assert32(tc);
1145            target_el = 1; // el 0 and 1 are handled together
1146            scr = readMiscReg(MISCREG_SCR, tc);
1147            secure_lookup = haveSecurity && !scr.ns;
1148            sys = tc->getSystemPtr();
1149            for (x = 0; x < sys->numContexts(); x++) {
1150                oc = sys->getThreadContext(x);
1151                assert(oc->getITBPtr() && oc->getDTBPtr());
1152                oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el);
1153                oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el);
1154
1155                // If CheckerCPU is connected, need to notify it of a flush
1156                CheckerCPU *checker = oc->getCheckerCpuPtr();
1157                if (checker) {
1158                    checker->getITBPtr()->flushAllSecurity(secure_lookup,
1159                                                           target_el);
1160                    checker->getDTBPtr()->flushAllSecurity(secure_lookup,
1161                                                           target_el);
1162                }
1163            }
1164            return;
1165          // TLBI all entries, EL0&1, instruction side
1166          case MISCREG_ITLBIALL:
1167            assert32(tc);
1168            target_el = 1; // el 0 and 1 are handled together
1169            scr = readMiscReg(MISCREG_SCR, tc);
1170            secure_lookup = haveSecurity && !scr.ns;
1171            tc->getITBPtr()->flushAllSecurity(secure_lookup, target_el);
1172            return;
1173          // TLBI all entries, EL0&1, data side
1174          case MISCREG_DTLBIALL:
1175            assert32(tc);
1176            target_el = 1; // el 0 and 1 are handled together
1177            scr = readMiscReg(MISCREG_SCR, tc);
1178            secure_lookup = haveSecurity && !scr.ns;
1179            tc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el);
1180            return;
1181          // TLBI based on VA, EL0&1 inner sharable (ignored)
1182          case MISCREG_TLBIMVAIS:
1183          case MISCREG_TLBIMVA:
1184            assert32(tc);
1185            target_el = 1; // el 0 and 1 are handled together
1186            scr = readMiscReg(MISCREG_SCR, tc);
1187            secure_lookup = haveSecurity && !scr.ns;
1188            sys = tc->getSystemPtr();
1189            for (x = 0; x < sys->numContexts(); x++) {
1190                oc = sys->getThreadContext(x);
1191                assert(oc->getITBPtr() && oc->getDTBPtr());
1192                oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
1193                                              bits(newVal, 7,0),
1194                                              secure_lookup, target_el);
1195                oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
1196                                              bits(newVal, 7,0),
1197                                              secure_lookup, target_el);
1198
1199                CheckerCPU *checker = oc->getCheckerCpuPtr();
1200                if (checker) {
1201                    checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
1202                        bits(newVal, 7,0), secure_lookup, target_el);
1203                    checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
1204                        bits(newVal, 7,0), secure_lookup, target_el);
1205                }
1206            }
1207            return;
1208          // TLBI by ASID, EL0&1, inner sharable
1209          case MISCREG_TLBIASIDIS:
1210          case MISCREG_TLBIASID:
1211            assert32(tc);
1212            target_el = 1; // el 0 and 1 are handled together
1213            scr = readMiscReg(MISCREG_SCR, tc);
1214            secure_lookup = haveSecurity && !scr.ns;
1215            sys = tc->getSystemPtr();
1216            for (x = 0; x < sys->numContexts(); x++) {
1217                oc = sys->getThreadContext(x);
1218                assert(oc->getITBPtr() && oc->getDTBPtr());
1219                oc->getITBPtr()->flushAsid(bits(newVal, 7,0),
1220                    secure_lookup, target_el);
1221                oc->getDTBPtr()->flushAsid(bits(newVal, 7,0),
1222                    secure_lookup, target_el);
1223                CheckerCPU *checker = oc->getCheckerCpuPtr();
1224                if (checker) {
1225                    checker->getITBPtr()->flushAsid(bits(newVal, 7,0),
1226                        secure_lookup, target_el);
1227                    checker->getDTBPtr()->flushAsid(bits(newVal, 7,0),
1228                        secure_lookup, target_el);
1229                }
1230            }
1231            return;
1232          // TLBI by address, EL0&1, inner sharable (ignored)
1233          case MISCREG_TLBIMVAAIS:
1234          case MISCREG_TLBIMVAA:
1235            assert32(tc);
1236            target_el = 1; // el 0 and 1 are handled together
1237            scr = readMiscReg(MISCREG_SCR, tc);
1238            secure_lookup = haveSecurity && !scr.ns;
1239            hyp = 0;
1240            tlbiMVA(tc, newVal, secure_lookup, hyp, target_el);
1241            return;
1242          // TLBI by address, EL2, hypervisor mode
1243          case MISCREG_TLBIMVAH:
1244          case MISCREG_TLBIMVAHIS:
1245            assert32(tc);
1246            target_el = 1; // aarch32, use hyp bit
1247            scr = readMiscReg(MISCREG_SCR, tc);
1248            secure_lookup = haveSecurity && !scr.ns;
1249            hyp = 1;
1250            tlbiMVA(tc, newVal, secure_lookup, hyp, target_el);
1251            return;
1252          // TLBI by address and asid, EL0&1, instruction side only
1253          case MISCREG_ITLBIMVA:
1254            assert32(tc);
1255            target_el = 1; // el 0 and 1 are handled together
1256            scr = readMiscReg(MISCREG_SCR, tc);
1257            secure_lookup = haveSecurity && !scr.ns;
1258            tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
1259                bits(newVal, 7,0), secure_lookup, target_el);
1260            return;
1261          // TLBI by address and asid, EL0&1, data side only
1262          case MISCREG_DTLBIMVA:
1263            assert32(tc);
1264            target_el = 1; // el 0 and 1 are handled together
1265            scr = readMiscReg(MISCREG_SCR, tc);
1266            secure_lookup = haveSecurity && !scr.ns;
1267            tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
1268                bits(newVal, 7,0), secure_lookup, target_el);
1269            return;
1270          // TLBI by ASID, EL0&1, instrution side only
1271          case MISCREG_ITLBIASID:
1272            assert32(tc);
1273            target_el = 1; // el 0 and 1 are handled together
1274            scr = readMiscReg(MISCREG_SCR, tc);
1275            secure_lookup = haveSecurity && !scr.ns;
1276            tc->getITBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup,
1277                                       target_el);
1278            return;
1279          // TLBI by ASID EL0&1 data size only
1280          case MISCREG_DTLBIASID:
1281            assert32(tc);
1282            target_el = 1; // el 0 and 1 are handled together
1283            scr = readMiscReg(MISCREG_SCR, tc);
1284            secure_lookup = haveSecurity && !scr.ns;
1285            tc->getDTBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup,
1286                                       target_el);
1287            return;
1288          // Invalidate entire Non-secure Hyp/Non-Hyp Unified TLB
1289          case MISCREG_TLBIALLNSNH:
1290          case MISCREG_TLBIALLNSNHIS:
1291            assert32(tc);
1292            target_el = 1; // el 0 and 1 are handled together
1293            hyp = 0;
1294            tlbiALLN(tc, hyp, target_el);
1295            return;
1296          // TLBI all entries, EL2, hyp,
1297          case MISCREG_TLBIALLH:
1298          case MISCREG_TLBIALLHIS:
1299            assert32(tc);
1300            target_el = 1; // aarch32, use hyp bit
1301            hyp = 1;
1302            tlbiALLN(tc, hyp, target_el);
1303            return;
1304          // AArch64 TLBI: invalidate all entries EL3
1305          case MISCREG_TLBI_ALLE3IS:
1306          case MISCREG_TLBI_ALLE3:
1307            assert64(tc);
1308            target_el = 3;
1309            secure_lookup = true;
1310            tlbiALL(tc, secure_lookup, target_el);
1311            return;
1312          // @todo: uncomment this to enable Virtualization
1313          // case MISCREG_TLBI_ALLE2IS:
1314          // case MISCREG_TLBI_ALLE2:
1315          // TLBI all entries, EL0&1
1316          case MISCREG_TLBI_ALLE1IS:
1317          case MISCREG_TLBI_ALLE1:
1318          // AArch64 TLBI: invalidate all entries, stage 1, current VMID
1319          case MISCREG_TLBI_VMALLE1IS:
1320          case MISCREG_TLBI_VMALLE1:
1321          // AArch64 TLBI: invalidate all entries, stages 1 & 2, current VMID
1322          case MISCREG_TLBI_VMALLS12E1IS:
1323          case MISCREG_TLBI_VMALLS12E1:
1324            // @todo: handle VMID and stage 2 to enable Virtualization
1325            assert64(tc);
1326            target_el = 1; // el 0 and 1 are handled together
1327            scr = readMiscReg(MISCREG_SCR, tc);
1328            secure_lookup = haveSecurity && !scr.ns;
1329            tlbiALL(tc, secure_lookup, target_el);
1330            return;
1331          // AArch64 TLBI: invalidate by VA and ASID, stage 1, current VMID
1332          // VAEx(IS) and VALEx(IS) are the same because TLBs only store entries
1333          // from the last level of translation table walks
1334          // @todo: handle VMID to enable Virtualization
1335          // TLBI all entries, EL0&1
1336          case MISCREG_TLBI_VAE3IS_Xt:
1337          case MISCREG_TLBI_VAE3_Xt:
1338          // TLBI by VA, EL3  regime stage 1, last level walk
1339          case MISCREG_TLBI_VALE3IS_Xt:
1340          case MISCREG_TLBI_VALE3_Xt:
1341            assert64(tc);
1342            target_el = 3;
1343            asid = 0xbeef; // does not matter, tlbi is global
1344            secure_lookup = true;
1345            tlbiVA(tc, newVal, asid, secure_lookup, target_el);
1346            return;
1347          // TLBI by VA, EL2
1348          case MISCREG_TLBI_VAE2IS_Xt:
1349          case MISCREG_TLBI_VAE2_Xt:
1350          // TLBI by VA, EL2, stage1 last level walk
1351          case MISCREG_TLBI_VALE2IS_Xt:
1352          case MISCREG_TLBI_VALE2_Xt:
1353            assert64(tc);
1354            target_el = 2;
1355            asid = 0xbeef; // does not matter, tlbi is global
1356            scr = readMiscReg(MISCREG_SCR, tc);
1357            secure_lookup = haveSecurity && !scr.ns;
1358            tlbiVA(tc, newVal, asid, secure_lookup, target_el);
1359            return;
1360          // TLBI by VA EL1 & 0, stage1, ASID, current VMID
1361          case MISCREG_TLBI_VAE1IS_Xt:
1362          case MISCREG_TLBI_VAE1_Xt:
1363          case MISCREG_TLBI_VALE1IS_Xt:
1364          case MISCREG_TLBI_VALE1_Xt:
1365            assert64(tc);
1366            asid = bits(newVal, 63, 48);
1367            target_el = 1; // el 0 and 1 are handled together
1368            scr = readMiscReg(MISCREG_SCR, tc);
1369            secure_lookup = haveSecurity && !scr.ns;
1370            tlbiVA(tc, newVal, asid, secure_lookup, target_el);
1371            return;
1372          // AArch64 TLBI: invalidate by ASID, stage 1, current VMID
1373          // @todo: handle VMID to enable Virtualization
1374          case MISCREG_TLBI_ASIDE1IS_Xt:
1375          case MISCREG_TLBI_ASIDE1_Xt:
1376            assert64(tc);
1377            target_el = 1; // el 0 and 1 are handled together
1378            scr = readMiscReg(MISCREG_SCR, tc);
1379            secure_lookup = haveSecurity && !scr.ns;
1380            sys = tc->getSystemPtr();
1381            for (x = 0; x < sys->numContexts(); x++) {
1382                oc = sys->getThreadContext(x);
1383                assert(oc->getITBPtr() && oc->getDTBPtr());
1384                asid = bits(newVal, 63, 48);
1385                if (!haveLargeAsid64)
1386                    asid &= mask(8);
1387                oc->getITBPtr()->flushAsid(asid, secure_lookup, target_el);
1388                oc->getDTBPtr()->flushAsid(asid, secure_lookup, target_el);
1389                CheckerCPU *checker = oc->getCheckerCpuPtr();
1390                if (checker) {
1391                    checker->getITBPtr()->flushAsid(asid,
1392                        secure_lookup, target_el);
1393                    checker->getDTBPtr()->flushAsid(asid,
1394                        secure_lookup, target_el);
1395                }
1396            }
1397            return;
1398          // AArch64 TLBI: invalidate by VA, ASID, stage 1, current VMID
1399          // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store
1400          // entries from the last level of translation table walks
1401          // @todo: handle VMID to enable Virtualization
1402          case MISCREG_TLBI_VAAE1IS_Xt:
1403          case MISCREG_TLBI_VAAE1_Xt:
1404          case MISCREG_TLBI_VAALE1IS_Xt:
1405          case MISCREG_TLBI_VAALE1_Xt:
1406            assert64(tc);
1407            target_el = 1; // el 0 and 1 are handled together
1408            scr = readMiscReg(MISCREG_SCR, tc);
1409            secure_lookup = haveSecurity && !scr.ns;
1410            sys = tc->getSystemPtr();
1411            for (x = 0; x < sys->numContexts(); x++) {
1412                // @todo: extra controls on TLBI broadcast?
1413                oc = sys->getThreadContext(x);
1414                assert(oc->getITBPtr() && oc->getDTBPtr());
1415                Addr va = ((Addr) bits(newVal, 43, 0)) << 12;
1416                oc->getITBPtr()->flushMva(va,
1417                    secure_lookup, false, target_el);
1418                oc->getDTBPtr()->flushMva(va,
1419                    secure_lookup, false, target_el);
1420
1421                CheckerCPU *checker = oc->getCheckerCpuPtr();
1422                if (checker) {
1423                    checker->getITBPtr()->flushMva(va,
1424                        secure_lookup, false, target_el);
1425                    checker->getDTBPtr()->flushMva(va,
1426                        secure_lookup, false, target_el);
1427                }
1428            }
1429            return;
1430          // AArch64 TLBI: invalidate by IPA, stage 2, current VMID
1431          case MISCREG_TLBI_IPAS2LE1IS_Xt:
1432          case MISCREG_TLBI_IPAS2LE1_Xt:
1433          case MISCREG_TLBI_IPAS2E1IS_Xt:
1434          case MISCREG_TLBI_IPAS2E1_Xt:
1435            assert64(tc);
1436            target_el = 1; // EL 0 and 1 are handled together
1437            scr = readMiscReg(MISCREG_SCR, tc);
1438            secure_lookup = haveSecurity && !scr.ns;
1439            sys = tc->getSystemPtr();
1440            for (x = 0; x < sys->numContexts(); x++) {
1441                oc = sys->getThreadContext(x);
1442                assert(oc->getITBPtr() && oc->getDTBPtr());
1443                Addr ipa = ((Addr) bits(newVal, 35, 0)) << 12;
1444                oc->getITBPtr()->flushIpaVmid(ipa,
1445                    secure_lookup, false, target_el);
1446                oc->getDTBPtr()->flushIpaVmid(ipa,
1447                    secure_lookup, false, target_el);
1448
1449                CheckerCPU *checker = oc->getCheckerCpuPtr();
1450                if (checker) {
1451                    checker->getITBPtr()->flushIpaVmid(ipa,
1452                        secure_lookup, false, target_el);
1453                    checker->getDTBPtr()->flushIpaVmid(ipa,
1454                        secure_lookup, false, target_el);
1455                }
1456            }
1457            return;
1458          case MISCREG_ACTLR:
1459            warn("Not doing anything for write of miscreg ACTLR\n");
1460            break;
1461
1462          case MISCREG_PMXEVTYPER_PMCCFILTR:
1463          case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
1464          case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
1465          case MISCREG_PMCR ... MISCREG_PMOVSSET:
1466            pmu->setMiscReg(misc_reg, newVal);
1467            break;
1468
1469
1470          case MISCREG_HSTR: // TJDBX, now redifined to be RES0
1471            {
1472                HSTR hstrMask = 0;
1473                hstrMask.tjdbx = 1;
1474                newVal &= ~((uint32_t) hstrMask);
1475                break;
1476            }
1477          case MISCREG_HCPTR:
1478            {
1479                // If a CP bit in NSACR is 0 then the corresponding bit in
1480                // HCPTR is RAO/WI. Same applies to NSASEDIS
1481                secure_lookup = haveSecurity &&
1482                    inSecureState(readMiscRegNoEffect(MISCREG_SCR),
1483                                  readMiscRegNoEffect(MISCREG_CPSR));
1484                if (!secure_lookup) {
1485                    MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR);
1486                    MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF;
1487                    newVal = (newVal & ~mask) | (oldValue & mask);
1488                }
1489                break;
1490            }
1491          case MISCREG_HDFAR: // alias for secure DFAR
1492            misc_reg = MISCREG_DFAR_S;
1493            break;
1494          case MISCREG_HIFAR: // alias for secure IFAR
1495            misc_reg = MISCREG_IFAR_S;
1496            break;
1497          case MISCREG_ATS1CPR:
1498          case MISCREG_ATS1CPW:
1499          case MISCREG_ATS1CUR:
1500          case MISCREG_ATS1CUW:
1501          case MISCREG_ATS12NSOPR:
1502          case MISCREG_ATS12NSOPW:
1503          case MISCREG_ATS12NSOUR:
1504          case MISCREG_ATS12NSOUW:
1505          case MISCREG_ATS1HR:
1506          case MISCREG_ATS1HW:
1507            {
1508              Request::Flags flags = 0;
1509              BaseTLB::Mode mode = BaseTLB::Read;
1510              TLB::ArmTranslationType tranType = TLB::NormalTran;
1511              Fault fault;
1512              switch(misc_reg) {
1513                case MISCREG_ATS1CPR:
1514                  flags    = TLB::MustBeOne;
1515                  tranType = TLB::S1CTran;
1516                  mode     = BaseTLB::Read;
1517                  break;
1518                case MISCREG_ATS1CPW:
1519                  flags    = TLB::MustBeOne;
1520                  tranType = TLB::S1CTran;
1521                  mode     = BaseTLB::Write;
1522                  break;
1523                case MISCREG_ATS1CUR:
1524                  flags    = TLB::MustBeOne | TLB::UserMode;
1525                  tranType = TLB::S1CTran;
1526                  mode     = BaseTLB::Read;
1527                  break;
1528                case MISCREG_ATS1CUW:
1529                  flags    = TLB::MustBeOne | TLB::UserMode;
1530                  tranType = TLB::S1CTran;
1531                  mode     = BaseTLB::Write;
1532                  break;
1533                case MISCREG_ATS12NSOPR:
1534                  if (!haveSecurity)
1535                      panic("Security Extensions required for ATS12NSOPR");
1536                  flags    = TLB::MustBeOne;
1537                  tranType = TLB::S1S2NsTran;
1538                  mode     = BaseTLB::Read;
1539                  break;
1540                case MISCREG_ATS12NSOPW:
1541                  if (!haveSecurity)
1542                      panic("Security Extensions required for ATS12NSOPW");
1543                  flags    = TLB::MustBeOne;
1544                  tranType = TLB::S1S2NsTran;
1545                  mode     = BaseTLB::Write;
1546                  break;
1547                case MISCREG_ATS12NSOUR:
1548                  if (!haveSecurity)
1549                      panic("Security Extensions required for ATS12NSOUR");
1550                  flags    = TLB::MustBeOne | TLB::UserMode;
1551                  tranType = TLB::S1S2NsTran;
1552                  mode     = BaseTLB::Read;
1553                  break;
1554                case MISCREG_ATS12NSOUW:
1555                  if (!haveSecurity)
1556                      panic("Security Extensions required for ATS12NSOUW");
1557                  flags    = TLB::MustBeOne | TLB::UserMode;
1558                  tranType = TLB::S1S2NsTran;
1559                  mode     = BaseTLB::Write;
1560                  break;
1561                case MISCREG_ATS1HR: // only really useful from secure mode.
1562                  flags    = TLB::MustBeOne;
1563                  tranType = TLB::HypMode;
1564                  mode     = BaseTLB::Read;
1565                  break;
1566                case MISCREG_ATS1HW:
1567                  flags    = TLB::MustBeOne;
1568                  tranType = TLB::HypMode;
1569                  mode     = BaseTLB::Write;
1570                  break;
1571              }
1572              // If we're in timing mode then doing the translation in
1573              // functional mode then we're slightly distorting performance
1574              // results obtained from simulations. The translation should be
1575              // done in the same mode the core is running in. NOTE: This
1576              // can't be an atomic translation because that causes problems
1577              // with unexpected atomic snoop requests.
1578              warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
1579              Request req(0, val, 0, flags,  Request::funcMasterId,
1580                          tc->pcState().pc(), tc->contextId());
1581              fault = tc->getDTBPtr()->translateFunctional(&req, tc, mode, tranType);
1582              TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1583              HCR   hcr   = readMiscRegNoEffect(MISCREG_HCR);
1584
1585              MiscReg newVal;
1586              if (fault == NoFault) {
1587                  Addr paddr = req.getPaddr();
1588                  if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode ||
1589                     ((tranType & TLB::S1S2NsTran) && hcr.vm) )) {
1590                      newVal = (paddr & mask(39, 12)) |
1591                               (tc->getDTBPtr()->getAttr());
1592                  } else {
1593                      newVal = (paddr & 0xfffff000) |
1594                               (tc->getDTBPtr()->getAttr());
1595                  }
1596                  DPRINTF(MiscRegs,
1597                          "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
1598                          val, newVal);
1599              } else {
1600                  ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get());
1601                  // Set fault bit and FSR
1602                  FSR fsr = armFault->getFsr(tc);
1603
1604                  newVal = ((fsr >> 9) & 1) << 11;
1605                  if (newVal) {
1606                    // LPAE - rearange fault status
1607                    newVal |= ((fsr >>  0) & 0x3f) << 1;
1608                  } else {
1609                    // VMSA - rearange fault status
1610                    newVal |= ((fsr >>  0) & 0xf) << 1;
1611                    newVal |= ((fsr >> 10) & 0x1) << 5;
1612                    newVal |= ((fsr >> 12) & 0x1) << 6;
1613                  }
1614                  newVal |= 0x1; // F bit
1615                  newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
1616                  newVal |= armFault->isStage2() ? 0x200 : 0;
1617                  DPRINTF(MiscRegs,
1618                          "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n",
1619                          val, fsr, newVal);
1620              }
1621              setMiscRegNoEffect(MISCREG_PAR, newVal);
1622              return;
1623            }
1624          case MISCREG_TTBCR:
1625            {
1626                TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1627                const uint32_t ones = (uint32_t)(-1);
1628                TTBCR ttbcrMask = 0;
1629                TTBCR ttbcrNew = newVal;
1630
1631                // ARM DDI 0406C.b, ARMv7-32
1632                ttbcrMask.n = ones; // T0SZ
1633                if (haveSecurity) {
1634                    ttbcrMask.pd0 = ones;
1635                    ttbcrMask.pd1 = ones;
1636                }
1637                ttbcrMask.epd0 = ones;
1638                ttbcrMask.irgn0 = ones;
1639                ttbcrMask.orgn0 = ones;
1640                ttbcrMask.sh0 = ones;
1641                ttbcrMask.ps = ones; // T1SZ
1642                ttbcrMask.a1 = ones;
1643                ttbcrMask.epd1 = ones;
1644                ttbcrMask.irgn1 = ones;
1645                ttbcrMask.orgn1 = ones;
1646                ttbcrMask.sh1 = ones;
1647                if (haveLPAE)
1648                    ttbcrMask.eae = ones;
1649
1650                if (haveLPAE && ttbcrNew.eae) {
1651                    newVal = newVal & ttbcrMask;
1652                } else {
1653                    newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask));
1654                }
1655            }
1656            M5_FALLTHROUGH;
1657          case MISCREG_TTBR0:
1658          case MISCREG_TTBR1:
1659            {
1660                TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1661                if (haveLPAE) {
1662                    if (ttbcr.eae) {
1663                        // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP
1664                        // ARMv8 AArch32 bit 63-56 only
1665                        uint64_t ttbrMask = mask(63,56) | mask(47,40);
1666                        newVal = (newVal & (~ttbrMask));
1667                    }
1668                }
1669            }
1670            M5_FALLTHROUGH;
1671          case MISCREG_SCTLR_EL1:
1672            {
1673                tc->getITBPtr()->invalidateMiscReg();
1674                tc->getDTBPtr()->invalidateMiscReg();
1675                setMiscRegNoEffect(misc_reg, newVal);
1676            }
1677            M5_FALLTHROUGH;
1678          case MISCREG_CONTEXTIDR:
1679          case MISCREG_PRRR:
1680          case MISCREG_NMRR:
1681          case MISCREG_MAIR0:
1682          case MISCREG_MAIR1:
1683          case MISCREG_DACR:
1684          case MISCREG_VTTBR:
1685          case MISCREG_SCR_EL3:
1686          case MISCREG_HCR_EL2:
1687          case MISCREG_TCR_EL1:
1688          case MISCREG_TCR_EL2:
1689          case MISCREG_TCR_EL3:
1690          case MISCREG_SCTLR_EL2:
1691          case MISCREG_SCTLR_EL3:
1692          case MISCREG_HSCTLR:
1693          case MISCREG_TTBR0_EL1:
1694          case MISCREG_TTBR1_EL1:
1695          case MISCREG_TTBR0_EL2:
1696          case MISCREG_TTBR0_EL3:
1697            tc->getITBPtr()->invalidateMiscReg();
1698            tc->getDTBPtr()->invalidateMiscReg();
1699            break;
1700          case MISCREG_NZCV:
1701            {
1702                CPSR cpsr = val;
1703
1704                tc->setCCReg(CCREG_NZ, cpsr.nz);
1705                tc->setCCReg(CCREG_C,  cpsr.c);
1706                tc->setCCReg(CCREG_V,  cpsr.v);
1707            }
1708            break;
1709          case MISCREG_DAIF:
1710            {
1711                CPSR cpsr = miscRegs[MISCREG_CPSR];
1712                cpsr.daif = (uint8_t) ((CPSR) newVal).daif;
1713                newVal = cpsr;
1714                misc_reg = MISCREG_CPSR;
1715            }
1716            break;
1717          case MISCREG_SP_EL0:
1718            tc->setIntReg(INTREG_SP0, newVal);
1719            break;
1720          case MISCREG_SP_EL1:
1721            tc->setIntReg(INTREG_SP1, newVal);
1722            break;
1723          case MISCREG_SP_EL2:
1724            tc->setIntReg(INTREG_SP2, newVal);
1725            break;
1726          case MISCREG_SPSEL:
1727            {
1728                CPSR cpsr = miscRegs[MISCREG_CPSR];
1729                cpsr.sp = (uint8_t) ((CPSR) newVal).sp;
1730                newVal = cpsr;
1731                misc_reg = MISCREG_CPSR;
1732            }
1733            break;
1734          case MISCREG_CURRENTEL:
1735            {
1736                CPSR cpsr = miscRegs[MISCREG_CPSR];
1737                cpsr.el = (uint8_t) ((CPSR) newVal).el;
1738                newVal = cpsr;
1739                misc_reg = MISCREG_CPSR;
1740            }
1741            break;
1742          case MISCREG_AT_S1E1R_Xt:
1743          case MISCREG_AT_S1E1W_Xt:
1744          case MISCREG_AT_S1E0R_Xt:
1745          case MISCREG_AT_S1E0W_Xt:
1746          case MISCREG_AT_S1E2R_Xt:
1747          case MISCREG_AT_S1E2W_Xt:
1748          case MISCREG_AT_S12E1R_Xt:
1749          case MISCREG_AT_S12E1W_Xt:
1750          case MISCREG_AT_S12E0R_Xt:
1751          case MISCREG_AT_S12E0W_Xt:
1752          case MISCREG_AT_S1E3R_Xt:
1753          case MISCREG_AT_S1E3W_Xt:
1754            {
1755                RequestPtr req = new Request;
1756                Request::Flags flags = 0;
1757                BaseTLB::Mode mode = BaseTLB::Read;
1758                TLB::ArmTranslationType tranType = TLB::NormalTran;
1759                Fault fault;
1760                switch(misc_reg) {
1761                  case MISCREG_AT_S1E1R_Xt:
1762                    flags    = TLB::MustBeOne;
1763                    tranType = TLB::S1E1Tran;
1764                    mode     = BaseTLB::Read;
1765                    break;
1766                  case MISCREG_AT_S1E1W_Xt:
1767                    flags    = TLB::MustBeOne;
1768                    tranType = TLB::S1E1Tran;
1769                    mode     = BaseTLB::Write;
1770                    break;
1771                  case MISCREG_AT_S1E0R_Xt:
1772                    flags    = TLB::MustBeOne | TLB::UserMode;
1773                    tranType = TLB::S1E0Tran;
1774                    mode     = BaseTLB::Read;
1775                    break;
1776                  case MISCREG_AT_S1E0W_Xt:
1777                    flags    = TLB::MustBeOne | TLB::UserMode;
1778                    tranType = TLB::S1E0Tran;
1779                    mode     = BaseTLB::Write;
1780                    break;
1781                  case MISCREG_AT_S1E2R_Xt:
1782                    flags    = TLB::MustBeOne;
1783                    tranType = TLB::S1E2Tran;
1784                    mode     = BaseTLB::Read;
1785                    break;
1786                  case MISCREG_AT_S1E2W_Xt:
1787                    flags    = TLB::MustBeOne;
1788                    tranType = TLB::S1E2Tran;
1789                    mode     = BaseTLB::Write;
1790                    break;
1791                  case MISCREG_AT_S12E0R_Xt:
1792                    flags    = TLB::MustBeOne | TLB::UserMode;
1793                    tranType = TLB::S12E0Tran;
1794                    mode     = BaseTLB::Read;
1795                    break;
1796                  case MISCREG_AT_S12E0W_Xt:
1797                    flags    = TLB::MustBeOne | TLB::UserMode;
1798                    tranType = TLB::S12E0Tran;
1799                    mode     = BaseTLB::Write;
1800                    break;
1801                  case MISCREG_AT_S12E1R_Xt:
1802                    flags    = TLB::MustBeOne;
1803                    tranType = TLB::S12E1Tran;
1804                    mode     = BaseTLB::Read;
1805                    break;
1806                  case MISCREG_AT_S12E1W_Xt:
1807                    flags    = TLB::MustBeOne;
1808                    tranType = TLB::S12E1Tran;
1809                    mode     = BaseTLB::Write;
1810                    break;
1811                  case MISCREG_AT_S1E3R_Xt:
1812                    flags    = TLB::MustBeOne;
1813                    tranType = TLB::S1E3Tran;
1814                    mode     = BaseTLB::Read;
1815                    break;
1816                  case MISCREG_AT_S1E3W_Xt:
1817                    flags    = TLB::MustBeOne;
1818                    tranType = TLB::S1E3Tran;
1819                    mode     = BaseTLB::Write;
1820                    break;
1821                }
1822                // If we're in timing mode then doing the translation in
1823                // functional mode then we're slightly distorting performance
1824                // results obtained from simulations. The translation should be
1825                // done in the same mode the core is running in. NOTE: This
1826                // can't be an atomic translation because that causes problems
1827                // with unexpected atomic snoop requests.
1828                warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
1829                req->setVirt(0, val, 0, flags,  Request::funcMasterId,
1830                               tc->pcState().pc());
1831                req->setContext(tc->contextId());
1832                fault = tc->getDTBPtr()->translateFunctional(req, tc, mode,
1833                                                             tranType);
1834
1835                MiscReg newVal;
1836                if (fault == NoFault) {
1837                    Addr paddr = req->getPaddr();
1838                    uint64_t attr = tc->getDTBPtr()->getAttr();
1839                    uint64_t attr1 = attr >> 56;
1840                    if (!attr1 || attr1 ==0x44) {
1841                        attr |= 0x100;
1842                        attr &= ~ uint64_t(0x80);
1843                    }
1844                    newVal = (paddr & mask(47, 12)) | attr;
1845                    DPRINTF(MiscRegs,
1846                          "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
1847                          val, newVal);
1848                } else {
1849                    ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get());
1850                    // Set fault bit and FSR
1851                    FSR fsr = armFault->getFsr(tc);
1852
1853                    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
1854                    if (cpsr.width) { // AArch32
1855                        newVal = ((fsr >> 9) & 1) << 11;
1856                        // rearrange fault status
1857                        newVal |= ((fsr >>  0) & 0x3f) << 1;
1858                        newVal |= 0x1; // F bit
1859                        newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
1860                        newVal |= armFault->isStage2() ? 0x200 : 0;
1861                    } else { // AArch64
1862                        newVal = 1; // F bit
1863                        newVal |= fsr << 1; // FST
1864                        // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit.
1865                        newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW
1866                        newVal |= armFault->isStage2() ? 1 << 9 : 0; // S
1867                        newVal |= 1 << 11; // RES1
1868                    }
1869                    DPRINTF(MiscRegs,
1870                            "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
1871                            val, fsr, newVal);
1872                }
1873                delete req;
1874                setMiscRegNoEffect(MISCREG_PAR_EL1, newVal);
1875                return;
1876            }
1877          case MISCREG_SPSR_EL3:
1878          case MISCREG_SPSR_EL2:
1879          case MISCREG_SPSR_EL1:
1880            // Force bits 23:21 to 0
1881            newVal = val & ~(0x7 << 21);
1882            break;
1883          case MISCREG_L2CTLR:
1884            warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
1885                 miscRegName[misc_reg], uint32_t(val));
1886            break;
1887
1888          // Generic Timer registers
1889          case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
1890          case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
1891          case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:
1892          case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1:
1893            getGenericTimer(tc).setMiscReg(misc_reg, newVal);
1894            break;
1895        }
1896    }
1897    setMiscRegNoEffect(misc_reg, newVal);
1898}
1899
1900void
1901ISA::tlbiVA(ThreadContext *tc, MiscReg newVal, uint16_t asid,
1902            bool secure_lookup, uint8_t target_el)
1903{
1904    if (!haveLargeAsid64)
1905        asid &= mask(8);
1906    Addr va = ((Addr) bits(newVal, 43, 0)) << 12;
1907    System *sys = tc->getSystemPtr();
1908    for (int x = 0; x < sys->numContexts(); x++) {
1909        ThreadContext *oc = sys->getThreadContext(x);
1910        assert(oc->getITBPtr() && oc->getDTBPtr());
1911        oc->getITBPtr()->flushMvaAsid(va, asid,
1912                                      secure_lookup, target_el);
1913        oc->getDTBPtr()->flushMvaAsid(va, asid,
1914                                      secure_lookup, target_el);
1915
1916        CheckerCPU *checker = oc->getCheckerCpuPtr();
1917        if (checker) {
1918            checker->getITBPtr()->flushMvaAsid(
1919                va, asid, secure_lookup, target_el);
1920            checker->getDTBPtr()->flushMvaAsid(
1921                va, asid, secure_lookup, target_el);
1922        }
1923    }
1924}
1925
1926void
1927ISA::tlbiALL(ThreadContext *tc, bool secure_lookup, uint8_t target_el)
1928{
1929    System *sys = tc->getSystemPtr();
1930    for (int x = 0; x < sys->numContexts(); x++) {
1931        ThreadContext *oc = sys->getThreadContext(x);
1932        assert(oc->getITBPtr() && oc->getDTBPtr());
1933        oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el);
1934        oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el);
1935
1936        // If CheckerCPU is connected, need to notify it of a flush
1937        CheckerCPU *checker = oc->getCheckerCpuPtr();
1938        if (checker) {
1939            checker->getITBPtr()->flushAllSecurity(secure_lookup,
1940                                                   target_el);
1941            checker->getDTBPtr()->flushAllSecurity(secure_lookup,
1942                                                   target_el);
1943        }
1944    }
1945}
1946
1947void
1948ISA::tlbiALLN(ThreadContext *tc, bool hyp, uint8_t target_el)
1949{
1950    System *sys = tc->getSystemPtr();
1951    for (int x = 0; x < sys->numContexts(); x++) {
1952      ThreadContext *oc = sys->getThreadContext(x);
1953      assert(oc->getITBPtr() && oc->getDTBPtr());
1954      oc->getITBPtr()->flushAllNs(hyp, target_el);
1955      oc->getDTBPtr()->flushAllNs(hyp, target_el);
1956
1957      CheckerCPU *checker = oc->getCheckerCpuPtr();
1958      if (checker) {
1959          checker->getITBPtr()->flushAllNs(hyp, target_el);
1960          checker->getDTBPtr()->flushAllNs(hyp, target_el);
1961      }
1962    }
1963}
1964
1965void
1966ISA::tlbiMVA(ThreadContext *tc, MiscReg newVal, bool secure_lookup, bool hyp,
1967             uint8_t target_el)
1968{
1969    System *sys = tc->getSystemPtr();
1970    for (int x = 0; x < sys->numContexts(); x++) {
1971        ThreadContext *oc = sys->getThreadContext(x);
1972        assert(oc->getITBPtr() && oc->getDTBPtr());
1973        oc->getITBPtr()->flushMva(mbits(newVal, 31,12),
1974            secure_lookup, hyp, target_el);
1975        oc->getDTBPtr()->flushMva(mbits(newVal, 31,12),
1976            secure_lookup, hyp, target_el);
1977
1978        CheckerCPU *checker = oc->getCheckerCpuPtr();
1979        if (checker) {
1980            checker->getITBPtr()->flushMva(mbits(newVal, 31,12),
1981                secure_lookup, hyp, target_el);
1982            checker->getDTBPtr()->flushMva(mbits(newVal, 31,12),
1983                secure_lookup, hyp, target_el);
1984        }
1985    }
1986}
1987
1988BaseISADevice &
1989ISA::getGenericTimer(ThreadContext *tc)
1990{
1991    // We only need to create an ISA interface the first time we try
1992    // to access the timer.
1993    if (timer)
1994        return *timer.get();
1995
1996    assert(system);
1997    GenericTimer *generic_timer(system->getGenericTimer());
1998    if (!generic_timer) {
1999        panic("Trying to get a generic timer from a system that hasn't "
2000              "been configured to use a generic timer.\n");
2001    }
2002
2003    timer.reset(new GenericTimerISA(*generic_timer, tc->contextId()));
2004    return *timer.get();
2005}
2006
2007}
2008
2009ArmISA::ISA *
2010ArmISAParams::create()
2011{
2012    return new ArmISA::ISA(this);
2013}
2014