isa.cc revision 11809:61c625151d9a
1/* 2 * Copyright (c) 2010-2016 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 */ 40 41#include "arch/arm/isa.hh" 42 43#include "arch/arm/pmu.hh" 44#include "arch/arm/system.hh" 45#include "cpu/base.hh" 46#include "cpu/checker/cpu.hh" 47#include "debug/Arm.hh" 48#include "debug/MiscRegs.hh" 49#include "dev/arm/generic_timer.hh" 50#include "params/ArmISA.hh" 51#include "sim/faults.hh" 52#include "sim/stat_control.hh" 53#include "sim/system.hh" 54 55namespace ArmISA 56{ 57 58 59/** 60 * Some registers alias with others, and therefore need to be translated. 61 * For each entry: 62 * The first value is the misc register that is to be looked up 63 * the second value is the lower part of the translation 64 * the third the upper part 65 * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543 66 */ 67const struct ISA::MiscRegInitializerEntry 68 ISA::MiscRegSwitch[] = { 69 {MISCREG_ACTLR_EL1, {MISCREG_ACTLR_NS, 0}}, 70 {MISCREG_AFSR0_EL1, {MISCREG_ADFSR_NS, 0}}, 71 {MISCREG_AFSR1_EL1, {MISCREG_AIFSR_NS, 0}}, 72 {MISCREG_AMAIR_EL1, {MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS}}, 73 {MISCREG_CONTEXTIDR_EL1, {MISCREG_CONTEXTIDR_NS, 0}}, 74 {MISCREG_CPACR_EL1, {MISCREG_CPACR, 0}}, 75 {MISCREG_CSSELR_EL1, {MISCREG_CSSELR_NS, 0}}, 76 {MISCREG_DACR32_EL2, {MISCREG_DACR_NS, 0}}, 77 {MISCREG_FAR_EL1, {MISCREG_DFAR_NS, MISCREG_IFAR_NS}}, 78 // ESR_EL1 -> DFSR 79 {MISCREG_HACR_EL2, {MISCREG_HACR, 0}}, 80 {MISCREG_ACTLR_EL2, {MISCREG_HACTLR, 0}}, 81 {MISCREG_AFSR0_EL2, {MISCREG_HADFSR, 0}}, 82 {MISCREG_AFSR1_EL2, {MISCREG_HAIFSR, 0}}, 83 {MISCREG_AMAIR_EL2, {MISCREG_HAMAIR0, MISCREG_HAMAIR1}}, 84 {MISCREG_CPTR_EL2, {MISCREG_HCPTR, 0}}, 85 {MISCREG_HCR_EL2, {MISCREG_HCR, 0 /*MISCREG_HCR2*/}}, 86 {MISCREG_MDCR_EL2, {MISCREG_HDCR, 0}}, 87 {MISCREG_FAR_EL2, {MISCREG_HDFAR, MISCREG_HIFAR}}, 88 {MISCREG_MAIR_EL2, {MISCREG_HMAIR0, MISCREG_HMAIR1}}, 89 {MISCREG_HPFAR_EL2, {MISCREG_HPFAR, 0}}, 90 {MISCREG_SCTLR_EL2, {MISCREG_HSCTLR, 0}}, 91 {MISCREG_ESR_EL2, {MISCREG_HSR, 0}}, 92 {MISCREG_HSTR_EL2, {MISCREG_HSTR, 0}}, 93 {MISCREG_TCR_EL2, {MISCREG_HTCR, 0}}, 94 {MISCREG_TPIDR_EL2, {MISCREG_HTPIDR, 0}}, 95 {MISCREG_TTBR0_EL2, {MISCREG_HTTBR, 0}}, 96 {MISCREG_VBAR_EL2, {MISCREG_HVBAR, 0}}, 97 {MISCREG_IFSR32_EL2, {MISCREG_IFSR_NS, 0}}, 98 {MISCREG_MAIR_EL1, {MISCREG_PRRR_NS, MISCREG_NMRR_NS}}, 99 {MISCREG_PAR_EL1, {MISCREG_PAR_NS, 0}}, 100 // RMR_EL1 -> RMR 101 // RMR_EL2 -> HRMR 102 {MISCREG_SCTLR_EL1, {MISCREG_SCTLR_NS, 0}}, 103 {MISCREG_SDER32_EL3, {MISCREG_SDER, 0}}, 104 {MISCREG_TPIDR_EL1, {MISCREG_TPIDRPRW_NS, 0}}, 105 {MISCREG_TPIDRRO_EL0, {MISCREG_TPIDRURO_NS, 0}}, 106 {MISCREG_TPIDR_EL0, {MISCREG_TPIDRURW_NS, 0}}, 107 {MISCREG_TCR_EL1, {MISCREG_TTBCR_NS, 0}}, 108 {MISCREG_TTBR0_EL1, {MISCREG_TTBR0_NS, 0}}, 109 {MISCREG_TTBR1_EL1, {MISCREG_TTBR1_NS, 0}}, 110 {MISCREG_VBAR_EL1, {MISCREG_VBAR_NS, 0}}, 111 {MISCREG_VMPIDR_EL2, {MISCREG_VMPIDR, 0}}, 112 {MISCREG_VPIDR_EL2, {MISCREG_VPIDR, 0}}, 113 {MISCREG_VTCR_EL2, {MISCREG_VTCR, 0}}, 114 {MISCREG_VTTBR_EL2, {MISCREG_VTTBR, 0}}, 115 {MISCREG_CNTFRQ_EL0, {MISCREG_CNTFRQ, 0}}, 116 {MISCREG_CNTHCTL_EL2, {MISCREG_CNTHCTL, 0}}, 117 {MISCREG_CNTHP_CTL_EL2, {MISCREG_CNTHP_CTL, 0}}, 118 {MISCREG_CNTHP_CVAL_EL2, {MISCREG_CNTHP_CVAL, 0}}, /* 64b */ 119 {MISCREG_CNTHP_TVAL_EL2, {MISCREG_CNTHP_TVAL, 0}}, 120 {MISCREG_CNTKCTL_EL1, {MISCREG_CNTKCTL, 0}}, 121 {MISCREG_CNTP_CTL_EL0, {MISCREG_CNTP_CTL_NS, 0}}, 122 {MISCREG_CNTP_CVAL_EL0, {MISCREG_CNTP_CVAL_NS, 0}}, /* 64b */ 123 {MISCREG_CNTP_TVAL_EL0, {MISCREG_CNTP_TVAL_NS, 0}}, 124 {MISCREG_CNTPCT_EL0, {MISCREG_CNTPCT, 0}}, /* 64b */ 125 {MISCREG_CNTV_CTL_EL0, {MISCREG_CNTV_CTL, 0}}, 126 {MISCREG_CNTV_CVAL_EL0, {MISCREG_CNTV_CVAL, 0}}, /* 64b */ 127 {MISCREG_CNTV_TVAL_EL0, {MISCREG_CNTV_TVAL, 0}}, 128 {MISCREG_CNTVCT_EL0, {MISCREG_CNTVCT, 0}}, /* 64b */ 129 {MISCREG_CNTVOFF_EL2, {MISCREG_CNTVOFF, 0}}, /* 64b */ 130 {MISCREG_DBGAUTHSTATUS_EL1, {MISCREG_DBGAUTHSTATUS, 0}}, 131 {MISCREG_DBGBCR0_EL1, {MISCREG_DBGBCR0, 0}}, 132 {MISCREG_DBGBCR1_EL1, {MISCREG_DBGBCR1, 0}}, 133 {MISCREG_DBGBCR2_EL1, {MISCREG_DBGBCR2, 0}}, 134 {MISCREG_DBGBCR3_EL1, {MISCREG_DBGBCR3, 0}}, 135 {MISCREG_DBGBCR4_EL1, {MISCREG_DBGBCR4, 0}}, 136 {MISCREG_DBGBCR5_EL1, {MISCREG_DBGBCR5, 0}}, 137 {MISCREG_DBGBVR0_EL1, {MISCREG_DBGBVR0, 0 /* MISCREG_DBGBXVR0 */}}, 138 {MISCREG_DBGBVR1_EL1, {MISCREG_DBGBVR1, 0 /* MISCREG_DBGBXVR1 */}}, 139 {MISCREG_DBGBVR2_EL1, {MISCREG_DBGBVR2, 0 /* MISCREG_DBGBXVR2 */}}, 140 {MISCREG_DBGBVR3_EL1, {MISCREG_DBGBVR3, 0 /* MISCREG_DBGBXVR3 */}}, 141 {MISCREG_DBGBVR4_EL1, {MISCREG_DBGBVR4, MISCREG_DBGBXVR4}}, 142 {MISCREG_DBGBVR5_EL1, {MISCREG_DBGBVR5, MISCREG_DBGBXVR5}}, 143 {MISCREG_DBGCLAIMSET_EL1, {MISCREG_DBGCLAIMSET, 0}}, 144 {MISCREG_DBGCLAIMCLR_EL1, {MISCREG_DBGCLAIMCLR, 0}}, 145 // DBGDTR_EL0 -> DBGDTR{R or T}Xint 146 // DBGDTRRX_EL0 -> DBGDTRRXint 147 // DBGDTRTX_EL0 -> DBGDTRRXint 148 {MISCREG_DBGPRCR_EL1, {MISCREG_DBGPRCR, 0}}, 149 {MISCREG_DBGVCR32_EL2, {MISCREG_DBGVCR, 0}}, 150 {MISCREG_DBGWCR0_EL1, {MISCREG_DBGWCR0, 0}}, 151 {MISCREG_DBGWCR1_EL1, {MISCREG_DBGWCR1, 0}}, 152 {MISCREG_DBGWCR2_EL1, {MISCREG_DBGWCR2, 0}}, 153 {MISCREG_DBGWCR3_EL1, {MISCREG_DBGWCR3, 0}}, 154 {MISCREG_DBGWVR0_EL1, {MISCREG_DBGWVR0, 0}}, 155 {MISCREG_DBGWVR1_EL1, {MISCREG_DBGWVR1, 0}}, 156 {MISCREG_DBGWVR2_EL1, {MISCREG_DBGWVR2, 0}}, 157 {MISCREG_DBGWVR3_EL1, {MISCREG_DBGWVR3, 0}}, 158 {MISCREG_ID_DFR0_EL1, {MISCREG_ID_DFR0, 0}}, 159 {MISCREG_MDCCSR_EL0, {MISCREG_DBGDSCRint, 0}}, 160 {MISCREG_MDRAR_EL1, {MISCREG_DBGDRAR, 0}}, 161 {MISCREG_MDSCR_EL1, {MISCREG_DBGDSCRext, 0}}, 162 {MISCREG_OSDLR_EL1, {MISCREG_DBGOSDLR, 0}}, 163 {MISCREG_OSDTRRX_EL1, {MISCREG_DBGDTRRXext, 0}}, 164 {MISCREG_OSDTRTX_EL1, {MISCREG_DBGDTRTXext, 0}}, 165 {MISCREG_OSECCR_EL1, {MISCREG_DBGOSECCR, 0}}, 166 {MISCREG_OSLAR_EL1, {MISCREG_DBGOSLAR, 0}}, 167 {MISCREG_OSLSR_EL1, {MISCREG_DBGOSLSR, 0}}, 168 {MISCREG_PMCCNTR_EL0, {MISCREG_PMCCNTR, 0}}, 169 {MISCREG_PMCEID0_EL0, {MISCREG_PMCEID0, 0}}, 170 {MISCREG_PMCEID1_EL0, {MISCREG_PMCEID1, 0}}, 171 {MISCREG_PMCNTENSET_EL0, {MISCREG_PMCNTENSET, 0}}, 172 {MISCREG_PMCNTENCLR_EL0, {MISCREG_PMCNTENCLR, 0}}, 173 {MISCREG_PMCR_EL0, {MISCREG_PMCR, 0}}, 174/* {MISCREG_PMEVCNTR0_EL0, {MISCREG_PMEVCNTR0, 0}}, 175 {MISCREG_PMEVCNTR1_EL0, {MISCREG_PMEVCNTR1, 0}}, 176 {MISCREG_PMEVCNTR2_EL0, {MISCREG_PMEVCNTR2, 0}}, 177 {MISCREG_PMEVCNTR3_EL0, {MISCREG_PMEVCNTR3, 0}}, 178 {MISCREG_PMEVCNTR4_EL0, {MISCREG_PMEVCNTR4, 0}}, 179 {MISCREG_PMEVCNTR5_EL0, {MISCREG_PMEVCNTR5, 0}}, 180 {MISCREG_PMEVTYPER0_EL0, {MISCREG_PMEVTYPER0, 0}}, 181 {MISCREG_PMEVTYPER1_EL0, {MISCREG_PMEVTYPER1, 0}}, 182 {MISCREG_PMEVTYPER2_EL0, {MISCREG_PMEVTYPER2, 0}}, 183 {MISCREG_PMEVTYPER3_EL0, {MISCREG_PMEVTYPER3, 0}}, 184 {MISCREG_PMEVTYPER4_EL0, {MISCREG_PMEVTYPER4, 0}}, 185 {MISCREG_PMEVTYPER5_EL0, {MISCREG_PMEVTYPER5, 0}}, */ 186 {MISCREG_PMINTENCLR_EL1, {MISCREG_PMINTENCLR, 0}}, 187 {MISCREG_PMINTENSET_EL1, {MISCREG_PMINTENSET, 0}}, 188// {MISCREG_PMOVSCLR_EL0, {MISCREG_PMOVSCLR, 0}}, 189 {MISCREG_PMOVSSET_EL0, {MISCREG_PMOVSSET, 0}}, 190 {MISCREG_PMSELR_EL0, {MISCREG_PMSELR, 0}}, 191 {MISCREG_PMSWINC_EL0, {MISCREG_PMSWINC, 0}}, 192 {MISCREG_PMUSERENR_EL0, {MISCREG_PMUSERENR, 0}}, 193 {MISCREG_PMXEVCNTR_EL0, {MISCREG_PMXEVCNTR, 0}}, 194 {MISCREG_PMXEVTYPER_EL0, {MISCREG_PMXEVTYPER, 0}}, 195 196 // from ARM DDI 0487A.i, template text 197 // "AArch64 System register ___ can be mapped to 198 // AArch32 System register ___, but this is not 199 // architecturally mandated." 200 {MISCREG_SCR_EL3, {MISCREG_SCR, 0}}, // D7-2005 201 // MDCR_EL3 -> SDCR, D7-2108 (the latter is unimpl. in gem5) 202 {MISCREG_SPSR_EL1, {MISCREG_SPSR_SVC, 0}}, // C5.2.17 SPSR_EL1 203 {MISCREG_SPSR_EL2, {MISCREG_SPSR_HYP, 0}}, // C5.2.18 SPSR_EL2 204 {MISCREG_SPSR_EL3, {MISCREG_SPSR_MON, 0}}, // C5.2.19 SPSR_EL3 205}; 206 207 208ISA::ISA(Params *p) 209 : SimObject(p), 210 system(NULL), 211 _decoderFlavour(p->decoderFlavour), 212 pmu(p->pmu), 213 lookUpMiscReg(NUM_MISCREGS, {0,0}) 214{ 215 miscRegs[MISCREG_SCTLR_RST] = 0; 216 217 // Hook up a dummy device if we haven't been configured with a 218 // real PMU. By using a dummy device, we don't need to check that 219 // the PMU exist every time we try to access a PMU register. 220 if (!pmu) 221 pmu = &dummyDevice; 222 223 // Give all ISA devices a pointer to this ISA 224 pmu->setISA(this); 225 226 system = dynamic_cast<ArmSystem *>(p->system); 227 228 // Cache system-level properties 229 if (FullSystem && system) { 230 highestELIs64 = system->highestELIs64(); 231 haveSecurity = system->haveSecurity(); 232 haveLPAE = system->haveLPAE(); 233 haveVirtualization = system->haveVirtualization(); 234 haveLargeAsid64 = system->haveLargeAsid64(); 235 physAddrRange64 = system->physAddrRange64(); 236 } else { 237 highestELIs64 = true; // ArmSystem::highestELIs64 does the same 238 haveSecurity = haveLPAE = haveVirtualization = false; 239 haveLargeAsid64 = false; 240 physAddrRange64 = 32; // dummy value 241 } 242 243 /** Fill in the miscReg translation table */ 244 for (auto sw : MiscRegSwitch) { 245 lookUpMiscReg[sw.index] = sw.entry; 246 } 247 248 preUnflattenMiscReg(); 249 250 clear(); 251} 252 253const ArmISAParams * 254ISA::params() const 255{ 256 return dynamic_cast<const Params *>(_params); 257} 258 259void 260ISA::clear() 261{ 262 const Params *p(params()); 263 264 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 265 memset(miscRegs, 0, sizeof(miscRegs)); 266 267 // Initialize configurable default values 268 miscRegs[MISCREG_MIDR] = p->midr; 269 miscRegs[MISCREG_MIDR_EL1] = p->midr; 270 miscRegs[MISCREG_VPIDR] = p->midr; 271 272 if (FullSystem && system->highestELIs64()) { 273 // Initialize AArch64 state 274 clear64(p); 275 return; 276 } 277 278 // Initialize AArch32 state... 279 280 CPSR cpsr = 0; 281 cpsr.mode = MODE_USER; 282 miscRegs[MISCREG_CPSR] = cpsr; 283 updateRegMap(cpsr); 284 285 SCTLR sctlr = 0; 286 sctlr.te = (bool) sctlr_rst.te; 287 sctlr.nmfi = (bool) sctlr_rst.nmfi; 288 sctlr.v = (bool) sctlr_rst.v; 289 sctlr.u = 1; 290 sctlr.xp = 1; 291 sctlr.rao2 = 1; 292 sctlr.rao3 = 1; 293 sctlr.rao4 = 0xf; // SCTLR[6:3] 294 sctlr.uci = 1; 295 sctlr.dze = 1; 296 miscRegs[MISCREG_SCTLR_NS] = sctlr; 297 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 298 miscRegs[MISCREG_HCPTR] = 0; 299 300 // Start with an event in the mailbox 301 miscRegs[MISCREG_SEV_MAILBOX] = 1; 302 303 // Separate Instruction and Data TLBs 304 miscRegs[MISCREG_TLBTR] = 1; 305 306 MVFR0 mvfr0 = 0; 307 mvfr0.advSimdRegisters = 2; 308 mvfr0.singlePrecision = 2; 309 mvfr0.doublePrecision = 2; 310 mvfr0.vfpExceptionTrapping = 0; 311 mvfr0.divide = 1; 312 mvfr0.squareRoot = 1; 313 mvfr0.shortVectors = 1; 314 mvfr0.roundingModes = 1; 315 miscRegs[MISCREG_MVFR0] = mvfr0; 316 317 MVFR1 mvfr1 = 0; 318 mvfr1.flushToZero = 1; 319 mvfr1.defaultNaN = 1; 320 mvfr1.advSimdLoadStore = 1; 321 mvfr1.advSimdInteger = 1; 322 mvfr1.advSimdSinglePrecision = 1; 323 mvfr1.advSimdHalfPrecision = 1; 324 mvfr1.vfpHalfPrecision = 1; 325 miscRegs[MISCREG_MVFR1] = mvfr1; 326 327 // Reset values of PRRR and NMRR are implementation dependent 328 329 // @todo: PRRR and NMRR in secure state? 330 miscRegs[MISCREG_PRRR_NS] = 331 (1 << 19) | // 19 332 (0 << 18) | // 18 333 (0 << 17) | // 17 334 (1 << 16) | // 16 335 (2 << 14) | // 15:14 336 (0 << 12) | // 13:12 337 (2 << 10) | // 11:10 338 (2 << 8) | // 9:8 339 (2 << 6) | // 7:6 340 (2 << 4) | // 5:4 341 (1 << 2) | // 3:2 342 0; // 1:0 343 miscRegs[MISCREG_NMRR_NS] = 344 (1 << 30) | // 31:30 345 (0 << 26) | // 27:26 346 (0 << 24) | // 25:24 347 (3 << 22) | // 23:22 348 (2 << 20) | // 21:20 349 (0 << 18) | // 19:18 350 (0 << 16) | // 17:16 351 (1 << 14) | // 15:14 352 (0 << 12) | // 13:12 353 (2 << 10) | // 11:10 354 (0 << 8) | // 9:8 355 (3 << 6) | // 7:6 356 (2 << 4) | // 5:4 357 (0 << 2) | // 3:2 358 0; // 1:0 359 360 miscRegs[MISCREG_CPACR] = 0; 361 362 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 363 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 364 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 365 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 366 367 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 368 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 369 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 370 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 371 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 372 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 373 374 miscRegs[MISCREG_FPSID] = p->fpsid; 375 376 if (haveLPAE) { 377 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 378 ttbcr.eae = 0; 379 miscRegs[MISCREG_TTBCR_NS] = ttbcr; 380 // Enforce consistency with system-level settings 381 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 382 } 383 384 if (haveSecurity) { 385 miscRegs[MISCREG_SCTLR_S] = sctlr; 386 miscRegs[MISCREG_SCR] = 0; 387 miscRegs[MISCREG_VBAR_S] = 0; 388 } else { 389 // we're always non-secure 390 miscRegs[MISCREG_SCR] = 1; 391 } 392 393 //XXX We need to initialize the rest of the state. 394} 395 396void 397ISA::clear64(const ArmISAParams *p) 398{ 399 CPSR cpsr = 0; 400 Addr rvbar = system->resetAddr64(); 401 switch (system->highestEL()) { 402 // Set initial EL to highest implemented EL using associated stack 403 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 404 // value 405 case EL3: 406 cpsr.mode = MODE_EL3H; 407 miscRegs[MISCREG_RVBAR_EL3] = rvbar; 408 break; 409 case EL2: 410 cpsr.mode = MODE_EL2H; 411 miscRegs[MISCREG_RVBAR_EL2] = rvbar; 412 break; 413 case EL1: 414 cpsr.mode = MODE_EL1H; 415 miscRegs[MISCREG_RVBAR_EL1] = rvbar; 416 break; 417 default: 418 panic("Invalid highest implemented exception level"); 419 break; 420 } 421 422 // Initialize rest of CPSR 423 cpsr.daif = 0xf; // Mask all interrupts 424 cpsr.ss = 0; 425 cpsr.il = 0; 426 miscRegs[MISCREG_CPSR] = cpsr; 427 updateRegMap(cpsr); 428 429 // Initialize other control registers 430 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 431 if (haveSecurity) { 432 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830; 433 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 434 } else if (haveVirtualization) { 435 // also MISCREG_SCTLR_EL2 (by mapping) 436 miscRegs[MISCREG_HSCTLR] = 0x30c50830; 437 } else { 438 // also MISCREG_SCTLR_EL1 (by mapping) 439 miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init 440 // Always non-secure 441 miscRegs[MISCREG_SCR_EL3] = 1; 442 } 443 444 // Initialize configurable id registers 445 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 446 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 447 miscRegs[MISCREG_ID_AA64DFR0_EL1] = 448 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 449 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 450 451 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 452 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 453 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 454 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 455 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 456 457 miscRegs[MISCREG_ID_DFR0_EL1] = 458 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 459 460 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 461 462 // Enforce consistency with system-level settings... 463 464 // EL3 465 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 466 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 467 haveSecurity ? 0x2 : 0x0); 468 // EL2 469 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 470 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 471 haveVirtualization ? 0x2 : 0x0); 472 // Large ASID support 473 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 474 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 475 haveLargeAsid64 ? 0x2 : 0x0); 476 // Physical address size 477 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 478 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 479 encodePhysAddrRange64(physAddrRange64)); 480} 481 482MiscReg 483ISA::readMiscRegNoEffect(int misc_reg) const 484{ 485 assert(misc_reg < NumMiscRegs); 486 487 auto regs = getMiscIndices(misc_reg); 488 int lower = regs.first, upper = regs.second; 489 return !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32)) 490 |(miscRegs[upper] << 32)); 491} 492 493 494MiscReg 495ISA::readMiscReg(int misc_reg, ThreadContext *tc) 496{ 497 CPSR cpsr = 0; 498 PCState pc = 0; 499 SCR scr = 0; 500 501 if (misc_reg == MISCREG_CPSR) { 502 cpsr = miscRegs[misc_reg]; 503 pc = tc->pcState(); 504 cpsr.j = pc.jazelle() ? 1 : 0; 505 cpsr.t = pc.thumb() ? 1 : 0; 506 return cpsr; 507 } 508 509#ifndef NDEBUG 510 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 511 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 512 warn("Unimplemented system register %s read.\n", 513 miscRegName[misc_reg]); 514 else 515 panic("Unimplemented system register %s read.\n", 516 miscRegName[misc_reg]); 517 } 518#endif 519 520 switch (unflattenMiscReg(misc_reg)) { 521 case MISCREG_HCR: 522 { 523 if (!haveVirtualization) 524 return 0; 525 else 526 return readMiscRegNoEffect(MISCREG_HCR); 527 } 528 case MISCREG_CPACR: 529 { 530 const uint32_t ones = (uint32_t)(-1); 531 CPACR cpacrMask = 0; 532 // Only cp10, cp11, and ase are implemented, nothing else should 533 // be readable? (straight copy from the write code) 534 cpacrMask.cp10 = ones; 535 cpacrMask.cp11 = ones; 536 cpacrMask.asedis = ones; 537 538 // Security Extensions may limit the readability of CPACR 539 if (haveSecurity) { 540 scr = readMiscRegNoEffect(MISCREG_SCR); 541 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 542 if (scr.ns && (cpsr.mode != MODE_MON)) { 543 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 544 // NB: Skipping the full loop, here 545 if (!nsacr.cp10) cpacrMask.cp10 = 0; 546 if (!nsacr.cp11) cpacrMask.cp11 = 0; 547 } 548 } 549 MiscReg val = readMiscRegNoEffect(MISCREG_CPACR); 550 val &= cpacrMask; 551 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 552 miscRegName[misc_reg], val); 553 return val; 554 } 555 case MISCREG_MPIDR: 556 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 557 scr = readMiscRegNoEffect(MISCREG_SCR); 558 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 559 return getMPIDR(system, tc); 560 } else { 561 return readMiscReg(MISCREG_VMPIDR, tc); 562 } 563 break; 564 case MISCREG_MPIDR_EL1: 565 // @todo in the absence of v8 virtualization support just return MPIDR_EL1 566 return getMPIDR(system, tc) & 0xffffffff; 567 case MISCREG_VMPIDR: 568 // top bit defined as RES1 569 return readMiscRegNoEffect(misc_reg) | 0x80000000; 570 case MISCREG_ID_AFR0: // not implemented, so alias MIDR 571 case MISCREG_REVIDR: // not implemented, so alias MIDR 572 case MISCREG_MIDR: 573 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 574 scr = readMiscRegNoEffect(MISCREG_SCR); 575 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 576 return readMiscRegNoEffect(misc_reg); 577 } else { 578 return readMiscRegNoEffect(MISCREG_VPIDR); 579 } 580 break; 581 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 582 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 583 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 584 case MISCREG_AIDR: // AUX ID set to 0 585 case MISCREG_TCMTR: // No TCM's 586 return 0; 587 588 case MISCREG_CLIDR: 589 warn_once("The clidr register always reports 0 caches.\n"); 590 warn_once("clidr LoUIS field of 0b001 to match current " 591 "ARM implementations.\n"); 592 return 0x00200000; 593 case MISCREG_CCSIDR: 594 warn_once("The ccsidr register isn't implemented and " 595 "always reads as 0.\n"); 596 break; 597 case MISCREG_CTR: // AArch32, ARMv7, top bit set 598 case MISCREG_CTR_EL0: // AArch64 599 { 600 //all caches have the same line size in gem5 601 //4 byte words in ARM 602 unsigned lineSizeWords = 603 tc->getSystemPtr()->cacheLineSize() / 4; 604 unsigned log2LineSizeWords = 0; 605 606 while (lineSizeWords >>= 1) { 607 ++log2LineSizeWords; 608 } 609 610 CTR ctr = 0; 611 //log2 of minimun i-cache line size (words) 612 ctr.iCacheLineSize = log2LineSizeWords; 613 //b11 - gem5 uses pipt 614 ctr.l1IndexPolicy = 0x3; 615 //log2 of minimum d-cache line size (words) 616 ctr.dCacheLineSize = log2LineSizeWords; 617 //log2 of max reservation size (words) 618 ctr.erg = log2LineSizeWords; 619 //log2 of max writeback size (words) 620 ctr.cwg = log2LineSizeWords; 621 //b100 - gem5 format is ARMv7 622 ctr.format = 0x4; 623 624 return ctr; 625 } 626 case MISCREG_ACTLR: 627 warn("Not doing anything for miscreg ACTLR\n"); 628 break; 629 630 case MISCREG_PMXEVTYPER_PMCCFILTR: 631 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 632 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 633 case MISCREG_PMCR ... MISCREG_PMOVSSET: 634 return pmu->readMiscReg(misc_reg); 635 636 case MISCREG_CPSR_Q: 637 panic("shouldn't be reading this register seperately\n"); 638 case MISCREG_FPSCR_QC: 639 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 640 case MISCREG_FPSCR_EXC: 641 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 642 case MISCREG_FPSR: 643 { 644 const uint32_t ones = (uint32_t)(-1); 645 FPSCR fpscrMask = 0; 646 fpscrMask.ioc = ones; 647 fpscrMask.dzc = ones; 648 fpscrMask.ofc = ones; 649 fpscrMask.ufc = ones; 650 fpscrMask.ixc = ones; 651 fpscrMask.idc = ones; 652 fpscrMask.qc = ones; 653 fpscrMask.v = ones; 654 fpscrMask.c = ones; 655 fpscrMask.z = ones; 656 fpscrMask.n = ones; 657 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 658 } 659 case MISCREG_FPCR: 660 { 661 const uint32_t ones = (uint32_t)(-1); 662 FPSCR fpscrMask = 0; 663 fpscrMask.ioe = ones; 664 fpscrMask.dze = ones; 665 fpscrMask.ofe = ones; 666 fpscrMask.ufe = ones; 667 fpscrMask.ixe = ones; 668 fpscrMask.ide = ones; 669 fpscrMask.len = ones; 670 fpscrMask.stride = ones; 671 fpscrMask.rMode = ones; 672 fpscrMask.fz = ones; 673 fpscrMask.dn = ones; 674 fpscrMask.ahp = ones; 675 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 676 } 677 case MISCREG_NZCV: 678 { 679 CPSR cpsr = 0; 680 cpsr.nz = tc->readCCReg(CCREG_NZ); 681 cpsr.c = tc->readCCReg(CCREG_C); 682 cpsr.v = tc->readCCReg(CCREG_V); 683 return cpsr; 684 } 685 case MISCREG_DAIF: 686 { 687 CPSR cpsr = 0; 688 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 689 return cpsr; 690 } 691 case MISCREG_SP_EL0: 692 { 693 return tc->readIntReg(INTREG_SP0); 694 } 695 case MISCREG_SP_EL1: 696 { 697 return tc->readIntReg(INTREG_SP1); 698 } 699 case MISCREG_SP_EL2: 700 { 701 return tc->readIntReg(INTREG_SP2); 702 } 703 case MISCREG_SPSEL: 704 { 705 return miscRegs[MISCREG_CPSR] & 0x1; 706 } 707 case MISCREG_CURRENTEL: 708 { 709 return miscRegs[MISCREG_CPSR] & 0xc; 710 } 711 case MISCREG_L2CTLR: 712 { 713 // mostly unimplemented, just set NumCPUs field from sim and return 714 L2CTLR l2ctlr = 0; 715 // b00:1CPU to b11:4CPUs 716 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 717 return l2ctlr; 718 } 719 case MISCREG_DBGDIDR: 720 /* For now just implement the version number. 721 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 722 */ 723 return 0x5 << 16; 724 case MISCREG_DBGDSCRint: 725 return 0; 726 case MISCREG_ISR: 727 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 728 readMiscRegNoEffect(MISCREG_HCR), 729 readMiscRegNoEffect(MISCREG_CPSR), 730 readMiscRegNoEffect(MISCREG_SCR)); 731 case MISCREG_ISR_EL1: 732 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 733 readMiscRegNoEffect(MISCREG_HCR_EL2), 734 readMiscRegNoEffect(MISCREG_CPSR), 735 readMiscRegNoEffect(MISCREG_SCR_EL3)); 736 case MISCREG_DCZID_EL0: 737 return 0x04; // DC ZVA clear 64-byte chunks 738 case MISCREG_HCPTR: 739 { 740 MiscReg val = readMiscRegNoEffect(misc_reg); 741 // The trap bit associated with CP14 is defined as RAZ 742 val &= ~(1 << 14); 743 // If a CP bit in NSACR is 0 then the corresponding bit in 744 // HCPTR is RAO/WI 745 bool secure_lookup = haveSecurity && 746 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 747 readMiscRegNoEffect(MISCREG_CPSR)); 748 if (!secure_lookup) { 749 MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR); 750 val |= (mask ^ 0x7FFF) & 0xBFFF; 751 } 752 // Set the bits for unimplemented coprocessors to RAO/WI 753 val |= 0x33FF; 754 return (val); 755 } 756 case MISCREG_HDFAR: // alias for secure DFAR 757 return readMiscRegNoEffect(MISCREG_DFAR_S); 758 case MISCREG_HIFAR: // alias for secure IFAR 759 return readMiscRegNoEffect(MISCREG_IFAR_S); 760 case MISCREG_HVBAR: // bottom bits reserved 761 return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0; 762 case MISCREG_SCTLR: 763 return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818; 764 case MISCREG_SCTLR_EL1: 765 return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800; 766 case MISCREG_SCTLR_EL2: 767 case MISCREG_SCTLR_EL3: 768 case MISCREG_HSCTLR: 769 return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; 770 771 case MISCREG_ID_PFR0: 772 // !ThumbEE | !Jazelle | Thumb | ARM 773 return 0x00000031; 774 case MISCREG_ID_PFR1: 775 { // Timer | Virti | !M Profile | TrustZone | ARMv4 776 bool haveTimer = (system->getGenericTimer() != NULL); 777 return 0x00000001 778 | (haveSecurity ? 0x00000010 : 0x0) 779 | (haveVirtualization ? 0x00001000 : 0x0) 780 | (haveTimer ? 0x00010000 : 0x0); 781 } 782 case MISCREG_ID_AA64PFR0_EL1: 783 return 0x0000000000000002 // AArch{64,32} supported at EL0 784 | 0x0000000000000020 // EL1 785 | (haveVirtualization ? 0x0000000000000200 : 0) // EL2 786 | (haveSecurity ? 0x0000000000002000 : 0); // EL3 787 case MISCREG_ID_AA64PFR1_EL1: 788 return 0; // bits [63:0] RES0 (reserved for future use) 789 790 // Generic Timer registers 791 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 792 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 793 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 794 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 795 return getGenericTimer(tc).readMiscReg(misc_reg); 796 797 default: 798 break; 799 800 } 801 return readMiscRegNoEffect(misc_reg); 802} 803 804void 805ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 806{ 807 assert(misc_reg < NumMiscRegs); 808 809 auto regs = getMiscIndices(misc_reg); 810 int lower = regs.first, upper = regs.second; 811 if (upper > 0) { 812 miscRegs[lower] = bits(val, 31, 0); 813 miscRegs[upper] = bits(val, 63, 32); 814 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 815 misc_reg, lower, upper, val); 816 } else { 817 miscRegs[lower] = val; 818 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 819 misc_reg, lower, val); 820 } 821} 822 823void 824ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 825{ 826 827 MiscReg newVal = val; 828 int x; 829 bool secure_lookup; 830 bool hyp; 831 System *sys; 832 ThreadContext *oc; 833 uint8_t target_el; 834 uint16_t asid; 835 SCR scr; 836 837 if (misc_reg == MISCREG_CPSR) { 838 updateRegMap(val); 839 840 841 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 842 int old_mode = old_cpsr.mode; 843 CPSR cpsr = val; 844 if (old_mode != cpsr.mode) { 845 tc->getITBPtr()->invalidateMiscReg(); 846 tc->getDTBPtr()->invalidateMiscReg(); 847 } 848 849 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 850 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 851 PCState pc = tc->pcState(); 852 pc.nextThumb(cpsr.t); 853 pc.nextJazelle(cpsr.j); 854 855 // Follow slightly different semantics if a CheckerCPU object 856 // is connected 857 CheckerCPU *checker = tc->getCheckerCpuPtr(); 858 if (checker) { 859 tc->pcStateNoRecord(pc); 860 } else { 861 tc->pcState(pc); 862 } 863 } else { 864#ifndef NDEBUG 865 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 866 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 867 warn("Unimplemented system register %s write with %#x.\n", 868 miscRegName[misc_reg], val); 869 else 870 panic("Unimplemented system register %s write with %#x.\n", 871 miscRegName[misc_reg], val); 872 } 873#endif 874 switch (unflattenMiscReg(misc_reg)) { 875 case MISCREG_CPACR: 876 { 877 878 const uint32_t ones = (uint32_t)(-1); 879 CPACR cpacrMask = 0; 880 // Only cp10, cp11, and ase are implemented, nothing else should 881 // be writable 882 cpacrMask.cp10 = ones; 883 cpacrMask.cp11 = ones; 884 cpacrMask.asedis = ones; 885 886 // Security Extensions may limit the writability of CPACR 887 if (haveSecurity) { 888 scr = readMiscRegNoEffect(MISCREG_SCR); 889 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 890 if (scr.ns && (cpsr.mode != MODE_MON)) { 891 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 892 // NB: Skipping the full loop, here 893 if (!nsacr.cp10) cpacrMask.cp10 = 0; 894 if (!nsacr.cp11) cpacrMask.cp11 = 0; 895 } 896 } 897 898 MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR); 899 newVal &= cpacrMask; 900 newVal |= old_val & ~cpacrMask; 901 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 902 miscRegName[misc_reg], newVal); 903 } 904 break; 905 case MISCREG_CPACR_EL1: 906 { 907 const uint32_t ones = (uint32_t)(-1); 908 CPACR cpacrMask = 0; 909 cpacrMask.tta = ones; 910 cpacrMask.fpen = ones; 911 newVal &= cpacrMask; 912 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 913 miscRegName[misc_reg], newVal); 914 } 915 break; 916 case MISCREG_CPTR_EL2: 917 { 918 const uint32_t ones = (uint32_t)(-1); 919 CPTR cptrMask = 0; 920 cptrMask.tcpac = ones; 921 cptrMask.tta = ones; 922 cptrMask.tfp = ones; 923 newVal &= cptrMask; 924 cptrMask = 0; 925 cptrMask.res1_13_12_el2 = ones; 926 cptrMask.res1_9_0_el2 = ones; 927 newVal |= cptrMask; 928 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 929 miscRegName[misc_reg], newVal); 930 } 931 break; 932 case MISCREG_CPTR_EL3: 933 { 934 const uint32_t ones = (uint32_t)(-1); 935 CPTR cptrMask = 0; 936 cptrMask.tcpac = ones; 937 cptrMask.tta = ones; 938 cptrMask.tfp = ones; 939 newVal &= cptrMask; 940 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 941 miscRegName[misc_reg], newVal); 942 } 943 break; 944 case MISCREG_CSSELR: 945 warn_once("The csselr register isn't implemented.\n"); 946 return; 947 948 case MISCREG_DC_ZVA_Xt: 949 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 950 return; 951 952 case MISCREG_FPSCR: 953 { 954 const uint32_t ones = (uint32_t)(-1); 955 FPSCR fpscrMask = 0; 956 fpscrMask.ioc = ones; 957 fpscrMask.dzc = ones; 958 fpscrMask.ofc = ones; 959 fpscrMask.ufc = ones; 960 fpscrMask.ixc = ones; 961 fpscrMask.idc = ones; 962 fpscrMask.ioe = ones; 963 fpscrMask.dze = ones; 964 fpscrMask.ofe = ones; 965 fpscrMask.ufe = ones; 966 fpscrMask.ixe = ones; 967 fpscrMask.ide = ones; 968 fpscrMask.len = ones; 969 fpscrMask.stride = ones; 970 fpscrMask.rMode = ones; 971 fpscrMask.fz = ones; 972 fpscrMask.dn = ones; 973 fpscrMask.ahp = ones; 974 fpscrMask.qc = ones; 975 fpscrMask.v = ones; 976 fpscrMask.c = ones; 977 fpscrMask.z = ones; 978 fpscrMask.n = ones; 979 newVal = (newVal & (uint32_t)fpscrMask) | 980 (readMiscRegNoEffect(MISCREG_FPSCR) & 981 ~(uint32_t)fpscrMask); 982 tc->getDecoderPtr()->setContext(newVal); 983 } 984 break; 985 case MISCREG_FPSR: 986 { 987 const uint32_t ones = (uint32_t)(-1); 988 FPSCR fpscrMask = 0; 989 fpscrMask.ioc = ones; 990 fpscrMask.dzc = ones; 991 fpscrMask.ofc = ones; 992 fpscrMask.ufc = ones; 993 fpscrMask.ixc = ones; 994 fpscrMask.idc = ones; 995 fpscrMask.qc = ones; 996 fpscrMask.v = ones; 997 fpscrMask.c = ones; 998 fpscrMask.z = ones; 999 fpscrMask.n = ones; 1000 newVal = (newVal & (uint32_t)fpscrMask) | 1001 (readMiscRegNoEffect(MISCREG_FPSCR) & 1002 ~(uint32_t)fpscrMask); 1003 misc_reg = MISCREG_FPSCR; 1004 } 1005 break; 1006 case MISCREG_FPCR: 1007 { 1008 const uint32_t ones = (uint32_t)(-1); 1009 FPSCR fpscrMask = 0; 1010 fpscrMask.ioe = ones; 1011 fpscrMask.dze = ones; 1012 fpscrMask.ofe = ones; 1013 fpscrMask.ufe = ones; 1014 fpscrMask.ixe = ones; 1015 fpscrMask.ide = ones; 1016 fpscrMask.len = ones; 1017 fpscrMask.stride = ones; 1018 fpscrMask.rMode = ones; 1019 fpscrMask.fz = ones; 1020 fpscrMask.dn = ones; 1021 fpscrMask.ahp = ones; 1022 newVal = (newVal & (uint32_t)fpscrMask) | 1023 (readMiscRegNoEffect(MISCREG_FPSCR) & 1024 ~(uint32_t)fpscrMask); 1025 misc_reg = MISCREG_FPSCR; 1026 } 1027 break; 1028 case MISCREG_CPSR_Q: 1029 { 1030 assert(!(newVal & ~CpsrMaskQ)); 1031 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 1032 misc_reg = MISCREG_CPSR; 1033 } 1034 break; 1035 case MISCREG_FPSCR_QC: 1036 { 1037 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 1038 (newVal & FpscrQcMask); 1039 misc_reg = MISCREG_FPSCR; 1040 } 1041 break; 1042 case MISCREG_FPSCR_EXC: 1043 { 1044 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 1045 (newVal & FpscrExcMask); 1046 misc_reg = MISCREG_FPSCR; 1047 } 1048 break; 1049 case MISCREG_FPEXC: 1050 { 1051 // vfpv3 architecture, section B.6.1 of DDI04068 1052 // bit 29 - valid only if fpexc[31] is 0 1053 const uint32_t fpexcMask = 0x60000000; 1054 newVal = (newVal & fpexcMask) | 1055 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 1056 } 1057 break; 1058 case MISCREG_HCR: 1059 { 1060 if (!haveVirtualization) 1061 return; 1062 } 1063 break; 1064 case MISCREG_IFSR: 1065 { 1066 // ARM ARM (ARM DDI 0406C.b) B4.1.96 1067 const uint32_t ifsrMask = 1068 mask(31, 13) | mask(11, 11) | mask(8, 6); 1069 newVal = newVal & ~ifsrMask; 1070 } 1071 break; 1072 case MISCREG_DFSR: 1073 { 1074 // ARM ARM (ARM DDI 0406C.b) B4.1.52 1075 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 1076 newVal = newVal & ~dfsrMask; 1077 } 1078 break; 1079 case MISCREG_AMAIR0: 1080 case MISCREG_AMAIR1: 1081 { 1082 // ARM ARM (ARM DDI 0406C.b) B4.1.5 1083 // Valid only with LPAE 1084 if (!haveLPAE) 1085 return; 1086 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 1087 } 1088 break; 1089 case MISCREG_SCR: 1090 tc->getITBPtr()->invalidateMiscReg(); 1091 tc->getDTBPtr()->invalidateMiscReg(); 1092 break; 1093 case MISCREG_SCTLR: 1094 { 1095 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 1096 scr = readMiscRegNoEffect(MISCREG_SCR); 1097 MiscRegIndex sctlr_idx = (haveSecurity && !scr.ns) 1098 ? MISCREG_SCTLR_S : MISCREG_SCTLR_NS; 1099 SCTLR sctlr = miscRegs[sctlr_idx]; 1100 SCTLR new_sctlr = newVal; 1101 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 1102 miscRegs[sctlr_idx] = (MiscReg)new_sctlr; 1103 tc->getITBPtr()->invalidateMiscReg(); 1104 tc->getDTBPtr()->invalidateMiscReg(); 1105 } 1106 case MISCREG_MIDR: 1107 case MISCREG_ID_PFR0: 1108 case MISCREG_ID_PFR1: 1109 case MISCREG_ID_DFR0: 1110 case MISCREG_ID_MMFR0: 1111 case MISCREG_ID_MMFR1: 1112 case MISCREG_ID_MMFR2: 1113 case MISCREG_ID_MMFR3: 1114 case MISCREG_ID_ISAR0: 1115 case MISCREG_ID_ISAR1: 1116 case MISCREG_ID_ISAR2: 1117 case MISCREG_ID_ISAR3: 1118 case MISCREG_ID_ISAR4: 1119 case MISCREG_ID_ISAR5: 1120 1121 case MISCREG_MPIDR: 1122 case MISCREG_FPSID: 1123 case MISCREG_TLBTR: 1124 case MISCREG_MVFR0: 1125 case MISCREG_MVFR1: 1126 1127 case MISCREG_ID_AA64AFR0_EL1: 1128 case MISCREG_ID_AA64AFR1_EL1: 1129 case MISCREG_ID_AA64DFR0_EL1: 1130 case MISCREG_ID_AA64DFR1_EL1: 1131 case MISCREG_ID_AA64ISAR0_EL1: 1132 case MISCREG_ID_AA64ISAR1_EL1: 1133 case MISCREG_ID_AA64MMFR0_EL1: 1134 case MISCREG_ID_AA64MMFR1_EL1: 1135 case MISCREG_ID_AA64PFR0_EL1: 1136 case MISCREG_ID_AA64PFR1_EL1: 1137 // ID registers are constants. 1138 return; 1139 1140 // TLBI all entries, EL0&1 inner sharable (ignored) 1141 case MISCREG_TLBIALLIS: 1142 case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 1143 assert32(tc); 1144 target_el = 1; // el 0 and 1 are handled together 1145 scr = readMiscReg(MISCREG_SCR, tc); 1146 secure_lookup = haveSecurity && !scr.ns; 1147 sys = tc->getSystemPtr(); 1148 for (x = 0; x < sys->numContexts(); x++) { 1149 oc = sys->getThreadContext(x); 1150 assert(oc->getITBPtr() && oc->getDTBPtr()); 1151 oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 1152 oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 1153 1154 // If CheckerCPU is connected, need to notify it of a flush 1155 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1156 if (checker) { 1157 checker->getITBPtr()->flushAllSecurity(secure_lookup, 1158 target_el); 1159 checker->getDTBPtr()->flushAllSecurity(secure_lookup, 1160 target_el); 1161 } 1162 } 1163 return; 1164 // TLBI all entries, EL0&1, instruction side 1165 case MISCREG_ITLBIALL: 1166 assert32(tc); 1167 target_el = 1; // el 0 and 1 are handled together 1168 scr = readMiscReg(MISCREG_SCR, tc); 1169 secure_lookup = haveSecurity && !scr.ns; 1170 tc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 1171 return; 1172 // TLBI all entries, EL0&1, data side 1173 case MISCREG_DTLBIALL: 1174 assert32(tc); 1175 target_el = 1; // el 0 and 1 are handled together 1176 scr = readMiscReg(MISCREG_SCR, tc); 1177 secure_lookup = haveSecurity && !scr.ns; 1178 tc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 1179 return; 1180 // TLBI based on VA, EL0&1 inner sharable (ignored) 1181 case MISCREG_TLBIMVAIS: 1182 case MISCREG_TLBIMVA: 1183 assert32(tc); 1184 target_el = 1; // el 0 and 1 are handled together 1185 scr = readMiscReg(MISCREG_SCR, tc); 1186 secure_lookup = haveSecurity && !scr.ns; 1187 sys = tc->getSystemPtr(); 1188 for (x = 0; x < sys->numContexts(); x++) { 1189 oc = sys->getThreadContext(x); 1190 assert(oc->getITBPtr() && oc->getDTBPtr()); 1191 oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1192 bits(newVal, 7,0), 1193 secure_lookup, target_el); 1194 oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1195 bits(newVal, 7,0), 1196 secure_lookup, target_el); 1197 1198 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1199 if (checker) { 1200 checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1201 bits(newVal, 7,0), secure_lookup, target_el); 1202 checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1203 bits(newVal, 7,0), secure_lookup, target_el); 1204 } 1205 } 1206 return; 1207 // TLBI by ASID, EL0&1, inner sharable 1208 case MISCREG_TLBIASIDIS: 1209 case MISCREG_TLBIASID: 1210 assert32(tc); 1211 target_el = 1; // el 0 and 1 are handled together 1212 scr = readMiscReg(MISCREG_SCR, tc); 1213 secure_lookup = haveSecurity && !scr.ns; 1214 sys = tc->getSystemPtr(); 1215 for (x = 0; x < sys->numContexts(); x++) { 1216 oc = sys->getThreadContext(x); 1217 assert(oc->getITBPtr() && oc->getDTBPtr()); 1218 oc->getITBPtr()->flushAsid(bits(newVal, 7,0), 1219 secure_lookup, target_el); 1220 oc->getDTBPtr()->flushAsid(bits(newVal, 7,0), 1221 secure_lookup, target_el); 1222 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1223 if (checker) { 1224 checker->getITBPtr()->flushAsid(bits(newVal, 7,0), 1225 secure_lookup, target_el); 1226 checker->getDTBPtr()->flushAsid(bits(newVal, 7,0), 1227 secure_lookup, target_el); 1228 } 1229 } 1230 return; 1231 // TLBI by address, EL0&1, inner sharable (ignored) 1232 case MISCREG_TLBIMVAAIS: 1233 case MISCREG_TLBIMVAA: 1234 assert32(tc); 1235 target_el = 1; // el 0 and 1 are handled together 1236 scr = readMiscReg(MISCREG_SCR, tc); 1237 secure_lookup = haveSecurity && !scr.ns; 1238 hyp = 0; 1239 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el); 1240 return; 1241 // TLBI by address, EL2, hypervisor mode 1242 case MISCREG_TLBIMVAH: 1243 case MISCREG_TLBIMVAHIS: 1244 assert32(tc); 1245 target_el = 1; // aarch32, use hyp bit 1246 scr = readMiscReg(MISCREG_SCR, tc); 1247 secure_lookup = haveSecurity && !scr.ns; 1248 hyp = 1; 1249 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el); 1250 return; 1251 // TLBI by address and asid, EL0&1, instruction side only 1252 case MISCREG_ITLBIMVA: 1253 assert32(tc); 1254 target_el = 1; // el 0 and 1 are handled together 1255 scr = readMiscReg(MISCREG_SCR, tc); 1256 secure_lookup = haveSecurity && !scr.ns; 1257 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1258 bits(newVal, 7,0), secure_lookup, target_el); 1259 return; 1260 // TLBI by address and asid, EL0&1, data side only 1261 case MISCREG_DTLBIMVA: 1262 assert32(tc); 1263 target_el = 1; // el 0 and 1 are handled together 1264 scr = readMiscReg(MISCREG_SCR, tc); 1265 secure_lookup = haveSecurity && !scr.ns; 1266 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1267 bits(newVal, 7,0), secure_lookup, target_el); 1268 return; 1269 // TLBI by ASID, EL0&1, instrution side only 1270 case MISCREG_ITLBIASID: 1271 assert32(tc); 1272 target_el = 1; // el 0 and 1 are handled together 1273 scr = readMiscReg(MISCREG_SCR, tc); 1274 secure_lookup = haveSecurity && !scr.ns; 1275 tc->getITBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup, 1276 target_el); 1277 return; 1278 // TLBI by ASID EL0&1 data size only 1279 case MISCREG_DTLBIASID: 1280 assert32(tc); 1281 target_el = 1; // el 0 and 1 are handled together 1282 scr = readMiscReg(MISCREG_SCR, tc); 1283 secure_lookup = haveSecurity && !scr.ns; 1284 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup, 1285 target_el); 1286 return; 1287 // Invalidate entire Non-secure Hyp/Non-Hyp Unified TLB 1288 case MISCREG_TLBIALLNSNH: 1289 case MISCREG_TLBIALLNSNHIS: 1290 assert32(tc); 1291 target_el = 1; // el 0 and 1 are handled together 1292 hyp = 0; 1293 tlbiALLN(tc, hyp, target_el); 1294 return; 1295 // TLBI all entries, EL2, hyp, 1296 case MISCREG_TLBIALLH: 1297 case MISCREG_TLBIALLHIS: 1298 assert32(tc); 1299 target_el = 1; // aarch32, use hyp bit 1300 hyp = 1; 1301 tlbiALLN(tc, hyp, target_el); 1302 return; 1303 // AArch64 TLBI: invalidate all entries EL3 1304 case MISCREG_TLBI_ALLE3IS: 1305 case MISCREG_TLBI_ALLE3: 1306 assert64(tc); 1307 target_el = 3; 1308 secure_lookup = true; 1309 tlbiALL(tc, secure_lookup, target_el); 1310 return; 1311 // @todo: uncomment this to enable Virtualization 1312 // case MISCREG_TLBI_ALLE2IS: 1313 // case MISCREG_TLBI_ALLE2: 1314 // TLBI all entries, EL0&1 1315 case MISCREG_TLBI_ALLE1IS: 1316 case MISCREG_TLBI_ALLE1: 1317 // AArch64 TLBI: invalidate all entries, stage 1, current VMID 1318 case MISCREG_TLBI_VMALLE1IS: 1319 case MISCREG_TLBI_VMALLE1: 1320 // AArch64 TLBI: invalidate all entries, stages 1 & 2, current VMID 1321 case MISCREG_TLBI_VMALLS12E1IS: 1322 case MISCREG_TLBI_VMALLS12E1: 1323 // @todo: handle VMID and stage 2 to enable Virtualization 1324 assert64(tc); 1325 target_el = 1; // el 0 and 1 are handled together 1326 scr = readMiscReg(MISCREG_SCR, tc); 1327 secure_lookup = haveSecurity && !scr.ns; 1328 tlbiALL(tc, secure_lookup, target_el); 1329 return; 1330 // AArch64 TLBI: invalidate by VA and ASID, stage 1, current VMID 1331 // VAEx(IS) and VALEx(IS) are the same because TLBs only store entries 1332 // from the last level of translation table walks 1333 // @todo: handle VMID to enable Virtualization 1334 // TLBI all entries, EL0&1 1335 case MISCREG_TLBI_VAE3IS_Xt: 1336 case MISCREG_TLBI_VAE3_Xt: 1337 // TLBI by VA, EL3 regime stage 1, last level walk 1338 case MISCREG_TLBI_VALE3IS_Xt: 1339 case MISCREG_TLBI_VALE3_Xt: 1340 assert64(tc); 1341 target_el = 3; 1342 asid = 0xbeef; // does not matter, tlbi is global 1343 secure_lookup = true; 1344 tlbiVA(tc, newVal, asid, secure_lookup, target_el); 1345 return; 1346 // TLBI by VA, EL2 1347 case MISCREG_TLBI_VAE2IS_Xt: 1348 case MISCREG_TLBI_VAE2_Xt: 1349 // TLBI by VA, EL2, stage1 last level walk 1350 case MISCREG_TLBI_VALE2IS_Xt: 1351 case MISCREG_TLBI_VALE2_Xt: 1352 assert64(tc); 1353 target_el = 2; 1354 asid = 0xbeef; // does not matter, tlbi is global 1355 scr = readMiscReg(MISCREG_SCR, tc); 1356 secure_lookup = haveSecurity && !scr.ns; 1357 tlbiVA(tc, newVal, asid, secure_lookup, target_el); 1358 return; 1359 // TLBI by VA EL1 & 0, stage1, ASID, current VMID 1360 case MISCREG_TLBI_VAE1IS_Xt: 1361 case MISCREG_TLBI_VAE1_Xt: 1362 case MISCREG_TLBI_VALE1IS_Xt: 1363 case MISCREG_TLBI_VALE1_Xt: 1364 assert64(tc); 1365 asid = bits(newVal, 63, 48); 1366 target_el = 1; // el 0 and 1 are handled together 1367 scr = readMiscReg(MISCREG_SCR, tc); 1368 secure_lookup = haveSecurity && !scr.ns; 1369 tlbiVA(tc, newVal, asid, secure_lookup, target_el); 1370 return; 1371 // AArch64 TLBI: invalidate by ASID, stage 1, current VMID 1372 // @todo: handle VMID to enable Virtualization 1373 case MISCREG_TLBI_ASIDE1IS_Xt: 1374 case MISCREG_TLBI_ASIDE1_Xt: 1375 assert64(tc); 1376 target_el = 1; // el 0 and 1 are handled together 1377 scr = readMiscReg(MISCREG_SCR, tc); 1378 secure_lookup = haveSecurity && !scr.ns; 1379 sys = tc->getSystemPtr(); 1380 for (x = 0; x < sys->numContexts(); x++) { 1381 oc = sys->getThreadContext(x); 1382 assert(oc->getITBPtr() && oc->getDTBPtr()); 1383 asid = bits(newVal, 63, 48); 1384 if (!haveLargeAsid64) 1385 asid &= mask(8); 1386 oc->getITBPtr()->flushAsid(asid, secure_lookup, target_el); 1387 oc->getDTBPtr()->flushAsid(asid, secure_lookup, target_el); 1388 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1389 if (checker) { 1390 checker->getITBPtr()->flushAsid(asid, 1391 secure_lookup, target_el); 1392 checker->getDTBPtr()->flushAsid(asid, 1393 secure_lookup, target_el); 1394 } 1395 } 1396 return; 1397 // AArch64 TLBI: invalidate by VA, ASID, stage 1, current VMID 1398 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 1399 // entries from the last level of translation table walks 1400 // @todo: handle VMID to enable Virtualization 1401 case MISCREG_TLBI_VAAE1IS_Xt: 1402 case MISCREG_TLBI_VAAE1_Xt: 1403 case MISCREG_TLBI_VAALE1IS_Xt: 1404 case MISCREG_TLBI_VAALE1_Xt: 1405 assert64(tc); 1406 target_el = 1; // el 0 and 1 are handled together 1407 scr = readMiscReg(MISCREG_SCR, tc); 1408 secure_lookup = haveSecurity && !scr.ns; 1409 sys = tc->getSystemPtr(); 1410 for (x = 0; x < sys->numContexts(); x++) { 1411 // @todo: extra controls on TLBI broadcast? 1412 oc = sys->getThreadContext(x); 1413 assert(oc->getITBPtr() && oc->getDTBPtr()); 1414 Addr va = ((Addr) bits(newVal, 43, 0)) << 12; 1415 oc->getITBPtr()->flushMva(va, 1416 secure_lookup, false, target_el); 1417 oc->getDTBPtr()->flushMva(va, 1418 secure_lookup, false, target_el); 1419 1420 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1421 if (checker) { 1422 checker->getITBPtr()->flushMva(va, 1423 secure_lookup, false, target_el); 1424 checker->getDTBPtr()->flushMva(va, 1425 secure_lookup, false, target_el); 1426 } 1427 } 1428 return; 1429 // AArch64 TLBI: invalidate by IPA, stage 2, current VMID 1430 case MISCREG_TLBI_IPAS2LE1IS_Xt: 1431 case MISCREG_TLBI_IPAS2LE1_Xt: 1432 case MISCREG_TLBI_IPAS2E1IS_Xt: 1433 case MISCREG_TLBI_IPAS2E1_Xt: 1434 assert64(tc); 1435 target_el = 1; // EL 0 and 1 are handled together 1436 scr = readMiscReg(MISCREG_SCR, tc); 1437 secure_lookup = haveSecurity && !scr.ns; 1438 sys = tc->getSystemPtr(); 1439 for (x = 0; x < sys->numContexts(); x++) { 1440 oc = sys->getThreadContext(x); 1441 assert(oc->getITBPtr() && oc->getDTBPtr()); 1442 Addr ipa = ((Addr) bits(newVal, 35, 0)) << 12; 1443 oc->getITBPtr()->flushIpaVmid(ipa, 1444 secure_lookup, false, target_el); 1445 oc->getDTBPtr()->flushIpaVmid(ipa, 1446 secure_lookup, false, target_el); 1447 1448 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1449 if (checker) { 1450 checker->getITBPtr()->flushIpaVmid(ipa, 1451 secure_lookup, false, target_el); 1452 checker->getDTBPtr()->flushIpaVmid(ipa, 1453 secure_lookup, false, target_el); 1454 } 1455 } 1456 return; 1457 case MISCREG_ACTLR: 1458 warn("Not doing anything for write of miscreg ACTLR\n"); 1459 break; 1460 1461 case MISCREG_PMXEVTYPER_PMCCFILTR: 1462 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 1463 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 1464 case MISCREG_PMCR ... MISCREG_PMOVSSET: 1465 pmu->setMiscReg(misc_reg, newVal); 1466 break; 1467 1468 1469 case MISCREG_HSTR: // TJDBX, now redifined to be RES0 1470 { 1471 HSTR hstrMask = 0; 1472 hstrMask.tjdbx = 1; 1473 newVal &= ~((uint32_t) hstrMask); 1474 break; 1475 } 1476 case MISCREG_HCPTR: 1477 { 1478 // If a CP bit in NSACR is 0 then the corresponding bit in 1479 // HCPTR is RAO/WI. Same applies to NSASEDIS 1480 secure_lookup = haveSecurity && 1481 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 1482 readMiscRegNoEffect(MISCREG_CPSR)); 1483 if (!secure_lookup) { 1484 MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 1485 MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 1486 newVal = (newVal & ~mask) | (oldValue & mask); 1487 } 1488 break; 1489 } 1490 case MISCREG_HDFAR: // alias for secure DFAR 1491 misc_reg = MISCREG_DFAR_S; 1492 break; 1493 case MISCREG_HIFAR: // alias for secure IFAR 1494 misc_reg = MISCREG_IFAR_S; 1495 break; 1496 case MISCREG_ATS1CPR: 1497 case MISCREG_ATS1CPW: 1498 case MISCREG_ATS1CUR: 1499 case MISCREG_ATS1CUW: 1500 case MISCREG_ATS12NSOPR: 1501 case MISCREG_ATS12NSOPW: 1502 case MISCREG_ATS12NSOUR: 1503 case MISCREG_ATS12NSOUW: 1504 case MISCREG_ATS1HR: 1505 case MISCREG_ATS1HW: 1506 { 1507 Request::Flags flags = 0; 1508 BaseTLB::Mode mode = BaseTLB::Read; 1509 TLB::ArmTranslationType tranType = TLB::NormalTran; 1510 Fault fault; 1511 switch(misc_reg) { 1512 case MISCREG_ATS1CPR: 1513 flags = TLB::MustBeOne; 1514 tranType = TLB::S1CTran; 1515 mode = BaseTLB::Read; 1516 break; 1517 case MISCREG_ATS1CPW: 1518 flags = TLB::MustBeOne; 1519 tranType = TLB::S1CTran; 1520 mode = BaseTLB::Write; 1521 break; 1522 case MISCREG_ATS1CUR: 1523 flags = TLB::MustBeOne | TLB::UserMode; 1524 tranType = TLB::S1CTran; 1525 mode = BaseTLB::Read; 1526 break; 1527 case MISCREG_ATS1CUW: 1528 flags = TLB::MustBeOne | TLB::UserMode; 1529 tranType = TLB::S1CTran; 1530 mode = BaseTLB::Write; 1531 break; 1532 case MISCREG_ATS12NSOPR: 1533 if (!haveSecurity) 1534 panic("Security Extensions required for ATS12NSOPR"); 1535 flags = TLB::MustBeOne; 1536 tranType = TLB::S1S2NsTran; 1537 mode = BaseTLB::Read; 1538 break; 1539 case MISCREG_ATS12NSOPW: 1540 if (!haveSecurity) 1541 panic("Security Extensions required for ATS12NSOPW"); 1542 flags = TLB::MustBeOne; 1543 tranType = TLB::S1S2NsTran; 1544 mode = BaseTLB::Write; 1545 break; 1546 case MISCREG_ATS12NSOUR: 1547 if (!haveSecurity) 1548 panic("Security Extensions required for ATS12NSOUR"); 1549 flags = TLB::MustBeOne | TLB::UserMode; 1550 tranType = TLB::S1S2NsTran; 1551 mode = BaseTLB::Read; 1552 break; 1553 case MISCREG_ATS12NSOUW: 1554 if (!haveSecurity) 1555 panic("Security Extensions required for ATS12NSOUW"); 1556 flags = TLB::MustBeOne | TLB::UserMode; 1557 tranType = TLB::S1S2NsTran; 1558 mode = BaseTLB::Write; 1559 break; 1560 case MISCREG_ATS1HR: // only really useful from secure mode. 1561 flags = TLB::MustBeOne; 1562 tranType = TLB::HypMode; 1563 mode = BaseTLB::Read; 1564 break; 1565 case MISCREG_ATS1HW: 1566 flags = TLB::MustBeOne; 1567 tranType = TLB::HypMode; 1568 mode = BaseTLB::Write; 1569 break; 1570 } 1571 // If we're in timing mode then doing the translation in 1572 // functional mode then we're slightly distorting performance 1573 // results obtained from simulations. The translation should be 1574 // done in the same mode the core is running in. NOTE: This 1575 // can't be an atomic translation because that causes problems 1576 // with unexpected atomic snoop requests. 1577 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1578 Request req(0, val, 0, flags, Request::funcMasterId, 1579 tc->pcState().pc(), tc->contextId()); 1580 fault = tc->getDTBPtr()->translateFunctional(&req, tc, mode, tranType); 1581 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1582 HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 1583 1584 MiscReg newVal; 1585 if (fault == NoFault) { 1586 Addr paddr = req.getPaddr(); 1587 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 1588 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 1589 newVal = (paddr & mask(39, 12)) | 1590 (tc->getDTBPtr()->getAttr()); 1591 } else { 1592 newVal = (paddr & 0xfffff000) | 1593 (tc->getDTBPtr()->getAttr()); 1594 } 1595 DPRINTF(MiscRegs, 1596 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 1597 val, newVal); 1598 } else { 1599 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 1600 // Set fault bit and FSR 1601 FSR fsr = armFault->getFsr(tc); 1602 1603 newVal = ((fsr >> 9) & 1) << 11; 1604 if (newVal) { 1605 // LPAE - rearange fault status 1606 newVal |= ((fsr >> 0) & 0x3f) << 1; 1607 } else { 1608 // VMSA - rearange fault status 1609 newVal |= ((fsr >> 0) & 0xf) << 1; 1610 newVal |= ((fsr >> 10) & 0x1) << 5; 1611 newVal |= ((fsr >> 12) & 0x1) << 6; 1612 } 1613 newVal |= 0x1; // F bit 1614 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1615 newVal |= armFault->isStage2() ? 0x200 : 0; 1616 DPRINTF(MiscRegs, 1617 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 1618 val, fsr, newVal); 1619 } 1620 setMiscRegNoEffect(MISCREG_PAR, newVal); 1621 return; 1622 } 1623 case MISCREG_TTBCR: 1624 { 1625 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1626 const uint32_t ones = (uint32_t)(-1); 1627 TTBCR ttbcrMask = 0; 1628 TTBCR ttbcrNew = newVal; 1629 1630 // ARM DDI 0406C.b, ARMv7-32 1631 ttbcrMask.n = ones; // T0SZ 1632 if (haveSecurity) { 1633 ttbcrMask.pd0 = ones; 1634 ttbcrMask.pd1 = ones; 1635 } 1636 ttbcrMask.epd0 = ones; 1637 ttbcrMask.irgn0 = ones; 1638 ttbcrMask.orgn0 = ones; 1639 ttbcrMask.sh0 = ones; 1640 ttbcrMask.ps = ones; // T1SZ 1641 ttbcrMask.a1 = ones; 1642 ttbcrMask.epd1 = ones; 1643 ttbcrMask.irgn1 = ones; 1644 ttbcrMask.orgn1 = ones; 1645 ttbcrMask.sh1 = ones; 1646 if (haveLPAE) 1647 ttbcrMask.eae = ones; 1648 1649 if (haveLPAE && ttbcrNew.eae) { 1650 newVal = newVal & ttbcrMask; 1651 } else { 1652 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 1653 } 1654 } 1655 case MISCREG_TTBR0: 1656 case MISCREG_TTBR1: 1657 { 1658 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1659 if (haveLPAE) { 1660 if (ttbcr.eae) { 1661 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 1662 // ARMv8 AArch32 bit 63-56 only 1663 uint64_t ttbrMask = mask(63,56) | mask(47,40); 1664 newVal = (newVal & (~ttbrMask)); 1665 } 1666 } 1667 } 1668 case MISCREG_SCTLR_EL1: 1669 { 1670 tc->getITBPtr()->invalidateMiscReg(); 1671 tc->getDTBPtr()->invalidateMiscReg(); 1672 setMiscRegNoEffect(misc_reg, newVal); 1673 } 1674 case MISCREG_CONTEXTIDR: 1675 case MISCREG_PRRR: 1676 case MISCREG_NMRR: 1677 case MISCREG_MAIR0: 1678 case MISCREG_MAIR1: 1679 case MISCREG_DACR: 1680 case MISCREG_VTTBR: 1681 case MISCREG_SCR_EL3: 1682 case MISCREG_HCR_EL2: 1683 case MISCREG_TCR_EL1: 1684 case MISCREG_TCR_EL2: 1685 case MISCREG_TCR_EL3: 1686 case MISCREG_SCTLR_EL2: 1687 case MISCREG_SCTLR_EL3: 1688 case MISCREG_HSCTLR: 1689 case MISCREG_TTBR0_EL1: 1690 case MISCREG_TTBR1_EL1: 1691 case MISCREG_TTBR0_EL2: 1692 case MISCREG_TTBR0_EL3: 1693 tc->getITBPtr()->invalidateMiscReg(); 1694 tc->getDTBPtr()->invalidateMiscReg(); 1695 break; 1696 case MISCREG_NZCV: 1697 { 1698 CPSR cpsr = val; 1699 1700 tc->setCCReg(CCREG_NZ, cpsr.nz); 1701 tc->setCCReg(CCREG_C, cpsr.c); 1702 tc->setCCReg(CCREG_V, cpsr.v); 1703 } 1704 break; 1705 case MISCREG_DAIF: 1706 { 1707 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1708 cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 1709 newVal = cpsr; 1710 misc_reg = MISCREG_CPSR; 1711 } 1712 break; 1713 case MISCREG_SP_EL0: 1714 tc->setIntReg(INTREG_SP0, newVal); 1715 break; 1716 case MISCREG_SP_EL1: 1717 tc->setIntReg(INTREG_SP1, newVal); 1718 break; 1719 case MISCREG_SP_EL2: 1720 tc->setIntReg(INTREG_SP2, newVal); 1721 break; 1722 case MISCREG_SPSEL: 1723 { 1724 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1725 cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 1726 newVal = cpsr; 1727 misc_reg = MISCREG_CPSR; 1728 } 1729 break; 1730 case MISCREG_CURRENTEL: 1731 { 1732 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1733 cpsr.el = (uint8_t) ((CPSR) newVal).el; 1734 newVal = cpsr; 1735 misc_reg = MISCREG_CPSR; 1736 } 1737 break; 1738 case MISCREG_AT_S1E1R_Xt: 1739 case MISCREG_AT_S1E1W_Xt: 1740 case MISCREG_AT_S1E0R_Xt: 1741 case MISCREG_AT_S1E0W_Xt: 1742 case MISCREG_AT_S1E2R_Xt: 1743 case MISCREG_AT_S1E2W_Xt: 1744 case MISCREG_AT_S12E1R_Xt: 1745 case MISCREG_AT_S12E1W_Xt: 1746 case MISCREG_AT_S12E0R_Xt: 1747 case MISCREG_AT_S12E0W_Xt: 1748 case MISCREG_AT_S1E3R_Xt: 1749 case MISCREG_AT_S1E3W_Xt: 1750 { 1751 RequestPtr req = new Request; 1752 Request::Flags flags = 0; 1753 BaseTLB::Mode mode = BaseTLB::Read; 1754 TLB::ArmTranslationType tranType = TLB::NormalTran; 1755 Fault fault; 1756 switch(misc_reg) { 1757 case MISCREG_AT_S1E1R_Xt: 1758 flags = TLB::MustBeOne; 1759 tranType = TLB::S1E1Tran; 1760 mode = BaseTLB::Read; 1761 break; 1762 case MISCREG_AT_S1E1W_Xt: 1763 flags = TLB::MustBeOne; 1764 tranType = TLB::S1E1Tran; 1765 mode = BaseTLB::Write; 1766 break; 1767 case MISCREG_AT_S1E0R_Xt: 1768 flags = TLB::MustBeOne | TLB::UserMode; 1769 tranType = TLB::S1E0Tran; 1770 mode = BaseTLB::Read; 1771 break; 1772 case MISCREG_AT_S1E0W_Xt: 1773 flags = TLB::MustBeOne | TLB::UserMode; 1774 tranType = TLB::S1E0Tran; 1775 mode = BaseTLB::Write; 1776 break; 1777 case MISCREG_AT_S1E2R_Xt: 1778 flags = TLB::MustBeOne; 1779 tranType = TLB::S1E2Tran; 1780 mode = BaseTLB::Read; 1781 break; 1782 case MISCREG_AT_S1E2W_Xt: 1783 flags = TLB::MustBeOne; 1784 tranType = TLB::S1E2Tran; 1785 mode = BaseTLB::Write; 1786 break; 1787 case MISCREG_AT_S12E0R_Xt: 1788 flags = TLB::MustBeOne | TLB::UserMode; 1789 tranType = TLB::S12E0Tran; 1790 mode = BaseTLB::Read; 1791 break; 1792 case MISCREG_AT_S12E0W_Xt: 1793 flags = TLB::MustBeOne | TLB::UserMode; 1794 tranType = TLB::S12E0Tran; 1795 mode = BaseTLB::Write; 1796 break; 1797 case MISCREG_AT_S12E1R_Xt: 1798 flags = TLB::MustBeOne; 1799 tranType = TLB::S12E1Tran; 1800 mode = BaseTLB::Read; 1801 break; 1802 case MISCREG_AT_S12E1W_Xt: 1803 flags = TLB::MustBeOne; 1804 tranType = TLB::S12E1Tran; 1805 mode = BaseTLB::Write; 1806 break; 1807 case MISCREG_AT_S1E3R_Xt: 1808 flags = TLB::MustBeOne; 1809 tranType = TLB::S1E3Tran; 1810 mode = BaseTLB::Read; 1811 break; 1812 case MISCREG_AT_S1E3W_Xt: 1813 flags = TLB::MustBeOne; 1814 tranType = TLB::S1E3Tran; 1815 mode = BaseTLB::Write; 1816 break; 1817 } 1818 // If we're in timing mode then doing the translation in 1819 // functional mode then we're slightly distorting performance 1820 // results obtained from simulations. The translation should be 1821 // done in the same mode the core is running in. NOTE: This 1822 // can't be an atomic translation because that causes problems 1823 // with unexpected atomic snoop requests. 1824 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1825 req->setVirt(0, val, 0, flags, Request::funcMasterId, 1826 tc->pcState().pc()); 1827 req->setContext(tc->contextId()); 1828 fault = tc->getDTBPtr()->translateFunctional(req, tc, mode, 1829 tranType); 1830 1831 MiscReg newVal; 1832 if (fault == NoFault) { 1833 Addr paddr = req->getPaddr(); 1834 uint64_t attr = tc->getDTBPtr()->getAttr(); 1835 uint64_t attr1 = attr >> 56; 1836 if (!attr1 || attr1 ==0x44) { 1837 attr |= 0x100; 1838 attr &= ~ uint64_t(0x80); 1839 } 1840 newVal = (paddr & mask(47, 12)) | attr; 1841 DPRINTF(MiscRegs, 1842 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 1843 val, newVal); 1844 } else { 1845 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 1846 // Set fault bit and FSR 1847 FSR fsr = armFault->getFsr(tc); 1848 1849 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1850 if (cpsr.width) { // AArch32 1851 newVal = ((fsr >> 9) & 1) << 11; 1852 // rearrange fault status 1853 newVal |= ((fsr >> 0) & 0x3f) << 1; 1854 newVal |= 0x1; // F bit 1855 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1856 newVal |= armFault->isStage2() ? 0x200 : 0; 1857 } else { // AArch64 1858 newVal = 1; // F bit 1859 newVal |= fsr << 1; // FST 1860 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit. 1861 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 1862 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 1863 newVal |= 1 << 11; // RES1 1864 } 1865 DPRINTF(MiscRegs, 1866 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 1867 val, fsr, newVal); 1868 } 1869 delete req; 1870 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 1871 return; 1872 } 1873 case MISCREG_SPSR_EL3: 1874 case MISCREG_SPSR_EL2: 1875 case MISCREG_SPSR_EL1: 1876 // Force bits 23:21 to 0 1877 newVal = val & ~(0x7 << 21); 1878 break; 1879 case MISCREG_L2CTLR: 1880 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 1881 miscRegName[misc_reg], uint32_t(val)); 1882 break; 1883 1884 // Generic Timer registers 1885 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 1886 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 1887 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 1888 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 1889 getGenericTimer(tc).setMiscReg(misc_reg, newVal); 1890 break; 1891 } 1892 } 1893 setMiscRegNoEffect(misc_reg, newVal); 1894} 1895 1896void 1897ISA::tlbiVA(ThreadContext *tc, MiscReg newVal, uint16_t asid, 1898 bool secure_lookup, uint8_t target_el) 1899{ 1900 if (!haveLargeAsid64) 1901 asid &= mask(8); 1902 Addr va = ((Addr) bits(newVal, 43, 0)) << 12; 1903 System *sys = tc->getSystemPtr(); 1904 for (int x = 0; x < sys->numContexts(); x++) { 1905 ThreadContext *oc = sys->getThreadContext(x); 1906 assert(oc->getITBPtr() && oc->getDTBPtr()); 1907 oc->getITBPtr()->flushMvaAsid(va, asid, 1908 secure_lookup, target_el); 1909 oc->getDTBPtr()->flushMvaAsid(va, asid, 1910 secure_lookup, target_el); 1911 1912 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1913 if (checker) { 1914 checker->getITBPtr()->flushMvaAsid( 1915 va, asid, secure_lookup, target_el); 1916 checker->getDTBPtr()->flushMvaAsid( 1917 va, asid, secure_lookup, target_el); 1918 } 1919 } 1920} 1921 1922void 1923ISA::tlbiALL(ThreadContext *tc, bool secure_lookup, uint8_t target_el) 1924{ 1925 System *sys = tc->getSystemPtr(); 1926 for (int x = 0; x < sys->numContexts(); x++) { 1927 ThreadContext *oc = sys->getThreadContext(x); 1928 assert(oc->getITBPtr() && oc->getDTBPtr()); 1929 oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 1930 oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 1931 1932 // If CheckerCPU is connected, need to notify it of a flush 1933 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1934 if (checker) { 1935 checker->getITBPtr()->flushAllSecurity(secure_lookup, 1936 target_el); 1937 checker->getDTBPtr()->flushAllSecurity(secure_lookup, 1938 target_el); 1939 } 1940 } 1941} 1942 1943void 1944ISA::tlbiALLN(ThreadContext *tc, bool hyp, uint8_t target_el) 1945{ 1946 System *sys = tc->getSystemPtr(); 1947 for (int x = 0; x < sys->numContexts(); x++) { 1948 ThreadContext *oc = sys->getThreadContext(x); 1949 assert(oc->getITBPtr() && oc->getDTBPtr()); 1950 oc->getITBPtr()->flushAllNs(hyp, target_el); 1951 oc->getDTBPtr()->flushAllNs(hyp, target_el); 1952 1953 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1954 if (checker) { 1955 checker->getITBPtr()->flushAllNs(hyp, target_el); 1956 checker->getDTBPtr()->flushAllNs(hyp, target_el); 1957 } 1958 } 1959} 1960 1961void 1962ISA::tlbiMVA(ThreadContext *tc, MiscReg newVal, bool secure_lookup, bool hyp, 1963 uint8_t target_el) 1964{ 1965 System *sys = tc->getSystemPtr(); 1966 for (int x = 0; x < sys->numContexts(); x++) { 1967 ThreadContext *oc = sys->getThreadContext(x); 1968 assert(oc->getITBPtr() && oc->getDTBPtr()); 1969 oc->getITBPtr()->flushMva(mbits(newVal, 31,12), 1970 secure_lookup, hyp, target_el); 1971 oc->getDTBPtr()->flushMva(mbits(newVal, 31,12), 1972 secure_lookup, hyp, target_el); 1973 1974 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1975 if (checker) { 1976 checker->getITBPtr()->flushMva(mbits(newVal, 31,12), 1977 secure_lookup, hyp, target_el); 1978 checker->getDTBPtr()->flushMva(mbits(newVal, 31,12), 1979 secure_lookup, hyp, target_el); 1980 } 1981 } 1982} 1983 1984BaseISADevice & 1985ISA::getGenericTimer(ThreadContext *tc) 1986{ 1987 // We only need to create an ISA interface the first time we try 1988 // to access the timer. 1989 if (timer) 1990 return *timer.get(); 1991 1992 assert(system); 1993 GenericTimer *generic_timer(system->getGenericTimer()); 1994 if (!generic_timer) { 1995 panic("Trying to get a generic timer from a system that hasn't " 1996 "been configured to use a generic timer.\n"); 1997 } 1998 1999 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 2000 return *timer.get(); 2001} 2002 2003} 2004 2005ArmISA::ISA * 2006ArmISAParams::create() 2007{ 2008 return new ArmISA::ISA(this); 2009} 2010