isa.cc revision 11774:4b62a0bf0168
1/* 2 * Copyright (c) 2010-2016 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 */ 40 41#include "arch/arm/isa.hh" 42#include "arch/arm/pmu.hh" 43#include "arch/arm/system.hh" 44#include "cpu/checker/cpu.hh" 45#include "cpu/base.hh" 46#include "debug/Arm.hh" 47#include "debug/MiscRegs.hh" 48#include "dev/arm/generic_timer.hh" 49#include "params/ArmISA.hh" 50#include "sim/faults.hh" 51#include "sim/stat_control.hh" 52#include "sim/system.hh" 53 54namespace ArmISA 55{ 56 57 58/** 59 * Some registers alias with others, and therefore need to be translated. 60 * For each entry: 61 * The first value is the misc register that is to be looked up 62 * the second value is the lower part of the translation 63 * the third the upper part 64 * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543 65 */ 66const struct ISA::MiscRegInitializerEntry 67 ISA::MiscRegSwitch[] = { 68 {MISCREG_ACTLR_EL1, {MISCREG_ACTLR_NS, 0}}, 69 {MISCREG_AFSR0_EL1, {MISCREG_ADFSR_NS, 0}}, 70 {MISCREG_AFSR1_EL1, {MISCREG_AIFSR_NS, 0}}, 71 {MISCREG_AMAIR_EL1, {MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS}}, 72 {MISCREG_CONTEXTIDR_EL1, {MISCREG_CONTEXTIDR_NS, 0}}, 73 {MISCREG_CPACR_EL1, {MISCREG_CPACR, 0}}, 74 {MISCREG_CSSELR_EL1, {MISCREG_CSSELR_NS, 0}}, 75 {MISCREG_DACR32_EL2, {MISCREG_DACR_NS, 0}}, 76 {MISCREG_FAR_EL1, {MISCREG_DFAR_NS, MISCREG_IFAR_NS}}, 77 // ESR_EL1 -> DFSR 78 {MISCREG_HACR_EL2, {MISCREG_HACR, 0}}, 79 {MISCREG_ACTLR_EL2, {MISCREG_HACTLR, 0}}, 80 {MISCREG_AFSR0_EL2, {MISCREG_HADFSR, 0}}, 81 {MISCREG_AFSR1_EL2, {MISCREG_HAIFSR, 0}}, 82 {MISCREG_AMAIR_EL2, {MISCREG_HAMAIR0, MISCREG_HAMAIR1}}, 83 {MISCREG_CPTR_EL2, {MISCREG_HCPTR, 0}}, 84 {MISCREG_HCR_EL2, {MISCREG_HCR, 0 /*MISCREG_HCR2*/}}, 85 {MISCREG_MDCR_EL2, {MISCREG_HDCR, 0}}, 86 {MISCREG_FAR_EL2, {MISCREG_HDFAR, MISCREG_HIFAR}}, 87 {MISCREG_MAIR_EL2, {MISCREG_HMAIR0, MISCREG_HMAIR1}}, 88 {MISCREG_HPFAR_EL2, {MISCREG_HPFAR, 0}}, 89 {MISCREG_SCTLR_EL2, {MISCREG_HSCTLR, 0}}, 90 {MISCREG_ESR_EL2, {MISCREG_HSR, 0}}, 91 {MISCREG_HSTR_EL2, {MISCREG_HSTR, 0}}, 92 {MISCREG_TCR_EL2, {MISCREG_HTCR, 0}}, 93 {MISCREG_TPIDR_EL2, {MISCREG_HTPIDR, 0}}, 94 {MISCREG_TTBR0_EL2, {MISCREG_HTTBR, 0}}, 95 {MISCREG_VBAR_EL2, {MISCREG_HVBAR, 0}}, 96 {MISCREG_IFSR32_EL2, {MISCREG_IFSR_NS, 0}}, 97 {MISCREG_MAIR_EL1, {MISCREG_PRRR_NS, MISCREG_NMRR_NS}}, 98 {MISCREG_PAR_EL1, {MISCREG_PAR_NS, 0}}, 99 // RMR_EL1 -> RMR 100 // RMR_EL2 -> HRMR 101 {MISCREG_SCTLR_EL1, {MISCREG_SCTLR_NS, 0}}, 102 {MISCREG_SDER32_EL3, {MISCREG_SDER, 0}}, 103 {MISCREG_TPIDR_EL1, {MISCREG_TPIDRPRW_NS, 0}}, 104 {MISCREG_TPIDRRO_EL0, {MISCREG_TPIDRURO_NS, 0}}, 105 {MISCREG_TPIDR_EL0, {MISCREG_TPIDRURW_NS, 0}}, 106 {MISCREG_TCR_EL1, {MISCREG_TTBCR_NS, 0}}, 107 {MISCREG_TTBR0_EL1, {MISCREG_TTBR0_NS, 0}}, 108 {MISCREG_TTBR1_EL1, {MISCREG_TTBR1_NS, 0}}, 109 {MISCREG_VBAR_EL1, {MISCREG_VBAR_NS, 0}}, 110 {MISCREG_VMPIDR_EL2, {MISCREG_VMPIDR, 0}}, 111 {MISCREG_VPIDR_EL2, {MISCREG_VPIDR, 0}}, 112 {MISCREG_VTCR_EL2, {MISCREG_VTCR, 0}}, 113 {MISCREG_VTTBR_EL2, {MISCREG_VTTBR, 0}}, 114 {MISCREG_CNTFRQ_EL0, {MISCREG_CNTFRQ, 0}}, 115 {MISCREG_CNTHCTL_EL2, {MISCREG_CNTHCTL, 0}}, 116 {MISCREG_CNTHP_CTL_EL2, {MISCREG_CNTHP_CTL, 0}}, 117 {MISCREG_CNTHP_CVAL_EL2, {MISCREG_CNTHP_CVAL, 0}}, /* 64b */ 118 {MISCREG_CNTHP_TVAL_EL2, {MISCREG_CNTHP_TVAL, 0}}, 119 {MISCREG_CNTKCTL_EL1, {MISCREG_CNTKCTL, 0}}, 120 {MISCREG_CNTP_CTL_EL0, {MISCREG_CNTP_CTL_NS, 0}}, 121 {MISCREG_CNTP_CVAL_EL0, {MISCREG_CNTP_CVAL_NS, 0}}, /* 64b */ 122 {MISCREG_CNTP_TVAL_EL0, {MISCREG_CNTP_TVAL_NS, 0}}, 123 {MISCREG_CNTPCT_EL0, {MISCREG_CNTPCT, 0}}, /* 64b */ 124 {MISCREG_CNTV_CTL_EL0, {MISCREG_CNTV_CTL, 0}}, 125 {MISCREG_CNTV_CVAL_EL0, {MISCREG_CNTV_CVAL, 0}}, /* 64b */ 126 {MISCREG_CNTV_TVAL_EL0, {MISCREG_CNTV_TVAL, 0}}, 127 {MISCREG_CNTVCT_EL0, {MISCREG_CNTVCT, 0}}, /* 64b */ 128 {MISCREG_CNTVOFF_EL2, {MISCREG_CNTVOFF, 0}}, /* 64b */ 129 {MISCREG_DBGAUTHSTATUS_EL1, {MISCREG_DBGAUTHSTATUS, 0}}, 130 {MISCREG_DBGBCR0_EL1, {MISCREG_DBGBCR0, 0}}, 131 {MISCREG_DBGBCR1_EL1, {MISCREG_DBGBCR1, 0}}, 132 {MISCREG_DBGBCR2_EL1, {MISCREG_DBGBCR2, 0}}, 133 {MISCREG_DBGBCR3_EL1, {MISCREG_DBGBCR3, 0}}, 134 {MISCREG_DBGBCR4_EL1, {MISCREG_DBGBCR4, 0}}, 135 {MISCREG_DBGBCR5_EL1, {MISCREG_DBGBCR5, 0}}, 136 {MISCREG_DBGBVR0_EL1, {MISCREG_DBGBVR0, 0 /* MISCREG_DBGBXVR0 */}}, 137 {MISCREG_DBGBVR1_EL1, {MISCREG_DBGBVR1, 0 /* MISCREG_DBGBXVR1 */}}, 138 {MISCREG_DBGBVR2_EL1, {MISCREG_DBGBVR2, 0 /* MISCREG_DBGBXVR2 */}}, 139 {MISCREG_DBGBVR3_EL1, {MISCREG_DBGBVR3, 0 /* MISCREG_DBGBXVR3 */}}, 140 {MISCREG_DBGBVR4_EL1, {MISCREG_DBGBVR4, MISCREG_DBGBXVR4}}, 141 {MISCREG_DBGBVR5_EL1, {MISCREG_DBGBVR5, MISCREG_DBGBXVR5}}, 142 {MISCREG_DBGCLAIMSET_EL1, {MISCREG_DBGCLAIMSET, 0}}, 143 {MISCREG_DBGCLAIMCLR_EL1, {MISCREG_DBGCLAIMCLR, 0}}, 144 // DBGDTR_EL0 -> DBGDTR{R or T}Xint 145 // DBGDTRRX_EL0 -> DBGDTRRXint 146 // DBGDTRTX_EL0 -> DBGDTRRXint 147 {MISCREG_DBGPRCR_EL1, {MISCREG_DBGPRCR, 0}}, 148 {MISCREG_DBGVCR32_EL2, {MISCREG_DBGVCR, 0}}, 149 {MISCREG_DBGWCR0_EL1, {MISCREG_DBGWCR0, 0}}, 150 {MISCREG_DBGWCR1_EL1, {MISCREG_DBGWCR1, 0}}, 151 {MISCREG_DBGWCR2_EL1, {MISCREG_DBGWCR2, 0}}, 152 {MISCREG_DBGWCR3_EL1, {MISCREG_DBGWCR3, 0}}, 153 {MISCREG_DBGWVR0_EL1, {MISCREG_DBGWVR0, 0}}, 154 {MISCREG_DBGWVR1_EL1, {MISCREG_DBGWVR1, 0}}, 155 {MISCREG_DBGWVR2_EL1, {MISCREG_DBGWVR2, 0}}, 156 {MISCREG_DBGWVR3_EL1, {MISCREG_DBGWVR3, 0}}, 157 {MISCREG_ID_DFR0_EL1, {MISCREG_ID_DFR0, 0}}, 158 {MISCREG_MDCCSR_EL0, {MISCREG_DBGDSCRint, 0}}, 159 {MISCREG_MDRAR_EL1, {MISCREG_DBGDRAR, 0}}, 160 {MISCREG_MDSCR_EL1, {MISCREG_DBGDSCRext, 0}}, 161 {MISCREG_OSDLR_EL1, {MISCREG_DBGOSDLR, 0}}, 162 {MISCREG_OSDTRRX_EL1, {MISCREG_DBGDTRRXext, 0}}, 163 {MISCREG_OSDTRTX_EL1, {MISCREG_DBGDTRTXext, 0}}, 164 {MISCREG_OSECCR_EL1, {MISCREG_DBGOSECCR, 0}}, 165 {MISCREG_OSLAR_EL1, {MISCREG_DBGOSLAR, 0}}, 166 {MISCREG_OSLSR_EL1, {MISCREG_DBGOSLSR, 0}}, 167 {MISCREG_PMCCNTR_EL0, {MISCREG_PMCCNTR, 0}}, 168 {MISCREG_PMCEID0_EL0, {MISCREG_PMCEID0, 0}}, 169 {MISCREG_PMCEID1_EL0, {MISCREG_PMCEID1, 0}}, 170 {MISCREG_PMCNTENSET_EL0, {MISCREG_PMCNTENSET, 0}}, 171 {MISCREG_PMCNTENCLR_EL0, {MISCREG_PMCNTENCLR, 0}}, 172 {MISCREG_PMCR_EL0, {MISCREG_PMCR, 0}}, 173/* {MISCREG_PMEVCNTR0_EL0, {MISCREG_PMEVCNTR0, 0}}, 174 {MISCREG_PMEVCNTR1_EL0, {MISCREG_PMEVCNTR1, 0}}, 175 {MISCREG_PMEVCNTR2_EL0, {MISCREG_PMEVCNTR2, 0}}, 176 {MISCREG_PMEVCNTR3_EL0, {MISCREG_PMEVCNTR3, 0}}, 177 {MISCREG_PMEVCNTR4_EL0, {MISCREG_PMEVCNTR4, 0}}, 178 {MISCREG_PMEVCNTR5_EL0, {MISCREG_PMEVCNTR5, 0}}, 179 {MISCREG_PMEVTYPER0_EL0, {MISCREG_PMEVTYPER0, 0}}, 180 {MISCREG_PMEVTYPER1_EL0, {MISCREG_PMEVTYPER1, 0}}, 181 {MISCREG_PMEVTYPER2_EL0, {MISCREG_PMEVTYPER2, 0}}, 182 {MISCREG_PMEVTYPER3_EL0, {MISCREG_PMEVTYPER3, 0}}, 183 {MISCREG_PMEVTYPER4_EL0, {MISCREG_PMEVTYPER4, 0}}, 184 {MISCREG_PMEVTYPER5_EL0, {MISCREG_PMEVTYPER5, 0}}, */ 185 {MISCREG_PMINTENCLR_EL1, {MISCREG_PMINTENCLR, 0}}, 186 {MISCREG_PMINTENSET_EL1, {MISCREG_PMINTENSET, 0}}, 187// {MISCREG_PMOVSCLR_EL0, {MISCREG_PMOVSCLR, 0}}, 188 {MISCREG_PMOVSSET_EL0, {MISCREG_PMOVSSET, 0}}, 189 {MISCREG_PMSELR_EL0, {MISCREG_PMSELR, 0}}, 190 {MISCREG_PMSWINC_EL0, {MISCREG_PMSWINC, 0}}, 191 {MISCREG_PMUSERENR_EL0, {MISCREG_PMUSERENR, 0}}, 192 {MISCREG_PMXEVCNTR_EL0, {MISCREG_PMXEVCNTR, 0}}, 193 {MISCREG_PMXEVTYPER_EL0, {MISCREG_PMXEVTYPER, 0}}, 194 195 // from ARM DDI 0487A.i, template text 196 // "AArch64 System register ___ can be mapped to 197 // AArch32 System register ___, but this is not 198 // architecturally mandated." 199 {MISCREG_SCR_EL3, {MISCREG_SCR, 0}}, // D7-2005 200 // MDCR_EL3 -> SDCR, D7-2108 (the latter is unimpl. in gem5) 201 {MISCREG_SPSR_EL1, {MISCREG_SPSR_SVC, 0}}, // C5.2.17 SPSR_EL1 202 {MISCREG_SPSR_EL2, {MISCREG_SPSR_HYP, 0}}, // C5.2.18 SPSR_EL2 203 {MISCREG_SPSR_EL3, {MISCREG_SPSR_MON, 0}}, // C5.2.19 SPSR_EL3 204}; 205 206 207ISA::ISA(Params *p) 208 : SimObject(p), 209 system(NULL), 210 _decoderFlavour(p->decoderFlavour), 211 pmu(p->pmu), 212 lookUpMiscReg(NUM_MISCREGS, {0,0}) 213{ 214 miscRegs[MISCREG_SCTLR_RST] = 0; 215 216 // Hook up a dummy device if we haven't been configured with a 217 // real PMU. By using a dummy device, we don't need to check that 218 // the PMU exist every time we try to access a PMU register. 219 if (!pmu) 220 pmu = &dummyDevice; 221 222 // Give all ISA devices a pointer to this ISA 223 pmu->setISA(this); 224 225 system = dynamic_cast<ArmSystem *>(p->system); 226 227 // Cache system-level properties 228 if (FullSystem && system) { 229 highestELIs64 = system->highestELIs64(); 230 haveSecurity = system->haveSecurity(); 231 haveLPAE = system->haveLPAE(); 232 haveVirtualization = system->haveVirtualization(); 233 haveLargeAsid64 = system->haveLargeAsid64(); 234 physAddrRange64 = system->physAddrRange64(); 235 } else { 236 highestELIs64 = true; // ArmSystem::highestELIs64 does the same 237 haveSecurity = haveLPAE = haveVirtualization = false; 238 haveLargeAsid64 = false; 239 physAddrRange64 = 32; // dummy value 240 } 241 242 /** Fill in the miscReg translation table */ 243 for (auto sw : MiscRegSwitch) { 244 lookUpMiscReg[sw.index] = sw.entry; 245 } 246 247 preUnflattenMiscReg(); 248 249 clear(); 250} 251 252const ArmISAParams * 253ISA::params() const 254{ 255 return dynamic_cast<const Params *>(_params); 256} 257 258void 259ISA::clear() 260{ 261 const Params *p(params()); 262 263 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 264 memset(miscRegs, 0, sizeof(miscRegs)); 265 266 // Initialize configurable default values 267 miscRegs[MISCREG_MIDR] = p->midr; 268 miscRegs[MISCREG_MIDR_EL1] = p->midr; 269 miscRegs[MISCREG_VPIDR] = p->midr; 270 271 if (FullSystem && system->highestELIs64()) { 272 // Initialize AArch64 state 273 clear64(p); 274 return; 275 } 276 277 // Initialize AArch32 state... 278 279 CPSR cpsr = 0; 280 cpsr.mode = MODE_USER; 281 miscRegs[MISCREG_CPSR] = cpsr; 282 updateRegMap(cpsr); 283 284 SCTLR sctlr = 0; 285 sctlr.te = (bool) sctlr_rst.te; 286 sctlr.nmfi = (bool) sctlr_rst.nmfi; 287 sctlr.v = (bool) sctlr_rst.v; 288 sctlr.u = 1; 289 sctlr.xp = 1; 290 sctlr.rao2 = 1; 291 sctlr.rao3 = 1; 292 sctlr.rao4 = 0xf; // SCTLR[6:3] 293 sctlr.uci = 1; 294 sctlr.dze = 1; 295 miscRegs[MISCREG_SCTLR_NS] = sctlr; 296 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 297 miscRegs[MISCREG_HCPTR] = 0; 298 299 // Start with an event in the mailbox 300 miscRegs[MISCREG_SEV_MAILBOX] = 1; 301 302 // Separate Instruction and Data TLBs 303 miscRegs[MISCREG_TLBTR] = 1; 304 305 MVFR0 mvfr0 = 0; 306 mvfr0.advSimdRegisters = 2; 307 mvfr0.singlePrecision = 2; 308 mvfr0.doublePrecision = 2; 309 mvfr0.vfpExceptionTrapping = 0; 310 mvfr0.divide = 1; 311 mvfr0.squareRoot = 1; 312 mvfr0.shortVectors = 1; 313 mvfr0.roundingModes = 1; 314 miscRegs[MISCREG_MVFR0] = mvfr0; 315 316 MVFR1 mvfr1 = 0; 317 mvfr1.flushToZero = 1; 318 mvfr1.defaultNaN = 1; 319 mvfr1.advSimdLoadStore = 1; 320 mvfr1.advSimdInteger = 1; 321 mvfr1.advSimdSinglePrecision = 1; 322 mvfr1.advSimdHalfPrecision = 1; 323 mvfr1.vfpHalfPrecision = 1; 324 miscRegs[MISCREG_MVFR1] = mvfr1; 325 326 // Reset values of PRRR and NMRR are implementation dependent 327 328 // @todo: PRRR and NMRR in secure state? 329 miscRegs[MISCREG_PRRR_NS] = 330 (1 << 19) | // 19 331 (0 << 18) | // 18 332 (0 << 17) | // 17 333 (1 << 16) | // 16 334 (2 << 14) | // 15:14 335 (0 << 12) | // 13:12 336 (2 << 10) | // 11:10 337 (2 << 8) | // 9:8 338 (2 << 6) | // 7:6 339 (2 << 4) | // 5:4 340 (1 << 2) | // 3:2 341 0; // 1:0 342 miscRegs[MISCREG_NMRR_NS] = 343 (1 << 30) | // 31:30 344 (0 << 26) | // 27:26 345 (0 << 24) | // 25:24 346 (3 << 22) | // 23:22 347 (2 << 20) | // 21:20 348 (0 << 18) | // 19:18 349 (0 << 16) | // 17:16 350 (1 << 14) | // 15:14 351 (0 << 12) | // 13:12 352 (2 << 10) | // 11:10 353 (0 << 8) | // 9:8 354 (3 << 6) | // 7:6 355 (2 << 4) | // 5:4 356 (0 << 2) | // 3:2 357 0; // 1:0 358 359 miscRegs[MISCREG_CPACR] = 0; 360 361 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 362 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 363 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 364 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 365 366 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 367 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 368 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 369 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 370 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 371 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 372 373 miscRegs[MISCREG_FPSID] = p->fpsid; 374 375 if (haveLPAE) { 376 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 377 ttbcr.eae = 0; 378 miscRegs[MISCREG_TTBCR_NS] = ttbcr; 379 // Enforce consistency with system-level settings 380 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 381 } 382 383 if (haveSecurity) { 384 miscRegs[MISCREG_SCTLR_S] = sctlr; 385 miscRegs[MISCREG_SCR] = 0; 386 miscRegs[MISCREG_VBAR_S] = 0; 387 } else { 388 // we're always non-secure 389 miscRegs[MISCREG_SCR] = 1; 390 } 391 392 //XXX We need to initialize the rest of the state. 393} 394 395void 396ISA::clear64(const ArmISAParams *p) 397{ 398 CPSR cpsr = 0; 399 Addr rvbar = system->resetAddr64(); 400 switch (system->highestEL()) { 401 // Set initial EL to highest implemented EL using associated stack 402 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 403 // value 404 case EL3: 405 cpsr.mode = MODE_EL3H; 406 miscRegs[MISCREG_RVBAR_EL3] = rvbar; 407 break; 408 case EL2: 409 cpsr.mode = MODE_EL2H; 410 miscRegs[MISCREG_RVBAR_EL2] = rvbar; 411 break; 412 case EL1: 413 cpsr.mode = MODE_EL1H; 414 miscRegs[MISCREG_RVBAR_EL1] = rvbar; 415 break; 416 default: 417 panic("Invalid highest implemented exception level"); 418 break; 419 } 420 421 // Initialize rest of CPSR 422 cpsr.daif = 0xf; // Mask all interrupts 423 cpsr.ss = 0; 424 cpsr.il = 0; 425 miscRegs[MISCREG_CPSR] = cpsr; 426 updateRegMap(cpsr); 427 428 // Initialize other control registers 429 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 430 if (haveSecurity) { 431 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830; 432 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 433 } else if (haveVirtualization) { 434 // also MISCREG_SCTLR_EL2 (by mapping) 435 miscRegs[MISCREG_HSCTLR] = 0x30c50830; 436 } else { 437 // also MISCREG_SCTLR_EL1 (by mapping) 438 miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init 439 // Always non-secure 440 miscRegs[MISCREG_SCR_EL3] = 1; 441 } 442 443 // Initialize configurable id registers 444 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 445 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 446 miscRegs[MISCREG_ID_AA64DFR0_EL1] = 447 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 448 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 449 450 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 451 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 452 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 453 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 454 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 455 456 miscRegs[MISCREG_ID_DFR0_EL1] = 457 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 458 459 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 460 461 // Enforce consistency with system-level settings... 462 463 // EL3 464 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 465 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 466 haveSecurity ? 0x2 : 0x0); 467 // EL2 468 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 469 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 470 haveVirtualization ? 0x2 : 0x0); 471 // Large ASID support 472 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 473 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 474 haveLargeAsid64 ? 0x2 : 0x0); 475 // Physical address size 476 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 477 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 478 encodePhysAddrRange64(physAddrRange64)); 479} 480 481MiscReg 482ISA::readMiscRegNoEffect(int misc_reg) const 483{ 484 assert(misc_reg < NumMiscRegs); 485 486 auto regs = getMiscIndices(misc_reg); 487 int lower = regs.first, upper = regs.second; 488 return !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32)) 489 |(miscRegs[upper] << 32)); 490} 491 492 493MiscReg 494ISA::readMiscReg(int misc_reg, ThreadContext *tc) 495{ 496 CPSR cpsr = 0; 497 PCState pc = 0; 498 SCR scr = 0; 499 500 if (misc_reg == MISCREG_CPSR) { 501 cpsr = miscRegs[misc_reg]; 502 pc = tc->pcState(); 503 cpsr.j = pc.jazelle() ? 1 : 0; 504 cpsr.t = pc.thumb() ? 1 : 0; 505 return cpsr; 506 } 507 508#ifndef NDEBUG 509 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 510 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 511 warn("Unimplemented system register %s read.\n", 512 miscRegName[misc_reg]); 513 else 514 panic("Unimplemented system register %s read.\n", 515 miscRegName[misc_reg]); 516 } 517#endif 518 519 switch (unflattenMiscReg(misc_reg)) { 520 case MISCREG_HCR: 521 { 522 if (!haveVirtualization) 523 return 0; 524 else 525 return readMiscRegNoEffect(MISCREG_HCR); 526 } 527 case MISCREG_CPACR: 528 { 529 const uint32_t ones = (uint32_t)(-1); 530 CPACR cpacrMask = 0; 531 // Only cp10, cp11, and ase are implemented, nothing else should 532 // be readable? (straight copy from the write code) 533 cpacrMask.cp10 = ones; 534 cpacrMask.cp11 = ones; 535 cpacrMask.asedis = ones; 536 537 // Security Extensions may limit the readability of CPACR 538 if (haveSecurity) { 539 scr = readMiscRegNoEffect(MISCREG_SCR); 540 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 541 if (scr.ns && (cpsr.mode != MODE_MON)) { 542 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 543 // NB: Skipping the full loop, here 544 if (!nsacr.cp10) cpacrMask.cp10 = 0; 545 if (!nsacr.cp11) cpacrMask.cp11 = 0; 546 } 547 } 548 MiscReg val = readMiscRegNoEffect(MISCREG_CPACR); 549 val &= cpacrMask; 550 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 551 miscRegName[misc_reg], val); 552 return val; 553 } 554 case MISCREG_MPIDR: 555 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 556 scr = readMiscRegNoEffect(MISCREG_SCR); 557 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 558 return getMPIDR(system, tc); 559 } else { 560 return readMiscReg(MISCREG_VMPIDR, tc); 561 } 562 break; 563 case MISCREG_MPIDR_EL1: 564 // @todo in the absence of v8 virtualization support just return MPIDR_EL1 565 return getMPIDR(system, tc) & 0xffffffff; 566 case MISCREG_VMPIDR: 567 // top bit defined as RES1 568 return readMiscRegNoEffect(misc_reg) | 0x80000000; 569 case MISCREG_ID_AFR0: // not implemented, so alias MIDR 570 case MISCREG_REVIDR: // not implemented, so alias MIDR 571 case MISCREG_MIDR: 572 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 573 scr = readMiscRegNoEffect(MISCREG_SCR); 574 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 575 return readMiscRegNoEffect(misc_reg); 576 } else { 577 return readMiscRegNoEffect(MISCREG_VPIDR); 578 } 579 break; 580 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 581 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 582 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 583 case MISCREG_AIDR: // AUX ID set to 0 584 case MISCREG_TCMTR: // No TCM's 585 return 0; 586 587 case MISCREG_CLIDR: 588 warn_once("The clidr register always reports 0 caches.\n"); 589 warn_once("clidr LoUIS field of 0b001 to match current " 590 "ARM implementations.\n"); 591 return 0x00200000; 592 case MISCREG_CCSIDR: 593 warn_once("The ccsidr register isn't implemented and " 594 "always reads as 0.\n"); 595 break; 596 case MISCREG_CTR: 597 { 598 //all caches have the same line size in gem5 599 //4 byte words in ARM 600 unsigned lineSizeWords = 601 tc->getSystemPtr()->cacheLineSize() / 4; 602 unsigned log2LineSizeWords = 0; 603 604 while (lineSizeWords >>= 1) { 605 ++log2LineSizeWords; 606 } 607 608 CTR ctr = 0; 609 //log2 of minimun i-cache line size (words) 610 ctr.iCacheLineSize = log2LineSizeWords; 611 //b11 - gem5 uses pipt 612 ctr.l1IndexPolicy = 0x3; 613 //log2 of minimum d-cache line size (words) 614 ctr.dCacheLineSize = log2LineSizeWords; 615 //log2 of max reservation size (words) 616 ctr.erg = log2LineSizeWords; 617 //log2 of max writeback size (words) 618 ctr.cwg = log2LineSizeWords; 619 //b100 - gem5 format is ARMv7 620 ctr.format = 0x4; 621 622 return ctr; 623 } 624 case MISCREG_ACTLR: 625 warn("Not doing anything for miscreg ACTLR\n"); 626 break; 627 628 case MISCREG_PMXEVTYPER_PMCCFILTR: 629 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 630 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 631 case MISCREG_PMCR ... MISCREG_PMOVSSET: 632 return pmu->readMiscReg(misc_reg); 633 634 case MISCREG_CPSR_Q: 635 panic("shouldn't be reading this register seperately\n"); 636 case MISCREG_FPSCR_QC: 637 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 638 case MISCREG_FPSCR_EXC: 639 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 640 case MISCREG_FPSR: 641 { 642 const uint32_t ones = (uint32_t)(-1); 643 FPSCR fpscrMask = 0; 644 fpscrMask.ioc = ones; 645 fpscrMask.dzc = ones; 646 fpscrMask.ofc = ones; 647 fpscrMask.ufc = ones; 648 fpscrMask.ixc = ones; 649 fpscrMask.idc = ones; 650 fpscrMask.qc = ones; 651 fpscrMask.v = ones; 652 fpscrMask.c = ones; 653 fpscrMask.z = ones; 654 fpscrMask.n = ones; 655 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 656 } 657 case MISCREG_FPCR: 658 { 659 const uint32_t ones = (uint32_t)(-1); 660 FPSCR fpscrMask = 0; 661 fpscrMask.ioe = ones; 662 fpscrMask.dze = ones; 663 fpscrMask.ofe = ones; 664 fpscrMask.ufe = ones; 665 fpscrMask.ixe = ones; 666 fpscrMask.ide = ones; 667 fpscrMask.len = ones; 668 fpscrMask.stride = ones; 669 fpscrMask.rMode = ones; 670 fpscrMask.fz = ones; 671 fpscrMask.dn = ones; 672 fpscrMask.ahp = ones; 673 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 674 } 675 case MISCREG_NZCV: 676 { 677 CPSR cpsr = 0; 678 cpsr.nz = tc->readCCReg(CCREG_NZ); 679 cpsr.c = tc->readCCReg(CCREG_C); 680 cpsr.v = tc->readCCReg(CCREG_V); 681 return cpsr; 682 } 683 case MISCREG_DAIF: 684 { 685 CPSR cpsr = 0; 686 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 687 return cpsr; 688 } 689 case MISCREG_SP_EL0: 690 { 691 return tc->readIntReg(INTREG_SP0); 692 } 693 case MISCREG_SP_EL1: 694 { 695 return tc->readIntReg(INTREG_SP1); 696 } 697 case MISCREG_SP_EL2: 698 { 699 return tc->readIntReg(INTREG_SP2); 700 } 701 case MISCREG_SPSEL: 702 { 703 return miscRegs[MISCREG_CPSR] & 0x1; 704 } 705 case MISCREG_CURRENTEL: 706 { 707 return miscRegs[MISCREG_CPSR] & 0xc; 708 } 709 case MISCREG_L2CTLR: 710 { 711 // mostly unimplemented, just set NumCPUs field from sim and return 712 L2CTLR l2ctlr = 0; 713 // b00:1CPU to b11:4CPUs 714 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 715 return l2ctlr; 716 } 717 case MISCREG_DBGDIDR: 718 /* For now just implement the version number. 719 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 720 */ 721 return 0x5 << 16; 722 case MISCREG_DBGDSCRint: 723 return 0; 724 case MISCREG_ISR: 725 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 726 readMiscRegNoEffect(MISCREG_HCR), 727 readMiscRegNoEffect(MISCREG_CPSR), 728 readMiscRegNoEffect(MISCREG_SCR)); 729 case MISCREG_ISR_EL1: 730 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 731 readMiscRegNoEffect(MISCREG_HCR_EL2), 732 readMiscRegNoEffect(MISCREG_CPSR), 733 readMiscRegNoEffect(MISCREG_SCR_EL3)); 734 case MISCREG_DCZID_EL0: 735 return 0x04; // DC ZVA clear 64-byte chunks 736 case MISCREG_HCPTR: 737 { 738 MiscReg val = readMiscRegNoEffect(misc_reg); 739 // The trap bit associated with CP14 is defined as RAZ 740 val &= ~(1 << 14); 741 // If a CP bit in NSACR is 0 then the corresponding bit in 742 // HCPTR is RAO/WI 743 bool secure_lookup = haveSecurity && 744 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 745 readMiscRegNoEffect(MISCREG_CPSR)); 746 if (!secure_lookup) { 747 MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR); 748 val |= (mask ^ 0x7FFF) & 0xBFFF; 749 } 750 // Set the bits for unimplemented coprocessors to RAO/WI 751 val |= 0x33FF; 752 return (val); 753 } 754 case MISCREG_HDFAR: // alias for secure DFAR 755 return readMiscRegNoEffect(MISCREG_DFAR_S); 756 case MISCREG_HIFAR: // alias for secure IFAR 757 return readMiscRegNoEffect(MISCREG_IFAR_S); 758 case MISCREG_HVBAR: // bottom bits reserved 759 return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0; 760 case MISCREG_SCTLR: 761 return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818; 762 case MISCREG_SCTLR_EL1: 763 return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800; 764 case MISCREG_SCTLR_EL2: 765 case MISCREG_SCTLR_EL3: 766 case MISCREG_HSCTLR: 767 return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; 768 769 case MISCREG_ID_PFR0: 770 // !ThumbEE | !Jazelle | Thumb | ARM 771 return 0x00000031; 772 case MISCREG_ID_PFR1: 773 { // Timer | Virti | !M Profile | TrustZone | ARMv4 774 bool haveTimer = (system->getGenericTimer() != NULL); 775 return 0x00000001 776 | (haveSecurity ? 0x00000010 : 0x0) 777 | (haveVirtualization ? 0x00001000 : 0x0) 778 | (haveTimer ? 0x00010000 : 0x0); 779 } 780 case MISCREG_ID_AA64PFR0_EL1: 781 return 0x0000000000000002 // AArch{64,32} supported at EL0 782 | 0x0000000000000020 // EL1 783 | (haveVirtualization ? 0x0000000000000200 : 0) // EL2 784 | (haveSecurity ? 0x0000000000002000 : 0); // EL3 785 case MISCREG_ID_AA64PFR1_EL1: 786 return 0; // bits [63:0] RES0 (reserved for future use) 787 788 // Generic Timer registers 789 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 790 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 791 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 792 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 793 return getGenericTimer(tc).readMiscReg(misc_reg); 794 795 default: 796 break; 797 798 } 799 return readMiscRegNoEffect(misc_reg); 800} 801 802void 803ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 804{ 805 assert(misc_reg < NumMiscRegs); 806 807 auto regs = getMiscIndices(misc_reg); 808 int lower = regs.first, upper = regs.second; 809 if (upper > 0) { 810 miscRegs[lower] = bits(val, 31, 0); 811 miscRegs[upper] = bits(val, 63, 32); 812 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 813 misc_reg, lower, upper, val); 814 } else { 815 miscRegs[lower] = val; 816 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 817 misc_reg, lower, val); 818 } 819} 820 821void 822ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 823{ 824 825 MiscReg newVal = val; 826 int x; 827 bool secure_lookup; 828 bool hyp; 829 System *sys; 830 ThreadContext *oc; 831 uint8_t target_el; 832 uint16_t asid; 833 SCR scr; 834 835 if (misc_reg == MISCREG_CPSR) { 836 updateRegMap(val); 837 838 839 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 840 int old_mode = old_cpsr.mode; 841 CPSR cpsr = val; 842 if (old_mode != cpsr.mode) { 843 tc->getITBPtr()->invalidateMiscReg(); 844 tc->getDTBPtr()->invalidateMiscReg(); 845 } 846 847 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 848 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 849 PCState pc = tc->pcState(); 850 pc.nextThumb(cpsr.t); 851 pc.nextJazelle(cpsr.j); 852 853 // Follow slightly different semantics if a CheckerCPU object 854 // is connected 855 CheckerCPU *checker = tc->getCheckerCpuPtr(); 856 if (checker) { 857 tc->pcStateNoRecord(pc); 858 } else { 859 tc->pcState(pc); 860 } 861 } else { 862#ifndef NDEBUG 863 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 864 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 865 warn("Unimplemented system register %s write with %#x.\n", 866 miscRegName[misc_reg], val); 867 else 868 panic("Unimplemented system register %s write with %#x.\n", 869 miscRegName[misc_reg], val); 870 } 871#endif 872 switch (unflattenMiscReg(misc_reg)) { 873 case MISCREG_CPACR: 874 { 875 876 const uint32_t ones = (uint32_t)(-1); 877 CPACR cpacrMask = 0; 878 // Only cp10, cp11, and ase are implemented, nothing else should 879 // be writable 880 cpacrMask.cp10 = ones; 881 cpacrMask.cp11 = ones; 882 cpacrMask.asedis = ones; 883 884 // Security Extensions may limit the writability of CPACR 885 if (haveSecurity) { 886 scr = readMiscRegNoEffect(MISCREG_SCR); 887 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 888 if (scr.ns && (cpsr.mode != MODE_MON)) { 889 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 890 // NB: Skipping the full loop, here 891 if (!nsacr.cp10) cpacrMask.cp10 = 0; 892 if (!nsacr.cp11) cpacrMask.cp11 = 0; 893 } 894 } 895 896 MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR); 897 newVal &= cpacrMask; 898 newVal |= old_val & ~cpacrMask; 899 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 900 miscRegName[misc_reg], newVal); 901 } 902 break; 903 case MISCREG_CPACR_EL1: 904 { 905 const uint32_t ones = (uint32_t)(-1); 906 CPACR cpacrMask = 0; 907 cpacrMask.tta = ones; 908 cpacrMask.fpen = ones; 909 newVal &= cpacrMask; 910 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 911 miscRegName[misc_reg], newVal); 912 } 913 break; 914 case MISCREG_CPTR_EL2: 915 { 916 const uint32_t ones = (uint32_t)(-1); 917 CPTR cptrMask = 0; 918 cptrMask.tcpac = ones; 919 cptrMask.tta = ones; 920 cptrMask.tfp = ones; 921 newVal &= cptrMask; 922 cptrMask = 0; 923 cptrMask.res1_13_12_el2 = ones; 924 cptrMask.res1_9_0_el2 = ones; 925 newVal |= cptrMask; 926 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 927 miscRegName[misc_reg], newVal); 928 } 929 break; 930 case MISCREG_CPTR_EL3: 931 { 932 const uint32_t ones = (uint32_t)(-1); 933 CPTR cptrMask = 0; 934 cptrMask.tcpac = ones; 935 cptrMask.tta = ones; 936 cptrMask.tfp = ones; 937 newVal &= cptrMask; 938 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 939 miscRegName[misc_reg], newVal); 940 } 941 break; 942 case MISCREG_CSSELR: 943 warn_once("The csselr register isn't implemented.\n"); 944 return; 945 946 case MISCREG_DC_ZVA_Xt: 947 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 948 return; 949 950 case MISCREG_FPSCR: 951 { 952 const uint32_t ones = (uint32_t)(-1); 953 FPSCR fpscrMask = 0; 954 fpscrMask.ioc = ones; 955 fpscrMask.dzc = ones; 956 fpscrMask.ofc = ones; 957 fpscrMask.ufc = ones; 958 fpscrMask.ixc = ones; 959 fpscrMask.idc = ones; 960 fpscrMask.ioe = ones; 961 fpscrMask.dze = ones; 962 fpscrMask.ofe = ones; 963 fpscrMask.ufe = ones; 964 fpscrMask.ixe = ones; 965 fpscrMask.ide = ones; 966 fpscrMask.len = ones; 967 fpscrMask.stride = ones; 968 fpscrMask.rMode = ones; 969 fpscrMask.fz = ones; 970 fpscrMask.dn = ones; 971 fpscrMask.ahp = ones; 972 fpscrMask.qc = ones; 973 fpscrMask.v = ones; 974 fpscrMask.c = ones; 975 fpscrMask.z = ones; 976 fpscrMask.n = ones; 977 newVal = (newVal & (uint32_t)fpscrMask) | 978 (readMiscRegNoEffect(MISCREG_FPSCR) & 979 ~(uint32_t)fpscrMask); 980 tc->getDecoderPtr()->setContext(newVal); 981 } 982 break; 983 case MISCREG_FPSR: 984 { 985 const uint32_t ones = (uint32_t)(-1); 986 FPSCR fpscrMask = 0; 987 fpscrMask.ioc = ones; 988 fpscrMask.dzc = ones; 989 fpscrMask.ofc = ones; 990 fpscrMask.ufc = ones; 991 fpscrMask.ixc = ones; 992 fpscrMask.idc = ones; 993 fpscrMask.qc = ones; 994 fpscrMask.v = ones; 995 fpscrMask.c = ones; 996 fpscrMask.z = ones; 997 fpscrMask.n = ones; 998 newVal = (newVal & (uint32_t)fpscrMask) | 999 (readMiscRegNoEffect(MISCREG_FPSCR) & 1000 ~(uint32_t)fpscrMask); 1001 misc_reg = MISCREG_FPSCR; 1002 } 1003 break; 1004 case MISCREG_FPCR: 1005 { 1006 const uint32_t ones = (uint32_t)(-1); 1007 FPSCR fpscrMask = 0; 1008 fpscrMask.ioe = ones; 1009 fpscrMask.dze = ones; 1010 fpscrMask.ofe = ones; 1011 fpscrMask.ufe = ones; 1012 fpscrMask.ixe = ones; 1013 fpscrMask.ide = ones; 1014 fpscrMask.len = ones; 1015 fpscrMask.stride = ones; 1016 fpscrMask.rMode = ones; 1017 fpscrMask.fz = ones; 1018 fpscrMask.dn = ones; 1019 fpscrMask.ahp = ones; 1020 newVal = (newVal & (uint32_t)fpscrMask) | 1021 (readMiscRegNoEffect(MISCREG_FPSCR) & 1022 ~(uint32_t)fpscrMask); 1023 misc_reg = MISCREG_FPSCR; 1024 } 1025 break; 1026 case MISCREG_CPSR_Q: 1027 { 1028 assert(!(newVal & ~CpsrMaskQ)); 1029 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 1030 misc_reg = MISCREG_CPSR; 1031 } 1032 break; 1033 case MISCREG_FPSCR_QC: 1034 { 1035 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 1036 (newVal & FpscrQcMask); 1037 misc_reg = MISCREG_FPSCR; 1038 } 1039 break; 1040 case MISCREG_FPSCR_EXC: 1041 { 1042 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 1043 (newVal & FpscrExcMask); 1044 misc_reg = MISCREG_FPSCR; 1045 } 1046 break; 1047 case MISCREG_FPEXC: 1048 { 1049 // vfpv3 architecture, section B.6.1 of DDI04068 1050 // bit 29 - valid only if fpexc[31] is 0 1051 const uint32_t fpexcMask = 0x60000000; 1052 newVal = (newVal & fpexcMask) | 1053 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 1054 } 1055 break; 1056 case MISCREG_HCR: 1057 { 1058 if (!haveVirtualization) 1059 return; 1060 } 1061 break; 1062 case MISCREG_IFSR: 1063 { 1064 // ARM ARM (ARM DDI 0406C.b) B4.1.96 1065 const uint32_t ifsrMask = 1066 mask(31, 13) | mask(11, 11) | mask(8, 6); 1067 newVal = newVal & ~ifsrMask; 1068 } 1069 break; 1070 case MISCREG_DFSR: 1071 { 1072 // ARM ARM (ARM DDI 0406C.b) B4.1.52 1073 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 1074 newVal = newVal & ~dfsrMask; 1075 } 1076 break; 1077 case MISCREG_AMAIR0: 1078 case MISCREG_AMAIR1: 1079 { 1080 // ARM ARM (ARM DDI 0406C.b) B4.1.5 1081 // Valid only with LPAE 1082 if (!haveLPAE) 1083 return; 1084 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 1085 } 1086 break; 1087 case MISCREG_SCR: 1088 tc->getITBPtr()->invalidateMiscReg(); 1089 tc->getDTBPtr()->invalidateMiscReg(); 1090 break; 1091 case MISCREG_SCTLR: 1092 { 1093 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 1094 scr = readMiscRegNoEffect(MISCREG_SCR); 1095 MiscRegIndex sctlr_idx = (haveSecurity && !scr.ns) 1096 ? MISCREG_SCTLR_S : MISCREG_SCTLR_NS; 1097 SCTLR sctlr = miscRegs[sctlr_idx]; 1098 SCTLR new_sctlr = newVal; 1099 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 1100 miscRegs[sctlr_idx] = (MiscReg)new_sctlr; 1101 tc->getITBPtr()->invalidateMiscReg(); 1102 tc->getDTBPtr()->invalidateMiscReg(); 1103 } 1104 case MISCREG_MIDR: 1105 case MISCREG_ID_PFR0: 1106 case MISCREG_ID_PFR1: 1107 case MISCREG_ID_DFR0: 1108 case MISCREG_ID_MMFR0: 1109 case MISCREG_ID_MMFR1: 1110 case MISCREG_ID_MMFR2: 1111 case MISCREG_ID_MMFR3: 1112 case MISCREG_ID_ISAR0: 1113 case MISCREG_ID_ISAR1: 1114 case MISCREG_ID_ISAR2: 1115 case MISCREG_ID_ISAR3: 1116 case MISCREG_ID_ISAR4: 1117 case MISCREG_ID_ISAR5: 1118 1119 case MISCREG_MPIDR: 1120 case MISCREG_FPSID: 1121 case MISCREG_TLBTR: 1122 case MISCREG_MVFR0: 1123 case MISCREG_MVFR1: 1124 1125 case MISCREG_ID_AA64AFR0_EL1: 1126 case MISCREG_ID_AA64AFR1_EL1: 1127 case MISCREG_ID_AA64DFR0_EL1: 1128 case MISCREG_ID_AA64DFR1_EL1: 1129 case MISCREG_ID_AA64ISAR0_EL1: 1130 case MISCREG_ID_AA64ISAR1_EL1: 1131 case MISCREG_ID_AA64MMFR0_EL1: 1132 case MISCREG_ID_AA64MMFR1_EL1: 1133 case MISCREG_ID_AA64PFR0_EL1: 1134 case MISCREG_ID_AA64PFR1_EL1: 1135 // ID registers are constants. 1136 return; 1137 1138 // TLBI all entries, EL0&1 inner sharable (ignored) 1139 case MISCREG_TLBIALLIS: 1140 case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 1141 assert32(tc); 1142 target_el = 1; // el 0 and 1 are handled together 1143 scr = readMiscReg(MISCREG_SCR, tc); 1144 secure_lookup = haveSecurity && !scr.ns; 1145 sys = tc->getSystemPtr(); 1146 for (x = 0; x < sys->numContexts(); x++) { 1147 oc = sys->getThreadContext(x); 1148 assert(oc->getITBPtr() && oc->getDTBPtr()); 1149 oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 1150 oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 1151 1152 // If CheckerCPU is connected, need to notify it of a flush 1153 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1154 if (checker) { 1155 checker->getITBPtr()->flushAllSecurity(secure_lookup, 1156 target_el); 1157 checker->getDTBPtr()->flushAllSecurity(secure_lookup, 1158 target_el); 1159 } 1160 } 1161 return; 1162 // TLBI all entries, EL0&1, instruction side 1163 case MISCREG_ITLBIALL: 1164 assert32(tc); 1165 target_el = 1; // el 0 and 1 are handled together 1166 scr = readMiscReg(MISCREG_SCR, tc); 1167 secure_lookup = haveSecurity && !scr.ns; 1168 tc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 1169 return; 1170 // TLBI all entries, EL0&1, data side 1171 case MISCREG_DTLBIALL: 1172 assert32(tc); 1173 target_el = 1; // el 0 and 1 are handled together 1174 scr = readMiscReg(MISCREG_SCR, tc); 1175 secure_lookup = haveSecurity && !scr.ns; 1176 tc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 1177 return; 1178 // TLBI based on VA, EL0&1 inner sharable (ignored) 1179 case MISCREG_TLBIMVAIS: 1180 case MISCREG_TLBIMVA: 1181 assert32(tc); 1182 target_el = 1; // el 0 and 1 are handled together 1183 scr = readMiscReg(MISCREG_SCR, tc); 1184 secure_lookup = haveSecurity && !scr.ns; 1185 sys = tc->getSystemPtr(); 1186 for (x = 0; x < sys->numContexts(); x++) { 1187 oc = sys->getThreadContext(x); 1188 assert(oc->getITBPtr() && oc->getDTBPtr()); 1189 oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1190 bits(newVal, 7,0), 1191 secure_lookup, target_el); 1192 oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1193 bits(newVal, 7,0), 1194 secure_lookup, target_el); 1195 1196 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1197 if (checker) { 1198 checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1199 bits(newVal, 7,0), secure_lookup, target_el); 1200 checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1201 bits(newVal, 7,0), secure_lookup, target_el); 1202 } 1203 } 1204 return; 1205 // TLBI by ASID, EL0&1, inner sharable 1206 case MISCREG_TLBIASIDIS: 1207 case MISCREG_TLBIASID: 1208 assert32(tc); 1209 target_el = 1; // el 0 and 1 are handled together 1210 scr = readMiscReg(MISCREG_SCR, tc); 1211 secure_lookup = haveSecurity && !scr.ns; 1212 sys = tc->getSystemPtr(); 1213 for (x = 0; x < sys->numContexts(); x++) { 1214 oc = sys->getThreadContext(x); 1215 assert(oc->getITBPtr() && oc->getDTBPtr()); 1216 oc->getITBPtr()->flushAsid(bits(newVal, 7,0), 1217 secure_lookup, target_el); 1218 oc->getDTBPtr()->flushAsid(bits(newVal, 7,0), 1219 secure_lookup, target_el); 1220 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1221 if (checker) { 1222 checker->getITBPtr()->flushAsid(bits(newVal, 7,0), 1223 secure_lookup, target_el); 1224 checker->getDTBPtr()->flushAsid(bits(newVal, 7,0), 1225 secure_lookup, target_el); 1226 } 1227 } 1228 return; 1229 // TLBI by address, EL0&1, inner sharable (ignored) 1230 case MISCREG_TLBIMVAAIS: 1231 case MISCREG_TLBIMVAA: 1232 assert32(tc); 1233 target_el = 1; // el 0 and 1 are handled together 1234 scr = readMiscReg(MISCREG_SCR, tc); 1235 secure_lookup = haveSecurity && !scr.ns; 1236 hyp = 0; 1237 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el); 1238 return; 1239 // TLBI by address, EL2, hypervisor mode 1240 case MISCREG_TLBIMVAH: 1241 case MISCREG_TLBIMVAHIS: 1242 assert32(tc); 1243 target_el = 1; // aarch32, use hyp bit 1244 scr = readMiscReg(MISCREG_SCR, tc); 1245 secure_lookup = haveSecurity && !scr.ns; 1246 hyp = 1; 1247 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el); 1248 return; 1249 // TLBI by address and asid, EL0&1, instruction side only 1250 case MISCREG_ITLBIMVA: 1251 assert32(tc); 1252 target_el = 1; // el 0 and 1 are handled together 1253 scr = readMiscReg(MISCREG_SCR, tc); 1254 secure_lookup = haveSecurity && !scr.ns; 1255 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1256 bits(newVal, 7,0), secure_lookup, target_el); 1257 return; 1258 // TLBI by address and asid, EL0&1, data side only 1259 case MISCREG_DTLBIMVA: 1260 assert32(tc); 1261 target_el = 1; // el 0 and 1 are handled together 1262 scr = readMiscReg(MISCREG_SCR, tc); 1263 secure_lookup = haveSecurity && !scr.ns; 1264 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1265 bits(newVal, 7,0), secure_lookup, target_el); 1266 return; 1267 // TLBI by ASID, EL0&1, instrution side only 1268 case MISCREG_ITLBIASID: 1269 assert32(tc); 1270 target_el = 1; // el 0 and 1 are handled together 1271 scr = readMiscReg(MISCREG_SCR, tc); 1272 secure_lookup = haveSecurity && !scr.ns; 1273 tc->getITBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup, 1274 target_el); 1275 return; 1276 // TLBI by ASID EL0&1 data size only 1277 case MISCREG_DTLBIASID: 1278 assert32(tc); 1279 target_el = 1; // el 0 and 1 are handled together 1280 scr = readMiscReg(MISCREG_SCR, tc); 1281 secure_lookup = haveSecurity && !scr.ns; 1282 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup, 1283 target_el); 1284 return; 1285 // Invalidate entire Non-secure Hyp/Non-Hyp Unified TLB 1286 case MISCREG_TLBIALLNSNH: 1287 case MISCREG_TLBIALLNSNHIS: 1288 assert32(tc); 1289 target_el = 1; // el 0 and 1 are handled together 1290 hyp = 0; 1291 tlbiALLN(tc, hyp, target_el); 1292 return; 1293 // TLBI all entries, EL2, hyp, 1294 case MISCREG_TLBIALLH: 1295 case MISCREG_TLBIALLHIS: 1296 assert32(tc); 1297 target_el = 1; // aarch32, use hyp bit 1298 hyp = 1; 1299 tlbiALLN(tc, hyp, target_el); 1300 return; 1301 // AArch64 TLBI: invalidate all entries EL3 1302 case MISCREG_TLBI_ALLE3IS: 1303 case MISCREG_TLBI_ALLE3: 1304 assert64(tc); 1305 target_el = 3; 1306 secure_lookup = true; 1307 tlbiALL(tc, secure_lookup, target_el); 1308 return; 1309 // @todo: uncomment this to enable Virtualization 1310 // case MISCREG_TLBI_ALLE2IS: 1311 // case MISCREG_TLBI_ALLE2: 1312 // TLBI all entries, EL0&1 1313 case MISCREG_TLBI_ALLE1IS: 1314 case MISCREG_TLBI_ALLE1: 1315 // AArch64 TLBI: invalidate all entries, stage 1, current VMID 1316 case MISCREG_TLBI_VMALLE1IS: 1317 case MISCREG_TLBI_VMALLE1: 1318 // AArch64 TLBI: invalidate all entries, stages 1 & 2, current VMID 1319 case MISCREG_TLBI_VMALLS12E1IS: 1320 case MISCREG_TLBI_VMALLS12E1: 1321 // @todo: handle VMID and stage 2 to enable Virtualization 1322 assert64(tc); 1323 target_el = 1; // el 0 and 1 are handled together 1324 scr = readMiscReg(MISCREG_SCR, tc); 1325 secure_lookup = haveSecurity && !scr.ns; 1326 tlbiALL(tc, secure_lookup, target_el); 1327 return; 1328 // AArch64 TLBI: invalidate by VA and ASID, stage 1, current VMID 1329 // VAEx(IS) and VALEx(IS) are the same because TLBs only store entries 1330 // from the last level of translation table walks 1331 // @todo: handle VMID to enable Virtualization 1332 // TLBI all entries, EL0&1 1333 case MISCREG_TLBI_VAE3IS_Xt: 1334 case MISCREG_TLBI_VAE3_Xt: 1335 // TLBI by VA, EL3 regime stage 1, last level walk 1336 case MISCREG_TLBI_VALE3IS_Xt: 1337 case MISCREG_TLBI_VALE3_Xt: 1338 assert64(tc); 1339 target_el = 3; 1340 asid = 0xbeef; // does not matter, tlbi is global 1341 secure_lookup = true; 1342 tlbiVA(tc, newVal, asid, secure_lookup, target_el); 1343 return; 1344 // TLBI by VA, EL2 1345 case MISCREG_TLBI_VAE2IS_Xt: 1346 case MISCREG_TLBI_VAE2_Xt: 1347 // TLBI by VA, EL2, stage1 last level walk 1348 case MISCREG_TLBI_VALE2IS_Xt: 1349 case MISCREG_TLBI_VALE2_Xt: 1350 assert64(tc); 1351 target_el = 2; 1352 asid = 0xbeef; // does not matter, tlbi is global 1353 scr = readMiscReg(MISCREG_SCR, tc); 1354 secure_lookup = haveSecurity && !scr.ns; 1355 tlbiVA(tc, newVal, asid, secure_lookup, target_el); 1356 return; 1357 // TLBI by VA EL1 & 0, stage1, ASID, current VMID 1358 case MISCREG_TLBI_VAE1IS_Xt: 1359 case MISCREG_TLBI_VAE1_Xt: 1360 case MISCREG_TLBI_VALE1IS_Xt: 1361 case MISCREG_TLBI_VALE1_Xt: 1362 assert64(tc); 1363 asid = bits(newVal, 63, 48); 1364 target_el = 1; // el 0 and 1 are handled together 1365 scr = readMiscReg(MISCREG_SCR, tc); 1366 secure_lookup = haveSecurity && !scr.ns; 1367 tlbiVA(tc, newVal, asid, secure_lookup, target_el); 1368 return; 1369 // AArch64 TLBI: invalidate by ASID, stage 1, current VMID 1370 // @todo: handle VMID to enable Virtualization 1371 case MISCREG_TLBI_ASIDE1IS_Xt: 1372 case MISCREG_TLBI_ASIDE1_Xt: 1373 assert64(tc); 1374 target_el = 1; // el 0 and 1 are handled together 1375 scr = readMiscReg(MISCREG_SCR, tc); 1376 secure_lookup = haveSecurity && !scr.ns; 1377 sys = tc->getSystemPtr(); 1378 for (x = 0; x < sys->numContexts(); x++) { 1379 oc = sys->getThreadContext(x); 1380 assert(oc->getITBPtr() && oc->getDTBPtr()); 1381 asid = bits(newVal, 63, 48); 1382 if (!haveLargeAsid64) 1383 asid &= mask(8); 1384 oc->getITBPtr()->flushAsid(asid, secure_lookup, target_el); 1385 oc->getDTBPtr()->flushAsid(asid, secure_lookup, target_el); 1386 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1387 if (checker) { 1388 checker->getITBPtr()->flushAsid(asid, 1389 secure_lookup, target_el); 1390 checker->getDTBPtr()->flushAsid(asid, 1391 secure_lookup, target_el); 1392 } 1393 } 1394 return; 1395 // AArch64 TLBI: invalidate by VA, ASID, stage 1, current VMID 1396 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 1397 // entries from the last level of translation table walks 1398 // @todo: handle VMID to enable Virtualization 1399 case MISCREG_TLBI_VAAE1IS_Xt: 1400 case MISCREG_TLBI_VAAE1_Xt: 1401 case MISCREG_TLBI_VAALE1IS_Xt: 1402 case MISCREG_TLBI_VAALE1_Xt: 1403 assert64(tc); 1404 target_el = 1; // el 0 and 1 are handled together 1405 scr = readMiscReg(MISCREG_SCR, tc); 1406 secure_lookup = haveSecurity && !scr.ns; 1407 sys = tc->getSystemPtr(); 1408 for (x = 0; x < sys->numContexts(); x++) { 1409 // @todo: extra controls on TLBI broadcast? 1410 oc = sys->getThreadContext(x); 1411 assert(oc->getITBPtr() && oc->getDTBPtr()); 1412 Addr va = ((Addr) bits(newVal, 43, 0)) << 12; 1413 oc->getITBPtr()->flushMva(va, 1414 secure_lookup, false, target_el); 1415 oc->getDTBPtr()->flushMva(va, 1416 secure_lookup, false, target_el); 1417 1418 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1419 if (checker) { 1420 checker->getITBPtr()->flushMva(va, 1421 secure_lookup, false, target_el); 1422 checker->getDTBPtr()->flushMva(va, 1423 secure_lookup, false, target_el); 1424 } 1425 } 1426 return; 1427 // AArch64 TLBI: invalidate by IPA, stage 2, current VMID 1428 case MISCREG_TLBI_IPAS2LE1IS_Xt: 1429 case MISCREG_TLBI_IPAS2LE1_Xt: 1430 case MISCREG_TLBI_IPAS2E1IS_Xt: 1431 case MISCREG_TLBI_IPAS2E1_Xt: 1432 assert64(tc); 1433 target_el = 1; // EL 0 and 1 are handled together 1434 scr = readMiscReg(MISCREG_SCR, tc); 1435 secure_lookup = haveSecurity && !scr.ns; 1436 sys = tc->getSystemPtr(); 1437 for (x = 0; x < sys->numContexts(); x++) { 1438 oc = sys->getThreadContext(x); 1439 assert(oc->getITBPtr() && oc->getDTBPtr()); 1440 Addr ipa = ((Addr) bits(newVal, 35, 0)) << 12; 1441 oc->getITBPtr()->flushIpaVmid(ipa, 1442 secure_lookup, false, target_el); 1443 oc->getDTBPtr()->flushIpaVmid(ipa, 1444 secure_lookup, false, target_el); 1445 1446 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1447 if (checker) { 1448 checker->getITBPtr()->flushIpaVmid(ipa, 1449 secure_lookup, false, target_el); 1450 checker->getDTBPtr()->flushIpaVmid(ipa, 1451 secure_lookup, false, target_el); 1452 } 1453 } 1454 return; 1455 case MISCREG_ACTLR: 1456 warn("Not doing anything for write of miscreg ACTLR\n"); 1457 break; 1458 1459 case MISCREG_PMXEVTYPER_PMCCFILTR: 1460 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 1461 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 1462 case MISCREG_PMCR ... MISCREG_PMOVSSET: 1463 pmu->setMiscReg(misc_reg, newVal); 1464 break; 1465 1466 1467 case MISCREG_HSTR: // TJDBX, now redifined to be RES0 1468 { 1469 HSTR hstrMask = 0; 1470 hstrMask.tjdbx = 1; 1471 newVal &= ~((uint32_t) hstrMask); 1472 break; 1473 } 1474 case MISCREG_HCPTR: 1475 { 1476 // If a CP bit in NSACR is 0 then the corresponding bit in 1477 // HCPTR is RAO/WI. Same applies to NSASEDIS 1478 secure_lookup = haveSecurity && 1479 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 1480 readMiscRegNoEffect(MISCREG_CPSR)); 1481 if (!secure_lookup) { 1482 MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 1483 MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 1484 newVal = (newVal & ~mask) | (oldValue & mask); 1485 } 1486 break; 1487 } 1488 case MISCREG_HDFAR: // alias for secure DFAR 1489 misc_reg = MISCREG_DFAR_S; 1490 break; 1491 case MISCREG_HIFAR: // alias for secure IFAR 1492 misc_reg = MISCREG_IFAR_S; 1493 break; 1494 case MISCREG_ATS1CPR: 1495 case MISCREG_ATS1CPW: 1496 case MISCREG_ATS1CUR: 1497 case MISCREG_ATS1CUW: 1498 case MISCREG_ATS12NSOPR: 1499 case MISCREG_ATS12NSOPW: 1500 case MISCREG_ATS12NSOUR: 1501 case MISCREG_ATS12NSOUW: 1502 case MISCREG_ATS1HR: 1503 case MISCREG_ATS1HW: 1504 { 1505 Request::Flags flags = 0; 1506 BaseTLB::Mode mode = BaseTLB::Read; 1507 TLB::ArmTranslationType tranType = TLB::NormalTran; 1508 Fault fault; 1509 switch(misc_reg) { 1510 case MISCREG_ATS1CPR: 1511 flags = TLB::MustBeOne; 1512 tranType = TLB::S1CTran; 1513 mode = BaseTLB::Read; 1514 break; 1515 case MISCREG_ATS1CPW: 1516 flags = TLB::MustBeOne; 1517 tranType = TLB::S1CTran; 1518 mode = BaseTLB::Write; 1519 break; 1520 case MISCREG_ATS1CUR: 1521 flags = TLB::MustBeOne | TLB::UserMode; 1522 tranType = TLB::S1CTran; 1523 mode = BaseTLB::Read; 1524 break; 1525 case MISCREG_ATS1CUW: 1526 flags = TLB::MustBeOne | TLB::UserMode; 1527 tranType = TLB::S1CTran; 1528 mode = BaseTLB::Write; 1529 break; 1530 case MISCREG_ATS12NSOPR: 1531 if (!haveSecurity) 1532 panic("Security Extensions required for ATS12NSOPR"); 1533 flags = TLB::MustBeOne; 1534 tranType = TLB::S1S2NsTran; 1535 mode = BaseTLB::Read; 1536 break; 1537 case MISCREG_ATS12NSOPW: 1538 if (!haveSecurity) 1539 panic("Security Extensions required for ATS12NSOPW"); 1540 flags = TLB::MustBeOne; 1541 tranType = TLB::S1S2NsTran; 1542 mode = BaseTLB::Write; 1543 break; 1544 case MISCREG_ATS12NSOUR: 1545 if (!haveSecurity) 1546 panic("Security Extensions required for ATS12NSOUR"); 1547 flags = TLB::MustBeOne | TLB::UserMode; 1548 tranType = TLB::S1S2NsTran; 1549 mode = BaseTLB::Read; 1550 break; 1551 case MISCREG_ATS12NSOUW: 1552 if (!haveSecurity) 1553 panic("Security Extensions required for ATS12NSOUW"); 1554 flags = TLB::MustBeOne | TLB::UserMode; 1555 tranType = TLB::S1S2NsTran; 1556 mode = BaseTLB::Write; 1557 break; 1558 case MISCREG_ATS1HR: // only really useful from secure mode. 1559 flags = TLB::MustBeOne; 1560 tranType = TLB::HypMode; 1561 mode = BaseTLB::Read; 1562 break; 1563 case MISCREG_ATS1HW: 1564 flags = TLB::MustBeOne; 1565 tranType = TLB::HypMode; 1566 mode = BaseTLB::Write; 1567 break; 1568 } 1569 // If we're in timing mode then doing the translation in 1570 // functional mode then we're slightly distorting performance 1571 // results obtained from simulations. The translation should be 1572 // done in the same mode the core is running in. NOTE: This 1573 // can't be an atomic translation because that causes problems 1574 // with unexpected atomic snoop requests. 1575 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1576 Request req(0, val, 0, flags, Request::funcMasterId, 1577 tc->pcState().pc(), tc->contextId()); 1578 fault = tc->getDTBPtr()->translateFunctional(&req, tc, mode, tranType); 1579 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1580 HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 1581 1582 MiscReg newVal; 1583 if (fault == NoFault) { 1584 Addr paddr = req.getPaddr(); 1585 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 1586 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 1587 newVal = (paddr & mask(39, 12)) | 1588 (tc->getDTBPtr()->getAttr()); 1589 } else { 1590 newVal = (paddr & 0xfffff000) | 1591 (tc->getDTBPtr()->getAttr()); 1592 } 1593 DPRINTF(MiscRegs, 1594 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 1595 val, newVal); 1596 } else { 1597 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 1598 // Set fault bit and FSR 1599 FSR fsr = armFault->getFsr(tc); 1600 1601 newVal = ((fsr >> 9) & 1) << 11; 1602 if (newVal) { 1603 // LPAE - rearange fault status 1604 newVal |= ((fsr >> 0) & 0x3f) << 1; 1605 } else { 1606 // VMSA - rearange fault status 1607 newVal |= ((fsr >> 0) & 0xf) << 1; 1608 newVal |= ((fsr >> 10) & 0x1) << 5; 1609 newVal |= ((fsr >> 12) & 0x1) << 6; 1610 } 1611 newVal |= 0x1; // F bit 1612 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1613 newVal |= armFault->isStage2() ? 0x200 : 0; 1614 DPRINTF(MiscRegs, 1615 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 1616 val, fsr, newVal); 1617 } 1618 setMiscRegNoEffect(MISCREG_PAR, newVal); 1619 return; 1620 } 1621 case MISCREG_TTBCR: 1622 { 1623 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1624 const uint32_t ones = (uint32_t)(-1); 1625 TTBCR ttbcrMask = 0; 1626 TTBCR ttbcrNew = newVal; 1627 1628 // ARM DDI 0406C.b, ARMv7-32 1629 ttbcrMask.n = ones; // T0SZ 1630 if (haveSecurity) { 1631 ttbcrMask.pd0 = ones; 1632 ttbcrMask.pd1 = ones; 1633 } 1634 ttbcrMask.epd0 = ones; 1635 ttbcrMask.irgn0 = ones; 1636 ttbcrMask.orgn0 = ones; 1637 ttbcrMask.sh0 = ones; 1638 ttbcrMask.ps = ones; // T1SZ 1639 ttbcrMask.a1 = ones; 1640 ttbcrMask.epd1 = ones; 1641 ttbcrMask.irgn1 = ones; 1642 ttbcrMask.orgn1 = ones; 1643 ttbcrMask.sh1 = ones; 1644 if (haveLPAE) 1645 ttbcrMask.eae = ones; 1646 1647 if (haveLPAE && ttbcrNew.eae) { 1648 newVal = newVal & ttbcrMask; 1649 } else { 1650 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 1651 } 1652 } 1653 case MISCREG_TTBR0: 1654 case MISCREG_TTBR1: 1655 { 1656 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1657 if (haveLPAE) { 1658 if (ttbcr.eae) { 1659 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 1660 // ARMv8 AArch32 bit 63-56 only 1661 uint64_t ttbrMask = mask(63,56) | mask(47,40); 1662 newVal = (newVal & (~ttbrMask)); 1663 } 1664 } 1665 } 1666 case MISCREG_SCTLR_EL1: 1667 { 1668 tc->getITBPtr()->invalidateMiscReg(); 1669 tc->getDTBPtr()->invalidateMiscReg(); 1670 setMiscRegNoEffect(misc_reg, newVal); 1671 } 1672 case MISCREG_CONTEXTIDR: 1673 case MISCREG_PRRR: 1674 case MISCREG_NMRR: 1675 case MISCREG_MAIR0: 1676 case MISCREG_MAIR1: 1677 case MISCREG_DACR: 1678 case MISCREG_VTTBR: 1679 case MISCREG_SCR_EL3: 1680 case MISCREG_HCR_EL2: 1681 case MISCREG_TCR_EL1: 1682 case MISCREG_TCR_EL2: 1683 case MISCREG_TCR_EL3: 1684 case MISCREG_SCTLR_EL2: 1685 case MISCREG_SCTLR_EL3: 1686 case MISCREG_HSCTLR: 1687 case MISCREG_TTBR0_EL1: 1688 case MISCREG_TTBR1_EL1: 1689 case MISCREG_TTBR0_EL2: 1690 case MISCREG_TTBR0_EL3: 1691 tc->getITBPtr()->invalidateMiscReg(); 1692 tc->getDTBPtr()->invalidateMiscReg(); 1693 break; 1694 case MISCREG_NZCV: 1695 { 1696 CPSR cpsr = val; 1697 1698 tc->setCCReg(CCREG_NZ, cpsr.nz); 1699 tc->setCCReg(CCREG_C, cpsr.c); 1700 tc->setCCReg(CCREG_V, cpsr.v); 1701 } 1702 break; 1703 case MISCREG_DAIF: 1704 { 1705 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1706 cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 1707 newVal = cpsr; 1708 misc_reg = MISCREG_CPSR; 1709 } 1710 break; 1711 case MISCREG_SP_EL0: 1712 tc->setIntReg(INTREG_SP0, newVal); 1713 break; 1714 case MISCREG_SP_EL1: 1715 tc->setIntReg(INTREG_SP1, newVal); 1716 break; 1717 case MISCREG_SP_EL2: 1718 tc->setIntReg(INTREG_SP2, newVal); 1719 break; 1720 case MISCREG_SPSEL: 1721 { 1722 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1723 cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 1724 newVal = cpsr; 1725 misc_reg = MISCREG_CPSR; 1726 } 1727 break; 1728 case MISCREG_CURRENTEL: 1729 { 1730 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1731 cpsr.el = (uint8_t) ((CPSR) newVal).el; 1732 newVal = cpsr; 1733 misc_reg = MISCREG_CPSR; 1734 } 1735 break; 1736 case MISCREG_AT_S1E1R_Xt: 1737 case MISCREG_AT_S1E1W_Xt: 1738 case MISCREG_AT_S1E0R_Xt: 1739 case MISCREG_AT_S1E0W_Xt: 1740 case MISCREG_AT_S1E2R_Xt: 1741 case MISCREG_AT_S1E2W_Xt: 1742 case MISCREG_AT_S12E1R_Xt: 1743 case MISCREG_AT_S12E1W_Xt: 1744 case MISCREG_AT_S12E0R_Xt: 1745 case MISCREG_AT_S12E0W_Xt: 1746 case MISCREG_AT_S1E3R_Xt: 1747 case MISCREG_AT_S1E3W_Xt: 1748 { 1749 RequestPtr req = new Request; 1750 Request::Flags flags = 0; 1751 BaseTLB::Mode mode = BaseTLB::Read; 1752 TLB::ArmTranslationType tranType = TLB::NormalTran; 1753 Fault fault; 1754 switch(misc_reg) { 1755 case MISCREG_AT_S1E1R_Xt: 1756 flags = TLB::MustBeOne; 1757 tranType = TLB::S1E1Tran; 1758 mode = BaseTLB::Read; 1759 break; 1760 case MISCREG_AT_S1E1W_Xt: 1761 flags = TLB::MustBeOne; 1762 tranType = TLB::S1E1Tran; 1763 mode = BaseTLB::Write; 1764 break; 1765 case MISCREG_AT_S1E0R_Xt: 1766 flags = TLB::MustBeOne | TLB::UserMode; 1767 tranType = TLB::S1E0Tran; 1768 mode = BaseTLB::Read; 1769 break; 1770 case MISCREG_AT_S1E0W_Xt: 1771 flags = TLB::MustBeOne | TLB::UserMode; 1772 tranType = TLB::S1E0Tran; 1773 mode = BaseTLB::Write; 1774 break; 1775 case MISCREG_AT_S1E2R_Xt: 1776 flags = TLB::MustBeOne; 1777 tranType = TLB::S1E2Tran; 1778 mode = BaseTLB::Read; 1779 break; 1780 case MISCREG_AT_S1E2W_Xt: 1781 flags = TLB::MustBeOne; 1782 tranType = TLB::S1E2Tran; 1783 mode = BaseTLB::Write; 1784 break; 1785 case MISCREG_AT_S12E0R_Xt: 1786 flags = TLB::MustBeOne | TLB::UserMode; 1787 tranType = TLB::S12E0Tran; 1788 mode = BaseTLB::Read; 1789 break; 1790 case MISCREG_AT_S12E0W_Xt: 1791 flags = TLB::MustBeOne | TLB::UserMode; 1792 tranType = TLB::S12E0Tran; 1793 mode = BaseTLB::Write; 1794 break; 1795 case MISCREG_AT_S12E1R_Xt: 1796 flags = TLB::MustBeOne; 1797 tranType = TLB::S12E1Tran; 1798 mode = BaseTLB::Read; 1799 break; 1800 case MISCREG_AT_S12E1W_Xt: 1801 flags = TLB::MustBeOne; 1802 tranType = TLB::S12E1Tran; 1803 mode = BaseTLB::Write; 1804 break; 1805 case MISCREG_AT_S1E3R_Xt: 1806 flags = TLB::MustBeOne; 1807 tranType = TLB::S1E3Tran; 1808 mode = BaseTLB::Read; 1809 break; 1810 case MISCREG_AT_S1E3W_Xt: 1811 flags = TLB::MustBeOne; 1812 tranType = TLB::S1E3Tran; 1813 mode = BaseTLB::Write; 1814 break; 1815 } 1816 // If we're in timing mode then doing the translation in 1817 // functional mode then we're slightly distorting performance 1818 // results obtained from simulations. The translation should be 1819 // done in the same mode the core is running in. NOTE: This 1820 // can't be an atomic translation because that causes problems 1821 // with unexpected atomic snoop requests. 1822 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1823 req->setVirt(0, val, 0, flags, Request::funcMasterId, 1824 tc->pcState().pc()); 1825 req->setContext(tc->contextId()); 1826 fault = tc->getDTBPtr()->translateFunctional(req, tc, mode, 1827 tranType); 1828 1829 MiscReg newVal; 1830 if (fault == NoFault) { 1831 Addr paddr = req->getPaddr(); 1832 uint64_t attr = tc->getDTBPtr()->getAttr(); 1833 uint64_t attr1 = attr >> 56; 1834 if (!attr1 || attr1 ==0x44) { 1835 attr |= 0x100; 1836 attr &= ~ uint64_t(0x80); 1837 } 1838 newVal = (paddr & mask(47, 12)) | attr; 1839 DPRINTF(MiscRegs, 1840 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 1841 val, newVal); 1842 } else { 1843 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 1844 // Set fault bit and FSR 1845 FSR fsr = armFault->getFsr(tc); 1846 1847 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1848 if (cpsr.width) { // AArch32 1849 newVal = ((fsr >> 9) & 1) << 11; 1850 // rearrange fault status 1851 newVal |= ((fsr >> 0) & 0x3f) << 1; 1852 newVal |= 0x1; // F bit 1853 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1854 newVal |= armFault->isStage2() ? 0x200 : 0; 1855 } else { // AArch64 1856 newVal = 1; // F bit 1857 newVal |= fsr << 1; // FST 1858 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit. 1859 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 1860 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 1861 newVal |= 1 << 11; // RES1 1862 } 1863 DPRINTF(MiscRegs, 1864 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 1865 val, fsr, newVal); 1866 } 1867 delete req; 1868 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 1869 return; 1870 } 1871 case MISCREG_SPSR_EL3: 1872 case MISCREG_SPSR_EL2: 1873 case MISCREG_SPSR_EL1: 1874 // Force bits 23:21 to 0 1875 newVal = val & ~(0x7 << 21); 1876 break; 1877 case MISCREG_L2CTLR: 1878 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 1879 miscRegName[misc_reg], uint32_t(val)); 1880 break; 1881 1882 // Generic Timer registers 1883 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 1884 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 1885 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 1886 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 1887 getGenericTimer(tc).setMiscReg(misc_reg, newVal); 1888 break; 1889 } 1890 } 1891 setMiscRegNoEffect(misc_reg, newVal); 1892} 1893 1894void 1895ISA::tlbiVA(ThreadContext *tc, MiscReg newVal, uint16_t asid, 1896 bool secure_lookup, uint8_t target_el) 1897{ 1898 if (!haveLargeAsid64) 1899 asid &= mask(8); 1900 Addr va = ((Addr) bits(newVal, 43, 0)) << 12; 1901 System *sys = tc->getSystemPtr(); 1902 for (int x = 0; x < sys->numContexts(); x++) { 1903 ThreadContext *oc = sys->getThreadContext(x); 1904 assert(oc->getITBPtr() && oc->getDTBPtr()); 1905 oc->getITBPtr()->flushMvaAsid(va, asid, 1906 secure_lookup, target_el); 1907 oc->getDTBPtr()->flushMvaAsid(va, asid, 1908 secure_lookup, target_el); 1909 1910 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1911 if (checker) { 1912 checker->getITBPtr()->flushMvaAsid( 1913 va, asid, secure_lookup, target_el); 1914 checker->getDTBPtr()->flushMvaAsid( 1915 va, asid, secure_lookup, target_el); 1916 } 1917 } 1918} 1919 1920void 1921ISA::tlbiALL(ThreadContext *tc, bool secure_lookup, uint8_t target_el) 1922{ 1923 System *sys = tc->getSystemPtr(); 1924 for (int x = 0; x < sys->numContexts(); x++) { 1925 ThreadContext *oc = sys->getThreadContext(x); 1926 assert(oc->getITBPtr() && oc->getDTBPtr()); 1927 oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 1928 oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 1929 1930 // If CheckerCPU is connected, need to notify it of a flush 1931 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1932 if (checker) { 1933 checker->getITBPtr()->flushAllSecurity(secure_lookup, 1934 target_el); 1935 checker->getDTBPtr()->flushAllSecurity(secure_lookup, 1936 target_el); 1937 } 1938 } 1939} 1940 1941void 1942ISA::tlbiALLN(ThreadContext *tc, bool hyp, uint8_t target_el) 1943{ 1944 System *sys = tc->getSystemPtr(); 1945 for (int x = 0; x < sys->numContexts(); x++) { 1946 ThreadContext *oc = sys->getThreadContext(x); 1947 assert(oc->getITBPtr() && oc->getDTBPtr()); 1948 oc->getITBPtr()->flushAllNs(hyp, target_el); 1949 oc->getDTBPtr()->flushAllNs(hyp, target_el); 1950 1951 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1952 if (checker) { 1953 checker->getITBPtr()->flushAllNs(hyp, target_el); 1954 checker->getDTBPtr()->flushAllNs(hyp, target_el); 1955 } 1956 } 1957} 1958 1959void 1960ISA::tlbiMVA(ThreadContext *tc, MiscReg newVal, bool secure_lookup, bool hyp, 1961 uint8_t target_el) 1962{ 1963 System *sys = tc->getSystemPtr(); 1964 for (int x = 0; x < sys->numContexts(); x++) { 1965 ThreadContext *oc = sys->getThreadContext(x); 1966 assert(oc->getITBPtr() && oc->getDTBPtr()); 1967 oc->getITBPtr()->flushMva(mbits(newVal, 31,12), 1968 secure_lookup, hyp, target_el); 1969 oc->getDTBPtr()->flushMva(mbits(newVal, 31,12), 1970 secure_lookup, hyp, target_el); 1971 1972 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1973 if (checker) { 1974 checker->getITBPtr()->flushMva(mbits(newVal, 31,12), 1975 secure_lookup, hyp, target_el); 1976 checker->getDTBPtr()->flushMva(mbits(newVal, 31,12), 1977 secure_lookup, hyp, target_el); 1978 } 1979 } 1980} 1981 1982BaseISADevice & 1983ISA::getGenericTimer(ThreadContext *tc) 1984{ 1985 // We only need to create an ISA interface the first time we try 1986 // to access the timer. 1987 if (timer) 1988 return *timer.get(); 1989 1990 assert(system); 1991 GenericTimer *generic_timer(system->getGenericTimer()); 1992 if (!generic_timer) { 1993 panic("Trying to get a generic timer from a system that hasn't " 1994 "been configured to use a generic timer.\n"); 1995 } 1996 1997 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 1998 return *timer.get(); 1999} 2000 2001} 2002 2003ArmISA::ISA * 2004ArmISAParams::create() 2005{ 2006 return new ArmISA::ISA(this); 2007} 2008