isa.cc revision 11773
1/*
2 * Copyright (c) 2010-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 *          Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42#include "arch/arm/pmu.hh"
43#include "arch/arm/system.hh"
44#include "cpu/checker/cpu.hh"
45#include "cpu/base.hh"
46#include "debug/Arm.hh"
47#include "debug/MiscRegs.hh"
48#include "dev/arm/generic_timer.hh"
49#include "params/ArmISA.hh"
50#include "sim/faults.hh"
51#include "sim/stat_control.hh"
52#include "sim/system.hh"
53
54namespace ArmISA
55{
56
57
58/**
59 * Some registers alias with others, and therefore need to be translated.
60 * For each entry:
61 * The first value is the misc register that is to be looked up
62 * the second value is the lower part of the translation
63 * the third the upper part
64 * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543
65 */
66const struct ISA::MiscRegInitializerEntry
67    ISA::MiscRegSwitch[] = {
68    {MISCREG_ACTLR_EL1, {MISCREG_ACTLR_NS, 0}},
69    {MISCREG_AFSR0_EL1, {MISCREG_ADFSR_NS, 0}},
70    {MISCREG_AFSR1_EL1, {MISCREG_AIFSR_NS, 0}},
71    {MISCREG_AMAIR_EL1, {MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS}},
72    {MISCREG_CONTEXTIDR_EL1, {MISCREG_CONTEXTIDR_NS, 0}},
73    {MISCREG_CPACR_EL1, {MISCREG_CPACR, 0}},
74    {MISCREG_CSSELR_EL1, {MISCREG_CSSELR_NS, 0}},
75    {MISCREG_DACR32_EL2, {MISCREG_DACR_NS, 0}},
76    {MISCREG_FAR_EL1, {MISCREG_DFAR_NS, MISCREG_IFAR_NS}},
77    // ESR_EL1 -> DFSR
78    {MISCREG_HACR_EL2, {MISCREG_HACR, 0}},
79    {MISCREG_ACTLR_EL2, {MISCREG_HACTLR, 0}},
80    {MISCREG_AFSR0_EL2, {MISCREG_HADFSR, 0}},
81    {MISCREG_AFSR1_EL2, {MISCREG_HAIFSR, 0}},
82    {MISCREG_AMAIR_EL2, {MISCREG_HAMAIR0, MISCREG_HAMAIR1}},
83    {MISCREG_CPTR_EL2, {MISCREG_HCPTR, 0}},
84    {MISCREG_HCR_EL2, {MISCREG_HCR, 0 /*MISCREG_HCR2*/}},
85    {MISCREG_MDCR_EL2, {MISCREG_HDCR, 0}},
86    {MISCREG_FAR_EL2, {MISCREG_HDFAR, MISCREG_HIFAR}},
87    {MISCREG_MAIR_EL2, {MISCREG_HMAIR0, MISCREG_HMAIR1}},
88    {MISCREG_HPFAR_EL2, {MISCREG_HPFAR, 0}},
89    {MISCREG_SCTLR_EL2, {MISCREG_HSCTLR, 0}},
90    {MISCREG_ESR_EL2, {MISCREG_HSR, 0}},
91    {MISCREG_HSTR_EL2, {MISCREG_HSTR, 0}},
92    {MISCREG_TCR_EL2, {MISCREG_HTCR, 0}},
93    {MISCREG_TPIDR_EL2, {MISCREG_HTPIDR, 0}},
94    {MISCREG_TTBR0_EL2, {MISCREG_HTTBR, 0}},
95    {MISCREG_VBAR_EL2, {MISCREG_HVBAR, 0}},
96    {MISCREG_IFSR32_EL2, {MISCREG_IFSR_NS, 0}},
97    {MISCREG_MAIR_EL1, {MISCREG_PRRR_NS, MISCREG_NMRR_NS}},
98    {MISCREG_PAR_EL1, {MISCREG_PAR_NS, 0}},
99    // RMR_EL1 -> RMR
100    // RMR_EL2 -> HRMR
101    {MISCREG_SCTLR_EL1, {MISCREG_SCTLR_NS, 0}},
102    {MISCREG_SDER32_EL3, {MISCREG_SDER, 0}},
103    {MISCREG_TPIDR_EL1, {MISCREG_TPIDRPRW_NS, 0}},
104    {MISCREG_TPIDRRO_EL0, {MISCREG_TPIDRURO_NS, 0}},
105    {MISCREG_TPIDR_EL0, {MISCREG_TPIDRURW_NS, 0}},
106    {MISCREG_TCR_EL1, {MISCREG_TTBCR_NS, 0}},
107    {MISCREG_TTBR0_EL1, {MISCREG_TTBR0_NS, 0}},
108    {MISCREG_TTBR1_EL1, {MISCREG_TTBR1_NS, 0}},
109    {MISCREG_VBAR_EL1, {MISCREG_VBAR_NS, 0}},
110    {MISCREG_VMPIDR_EL2, {MISCREG_VMPIDR, 0}},
111    {MISCREG_VPIDR_EL2, {MISCREG_VPIDR, 0}},
112    {MISCREG_VTCR_EL2, {MISCREG_VTCR, 0}},
113    {MISCREG_VTTBR_EL2, {MISCREG_VTTBR, 0}},
114    {MISCREG_CNTFRQ_EL0, {MISCREG_CNTFRQ, 0}},
115    {MISCREG_CNTHCTL_EL2, {MISCREG_CNTHCTL, 0}},
116    {MISCREG_CNTHP_CTL_EL2, {MISCREG_CNTHP_CTL, 0}},
117    {MISCREG_CNTHP_CVAL_EL2, {MISCREG_CNTHP_CVAL, 0}}, /* 64b */
118    {MISCREG_CNTHP_TVAL_EL2, {MISCREG_CNTHP_TVAL, 0}},
119    {MISCREG_CNTKCTL_EL1, {MISCREG_CNTKCTL, 0}},
120    {MISCREG_CNTP_CTL_EL0, {MISCREG_CNTP_CTL_NS, 0}},
121    {MISCREG_CNTP_CVAL_EL0, {MISCREG_CNTP_CVAL_NS, 0}}, /* 64b */
122    {MISCREG_CNTP_TVAL_EL0, {MISCREG_CNTP_TVAL_NS, 0}},
123    {MISCREG_CNTPCT_EL0, {MISCREG_CNTPCT, 0}}, /* 64b */
124    {MISCREG_CNTV_CTL_EL0, {MISCREG_CNTV_CTL, 0}},
125    {MISCREG_CNTV_CVAL_EL0, {MISCREG_CNTV_CVAL, 0}}, /* 64b */
126    {MISCREG_CNTV_TVAL_EL0, {MISCREG_CNTV_TVAL, 0}},
127    {MISCREG_CNTVCT_EL0, {MISCREG_CNTVCT, 0}}, /* 64b */
128    {MISCREG_CNTVOFF_EL2, {MISCREG_CNTVOFF, 0}}, /* 64b */
129    {MISCREG_DBGAUTHSTATUS_EL1, {MISCREG_DBGAUTHSTATUS, 0}},
130    {MISCREG_DBGBCR0_EL1, {MISCREG_DBGBCR0, 0}},
131    {MISCREG_DBGBCR1_EL1, {MISCREG_DBGBCR1, 0}},
132    {MISCREG_DBGBCR2_EL1, {MISCREG_DBGBCR2, 0}},
133    {MISCREG_DBGBCR3_EL1, {MISCREG_DBGBCR3, 0}},
134    {MISCREG_DBGBCR4_EL1, {MISCREG_DBGBCR4, 0}},
135    {MISCREG_DBGBCR5_EL1, {MISCREG_DBGBCR5, 0}},
136    {MISCREG_DBGBVR0_EL1, {MISCREG_DBGBVR0, 0 /* MISCREG_DBGBXVR0 */}},
137    {MISCREG_DBGBVR1_EL1, {MISCREG_DBGBVR1, 0 /* MISCREG_DBGBXVR1 */}},
138    {MISCREG_DBGBVR2_EL1, {MISCREG_DBGBVR2, 0 /* MISCREG_DBGBXVR2 */}},
139    {MISCREG_DBGBVR3_EL1, {MISCREG_DBGBVR3, 0 /* MISCREG_DBGBXVR3 */}},
140    {MISCREG_DBGBVR4_EL1, {MISCREG_DBGBVR4, MISCREG_DBGBXVR4}},
141    {MISCREG_DBGBVR5_EL1, {MISCREG_DBGBVR5, MISCREG_DBGBXVR5}},
142    {MISCREG_DBGCLAIMSET_EL1, {MISCREG_DBGCLAIMSET, 0}},
143    {MISCREG_DBGCLAIMCLR_EL1, {MISCREG_DBGCLAIMCLR, 0}},
144    // DBGDTR_EL0 -> DBGDTR{R or T}Xint
145    // DBGDTRRX_EL0 -> DBGDTRRXint
146    // DBGDTRTX_EL0 -> DBGDTRRXint
147    {MISCREG_DBGPRCR_EL1, {MISCREG_DBGPRCR, 0}},
148    {MISCREG_DBGVCR32_EL2, {MISCREG_DBGVCR, 0}},
149    {MISCREG_DBGWCR0_EL1, {MISCREG_DBGWCR0, 0}},
150    {MISCREG_DBGWCR1_EL1, {MISCREG_DBGWCR1, 0}},
151    {MISCREG_DBGWCR2_EL1, {MISCREG_DBGWCR2, 0}},
152    {MISCREG_DBGWCR3_EL1, {MISCREG_DBGWCR3, 0}},
153    {MISCREG_DBGWVR0_EL1, {MISCREG_DBGWVR0, 0}},
154    {MISCREG_DBGWVR1_EL1, {MISCREG_DBGWVR1, 0}},
155    {MISCREG_DBGWVR2_EL1, {MISCREG_DBGWVR2, 0}},
156    {MISCREG_DBGWVR3_EL1, {MISCREG_DBGWVR3, 0}},
157    {MISCREG_ID_DFR0_EL1, {MISCREG_ID_DFR0, 0}},
158    {MISCREG_MDCCSR_EL0, {MISCREG_DBGDSCRint, 0}},
159    {MISCREG_MDRAR_EL1, {MISCREG_DBGDRAR, 0}},
160    {MISCREG_MDSCR_EL1, {MISCREG_DBGDSCRext, 0}},
161    {MISCREG_OSDLR_EL1, {MISCREG_DBGOSDLR, 0}},
162    {MISCREG_OSDTRRX_EL1, {MISCREG_DBGDTRRXext, 0}},
163    {MISCREG_OSDTRTX_EL1, {MISCREG_DBGDTRTXext, 0}},
164    {MISCREG_OSECCR_EL1, {MISCREG_DBGOSECCR, 0}},
165    {MISCREG_OSLAR_EL1, {MISCREG_DBGOSLAR, 0}},
166    {MISCREG_OSLSR_EL1, {MISCREG_DBGOSLSR, 0}},
167    {MISCREG_PMCCNTR_EL0, {MISCREG_PMCCNTR, 0}},
168    {MISCREG_PMCEID0_EL0, {MISCREG_PMCEID0, 0}},
169    {MISCREG_PMCEID1_EL0, {MISCREG_PMCEID1, 0}},
170    {MISCREG_PMCNTENSET_EL0, {MISCREG_PMCNTENSET, 0}},
171    {MISCREG_PMCNTENCLR_EL0, {MISCREG_PMCNTENCLR, 0}},
172    {MISCREG_PMCR_EL0, {MISCREG_PMCR, 0}},
173/*  {MISCREG_PMEVCNTR0_EL0, {MISCREG_PMEVCNTR0, 0}},
174    {MISCREG_PMEVCNTR1_EL0, {MISCREG_PMEVCNTR1, 0}},
175    {MISCREG_PMEVCNTR2_EL0, {MISCREG_PMEVCNTR2, 0}},
176    {MISCREG_PMEVCNTR3_EL0, {MISCREG_PMEVCNTR3, 0}},
177    {MISCREG_PMEVCNTR4_EL0, {MISCREG_PMEVCNTR4, 0}},
178    {MISCREG_PMEVCNTR5_EL0, {MISCREG_PMEVCNTR5, 0}},
179    {MISCREG_PMEVTYPER0_EL0, {MISCREG_PMEVTYPER0, 0}},
180    {MISCREG_PMEVTYPER1_EL0, {MISCREG_PMEVTYPER1, 0}},
181    {MISCREG_PMEVTYPER2_EL0, {MISCREG_PMEVTYPER2, 0}},
182    {MISCREG_PMEVTYPER3_EL0, {MISCREG_PMEVTYPER3, 0}},
183    {MISCREG_PMEVTYPER4_EL0, {MISCREG_PMEVTYPER4, 0}},
184    {MISCREG_PMEVTYPER5_EL0, {MISCREG_PMEVTYPER5, 0}}, */
185    {MISCREG_PMINTENCLR_EL1, {MISCREG_PMINTENCLR, 0}},
186    {MISCREG_PMINTENSET_EL1, {MISCREG_PMINTENSET, 0}},
187//  {MISCREG_PMOVSCLR_EL0, {MISCREG_PMOVSCLR, 0}},
188    {MISCREG_PMOVSSET_EL0, {MISCREG_PMOVSSET, 0}},
189    {MISCREG_PMSELR_EL0, {MISCREG_PMSELR, 0}},
190    {MISCREG_PMSWINC_EL0, {MISCREG_PMSWINC, 0}},
191    {MISCREG_PMUSERENR_EL0, {MISCREG_PMUSERENR, 0}},
192    {MISCREG_PMXEVCNTR_EL0, {MISCREG_PMXEVCNTR, 0}},
193    {MISCREG_PMXEVTYPER_EL0, {MISCREG_PMXEVTYPER, 0}},
194
195    // from ARM DDI 0487A.i, template text
196    // "AArch64 System register ___ can be mapped to
197    //  AArch32 System register ___, but this is not
198    //  architecturally mandated."
199    {MISCREG_SCR_EL3, {MISCREG_SCR, 0}}, // D7-2005
200    // MDCR_EL3 -> SDCR, D7-2108 (the latter is unimpl. in gem5)
201    {MISCREG_SPSR_EL1, {MISCREG_SPSR_SVC, 0}}, // C5.2.17 SPSR_EL1
202    {MISCREG_SPSR_EL2, {MISCREG_SPSR_HYP, 0}}, // C5.2.18 SPSR_EL2
203    {MISCREG_SPSR_EL3, {MISCREG_SPSR_MON, 0}}, // C5.2.19 SPSR_EL3
204};
205
206
207ISA::ISA(Params *p)
208    : SimObject(p),
209      system(NULL),
210      _decoderFlavour(p->decoderFlavour),
211      pmu(p->pmu),
212      lookUpMiscReg(NUM_MISCREGS, {0,0})
213{
214    miscRegs[MISCREG_SCTLR_RST] = 0;
215
216    // Hook up a dummy device if we haven't been configured with a
217    // real PMU. By using a dummy device, we don't need to check that
218    // the PMU exist every time we try to access a PMU register.
219    if (!pmu)
220        pmu = &dummyDevice;
221
222    // Give all ISA devices a pointer to this ISA
223    pmu->setISA(this);
224
225    system = dynamic_cast<ArmSystem *>(p->system);
226
227    // Cache system-level properties
228    if (FullSystem && system) {
229        highestELIs64 = system->highestELIs64();
230        haveSecurity = system->haveSecurity();
231        haveLPAE = system->haveLPAE();
232        haveVirtualization = system->haveVirtualization();
233        haveLargeAsid64 = system->haveLargeAsid64();
234        physAddrRange64 = system->physAddrRange64();
235    } else {
236        highestELIs64 = true; // ArmSystem::highestELIs64 does the same
237        haveSecurity = haveLPAE = haveVirtualization = false;
238        haveLargeAsid64 = false;
239        physAddrRange64 = 32;  // dummy value
240    }
241
242    /** Fill in the miscReg translation table */
243    for (auto sw : MiscRegSwitch) {
244        lookUpMiscReg[sw.index] = sw.entry;
245    }
246
247    preUnflattenMiscReg();
248
249    clear();
250}
251
252const ArmISAParams *
253ISA::params() const
254{
255    return dynamic_cast<const Params *>(_params);
256}
257
258void
259ISA::clear()
260{
261    const Params *p(params());
262
263    SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
264    memset(miscRegs, 0, sizeof(miscRegs));
265
266    // Initialize configurable default values
267    miscRegs[MISCREG_MIDR] = p->midr;
268    miscRegs[MISCREG_MIDR_EL1] = p->midr;
269    miscRegs[MISCREG_VPIDR] = p->midr;
270
271    if (FullSystem && system->highestELIs64()) {
272        // Initialize AArch64 state
273        clear64(p);
274        return;
275    }
276
277    // Initialize AArch32 state...
278
279    CPSR cpsr = 0;
280    cpsr.mode = MODE_USER;
281    miscRegs[MISCREG_CPSR] = cpsr;
282    updateRegMap(cpsr);
283
284    SCTLR sctlr = 0;
285    sctlr.te = (bool) sctlr_rst.te;
286    sctlr.nmfi = (bool) sctlr_rst.nmfi;
287    sctlr.v = (bool) sctlr_rst.v;
288    sctlr.u = 1;
289    sctlr.xp = 1;
290    sctlr.rao2 = 1;
291    sctlr.rao3 = 1;
292    sctlr.rao4 = 0xf;  // SCTLR[6:3]
293    sctlr.uci = 1;
294    sctlr.dze = 1;
295    miscRegs[MISCREG_SCTLR_NS] = sctlr;
296    miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
297    miscRegs[MISCREG_HCPTR] = 0;
298
299    // Start with an event in the mailbox
300    miscRegs[MISCREG_SEV_MAILBOX] = 1;
301
302    // Separate Instruction and Data TLBs
303    miscRegs[MISCREG_TLBTR] = 1;
304
305    MVFR0 mvfr0 = 0;
306    mvfr0.advSimdRegisters = 2;
307    mvfr0.singlePrecision = 2;
308    mvfr0.doublePrecision = 2;
309    mvfr0.vfpExceptionTrapping = 0;
310    mvfr0.divide = 1;
311    mvfr0.squareRoot = 1;
312    mvfr0.shortVectors = 1;
313    mvfr0.roundingModes = 1;
314    miscRegs[MISCREG_MVFR0] = mvfr0;
315
316    MVFR1 mvfr1 = 0;
317    mvfr1.flushToZero = 1;
318    mvfr1.defaultNaN = 1;
319    mvfr1.advSimdLoadStore = 1;
320    mvfr1.advSimdInteger = 1;
321    mvfr1.advSimdSinglePrecision = 1;
322    mvfr1.advSimdHalfPrecision = 1;
323    mvfr1.vfpHalfPrecision = 1;
324    miscRegs[MISCREG_MVFR1] = mvfr1;
325
326    // Reset values of PRRR and NMRR are implementation dependent
327
328    // @todo: PRRR and NMRR in secure state?
329    miscRegs[MISCREG_PRRR_NS] =
330        (1 << 19) | // 19
331        (0 << 18) | // 18
332        (0 << 17) | // 17
333        (1 << 16) | // 16
334        (2 << 14) | // 15:14
335        (0 << 12) | // 13:12
336        (2 << 10) | // 11:10
337        (2 << 8)  | // 9:8
338        (2 << 6)  | // 7:6
339        (2 << 4)  | // 5:4
340        (1 << 2)  | // 3:2
341        0;          // 1:0
342    miscRegs[MISCREG_NMRR_NS] =
343        (1 << 30) | // 31:30
344        (0 << 26) | // 27:26
345        (0 << 24) | // 25:24
346        (3 << 22) | // 23:22
347        (2 << 20) | // 21:20
348        (0 << 18) | // 19:18
349        (0 << 16) | // 17:16
350        (1 << 14) | // 15:14
351        (0 << 12) | // 13:12
352        (2 << 10) | // 11:10
353        (0 << 8)  | // 9:8
354        (3 << 6)  | // 7:6
355        (2 << 4)  | // 5:4
356        (0 << 2)  | // 3:2
357        0;          // 1:0
358
359    miscRegs[MISCREG_CPACR] = 0;
360
361    miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
362    miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
363    miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
364    miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
365
366    miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
367    miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
368    miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
369    miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
370    miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
371    miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
372
373    miscRegs[MISCREG_FPSID] = p->fpsid;
374
375    if (haveLPAE) {
376        TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS];
377        ttbcr.eae = 0;
378        miscRegs[MISCREG_TTBCR_NS] = ttbcr;
379        // Enforce consistency with system-level settings
380        miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5;
381    }
382
383    if (haveSecurity) {
384        miscRegs[MISCREG_SCTLR_S] = sctlr;
385        miscRegs[MISCREG_SCR] = 0;
386        miscRegs[MISCREG_VBAR_S] = 0;
387    } else {
388        // we're always non-secure
389        miscRegs[MISCREG_SCR] = 1;
390    }
391
392    //XXX We need to initialize the rest of the state.
393}
394
395void
396ISA::clear64(const ArmISAParams *p)
397{
398    CPSR cpsr = 0;
399    Addr rvbar = system->resetAddr64();
400    switch (system->highestEL()) {
401        // Set initial EL to highest implemented EL using associated stack
402        // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
403        // value
404      case EL3:
405        cpsr.mode = MODE_EL3H;
406        miscRegs[MISCREG_RVBAR_EL3] = rvbar;
407        break;
408      case EL2:
409        cpsr.mode = MODE_EL2H;
410        miscRegs[MISCREG_RVBAR_EL2] = rvbar;
411        break;
412      case EL1:
413        cpsr.mode = MODE_EL1H;
414        miscRegs[MISCREG_RVBAR_EL1] = rvbar;
415        break;
416      default:
417        panic("Invalid highest implemented exception level");
418        break;
419    }
420
421    // Initialize rest of CPSR
422    cpsr.daif = 0xf;  // Mask all interrupts
423    cpsr.ss = 0;
424    cpsr.il = 0;
425    miscRegs[MISCREG_CPSR] = cpsr;
426    updateRegMap(cpsr);
427
428    // Initialize other control registers
429    miscRegs[MISCREG_MPIDR_EL1] = 0x80000000;
430    if (haveSecurity) {
431        miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830;
432        miscRegs[MISCREG_SCR_EL3]   = 0x00000030;  // RES1 fields
433    } else if (haveVirtualization) {
434        // also  MISCREG_SCTLR_EL2 (by mapping)
435        miscRegs[MISCREG_HSCTLR] = 0x30c50830;
436    } else {
437        // also  MISCREG_SCTLR_EL1 (by mapping)
438        miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init
439        // Always non-secure
440        miscRegs[MISCREG_SCR_EL3] = 1;
441    }
442
443    // Initialize configurable id registers
444    miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1;
445    miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1;
446    miscRegs[MISCREG_ID_AA64DFR0_EL1] =
447        (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) |
448        (p->pmu ?             0x0000000000000100ULL : 0); // Enable PMUv3
449
450    miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1;
451    miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1;
452    miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1;
453    miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1;
454    miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1;
455
456    miscRegs[MISCREG_ID_DFR0_EL1] =
457        (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3
458
459    miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1];
460
461    // Enforce consistency with system-level settings...
462
463    // EL3
464    miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
465        miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12,
466        haveSecurity ? 0x2 : 0x0);
467    // EL2
468    miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
469        miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8,
470        haveVirtualization ? 0x2 : 0x0);
471    // Large ASID support
472    miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
473        miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4,
474        haveLargeAsid64 ? 0x2 : 0x0);
475    // Physical address size
476    miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
477        miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0,
478        encodePhysAddrRange64(physAddrRange64));
479}
480
481MiscReg
482ISA::readMiscRegNoEffect(int misc_reg) const
483{
484    assert(misc_reg < NumMiscRegs);
485
486    auto regs = getMiscIndices(misc_reg);
487    int lower = regs.first, upper = regs.second;
488    return !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32))
489                                      |(miscRegs[upper] << 32));
490}
491
492
493MiscReg
494ISA::readMiscReg(int misc_reg, ThreadContext *tc)
495{
496    CPSR cpsr = 0;
497    PCState pc = 0;
498    SCR scr = 0;
499
500    if (misc_reg == MISCREG_CPSR) {
501        cpsr = miscRegs[misc_reg];
502        pc = tc->pcState();
503        cpsr.j = pc.jazelle() ? 1 : 0;
504        cpsr.t = pc.thumb() ? 1 : 0;
505        return cpsr;
506    }
507
508#ifndef NDEBUG
509    if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
510        if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
511            warn("Unimplemented system register %s read.\n",
512                 miscRegName[misc_reg]);
513        else
514            panic("Unimplemented system register %s read.\n",
515                  miscRegName[misc_reg]);
516    }
517#endif
518
519    switch (unflattenMiscReg(misc_reg)) {
520      case MISCREG_HCR:
521        {
522            if (!haveVirtualization)
523                return 0;
524            else
525                return readMiscRegNoEffect(MISCREG_HCR);
526        }
527      case MISCREG_CPACR:
528        {
529            const uint32_t ones = (uint32_t)(-1);
530            CPACR cpacrMask = 0;
531            // Only cp10, cp11, and ase are implemented, nothing else should
532            // be readable? (straight copy from the write code)
533            cpacrMask.cp10 = ones;
534            cpacrMask.cp11 = ones;
535            cpacrMask.asedis = ones;
536
537            // Security Extensions may limit the readability of CPACR
538            if (haveSecurity) {
539                scr = readMiscRegNoEffect(MISCREG_SCR);
540                cpsr = readMiscRegNoEffect(MISCREG_CPSR);
541                if (scr.ns && (cpsr.mode != MODE_MON)) {
542                    NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
543                    // NB: Skipping the full loop, here
544                    if (!nsacr.cp10) cpacrMask.cp10 = 0;
545                    if (!nsacr.cp11) cpacrMask.cp11 = 0;
546                }
547            }
548            MiscReg val = readMiscRegNoEffect(MISCREG_CPACR);
549            val &= cpacrMask;
550            DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n",
551                    miscRegName[misc_reg], val);
552            return val;
553        }
554      case MISCREG_MPIDR:
555        cpsr = readMiscRegNoEffect(MISCREG_CPSR);
556        scr  = readMiscRegNoEffect(MISCREG_SCR);
557        if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) {
558            return getMPIDR(system, tc);
559        } else {
560            return readMiscReg(MISCREG_VMPIDR, tc);
561        }
562            break;
563      case MISCREG_MPIDR_EL1:
564        // @todo in the absence of v8 virtualization support just return MPIDR_EL1
565        return getMPIDR(system, tc) & 0xffffffff;
566      case MISCREG_VMPIDR:
567        // top bit defined as RES1
568        return readMiscRegNoEffect(misc_reg) | 0x80000000;
569      case MISCREG_ID_AFR0: // not implemented, so alias MIDR
570      case MISCREG_REVIDR:  // not implemented, so alias MIDR
571      case MISCREG_MIDR:
572        cpsr = readMiscRegNoEffect(MISCREG_CPSR);
573        scr  = readMiscRegNoEffect(MISCREG_SCR);
574        if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) {
575            return readMiscRegNoEffect(misc_reg);
576        } else {
577            return readMiscRegNoEffect(MISCREG_VPIDR);
578        }
579        break;
580      case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI
581      case MISCREG_JMCR:  // Jazelle trivial implementation, RAZ/WI
582      case MISCREG_JIDR:  // Jazelle trivial implementation, RAZ/WI
583      case MISCREG_AIDR:  // AUX ID set to 0
584      case MISCREG_TCMTR: // No TCM's
585        return 0;
586
587      case MISCREG_CLIDR:
588        warn_once("The clidr register always reports 0 caches.\n");
589        warn_once("clidr LoUIS field of 0b001 to match current "
590                  "ARM implementations.\n");
591        return 0x00200000;
592      case MISCREG_CCSIDR:
593        warn_once("The ccsidr register isn't implemented and "
594                "always reads as 0.\n");
595        break;
596      case MISCREG_CTR:
597        {
598            //all caches have the same line size in gem5
599            //4 byte words in ARM
600            unsigned lineSizeWords =
601                tc->getSystemPtr()->cacheLineSize() / 4;
602            unsigned log2LineSizeWords = 0;
603
604            while (lineSizeWords >>= 1) {
605                ++log2LineSizeWords;
606            }
607
608            CTR ctr = 0;
609            //log2 of minimun i-cache line size (words)
610            ctr.iCacheLineSize = log2LineSizeWords;
611            //b11 - gem5 uses pipt
612            ctr.l1IndexPolicy = 0x3;
613            //log2 of minimum d-cache line size (words)
614            ctr.dCacheLineSize = log2LineSizeWords;
615            //log2 of max reservation size (words)
616            ctr.erg = log2LineSizeWords;
617            //log2 of max writeback size (words)
618            ctr.cwg = log2LineSizeWords;
619            //b100 - gem5 format is ARMv7
620            ctr.format = 0x4;
621
622            return ctr;
623        }
624      case MISCREG_ACTLR:
625        warn("Not doing anything for miscreg ACTLR\n");
626        break;
627
628      case MISCREG_PMXEVTYPER_PMCCFILTR:
629      case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
630      case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
631      case MISCREG_PMCR ... MISCREG_PMOVSSET:
632        return pmu->readMiscReg(misc_reg);
633
634      case MISCREG_CPSR_Q:
635        panic("shouldn't be reading this register seperately\n");
636      case MISCREG_FPSCR_QC:
637        return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
638      case MISCREG_FPSCR_EXC:
639        return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
640      case MISCREG_FPSR:
641        {
642            const uint32_t ones = (uint32_t)(-1);
643            FPSCR fpscrMask = 0;
644            fpscrMask.ioc = ones;
645            fpscrMask.dzc = ones;
646            fpscrMask.ofc = ones;
647            fpscrMask.ufc = ones;
648            fpscrMask.ixc = ones;
649            fpscrMask.idc = ones;
650            fpscrMask.qc = ones;
651            fpscrMask.v = ones;
652            fpscrMask.c = ones;
653            fpscrMask.z = ones;
654            fpscrMask.n = ones;
655            return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
656        }
657      case MISCREG_FPCR:
658        {
659            const uint32_t ones = (uint32_t)(-1);
660            FPSCR fpscrMask  = 0;
661            fpscrMask.ioe = ones;
662            fpscrMask.dze = ones;
663            fpscrMask.ofe = ones;
664            fpscrMask.ufe = ones;
665            fpscrMask.ixe = ones;
666            fpscrMask.ide = ones;
667            fpscrMask.len    = ones;
668            fpscrMask.stride = ones;
669            fpscrMask.rMode  = ones;
670            fpscrMask.fz     = ones;
671            fpscrMask.dn     = ones;
672            fpscrMask.ahp    = ones;
673            return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
674        }
675      case MISCREG_NZCV:
676        {
677            CPSR cpsr = 0;
678            cpsr.nz   = tc->readCCReg(CCREG_NZ);
679            cpsr.c    = tc->readCCReg(CCREG_C);
680            cpsr.v    = tc->readCCReg(CCREG_V);
681            return cpsr;
682        }
683      case MISCREG_DAIF:
684        {
685            CPSR cpsr = 0;
686            cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif;
687            return cpsr;
688        }
689      case MISCREG_SP_EL0:
690        {
691            return tc->readIntReg(INTREG_SP0);
692        }
693      case MISCREG_SP_EL1:
694        {
695            return tc->readIntReg(INTREG_SP1);
696        }
697      case MISCREG_SP_EL2:
698        {
699            return tc->readIntReg(INTREG_SP2);
700        }
701      case MISCREG_SPSEL:
702        {
703            return miscRegs[MISCREG_CPSR] & 0x1;
704        }
705      case MISCREG_CURRENTEL:
706        {
707            return miscRegs[MISCREG_CPSR] & 0xc;
708        }
709      case MISCREG_L2CTLR:
710        {
711            // mostly unimplemented, just set NumCPUs field from sim and return
712            L2CTLR l2ctlr = 0;
713            // b00:1CPU to b11:4CPUs
714            l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1;
715            return l2ctlr;
716        }
717      case MISCREG_DBGDIDR:
718        /* For now just implement the version number.
719         * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
720         */
721        return 0x5 << 16;
722      case MISCREG_DBGDSCRint:
723        return 0;
724      case MISCREG_ISR:
725        return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR(
726            readMiscRegNoEffect(MISCREG_HCR),
727            readMiscRegNoEffect(MISCREG_CPSR),
728            readMiscRegNoEffect(MISCREG_SCR));
729      case MISCREG_ISR_EL1:
730        return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR(
731            readMiscRegNoEffect(MISCREG_HCR_EL2),
732            readMiscRegNoEffect(MISCREG_CPSR),
733            readMiscRegNoEffect(MISCREG_SCR_EL3));
734      case MISCREG_DCZID_EL0:
735        return 0x04;  // DC ZVA clear 64-byte chunks
736      case MISCREG_HCPTR:
737        {
738            MiscReg val = readMiscRegNoEffect(misc_reg);
739            // The trap bit associated with CP14 is defined as RAZ
740            val &= ~(1 << 14);
741            // If a CP bit in NSACR is 0 then the corresponding bit in
742            // HCPTR is RAO/WI
743            bool secure_lookup = haveSecurity &&
744                inSecureState(readMiscRegNoEffect(MISCREG_SCR),
745                              readMiscRegNoEffect(MISCREG_CPSR));
746            if (!secure_lookup) {
747                MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR);
748                val |= (mask ^ 0x7FFF) & 0xBFFF;
749            }
750            // Set the bits for unimplemented coprocessors to RAO/WI
751            val |= 0x33FF;
752            return (val);
753        }
754      case MISCREG_HDFAR: // alias for secure DFAR
755        return readMiscRegNoEffect(MISCREG_DFAR_S);
756      case MISCREG_HIFAR: // alias for secure IFAR
757        return readMiscRegNoEffect(MISCREG_IFAR_S);
758      case MISCREG_HVBAR: // bottom bits reserved
759        return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0;
760      case MISCREG_SCTLR:
761        return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818;
762      case MISCREG_SCTLR_EL1:
763        return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800;
764      case MISCREG_SCTLR_EL2:
765      case MISCREG_SCTLR_EL3:
766      case MISCREG_HSCTLR:
767        return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830;
768
769      case MISCREG_ID_PFR0:
770        // !ThumbEE | !Jazelle | Thumb | ARM
771        return 0x00000031;
772      case MISCREG_ID_PFR1:
773        // !Timer | Virti | !M Profile | TrustZone | ARMv4
774        return 0x00000001
775             | (haveSecurity       ? 0x00000010 : 0x0)
776             | (haveVirtualization ? 0x00001000 : 0x0);
777      case MISCREG_ID_AA64PFR0_EL1:
778        return 0x0000000000000002   // AArch{64,32} supported at EL0
779             | 0x0000000000000020                             // EL1
780             | (haveVirtualization ? 0x0000000000000200 : 0)  // EL2
781             | (haveSecurity       ? 0x0000000000002000 : 0); // EL3
782      case MISCREG_ID_AA64PFR1_EL1:
783        return 0; // bits [63:0] RES0 (reserved for future use)
784
785      // Generic Timer registers
786      case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
787      case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
788      case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:
789      case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1:
790        return getGenericTimer(tc).readMiscReg(misc_reg);
791
792      default:
793        break;
794
795    }
796    return readMiscRegNoEffect(misc_reg);
797}
798
799void
800ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
801{
802    assert(misc_reg < NumMiscRegs);
803
804    auto regs = getMiscIndices(misc_reg);
805    int lower = regs.first, upper = regs.second;
806    if (upper > 0) {
807        miscRegs[lower] = bits(val, 31, 0);
808        miscRegs[upper] = bits(val, 63, 32);
809        DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n",
810                misc_reg, lower, upper, val);
811    } else {
812        miscRegs[lower] = val;
813        DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n",
814                misc_reg, lower, val);
815    }
816}
817
818void
819ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
820{
821
822    MiscReg newVal = val;
823    int x;
824    bool secure_lookup;
825    bool hyp;
826    System *sys;
827    ThreadContext *oc;
828    uint8_t target_el;
829    uint16_t asid;
830    SCR scr;
831
832    if (misc_reg == MISCREG_CPSR) {
833        updateRegMap(val);
834
835
836        CPSR old_cpsr = miscRegs[MISCREG_CPSR];
837        int old_mode = old_cpsr.mode;
838        CPSR cpsr = val;
839        if (old_mode != cpsr.mode) {
840            tc->getITBPtr()->invalidateMiscReg();
841            tc->getDTBPtr()->invalidateMiscReg();
842        }
843
844        DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
845                miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
846        PCState pc = tc->pcState();
847        pc.nextThumb(cpsr.t);
848        pc.nextJazelle(cpsr.j);
849
850        // Follow slightly different semantics if a CheckerCPU object
851        // is connected
852        CheckerCPU *checker = tc->getCheckerCpuPtr();
853        if (checker) {
854            tc->pcStateNoRecord(pc);
855        } else {
856            tc->pcState(pc);
857        }
858    } else {
859#ifndef NDEBUG
860        if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
861            if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
862                warn("Unimplemented system register %s write with %#x.\n",
863                    miscRegName[misc_reg], val);
864            else
865                panic("Unimplemented system register %s write with %#x.\n",
866                    miscRegName[misc_reg], val);
867        }
868#endif
869        switch (unflattenMiscReg(misc_reg)) {
870          case MISCREG_CPACR:
871            {
872
873                const uint32_t ones = (uint32_t)(-1);
874                CPACR cpacrMask = 0;
875                // Only cp10, cp11, and ase are implemented, nothing else should
876                // be writable
877                cpacrMask.cp10 = ones;
878                cpacrMask.cp11 = ones;
879                cpacrMask.asedis = ones;
880
881                // Security Extensions may limit the writability of CPACR
882                if (haveSecurity) {
883                    scr = readMiscRegNoEffect(MISCREG_SCR);
884                    CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR);
885                    if (scr.ns && (cpsr.mode != MODE_MON)) {
886                        NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
887                        // NB: Skipping the full loop, here
888                        if (!nsacr.cp10) cpacrMask.cp10 = 0;
889                        if (!nsacr.cp11) cpacrMask.cp11 = 0;
890                    }
891                }
892
893                MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR);
894                newVal &= cpacrMask;
895                newVal |= old_val & ~cpacrMask;
896                DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
897                        miscRegName[misc_reg], newVal);
898            }
899            break;
900          case MISCREG_CPACR_EL1:
901            {
902                const uint32_t ones = (uint32_t)(-1);
903                CPACR cpacrMask = 0;
904                cpacrMask.tta = ones;
905                cpacrMask.fpen = ones;
906                newVal &= cpacrMask;
907                DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
908                        miscRegName[misc_reg], newVal);
909            }
910            break;
911          case MISCREG_CPTR_EL2:
912            {
913                const uint32_t ones = (uint32_t)(-1);
914                CPTR cptrMask = 0;
915                cptrMask.tcpac = ones;
916                cptrMask.tta = ones;
917                cptrMask.tfp = ones;
918                newVal &= cptrMask;
919                cptrMask = 0;
920                cptrMask.res1_13_12_el2 = ones;
921                cptrMask.res1_9_0_el2 = ones;
922                newVal |= cptrMask;
923                DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
924                        miscRegName[misc_reg], newVal);
925            }
926            break;
927          case MISCREG_CPTR_EL3:
928            {
929                const uint32_t ones = (uint32_t)(-1);
930                CPTR cptrMask = 0;
931                cptrMask.tcpac = ones;
932                cptrMask.tta = ones;
933                cptrMask.tfp = ones;
934                newVal &= cptrMask;
935                DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
936                        miscRegName[misc_reg], newVal);
937            }
938            break;
939          case MISCREG_CSSELR:
940            warn_once("The csselr register isn't implemented.\n");
941            return;
942
943          case MISCREG_DC_ZVA_Xt:
944            warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n");
945            return;
946
947          case MISCREG_FPSCR:
948            {
949                const uint32_t ones = (uint32_t)(-1);
950                FPSCR fpscrMask = 0;
951                fpscrMask.ioc = ones;
952                fpscrMask.dzc = ones;
953                fpscrMask.ofc = ones;
954                fpscrMask.ufc = ones;
955                fpscrMask.ixc = ones;
956                fpscrMask.idc = ones;
957                fpscrMask.ioe = ones;
958                fpscrMask.dze = ones;
959                fpscrMask.ofe = ones;
960                fpscrMask.ufe = ones;
961                fpscrMask.ixe = ones;
962                fpscrMask.ide = ones;
963                fpscrMask.len = ones;
964                fpscrMask.stride = ones;
965                fpscrMask.rMode = ones;
966                fpscrMask.fz = ones;
967                fpscrMask.dn = ones;
968                fpscrMask.ahp = ones;
969                fpscrMask.qc = ones;
970                fpscrMask.v = ones;
971                fpscrMask.c = ones;
972                fpscrMask.z = ones;
973                fpscrMask.n = ones;
974                newVal = (newVal & (uint32_t)fpscrMask) |
975                         (readMiscRegNoEffect(MISCREG_FPSCR) &
976                          ~(uint32_t)fpscrMask);
977                tc->getDecoderPtr()->setContext(newVal);
978            }
979            break;
980          case MISCREG_FPSR:
981            {
982                const uint32_t ones = (uint32_t)(-1);
983                FPSCR fpscrMask = 0;
984                fpscrMask.ioc = ones;
985                fpscrMask.dzc = ones;
986                fpscrMask.ofc = ones;
987                fpscrMask.ufc = ones;
988                fpscrMask.ixc = ones;
989                fpscrMask.idc = ones;
990                fpscrMask.qc = ones;
991                fpscrMask.v = ones;
992                fpscrMask.c = ones;
993                fpscrMask.z = ones;
994                fpscrMask.n = ones;
995                newVal = (newVal & (uint32_t)fpscrMask) |
996                         (readMiscRegNoEffect(MISCREG_FPSCR) &
997                          ~(uint32_t)fpscrMask);
998                misc_reg = MISCREG_FPSCR;
999            }
1000            break;
1001          case MISCREG_FPCR:
1002            {
1003                const uint32_t ones = (uint32_t)(-1);
1004                FPSCR fpscrMask  = 0;
1005                fpscrMask.ioe = ones;
1006                fpscrMask.dze = ones;
1007                fpscrMask.ofe = ones;
1008                fpscrMask.ufe = ones;
1009                fpscrMask.ixe = ones;
1010                fpscrMask.ide = ones;
1011                fpscrMask.len    = ones;
1012                fpscrMask.stride = ones;
1013                fpscrMask.rMode  = ones;
1014                fpscrMask.fz     = ones;
1015                fpscrMask.dn     = ones;
1016                fpscrMask.ahp    = ones;
1017                newVal = (newVal & (uint32_t)fpscrMask) |
1018                         (readMiscRegNoEffect(MISCREG_FPSCR) &
1019                          ~(uint32_t)fpscrMask);
1020                misc_reg = MISCREG_FPSCR;
1021            }
1022            break;
1023          case MISCREG_CPSR_Q:
1024            {
1025                assert(!(newVal & ~CpsrMaskQ));
1026                newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal;
1027                misc_reg = MISCREG_CPSR;
1028            }
1029            break;
1030          case MISCREG_FPSCR_QC:
1031            {
1032                newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
1033                         (newVal & FpscrQcMask);
1034                misc_reg = MISCREG_FPSCR;
1035            }
1036            break;
1037          case MISCREG_FPSCR_EXC:
1038            {
1039                newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
1040                         (newVal & FpscrExcMask);
1041                misc_reg = MISCREG_FPSCR;
1042            }
1043            break;
1044          case MISCREG_FPEXC:
1045            {
1046                // vfpv3 architecture, section B.6.1 of DDI04068
1047                // bit 29 - valid only if fpexc[31] is 0
1048                const uint32_t fpexcMask = 0x60000000;
1049                newVal = (newVal & fpexcMask) |
1050                         (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask);
1051            }
1052            break;
1053          case MISCREG_HCR:
1054            {
1055                if (!haveVirtualization)
1056                    return;
1057            }
1058            break;
1059          case MISCREG_IFSR:
1060            {
1061                // ARM ARM (ARM DDI 0406C.b) B4.1.96
1062                const uint32_t ifsrMask =
1063                    mask(31, 13) | mask(11, 11) | mask(8, 6);
1064                newVal = newVal & ~ifsrMask;
1065            }
1066            break;
1067          case MISCREG_DFSR:
1068            {
1069                // ARM ARM (ARM DDI 0406C.b) B4.1.52
1070                const uint32_t dfsrMask = mask(31, 14) | mask(8, 8);
1071                newVal = newVal & ~dfsrMask;
1072            }
1073            break;
1074          case MISCREG_AMAIR0:
1075          case MISCREG_AMAIR1:
1076            {
1077                // ARM ARM (ARM DDI 0406C.b) B4.1.5
1078                // Valid only with LPAE
1079                if (!haveLPAE)
1080                    return;
1081                DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal);
1082            }
1083            break;
1084          case MISCREG_SCR:
1085            tc->getITBPtr()->invalidateMiscReg();
1086            tc->getDTBPtr()->invalidateMiscReg();
1087            break;
1088          case MISCREG_SCTLR:
1089            {
1090                DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
1091                scr = readMiscRegNoEffect(MISCREG_SCR);
1092                MiscRegIndex sctlr_idx = (haveSecurity && !scr.ns)
1093                                         ? MISCREG_SCTLR_S : MISCREG_SCTLR_NS;
1094                SCTLR sctlr = miscRegs[sctlr_idx];
1095                SCTLR new_sctlr = newVal;
1096                new_sctlr.nmfi =  ((bool)sctlr.nmfi) && !haveVirtualization;
1097                miscRegs[sctlr_idx] = (MiscReg)new_sctlr;
1098                tc->getITBPtr()->invalidateMiscReg();
1099                tc->getDTBPtr()->invalidateMiscReg();
1100            }
1101          case MISCREG_MIDR:
1102          case MISCREG_ID_PFR0:
1103          case MISCREG_ID_PFR1:
1104          case MISCREG_ID_DFR0:
1105          case MISCREG_ID_MMFR0:
1106          case MISCREG_ID_MMFR1:
1107          case MISCREG_ID_MMFR2:
1108          case MISCREG_ID_MMFR3:
1109          case MISCREG_ID_ISAR0:
1110          case MISCREG_ID_ISAR1:
1111          case MISCREG_ID_ISAR2:
1112          case MISCREG_ID_ISAR3:
1113          case MISCREG_ID_ISAR4:
1114          case MISCREG_ID_ISAR5:
1115
1116          case MISCREG_MPIDR:
1117          case MISCREG_FPSID:
1118          case MISCREG_TLBTR:
1119          case MISCREG_MVFR0:
1120          case MISCREG_MVFR1:
1121
1122          case MISCREG_ID_AA64AFR0_EL1:
1123          case MISCREG_ID_AA64AFR1_EL1:
1124          case MISCREG_ID_AA64DFR0_EL1:
1125          case MISCREG_ID_AA64DFR1_EL1:
1126          case MISCREG_ID_AA64ISAR0_EL1:
1127          case MISCREG_ID_AA64ISAR1_EL1:
1128          case MISCREG_ID_AA64MMFR0_EL1:
1129          case MISCREG_ID_AA64MMFR1_EL1:
1130          case MISCREG_ID_AA64PFR0_EL1:
1131          case MISCREG_ID_AA64PFR1_EL1:
1132            // ID registers are constants.
1133            return;
1134
1135          // TLBI all entries, EL0&1 inner sharable (ignored)
1136          case MISCREG_TLBIALLIS:
1137          case MISCREG_TLBIALL: // TLBI all entries, EL0&1,
1138            assert32(tc);
1139            target_el = 1; // el 0 and 1 are handled together
1140            scr = readMiscReg(MISCREG_SCR, tc);
1141            secure_lookup = haveSecurity && !scr.ns;
1142            sys = tc->getSystemPtr();
1143            for (x = 0; x < sys->numContexts(); x++) {
1144                oc = sys->getThreadContext(x);
1145                assert(oc->getITBPtr() && oc->getDTBPtr());
1146                oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el);
1147                oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el);
1148
1149                // If CheckerCPU is connected, need to notify it of a flush
1150                CheckerCPU *checker = oc->getCheckerCpuPtr();
1151                if (checker) {
1152                    checker->getITBPtr()->flushAllSecurity(secure_lookup,
1153                                                           target_el);
1154                    checker->getDTBPtr()->flushAllSecurity(secure_lookup,
1155                                                           target_el);
1156                }
1157            }
1158            return;
1159          // TLBI all entries, EL0&1, instruction side
1160          case MISCREG_ITLBIALL:
1161            assert32(tc);
1162            target_el = 1; // el 0 and 1 are handled together
1163            scr = readMiscReg(MISCREG_SCR, tc);
1164            secure_lookup = haveSecurity && !scr.ns;
1165            tc->getITBPtr()->flushAllSecurity(secure_lookup, target_el);
1166            return;
1167          // TLBI all entries, EL0&1, data side
1168          case MISCREG_DTLBIALL:
1169            assert32(tc);
1170            target_el = 1; // el 0 and 1 are handled together
1171            scr = readMiscReg(MISCREG_SCR, tc);
1172            secure_lookup = haveSecurity && !scr.ns;
1173            tc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el);
1174            return;
1175          // TLBI based on VA, EL0&1 inner sharable (ignored)
1176          case MISCREG_TLBIMVAIS:
1177          case MISCREG_TLBIMVA:
1178            assert32(tc);
1179            target_el = 1; // el 0 and 1 are handled together
1180            scr = readMiscReg(MISCREG_SCR, tc);
1181            secure_lookup = haveSecurity && !scr.ns;
1182            sys = tc->getSystemPtr();
1183            for (x = 0; x < sys->numContexts(); x++) {
1184                oc = sys->getThreadContext(x);
1185                assert(oc->getITBPtr() && oc->getDTBPtr());
1186                oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
1187                                              bits(newVal, 7,0),
1188                                              secure_lookup, target_el);
1189                oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
1190                                              bits(newVal, 7,0),
1191                                              secure_lookup, target_el);
1192
1193                CheckerCPU *checker = oc->getCheckerCpuPtr();
1194                if (checker) {
1195                    checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
1196                        bits(newVal, 7,0), secure_lookup, target_el);
1197                    checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
1198                        bits(newVal, 7,0), secure_lookup, target_el);
1199                }
1200            }
1201            return;
1202          // TLBI by ASID, EL0&1, inner sharable
1203          case MISCREG_TLBIASIDIS:
1204          case MISCREG_TLBIASID:
1205            assert32(tc);
1206            target_el = 1; // el 0 and 1 are handled together
1207            scr = readMiscReg(MISCREG_SCR, tc);
1208            secure_lookup = haveSecurity && !scr.ns;
1209            sys = tc->getSystemPtr();
1210            for (x = 0; x < sys->numContexts(); x++) {
1211                oc = sys->getThreadContext(x);
1212                assert(oc->getITBPtr() && oc->getDTBPtr());
1213                oc->getITBPtr()->flushAsid(bits(newVal, 7,0),
1214                    secure_lookup, target_el);
1215                oc->getDTBPtr()->flushAsid(bits(newVal, 7,0),
1216                    secure_lookup, target_el);
1217                CheckerCPU *checker = oc->getCheckerCpuPtr();
1218                if (checker) {
1219                    checker->getITBPtr()->flushAsid(bits(newVal, 7,0),
1220                        secure_lookup, target_el);
1221                    checker->getDTBPtr()->flushAsid(bits(newVal, 7,0),
1222                        secure_lookup, target_el);
1223                }
1224            }
1225            return;
1226          // TLBI by address, EL0&1, inner sharable (ignored)
1227          case MISCREG_TLBIMVAAIS:
1228          case MISCREG_TLBIMVAA:
1229            assert32(tc);
1230            target_el = 1; // el 0 and 1 are handled together
1231            scr = readMiscReg(MISCREG_SCR, tc);
1232            secure_lookup = haveSecurity && !scr.ns;
1233            hyp = 0;
1234            tlbiMVA(tc, newVal, secure_lookup, hyp, target_el);
1235            return;
1236          // TLBI by address, EL2, hypervisor mode
1237          case MISCREG_TLBIMVAH:
1238          case MISCREG_TLBIMVAHIS:
1239            assert32(tc);
1240            target_el = 1; // aarch32, use hyp bit
1241            scr = readMiscReg(MISCREG_SCR, tc);
1242            secure_lookup = haveSecurity && !scr.ns;
1243            hyp = 1;
1244            tlbiMVA(tc, newVal, secure_lookup, hyp, target_el);
1245            return;
1246          // TLBI by address and asid, EL0&1, instruction side only
1247          case MISCREG_ITLBIMVA:
1248            assert32(tc);
1249            target_el = 1; // el 0 and 1 are handled together
1250            scr = readMiscReg(MISCREG_SCR, tc);
1251            secure_lookup = haveSecurity && !scr.ns;
1252            tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
1253                bits(newVal, 7,0), secure_lookup, target_el);
1254            return;
1255          // TLBI by address and asid, EL0&1, data side only
1256          case MISCREG_DTLBIMVA:
1257            assert32(tc);
1258            target_el = 1; // el 0 and 1 are handled together
1259            scr = readMiscReg(MISCREG_SCR, tc);
1260            secure_lookup = haveSecurity && !scr.ns;
1261            tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
1262                bits(newVal, 7,0), secure_lookup, target_el);
1263            return;
1264          // TLBI by ASID, EL0&1, instrution side only
1265          case MISCREG_ITLBIASID:
1266            assert32(tc);
1267            target_el = 1; // el 0 and 1 are handled together
1268            scr = readMiscReg(MISCREG_SCR, tc);
1269            secure_lookup = haveSecurity && !scr.ns;
1270            tc->getITBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup,
1271                                       target_el);
1272            return;
1273          // TLBI by ASID EL0&1 data size only
1274          case MISCREG_DTLBIASID:
1275            assert32(tc);
1276            target_el = 1; // el 0 and 1 are handled together
1277            scr = readMiscReg(MISCREG_SCR, tc);
1278            secure_lookup = haveSecurity && !scr.ns;
1279            tc->getDTBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup,
1280                                       target_el);
1281            return;
1282          // Invalidate entire Non-secure Hyp/Non-Hyp Unified TLB
1283          case MISCREG_TLBIALLNSNH:
1284          case MISCREG_TLBIALLNSNHIS:
1285            assert32(tc);
1286            target_el = 1; // el 0 and 1 are handled together
1287            hyp = 0;
1288            tlbiALLN(tc, hyp, target_el);
1289            return;
1290          // TLBI all entries, EL2, hyp,
1291          case MISCREG_TLBIALLH:
1292          case MISCREG_TLBIALLHIS:
1293            assert32(tc);
1294            target_el = 1; // aarch32, use hyp bit
1295            hyp = 1;
1296            tlbiALLN(tc, hyp, target_el);
1297            return;
1298          // AArch64 TLBI: invalidate all entries EL3
1299          case MISCREG_TLBI_ALLE3IS:
1300          case MISCREG_TLBI_ALLE3:
1301            assert64(tc);
1302            target_el = 3;
1303            secure_lookup = true;
1304            tlbiALL(tc, secure_lookup, target_el);
1305            return;
1306          // @todo: uncomment this to enable Virtualization
1307          // case MISCREG_TLBI_ALLE2IS:
1308          // case MISCREG_TLBI_ALLE2:
1309          // TLBI all entries, EL0&1
1310          case MISCREG_TLBI_ALLE1IS:
1311          case MISCREG_TLBI_ALLE1:
1312          // AArch64 TLBI: invalidate all entries, stage 1, current VMID
1313          case MISCREG_TLBI_VMALLE1IS:
1314          case MISCREG_TLBI_VMALLE1:
1315          // AArch64 TLBI: invalidate all entries, stages 1 & 2, current VMID
1316          case MISCREG_TLBI_VMALLS12E1IS:
1317          case MISCREG_TLBI_VMALLS12E1:
1318            // @todo: handle VMID and stage 2 to enable Virtualization
1319            assert64(tc);
1320            target_el = 1; // el 0 and 1 are handled together
1321            scr = readMiscReg(MISCREG_SCR, tc);
1322            secure_lookup = haveSecurity && !scr.ns;
1323            tlbiALL(tc, secure_lookup, target_el);
1324            return;
1325          // AArch64 TLBI: invalidate by VA and ASID, stage 1, current VMID
1326          // VAEx(IS) and VALEx(IS) are the same because TLBs only store entries
1327          // from the last level of translation table walks
1328          // @todo: handle VMID to enable Virtualization
1329          // TLBI all entries, EL0&1
1330          case MISCREG_TLBI_VAE3IS_Xt:
1331          case MISCREG_TLBI_VAE3_Xt:
1332          // TLBI by VA, EL3  regime stage 1, last level walk
1333          case MISCREG_TLBI_VALE3IS_Xt:
1334          case MISCREG_TLBI_VALE3_Xt:
1335            assert64(tc);
1336            target_el = 3;
1337            asid = 0xbeef; // does not matter, tlbi is global
1338            secure_lookup = true;
1339            tlbiVA(tc, newVal, asid, secure_lookup, target_el);
1340            return;
1341          // TLBI by VA, EL2
1342          case MISCREG_TLBI_VAE2IS_Xt:
1343          case MISCREG_TLBI_VAE2_Xt:
1344          // TLBI by VA, EL2, stage1 last level walk
1345          case MISCREG_TLBI_VALE2IS_Xt:
1346          case MISCREG_TLBI_VALE2_Xt:
1347            assert64(tc);
1348            target_el = 2;
1349            asid = 0xbeef; // does not matter, tlbi is global
1350            scr = readMiscReg(MISCREG_SCR, tc);
1351            secure_lookup = haveSecurity && !scr.ns;
1352            tlbiVA(tc, newVal, asid, secure_lookup, target_el);
1353            return;
1354          // TLBI by VA EL1 & 0, stage1, ASID, current VMID
1355          case MISCREG_TLBI_VAE1IS_Xt:
1356          case MISCREG_TLBI_VAE1_Xt:
1357          case MISCREG_TLBI_VALE1IS_Xt:
1358          case MISCREG_TLBI_VALE1_Xt:
1359            assert64(tc);
1360            asid = bits(newVal, 63, 48);
1361            target_el = 1; // el 0 and 1 are handled together
1362            scr = readMiscReg(MISCREG_SCR, tc);
1363            secure_lookup = haveSecurity && !scr.ns;
1364            tlbiVA(tc, newVal, asid, secure_lookup, target_el);
1365            return;
1366          // AArch64 TLBI: invalidate by ASID, stage 1, current VMID
1367          // @todo: handle VMID to enable Virtualization
1368          case MISCREG_TLBI_ASIDE1IS_Xt:
1369          case MISCREG_TLBI_ASIDE1_Xt:
1370            assert64(tc);
1371            target_el = 1; // el 0 and 1 are handled together
1372            scr = readMiscReg(MISCREG_SCR, tc);
1373            secure_lookup = haveSecurity && !scr.ns;
1374            sys = tc->getSystemPtr();
1375            for (x = 0; x < sys->numContexts(); x++) {
1376                oc = sys->getThreadContext(x);
1377                assert(oc->getITBPtr() && oc->getDTBPtr());
1378                asid = bits(newVal, 63, 48);
1379                if (!haveLargeAsid64)
1380                    asid &= mask(8);
1381                oc->getITBPtr()->flushAsid(asid, secure_lookup, target_el);
1382                oc->getDTBPtr()->flushAsid(asid, secure_lookup, target_el);
1383                CheckerCPU *checker = oc->getCheckerCpuPtr();
1384                if (checker) {
1385                    checker->getITBPtr()->flushAsid(asid,
1386                        secure_lookup, target_el);
1387                    checker->getDTBPtr()->flushAsid(asid,
1388                        secure_lookup, target_el);
1389                }
1390            }
1391            return;
1392          // AArch64 TLBI: invalidate by VA, ASID, stage 1, current VMID
1393          // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store
1394          // entries from the last level of translation table walks
1395          // @todo: handle VMID to enable Virtualization
1396          case MISCREG_TLBI_VAAE1IS_Xt:
1397          case MISCREG_TLBI_VAAE1_Xt:
1398          case MISCREG_TLBI_VAALE1IS_Xt:
1399          case MISCREG_TLBI_VAALE1_Xt:
1400            assert64(tc);
1401            target_el = 1; // el 0 and 1 are handled together
1402            scr = readMiscReg(MISCREG_SCR, tc);
1403            secure_lookup = haveSecurity && !scr.ns;
1404            sys = tc->getSystemPtr();
1405            for (x = 0; x < sys->numContexts(); x++) {
1406                // @todo: extra controls on TLBI broadcast?
1407                oc = sys->getThreadContext(x);
1408                assert(oc->getITBPtr() && oc->getDTBPtr());
1409                Addr va = ((Addr) bits(newVal, 43, 0)) << 12;
1410                oc->getITBPtr()->flushMva(va,
1411                    secure_lookup, false, target_el);
1412                oc->getDTBPtr()->flushMva(va,
1413                    secure_lookup, false, target_el);
1414
1415                CheckerCPU *checker = oc->getCheckerCpuPtr();
1416                if (checker) {
1417                    checker->getITBPtr()->flushMva(va,
1418                        secure_lookup, false, target_el);
1419                    checker->getDTBPtr()->flushMva(va,
1420                        secure_lookup, false, target_el);
1421                }
1422            }
1423            return;
1424          // AArch64 TLBI: invalidate by IPA, stage 2, current VMID
1425          case MISCREG_TLBI_IPAS2LE1IS_Xt:
1426          case MISCREG_TLBI_IPAS2LE1_Xt:
1427          case MISCREG_TLBI_IPAS2E1IS_Xt:
1428          case MISCREG_TLBI_IPAS2E1_Xt:
1429            assert64(tc);
1430            target_el = 1; // EL 0 and 1 are handled together
1431            scr = readMiscReg(MISCREG_SCR, tc);
1432            secure_lookup = haveSecurity && !scr.ns;
1433            sys = tc->getSystemPtr();
1434            for (x = 0; x < sys->numContexts(); x++) {
1435                oc = sys->getThreadContext(x);
1436                assert(oc->getITBPtr() && oc->getDTBPtr());
1437                Addr ipa = ((Addr) bits(newVal, 35, 0)) << 12;
1438                oc->getITBPtr()->flushIpaVmid(ipa,
1439                    secure_lookup, false, target_el);
1440                oc->getDTBPtr()->flushIpaVmid(ipa,
1441                    secure_lookup, false, target_el);
1442
1443                CheckerCPU *checker = oc->getCheckerCpuPtr();
1444                if (checker) {
1445                    checker->getITBPtr()->flushIpaVmid(ipa,
1446                        secure_lookup, false, target_el);
1447                    checker->getDTBPtr()->flushIpaVmid(ipa,
1448                        secure_lookup, false, target_el);
1449                }
1450            }
1451            return;
1452          case MISCREG_ACTLR:
1453            warn("Not doing anything for write of miscreg ACTLR\n");
1454            break;
1455
1456          case MISCREG_PMXEVTYPER_PMCCFILTR:
1457          case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
1458          case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
1459          case MISCREG_PMCR ... MISCREG_PMOVSSET:
1460            pmu->setMiscReg(misc_reg, newVal);
1461            break;
1462
1463
1464          case MISCREG_HSTR: // TJDBX, now redifined to be RES0
1465            {
1466                HSTR hstrMask = 0;
1467                hstrMask.tjdbx = 1;
1468                newVal &= ~((uint32_t) hstrMask);
1469                break;
1470            }
1471          case MISCREG_HCPTR:
1472            {
1473                // If a CP bit in NSACR is 0 then the corresponding bit in
1474                // HCPTR is RAO/WI. Same applies to NSASEDIS
1475                secure_lookup = haveSecurity &&
1476                    inSecureState(readMiscRegNoEffect(MISCREG_SCR),
1477                                  readMiscRegNoEffect(MISCREG_CPSR));
1478                if (!secure_lookup) {
1479                    MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR);
1480                    MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF;
1481                    newVal = (newVal & ~mask) | (oldValue & mask);
1482                }
1483                break;
1484            }
1485          case MISCREG_HDFAR: // alias for secure DFAR
1486            misc_reg = MISCREG_DFAR_S;
1487            break;
1488          case MISCREG_HIFAR: // alias for secure IFAR
1489            misc_reg = MISCREG_IFAR_S;
1490            break;
1491          case MISCREG_ATS1CPR:
1492          case MISCREG_ATS1CPW:
1493          case MISCREG_ATS1CUR:
1494          case MISCREG_ATS1CUW:
1495          case MISCREG_ATS12NSOPR:
1496          case MISCREG_ATS12NSOPW:
1497          case MISCREG_ATS12NSOUR:
1498          case MISCREG_ATS12NSOUW:
1499          case MISCREG_ATS1HR:
1500          case MISCREG_ATS1HW:
1501            {
1502              Request::Flags flags = 0;
1503              BaseTLB::Mode mode = BaseTLB::Read;
1504              TLB::ArmTranslationType tranType = TLB::NormalTran;
1505              Fault fault;
1506              switch(misc_reg) {
1507                case MISCREG_ATS1CPR:
1508                  flags    = TLB::MustBeOne;
1509                  tranType = TLB::S1CTran;
1510                  mode     = BaseTLB::Read;
1511                  break;
1512                case MISCREG_ATS1CPW:
1513                  flags    = TLB::MustBeOne;
1514                  tranType = TLB::S1CTran;
1515                  mode     = BaseTLB::Write;
1516                  break;
1517                case MISCREG_ATS1CUR:
1518                  flags    = TLB::MustBeOne | TLB::UserMode;
1519                  tranType = TLB::S1CTran;
1520                  mode     = BaseTLB::Read;
1521                  break;
1522                case MISCREG_ATS1CUW:
1523                  flags    = TLB::MustBeOne | TLB::UserMode;
1524                  tranType = TLB::S1CTran;
1525                  mode     = BaseTLB::Write;
1526                  break;
1527                case MISCREG_ATS12NSOPR:
1528                  if (!haveSecurity)
1529                      panic("Security Extensions required for ATS12NSOPR");
1530                  flags    = TLB::MustBeOne;
1531                  tranType = TLB::S1S2NsTran;
1532                  mode     = BaseTLB::Read;
1533                  break;
1534                case MISCREG_ATS12NSOPW:
1535                  if (!haveSecurity)
1536                      panic("Security Extensions required for ATS12NSOPW");
1537                  flags    = TLB::MustBeOne;
1538                  tranType = TLB::S1S2NsTran;
1539                  mode     = BaseTLB::Write;
1540                  break;
1541                case MISCREG_ATS12NSOUR:
1542                  if (!haveSecurity)
1543                      panic("Security Extensions required for ATS12NSOUR");
1544                  flags    = TLB::MustBeOne | TLB::UserMode;
1545                  tranType = TLB::S1S2NsTran;
1546                  mode     = BaseTLB::Read;
1547                  break;
1548                case MISCREG_ATS12NSOUW:
1549                  if (!haveSecurity)
1550                      panic("Security Extensions required for ATS12NSOUW");
1551                  flags    = TLB::MustBeOne | TLB::UserMode;
1552                  tranType = TLB::S1S2NsTran;
1553                  mode     = BaseTLB::Write;
1554                  break;
1555                case MISCREG_ATS1HR: // only really useful from secure mode.
1556                  flags    = TLB::MustBeOne;
1557                  tranType = TLB::HypMode;
1558                  mode     = BaseTLB::Read;
1559                  break;
1560                case MISCREG_ATS1HW:
1561                  flags    = TLB::MustBeOne;
1562                  tranType = TLB::HypMode;
1563                  mode     = BaseTLB::Write;
1564                  break;
1565              }
1566              // If we're in timing mode then doing the translation in
1567              // functional mode then we're slightly distorting performance
1568              // results obtained from simulations. The translation should be
1569              // done in the same mode the core is running in. NOTE: This
1570              // can't be an atomic translation because that causes problems
1571              // with unexpected atomic snoop requests.
1572              warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
1573              Request req(0, val, 0, flags,  Request::funcMasterId,
1574                          tc->pcState().pc(), tc->contextId());
1575              fault = tc->getDTBPtr()->translateFunctional(&req, tc, mode, tranType);
1576              TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1577              HCR   hcr   = readMiscRegNoEffect(MISCREG_HCR);
1578
1579              MiscReg newVal;
1580              if (fault == NoFault) {
1581                  Addr paddr = req.getPaddr();
1582                  if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode ||
1583                     ((tranType & TLB::S1S2NsTran) && hcr.vm) )) {
1584                      newVal = (paddr & mask(39, 12)) |
1585                               (tc->getDTBPtr()->getAttr());
1586                  } else {
1587                      newVal = (paddr & 0xfffff000) |
1588                               (tc->getDTBPtr()->getAttr());
1589                  }
1590                  DPRINTF(MiscRegs,
1591                          "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
1592                          val, newVal);
1593              } else {
1594                  ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get());
1595                  // Set fault bit and FSR
1596                  FSR fsr = armFault->getFsr(tc);
1597
1598                  newVal = ((fsr >> 9) & 1) << 11;
1599                  if (newVal) {
1600                    // LPAE - rearange fault status
1601                    newVal |= ((fsr >>  0) & 0x3f) << 1;
1602                  } else {
1603                    // VMSA - rearange fault status
1604                    newVal |= ((fsr >>  0) & 0xf) << 1;
1605                    newVal |= ((fsr >> 10) & 0x1) << 5;
1606                    newVal |= ((fsr >> 12) & 0x1) << 6;
1607                  }
1608                  newVal |= 0x1; // F bit
1609                  newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
1610                  newVal |= armFault->isStage2() ? 0x200 : 0;
1611                  DPRINTF(MiscRegs,
1612                          "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n",
1613                          val, fsr, newVal);
1614              }
1615              setMiscRegNoEffect(MISCREG_PAR, newVal);
1616              return;
1617            }
1618          case MISCREG_TTBCR:
1619            {
1620                TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1621                const uint32_t ones = (uint32_t)(-1);
1622                TTBCR ttbcrMask = 0;
1623                TTBCR ttbcrNew = newVal;
1624
1625                // ARM DDI 0406C.b, ARMv7-32
1626                ttbcrMask.n = ones; // T0SZ
1627                if (haveSecurity) {
1628                    ttbcrMask.pd0 = ones;
1629                    ttbcrMask.pd1 = ones;
1630                }
1631                ttbcrMask.epd0 = ones;
1632                ttbcrMask.irgn0 = ones;
1633                ttbcrMask.orgn0 = ones;
1634                ttbcrMask.sh0 = ones;
1635                ttbcrMask.ps = ones; // T1SZ
1636                ttbcrMask.a1 = ones;
1637                ttbcrMask.epd1 = ones;
1638                ttbcrMask.irgn1 = ones;
1639                ttbcrMask.orgn1 = ones;
1640                ttbcrMask.sh1 = ones;
1641                if (haveLPAE)
1642                    ttbcrMask.eae = ones;
1643
1644                if (haveLPAE && ttbcrNew.eae) {
1645                    newVal = newVal & ttbcrMask;
1646                } else {
1647                    newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask));
1648                }
1649            }
1650          case MISCREG_TTBR0:
1651          case MISCREG_TTBR1:
1652            {
1653                TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1654                if (haveLPAE) {
1655                    if (ttbcr.eae) {
1656                        // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP
1657                        // ARMv8 AArch32 bit 63-56 only
1658                        uint64_t ttbrMask = mask(63,56) | mask(47,40);
1659                        newVal = (newVal & (~ttbrMask));
1660                    }
1661                }
1662            }
1663          case MISCREG_SCTLR_EL1:
1664            {
1665                tc->getITBPtr()->invalidateMiscReg();
1666                tc->getDTBPtr()->invalidateMiscReg();
1667                setMiscRegNoEffect(misc_reg, newVal);
1668            }
1669          case MISCREG_CONTEXTIDR:
1670          case MISCREG_PRRR:
1671          case MISCREG_NMRR:
1672          case MISCREG_MAIR0:
1673          case MISCREG_MAIR1:
1674          case MISCREG_DACR:
1675          case MISCREG_VTTBR:
1676          case MISCREG_SCR_EL3:
1677          case MISCREG_HCR_EL2:
1678          case MISCREG_TCR_EL1:
1679          case MISCREG_TCR_EL2:
1680          case MISCREG_TCR_EL3:
1681          case MISCREG_SCTLR_EL2:
1682          case MISCREG_SCTLR_EL3:
1683          case MISCREG_HSCTLR:
1684          case MISCREG_TTBR0_EL1:
1685          case MISCREG_TTBR1_EL1:
1686          case MISCREG_TTBR0_EL2:
1687          case MISCREG_TTBR0_EL3:
1688            tc->getITBPtr()->invalidateMiscReg();
1689            tc->getDTBPtr()->invalidateMiscReg();
1690            break;
1691          case MISCREG_NZCV:
1692            {
1693                CPSR cpsr = val;
1694
1695                tc->setCCReg(CCREG_NZ, cpsr.nz);
1696                tc->setCCReg(CCREG_C,  cpsr.c);
1697                tc->setCCReg(CCREG_V,  cpsr.v);
1698            }
1699            break;
1700          case MISCREG_DAIF:
1701            {
1702                CPSR cpsr = miscRegs[MISCREG_CPSR];
1703                cpsr.daif = (uint8_t) ((CPSR) newVal).daif;
1704                newVal = cpsr;
1705                misc_reg = MISCREG_CPSR;
1706            }
1707            break;
1708          case MISCREG_SP_EL0:
1709            tc->setIntReg(INTREG_SP0, newVal);
1710            break;
1711          case MISCREG_SP_EL1:
1712            tc->setIntReg(INTREG_SP1, newVal);
1713            break;
1714          case MISCREG_SP_EL2:
1715            tc->setIntReg(INTREG_SP2, newVal);
1716            break;
1717          case MISCREG_SPSEL:
1718            {
1719                CPSR cpsr = miscRegs[MISCREG_CPSR];
1720                cpsr.sp = (uint8_t) ((CPSR) newVal).sp;
1721                newVal = cpsr;
1722                misc_reg = MISCREG_CPSR;
1723            }
1724            break;
1725          case MISCREG_CURRENTEL:
1726            {
1727                CPSR cpsr = miscRegs[MISCREG_CPSR];
1728                cpsr.el = (uint8_t) ((CPSR) newVal).el;
1729                newVal = cpsr;
1730                misc_reg = MISCREG_CPSR;
1731            }
1732            break;
1733          case MISCREG_AT_S1E1R_Xt:
1734          case MISCREG_AT_S1E1W_Xt:
1735          case MISCREG_AT_S1E0R_Xt:
1736          case MISCREG_AT_S1E0W_Xt:
1737          case MISCREG_AT_S1E2R_Xt:
1738          case MISCREG_AT_S1E2W_Xt:
1739          case MISCREG_AT_S12E1R_Xt:
1740          case MISCREG_AT_S12E1W_Xt:
1741          case MISCREG_AT_S12E0R_Xt:
1742          case MISCREG_AT_S12E0W_Xt:
1743          case MISCREG_AT_S1E3R_Xt:
1744          case MISCREG_AT_S1E3W_Xt:
1745            {
1746                RequestPtr req = new Request;
1747                Request::Flags flags = 0;
1748                BaseTLB::Mode mode = BaseTLB::Read;
1749                TLB::ArmTranslationType tranType = TLB::NormalTran;
1750                Fault fault;
1751                switch(misc_reg) {
1752                  case MISCREG_AT_S1E1R_Xt:
1753                    flags    = TLB::MustBeOne;
1754                    tranType = TLB::S1E1Tran;
1755                    mode     = BaseTLB::Read;
1756                    break;
1757                  case MISCREG_AT_S1E1W_Xt:
1758                    flags    = TLB::MustBeOne;
1759                    tranType = TLB::S1E1Tran;
1760                    mode     = BaseTLB::Write;
1761                    break;
1762                  case MISCREG_AT_S1E0R_Xt:
1763                    flags    = TLB::MustBeOne | TLB::UserMode;
1764                    tranType = TLB::S1E0Tran;
1765                    mode     = BaseTLB::Read;
1766                    break;
1767                  case MISCREG_AT_S1E0W_Xt:
1768                    flags    = TLB::MustBeOne | TLB::UserMode;
1769                    tranType = TLB::S1E0Tran;
1770                    mode     = BaseTLB::Write;
1771                    break;
1772                  case MISCREG_AT_S1E2R_Xt:
1773                    flags    = TLB::MustBeOne;
1774                    tranType = TLB::S1E2Tran;
1775                    mode     = BaseTLB::Read;
1776                    break;
1777                  case MISCREG_AT_S1E2W_Xt:
1778                    flags    = TLB::MustBeOne;
1779                    tranType = TLB::S1E2Tran;
1780                    mode     = BaseTLB::Write;
1781                    break;
1782                  case MISCREG_AT_S12E0R_Xt:
1783                    flags    = TLB::MustBeOne | TLB::UserMode;
1784                    tranType = TLB::S12E0Tran;
1785                    mode     = BaseTLB::Read;
1786                    break;
1787                  case MISCREG_AT_S12E0W_Xt:
1788                    flags    = TLB::MustBeOne | TLB::UserMode;
1789                    tranType = TLB::S12E0Tran;
1790                    mode     = BaseTLB::Write;
1791                    break;
1792                  case MISCREG_AT_S12E1R_Xt:
1793                    flags    = TLB::MustBeOne;
1794                    tranType = TLB::S12E1Tran;
1795                    mode     = BaseTLB::Read;
1796                    break;
1797                  case MISCREG_AT_S12E1W_Xt:
1798                    flags    = TLB::MustBeOne;
1799                    tranType = TLB::S12E1Tran;
1800                    mode     = BaseTLB::Write;
1801                    break;
1802                  case MISCREG_AT_S1E3R_Xt:
1803                    flags    = TLB::MustBeOne;
1804                    tranType = TLB::S1E3Tran;
1805                    mode     = BaseTLB::Read;
1806                    break;
1807                  case MISCREG_AT_S1E3W_Xt:
1808                    flags    = TLB::MustBeOne;
1809                    tranType = TLB::S1E3Tran;
1810                    mode     = BaseTLB::Write;
1811                    break;
1812                }
1813                // If we're in timing mode then doing the translation in
1814                // functional mode then we're slightly distorting performance
1815                // results obtained from simulations. The translation should be
1816                // done in the same mode the core is running in. NOTE: This
1817                // can't be an atomic translation because that causes problems
1818                // with unexpected atomic snoop requests.
1819                warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
1820                req->setVirt(0, val, 0, flags,  Request::funcMasterId,
1821                               tc->pcState().pc());
1822                req->setContext(tc->contextId());
1823                fault = tc->getDTBPtr()->translateFunctional(req, tc, mode,
1824                                                             tranType);
1825
1826                MiscReg newVal;
1827                if (fault == NoFault) {
1828                    Addr paddr = req->getPaddr();
1829                    uint64_t attr = tc->getDTBPtr()->getAttr();
1830                    uint64_t attr1 = attr >> 56;
1831                    if (!attr1 || attr1 ==0x44) {
1832                        attr |= 0x100;
1833                        attr &= ~ uint64_t(0x80);
1834                    }
1835                    newVal = (paddr & mask(47, 12)) | attr;
1836                    DPRINTF(MiscRegs,
1837                          "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
1838                          val, newVal);
1839                } else {
1840                    ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get());
1841                    // Set fault bit and FSR
1842                    FSR fsr = armFault->getFsr(tc);
1843
1844                    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
1845                    if (cpsr.width) { // AArch32
1846                        newVal = ((fsr >> 9) & 1) << 11;
1847                        // rearrange fault status
1848                        newVal |= ((fsr >>  0) & 0x3f) << 1;
1849                        newVal |= 0x1; // F bit
1850                        newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
1851                        newVal |= armFault->isStage2() ? 0x200 : 0;
1852                    } else { // AArch64
1853                        newVal = 1; // F bit
1854                        newVal |= fsr << 1; // FST
1855                        // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit.
1856                        newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW
1857                        newVal |= armFault->isStage2() ? 1 << 9 : 0; // S
1858                        newVal |= 1 << 11; // RES1
1859                    }
1860                    DPRINTF(MiscRegs,
1861                            "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
1862                            val, fsr, newVal);
1863                }
1864                delete req;
1865                setMiscRegNoEffect(MISCREG_PAR_EL1, newVal);
1866                return;
1867            }
1868          case MISCREG_SPSR_EL3:
1869          case MISCREG_SPSR_EL2:
1870          case MISCREG_SPSR_EL1:
1871            // Force bits 23:21 to 0
1872            newVal = val & ~(0x7 << 21);
1873            break;
1874          case MISCREG_L2CTLR:
1875            warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
1876                 miscRegName[misc_reg], uint32_t(val));
1877            break;
1878
1879          // Generic Timer registers
1880          case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
1881          case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
1882          case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:
1883          case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1:
1884            getGenericTimer(tc).setMiscReg(misc_reg, newVal);
1885            break;
1886        }
1887    }
1888    setMiscRegNoEffect(misc_reg, newVal);
1889}
1890
1891void
1892ISA::tlbiVA(ThreadContext *tc, MiscReg newVal, uint16_t asid,
1893            bool secure_lookup, uint8_t target_el)
1894{
1895    if (!haveLargeAsid64)
1896        asid &= mask(8);
1897    Addr va = ((Addr) bits(newVal, 43, 0)) << 12;
1898    System *sys = tc->getSystemPtr();
1899    for (int x = 0; x < sys->numContexts(); x++) {
1900        ThreadContext *oc = sys->getThreadContext(x);
1901        assert(oc->getITBPtr() && oc->getDTBPtr());
1902        oc->getITBPtr()->flushMvaAsid(va, asid,
1903                                      secure_lookup, target_el);
1904        oc->getDTBPtr()->flushMvaAsid(va, asid,
1905                                      secure_lookup, target_el);
1906
1907        CheckerCPU *checker = oc->getCheckerCpuPtr();
1908        if (checker) {
1909            checker->getITBPtr()->flushMvaAsid(
1910                va, asid, secure_lookup, target_el);
1911            checker->getDTBPtr()->flushMvaAsid(
1912                va, asid, secure_lookup, target_el);
1913        }
1914    }
1915}
1916
1917void
1918ISA::tlbiALL(ThreadContext *tc, bool secure_lookup, uint8_t target_el)
1919{
1920    System *sys = tc->getSystemPtr();
1921    for (int x = 0; x < sys->numContexts(); x++) {
1922        ThreadContext *oc = sys->getThreadContext(x);
1923        assert(oc->getITBPtr() && oc->getDTBPtr());
1924        oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el);
1925        oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el);
1926
1927        // If CheckerCPU is connected, need to notify it of a flush
1928        CheckerCPU *checker = oc->getCheckerCpuPtr();
1929        if (checker) {
1930            checker->getITBPtr()->flushAllSecurity(secure_lookup,
1931                                                   target_el);
1932            checker->getDTBPtr()->flushAllSecurity(secure_lookup,
1933                                                   target_el);
1934        }
1935    }
1936}
1937
1938void
1939ISA::tlbiALLN(ThreadContext *tc, bool hyp, uint8_t target_el)
1940{
1941    System *sys = tc->getSystemPtr();
1942    for (int x = 0; x < sys->numContexts(); x++) {
1943      ThreadContext *oc = sys->getThreadContext(x);
1944      assert(oc->getITBPtr() && oc->getDTBPtr());
1945      oc->getITBPtr()->flushAllNs(hyp, target_el);
1946      oc->getDTBPtr()->flushAllNs(hyp, target_el);
1947
1948      CheckerCPU *checker = oc->getCheckerCpuPtr();
1949      if (checker) {
1950          checker->getITBPtr()->flushAllNs(hyp, target_el);
1951          checker->getDTBPtr()->flushAllNs(hyp, target_el);
1952      }
1953    }
1954}
1955
1956void
1957ISA::tlbiMVA(ThreadContext *tc, MiscReg newVal, bool secure_lookup, bool hyp,
1958             uint8_t target_el)
1959{
1960    System *sys = tc->getSystemPtr();
1961    for (int x = 0; x < sys->numContexts(); x++) {
1962        ThreadContext *oc = sys->getThreadContext(x);
1963        assert(oc->getITBPtr() && oc->getDTBPtr());
1964        oc->getITBPtr()->flushMva(mbits(newVal, 31,12),
1965            secure_lookup, hyp, target_el);
1966        oc->getDTBPtr()->flushMva(mbits(newVal, 31,12),
1967            secure_lookup, hyp, target_el);
1968
1969        CheckerCPU *checker = oc->getCheckerCpuPtr();
1970        if (checker) {
1971            checker->getITBPtr()->flushMva(mbits(newVal, 31,12),
1972                secure_lookup, hyp, target_el);
1973            checker->getDTBPtr()->flushMva(mbits(newVal, 31,12),
1974                secure_lookup, hyp, target_el);
1975        }
1976    }
1977}
1978
1979BaseISADevice &
1980ISA::getGenericTimer(ThreadContext *tc)
1981{
1982    // We only need to create an ISA interface the first time we try
1983    // to access the timer.
1984    if (timer)
1985        return *timer.get();
1986
1987    assert(system);
1988    GenericTimer *generic_timer(system->getGenericTimer());
1989    if (!generic_timer) {
1990        panic("Trying to get a generic timer from a system that hasn't "
1991              "been configured to use a generic timer.\n");
1992    }
1993
1994    timer.reset(new GenericTimerISA(*generic_timer, tc->contextId()));
1995    return *timer.get();
1996}
1997
1998}
1999
2000ArmISA::ISA *
2001ArmISAParams::create()
2002{
2003    return new ArmISA::ISA(this);
2004}
2005