isa.cc revision 11770:0d7119bed18e
1/* 2 * Copyright (c) 2010-2016 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 */ 40 41#include "arch/arm/isa.hh" 42#include "arch/arm/pmu.hh" 43#include "arch/arm/system.hh" 44#include "cpu/checker/cpu.hh" 45#include "cpu/base.hh" 46#include "debug/Arm.hh" 47#include "debug/MiscRegs.hh" 48#include "dev/arm/generic_timer.hh" 49#include "params/ArmISA.hh" 50#include "sim/faults.hh" 51#include "sim/stat_control.hh" 52#include "sim/system.hh" 53 54namespace ArmISA 55{ 56 57 58/** 59 * Some registers alias with others, and therefore need to be translated. 60 * For each entry: 61 * The first value is the misc register that is to be looked up 62 * the second value is the lower part of the translation 63 * the third the upper part 64 * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543 65 */ 66const struct ISA::MiscRegInitializerEntry 67 ISA::MiscRegSwitch[] = { 68 {MISCREG_ACTLR_EL1, {MISCREG_ACTLR_NS, 0}}, 69 {MISCREG_AFSR0_EL1, {MISCREG_ADFSR_NS, 0}}, 70 {MISCREG_AFSR1_EL1, {MISCREG_AIFSR_NS, 0}}, 71 {MISCREG_AMAIR_EL1, {MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS}}, 72 {MISCREG_CONTEXTIDR_EL1, {MISCREG_CONTEXTIDR_NS, 0}}, 73 {MISCREG_CPACR_EL1, {MISCREG_CPACR, 0}}, 74 {MISCREG_CSSELR_EL1, {MISCREG_CSSELR_NS, 0}}, 75 {MISCREG_DACR32_EL2, {MISCREG_DACR_NS, 0}}, 76 {MISCREG_FAR_EL1, {MISCREG_DFAR_NS, MISCREG_IFAR_NS}}, 77 // ESR_EL1 -> DFSR 78 {MISCREG_HACR_EL2, {MISCREG_HACR, 0}}, 79 {MISCREG_ACTLR_EL2, {MISCREG_HACTLR, 0}}, 80 {MISCREG_AFSR0_EL2, {MISCREG_HADFSR, 0}}, 81 {MISCREG_AFSR1_EL2, {MISCREG_HAIFSR, 0}}, 82 {MISCREG_AMAIR_EL2, {MISCREG_HAMAIR0, MISCREG_HAMAIR1}}, 83 {MISCREG_CPTR_EL2, {MISCREG_HCPTR, 0}}, 84 {MISCREG_HCR_EL2, {MISCREG_HCR, 0 /*MISCREG_HCR2*/}}, 85 {MISCREG_MDCR_EL2, {MISCREG_HDCR, 0}}, 86 {MISCREG_FAR_EL2, {MISCREG_HDFAR, MISCREG_HIFAR}}, 87 {MISCREG_MAIR_EL2, {MISCREG_HMAIR0, MISCREG_HMAIR1}}, 88 {MISCREG_HPFAR_EL2, {MISCREG_HPFAR, 0}}, 89 {MISCREG_SCTLR_EL2, {MISCREG_HSCTLR, 0}}, 90 {MISCREG_ESR_EL2, {MISCREG_HSR, 0}}, 91 {MISCREG_HSTR_EL2, {MISCREG_HSTR, 0}}, 92 {MISCREG_TCR_EL2, {MISCREG_HTCR, 0}}, 93 {MISCREG_TPIDR_EL2, {MISCREG_HTPIDR, 0}}, 94 {MISCREG_TTBR0_EL2, {MISCREG_HTTBR, 0}}, 95 {MISCREG_VBAR_EL2, {MISCREG_HVBAR, 0}}, 96 {MISCREG_IFSR32_EL2, {MISCREG_IFSR_NS, 0}}, 97 {MISCREG_MAIR_EL1, {MISCREG_PRRR_NS, MISCREG_NMRR_NS}}, 98 {MISCREG_PAR_EL1, {MISCREG_PAR_NS, 0}}, 99 // RMR_EL1 -> RMR 100 // RMR_EL2 -> HRMR 101 {MISCREG_SCTLR_EL1, {MISCREG_SCTLR_NS, 0}}, 102 {MISCREG_SDER32_EL3, {MISCREG_SDER, 0}}, 103 {MISCREG_TPIDR_EL1, {MISCREG_TPIDRPRW_NS, 0}}, 104 {MISCREG_TPIDRRO_EL0, {MISCREG_TPIDRURO_NS, 0}}, 105 {MISCREG_TPIDR_EL0, {MISCREG_TPIDRURW_NS, 0}}, 106 {MISCREG_TCR_EL1, {MISCREG_TTBCR_NS, 0}}, 107 {MISCREG_TTBR0_EL1, {MISCREG_TTBR0_NS, 0}}, 108 {MISCREG_TTBR1_EL1, {MISCREG_TTBR1_NS, 0}}, 109 {MISCREG_VBAR_EL1, {MISCREG_VBAR_NS, 0}}, 110 {MISCREG_VMPIDR_EL2, {MISCREG_VMPIDR, 0}}, 111 {MISCREG_VPIDR_EL2, {MISCREG_VPIDR, 0}}, 112 {MISCREG_VTCR_EL2, {MISCREG_VTCR, 0}}, 113 {MISCREG_VTTBR_EL2, {MISCREG_VTTBR, 0}}, 114 {MISCREG_CNTFRQ_EL0, {MISCREG_CNTFRQ, 0}}, 115 {MISCREG_CNTHCTL_EL2, {MISCREG_CNTHCTL, 0}}, 116 {MISCREG_CNTHP_CTL_EL2, {MISCREG_CNTHP_CTL, 0}}, 117 {MISCREG_CNTHP_CVAL_EL2, {MISCREG_CNTHP_CVAL, 0}}, /* 64b */ 118 {MISCREG_CNTHP_TVAL_EL2, {MISCREG_CNTHP_TVAL, 0}}, 119 {MISCREG_CNTKCTL_EL1, {MISCREG_CNTKCTL, 0}}, 120 {MISCREG_CNTP_CTL_EL0, {MISCREG_CNTP_CTL_NS, 0}}, 121 {MISCREG_CNTP_CVAL_EL0, {MISCREG_CNTP_CVAL_NS, 0}}, /* 64b */ 122 {MISCREG_CNTP_TVAL_EL0, {MISCREG_CNTP_TVAL_NS, 0}}, 123 {MISCREG_CNTPCT_EL0, {MISCREG_CNTPCT, 0}}, /* 64b */ 124 {MISCREG_CNTV_CTL_EL0, {MISCREG_CNTV_CTL, 0}}, 125 {MISCREG_CNTV_CVAL_EL0, {MISCREG_CNTV_CVAL, 0}}, /* 64b */ 126 {MISCREG_CNTV_TVAL_EL0, {MISCREG_CNTV_TVAL, 0}}, 127 {MISCREG_CNTVCT_EL0, {MISCREG_CNTVCT, 0}}, /* 64b */ 128 {MISCREG_CNTVOFF_EL2, {MISCREG_CNTVOFF, 0}}, /* 64b */ 129 {MISCREG_DBGAUTHSTATUS_EL1, {MISCREG_DBGAUTHSTATUS, 0}}, 130 {MISCREG_DBGBCR0_EL1, {MISCREG_DBGBCR0, 0}}, 131 {MISCREG_DBGBCR1_EL1, {MISCREG_DBGBCR1, 0}}, 132 {MISCREG_DBGBCR2_EL1, {MISCREG_DBGBCR2, 0}}, 133 {MISCREG_DBGBCR3_EL1, {MISCREG_DBGBCR3, 0}}, 134 {MISCREG_DBGBCR4_EL1, {MISCREG_DBGBCR4, 0}}, 135 {MISCREG_DBGBCR5_EL1, {MISCREG_DBGBCR5, 0}}, 136 {MISCREG_DBGBVR0_EL1, {MISCREG_DBGBVR0, 0 /* MISCREG_DBGBXVR0 */}}, 137 {MISCREG_DBGBVR1_EL1, {MISCREG_DBGBVR1, 0 /* MISCREG_DBGBXVR1 */}}, 138 {MISCREG_DBGBVR2_EL1, {MISCREG_DBGBVR2, 0 /* MISCREG_DBGBXVR2 */}}, 139 {MISCREG_DBGBVR3_EL1, {MISCREG_DBGBVR3, 0 /* MISCREG_DBGBXVR3 */}}, 140 {MISCREG_DBGBVR4_EL1, {MISCREG_DBGBVR4, MISCREG_DBGBXVR4}}, 141 {MISCREG_DBGBVR5_EL1, {MISCREG_DBGBVR5, MISCREG_DBGBXVR5}}, 142 {MISCREG_DBGCLAIMSET_EL1, {MISCREG_DBGCLAIMSET, 0}}, 143 {MISCREG_DBGCLAIMCLR_EL1, {MISCREG_DBGCLAIMCLR, 0}}, 144 // DBGDTR_EL0 -> DBGDTR{R or T}Xint 145 // DBGDTRRX_EL0 -> DBGDTRRXint 146 // DBGDTRTX_EL0 -> DBGDTRRXint 147 {MISCREG_DBGPRCR_EL1, {MISCREG_DBGPRCR, 0}}, 148 {MISCREG_DBGVCR32_EL2, {MISCREG_DBGVCR, 0}}, 149 {MISCREG_DBGWCR0_EL1, {MISCREG_DBGWCR0, 0}}, 150 {MISCREG_DBGWCR1_EL1, {MISCREG_DBGWCR1, 0}}, 151 {MISCREG_DBGWCR2_EL1, {MISCREG_DBGWCR2, 0}}, 152 {MISCREG_DBGWCR3_EL1, {MISCREG_DBGWCR3, 0}}, 153 {MISCREG_DBGWVR0_EL1, {MISCREG_DBGWVR0, 0}}, 154 {MISCREG_DBGWVR1_EL1, {MISCREG_DBGWVR1, 0}}, 155 {MISCREG_DBGWVR2_EL1, {MISCREG_DBGWVR2, 0}}, 156 {MISCREG_DBGWVR3_EL1, {MISCREG_DBGWVR3, 0}}, 157 {MISCREG_ID_DFR0_EL1, {MISCREG_ID_DFR0, 0}}, 158 {MISCREG_MDCCSR_EL0, {MISCREG_DBGDSCRint, 0}}, 159 {MISCREG_MDRAR_EL1, {MISCREG_DBGDRAR, 0}}, 160 {MISCREG_MDSCR_EL1, {MISCREG_DBGDSCRext, 0}}, 161 {MISCREG_OSDLR_EL1, {MISCREG_DBGOSDLR, 0}}, 162 {MISCREG_OSDTRRX_EL1, {MISCREG_DBGDTRRXext, 0}}, 163 {MISCREG_OSDTRTX_EL1, {MISCREG_DBGDTRTXext, 0}}, 164 {MISCREG_OSECCR_EL1, {MISCREG_DBGOSECCR, 0}}, 165 {MISCREG_OSLAR_EL1, {MISCREG_DBGOSLAR, 0}}, 166 {MISCREG_OSLSR_EL1, {MISCREG_DBGOSLSR, 0}}, 167 {MISCREG_PMCCNTR_EL0, {MISCREG_PMCCNTR, 0}}, 168 {MISCREG_PMCEID0_EL0, {MISCREG_PMCEID0, 0}}, 169 {MISCREG_PMCEID1_EL0, {MISCREG_PMCEID1, 0}}, 170 {MISCREG_PMCNTENSET_EL0, {MISCREG_PMCNTENSET, 0}}, 171 {MISCREG_PMCNTENCLR_EL0, {MISCREG_PMCNTENCLR, 0}}, 172 {MISCREG_PMCR_EL0, {MISCREG_PMCR, 0}}, 173/* {MISCREG_PMEVCNTR0_EL0, {MISCREG_PMEVCNTR0, 0}}, 174 {MISCREG_PMEVCNTR1_EL0, {MISCREG_PMEVCNTR1, 0}}, 175 {MISCREG_PMEVCNTR2_EL0, {MISCREG_PMEVCNTR2, 0}}, 176 {MISCREG_PMEVCNTR3_EL0, {MISCREG_PMEVCNTR3, 0}}, 177 {MISCREG_PMEVCNTR4_EL0, {MISCREG_PMEVCNTR4, 0}}, 178 {MISCREG_PMEVCNTR5_EL0, {MISCREG_PMEVCNTR5, 0}}, 179 {MISCREG_PMEVTYPER0_EL0, {MISCREG_PMEVTYPER0, 0}}, 180 {MISCREG_PMEVTYPER1_EL0, {MISCREG_PMEVTYPER1, 0}}, 181 {MISCREG_PMEVTYPER2_EL0, {MISCREG_PMEVTYPER2, 0}}, 182 {MISCREG_PMEVTYPER3_EL0, {MISCREG_PMEVTYPER3, 0}}, 183 {MISCREG_PMEVTYPER4_EL0, {MISCREG_PMEVTYPER4, 0}}, 184 {MISCREG_PMEVTYPER5_EL0, {MISCREG_PMEVTYPER5, 0}}, */ 185 {MISCREG_PMINTENCLR_EL1, {MISCREG_PMINTENCLR, 0}}, 186 {MISCREG_PMINTENSET_EL1, {MISCREG_PMINTENSET, 0}}, 187// {MISCREG_PMOVSCLR_EL0, {MISCREG_PMOVSCLR, 0}}, 188 {MISCREG_PMOVSSET_EL0, {MISCREG_PMOVSSET, 0}}, 189 {MISCREG_PMSELR_EL0, {MISCREG_PMSELR, 0}}, 190 {MISCREG_PMSWINC_EL0, {MISCREG_PMSWINC, 0}}, 191 {MISCREG_PMUSERENR_EL0, {MISCREG_PMUSERENR, 0}}, 192 {MISCREG_PMXEVCNTR_EL0, {MISCREG_PMXEVCNTR, 0}}, 193 {MISCREG_PMXEVTYPER_EL0, {MISCREG_PMXEVTYPER, 0}}, 194 195 // from ARM DDI 0487A.i, template text 196 // "AArch64 System register ___ can be mapped to 197 // AArch32 System register ___, but this is not 198 // architecturally mandated." 199 {MISCREG_SCR_EL3, {MISCREG_SCR, 0}}, // D7-2005 200 // MDCR_EL3 -> SDCR, D7-2108 (the latter is unimpl. in gem5) 201 {MISCREG_SPSR_EL1, {MISCREG_SPSR_SVC, 0}}, // C5.2.17 SPSR_EL1 202 {MISCREG_SPSR_EL2, {MISCREG_SPSR_HYP, 0}}, // C5.2.18 SPSR_EL2 203 {MISCREG_SPSR_EL3, {MISCREG_SPSR_MON, 0}}, // C5.2.19 SPSR_EL3 204}; 205 206 207ISA::ISA(Params *p) 208 : SimObject(p), 209 system(NULL), 210 _decoderFlavour(p->decoderFlavour), 211 pmu(p->pmu), 212 lookUpMiscReg(NUM_MISCREGS, {0,0}) 213{ 214 miscRegs[MISCREG_SCTLR_RST] = 0; 215 216 // Hook up a dummy device if we haven't been configured with a 217 // real PMU. By using a dummy device, we don't need to check that 218 // the PMU exist every time we try to access a PMU register. 219 if (!pmu) 220 pmu = &dummyDevice; 221 222 // Give all ISA devices a pointer to this ISA 223 pmu->setISA(this); 224 225 system = dynamic_cast<ArmSystem *>(p->system); 226 227 // Cache system-level properties 228 if (FullSystem && system) { 229 haveSecurity = system->haveSecurity(); 230 haveLPAE = system->haveLPAE(); 231 haveVirtualization = system->haveVirtualization(); 232 haveLargeAsid64 = system->haveLargeAsid64(); 233 physAddrRange64 = system->physAddrRange64(); 234 } else { 235 haveSecurity = haveLPAE = haveVirtualization = false; 236 haveLargeAsid64 = false; 237 physAddrRange64 = 32; // dummy value 238 } 239 240 /** Fill in the miscReg translation table */ 241 for (auto sw : MiscRegSwitch) { 242 lookUpMiscReg[sw.index] = sw.entry; 243 } 244 245 preUnflattenMiscReg(); 246 247 clear(); 248} 249 250const ArmISAParams * 251ISA::params() const 252{ 253 return dynamic_cast<const Params *>(_params); 254} 255 256void 257ISA::clear() 258{ 259 const Params *p(params()); 260 261 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 262 memset(miscRegs, 0, sizeof(miscRegs)); 263 264 // Initialize configurable default values 265 miscRegs[MISCREG_MIDR] = p->midr; 266 miscRegs[MISCREG_MIDR_EL1] = p->midr; 267 miscRegs[MISCREG_VPIDR] = p->midr; 268 269 if (FullSystem && system->highestELIs64()) { 270 // Initialize AArch64 state 271 clear64(p); 272 return; 273 } 274 275 // Initialize AArch32 state... 276 277 CPSR cpsr = 0; 278 cpsr.mode = MODE_USER; 279 miscRegs[MISCREG_CPSR] = cpsr; 280 updateRegMap(cpsr); 281 282 SCTLR sctlr = 0; 283 sctlr.te = (bool) sctlr_rst.te; 284 sctlr.nmfi = (bool) sctlr_rst.nmfi; 285 sctlr.v = (bool) sctlr_rst.v; 286 sctlr.u = 1; 287 sctlr.xp = 1; 288 sctlr.rao2 = 1; 289 sctlr.rao3 = 1; 290 sctlr.rao4 = 0xf; // SCTLR[6:3] 291 sctlr.uci = 1; 292 sctlr.dze = 1; 293 miscRegs[MISCREG_SCTLR_NS] = sctlr; 294 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 295 miscRegs[MISCREG_HCPTR] = 0; 296 297 // Start with an event in the mailbox 298 miscRegs[MISCREG_SEV_MAILBOX] = 1; 299 300 // Separate Instruction and Data TLBs 301 miscRegs[MISCREG_TLBTR] = 1; 302 303 MVFR0 mvfr0 = 0; 304 mvfr0.advSimdRegisters = 2; 305 mvfr0.singlePrecision = 2; 306 mvfr0.doublePrecision = 2; 307 mvfr0.vfpExceptionTrapping = 0; 308 mvfr0.divide = 1; 309 mvfr0.squareRoot = 1; 310 mvfr0.shortVectors = 1; 311 mvfr0.roundingModes = 1; 312 miscRegs[MISCREG_MVFR0] = mvfr0; 313 314 MVFR1 mvfr1 = 0; 315 mvfr1.flushToZero = 1; 316 mvfr1.defaultNaN = 1; 317 mvfr1.advSimdLoadStore = 1; 318 mvfr1.advSimdInteger = 1; 319 mvfr1.advSimdSinglePrecision = 1; 320 mvfr1.advSimdHalfPrecision = 1; 321 mvfr1.vfpHalfPrecision = 1; 322 miscRegs[MISCREG_MVFR1] = mvfr1; 323 324 // Reset values of PRRR and NMRR are implementation dependent 325 326 // @todo: PRRR and NMRR in secure state? 327 miscRegs[MISCREG_PRRR_NS] = 328 (1 << 19) | // 19 329 (0 << 18) | // 18 330 (0 << 17) | // 17 331 (1 << 16) | // 16 332 (2 << 14) | // 15:14 333 (0 << 12) | // 13:12 334 (2 << 10) | // 11:10 335 (2 << 8) | // 9:8 336 (2 << 6) | // 7:6 337 (2 << 4) | // 5:4 338 (1 << 2) | // 3:2 339 0; // 1:0 340 miscRegs[MISCREG_NMRR_NS] = 341 (1 << 30) | // 31:30 342 (0 << 26) | // 27:26 343 (0 << 24) | // 25:24 344 (3 << 22) | // 23:22 345 (2 << 20) | // 21:20 346 (0 << 18) | // 19:18 347 (0 << 16) | // 17:16 348 (1 << 14) | // 15:14 349 (0 << 12) | // 13:12 350 (2 << 10) | // 11:10 351 (0 << 8) | // 9:8 352 (3 << 6) | // 7:6 353 (2 << 4) | // 5:4 354 (0 << 2) | // 3:2 355 0; // 1:0 356 357 miscRegs[MISCREG_CPACR] = 0; 358 359 360 miscRegs[MISCREG_ID_PFR0] = p->id_pfr0; 361 miscRegs[MISCREG_ID_PFR1] = p->id_pfr1; 362 363 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 364 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 365 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 366 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 367 368 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 369 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 370 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 371 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 372 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 373 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 374 375 miscRegs[MISCREG_FPSID] = p->fpsid; 376 377 if (haveLPAE) { 378 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 379 ttbcr.eae = 0; 380 miscRegs[MISCREG_TTBCR_NS] = ttbcr; 381 // Enforce consistency with system-level settings 382 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 383 } 384 385 if (haveSecurity) { 386 miscRegs[MISCREG_SCTLR_S] = sctlr; 387 miscRegs[MISCREG_SCR] = 0; 388 miscRegs[MISCREG_VBAR_S] = 0; 389 } else { 390 // we're always non-secure 391 miscRegs[MISCREG_SCR] = 1; 392 } 393 394 //XXX We need to initialize the rest of the state. 395} 396 397void 398ISA::clear64(const ArmISAParams *p) 399{ 400 CPSR cpsr = 0; 401 Addr rvbar = system->resetAddr64(); 402 switch (system->highestEL()) { 403 // Set initial EL to highest implemented EL using associated stack 404 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 405 // value 406 case EL3: 407 cpsr.mode = MODE_EL3H; 408 miscRegs[MISCREG_RVBAR_EL3] = rvbar; 409 break; 410 case EL2: 411 cpsr.mode = MODE_EL2H; 412 miscRegs[MISCREG_RVBAR_EL2] = rvbar; 413 break; 414 case EL1: 415 cpsr.mode = MODE_EL1H; 416 miscRegs[MISCREG_RVBAR_EL1] = rvbar; 417 break; 418 default: 419 panic("Invalid highest implemented exception level"); 420 break; 421 } 422 423 // Initialize rest of CPSR 424 cpsr.daif = 0xf; // Mask all interrupts 425 cpsr.ss = 0; 426 cpsr.il = 0; 427 miscRegs[MISCREG_CPSR] = cpsr; 428 updateRegMap(cpsr); 429 430 // Initialize other control registers 431 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 432 if (haveSecurity) { 433 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830; 434 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 435 } else if (haveVirtualization) { 436 // also MISCREG_SCTLR_EL2 (by mapping) 437 miscRegs[MISCREG_HSCTLR] = 0x30c50830; 438 } else { 439 // also MISCREG_SCTLR_EL1 (by mapping) 440 miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init 441 // Always non-secure 442 miscRegs[MISCREG_SCR_EL3] = 1; 443 } 444 445 // Initialize configurable id registers 446 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 447 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 448 miscRegs[MISCREG_ID_AA64DFR0_EL1] = 449 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 450 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 451 452 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 453 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 454 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 455 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 456 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 457 miscRegs[MISCREG_ID_AA64PFR0_EL1] = p->id_aa64pfr0_el1; 458 miscRegs[MISCREG_ID_AA64PFR1_EL1] = p->id_aa64pfr1_el1; 459 460 miscRegs[MISCREG_ID_DFR0_EL1] = 461 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 462 463 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 464 465 // Enforce consistency with system-level settings... 466 467 // EL3 468 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 469 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 470 haveSecurity ? 0x2 : 0x0); 471 // EL2 472 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 473 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 474 haveVirtualization ? 0x2 : 0x0); 475 // Large ASID support 476 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 477 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 478 haveLargeAsid64 ? 0x2 : 0x0); 479 // Physical address size 480 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 481 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 482 encodePhysAddrRange64(physAddrRange64)); 483} 484 485MiscReg 486ISA::readMiscRegNoEffect(int misc_reg) const 487{ 488 assert(misc_reg < NumMiscRegs); 489 490 int flat_idx = flattenMiscIndex(misc_reg); // Note: indexes of AArch64 491 // registers are left unchanged 492 MiscReg val; 493 494 if (lookUpMiscReg[flat_idx].lower == 0 || flat_idx == MISCREG_SPSR) { 495 if (flat_idx == MISCREG_SPSR) 496 flat_idx = flattenMiscIndex(MISCREG_SPSR); 497 val = miscRegs[flat_idx]; 498 } else 499 if (lookUpMiscReg[flat_idx].upper > 0) 500 val = ((miscRegs[lookUpMiscReg[flat_idx].lower] & mask(32)) 501 | (miscRegs[lookUpMiscReg[flat_idx].upper] << 32)); 502 else 503 val = miscRegs[lookUpMiscReg[flat_idx].lower]; 504 505 return val; 506} 507 508 509MiscReg 510ISA::readMiscReg(int misc_reg, ThreadContext *tc) 511{ 512 CPSR cpsr = 0; 513 PCState pc = 0; 514 SCR scr = 0; 515 516 if (misc_reg == MISCREG_CPSR) { 517 cpsr = miscRegs[misc_reg]; 518 pc = tc->pcState(); 519 cpsr.j = pc.jazelle() ? 1 : 0; 520 cpsr.t = pc.thumb() ? 1 : 0; 521 return cpsr; 522 } 523 524#ifndef NDEBUG 525 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 526 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 527 warn("Unimplemented system register %s read.\n", 528 miscRegName[misc_reg]); 529 else 530 panic("Unimplemented system register %s read.\n", 531 miscRegName[misc_reg]); 532 } 533#endif 534 535 switch (unflattenMiscReg(misc_reg)) { 536 case MISCREG_HCR: 537 { 538 if (!haveVirtualization) 539 return 0; 540 else 541 return readMiscRegNoEffect(MISCREG_HCR); 542 } 543 case MISCREG_CPACR: 544 { 545 const uint32_t ones = (uint32_t)(-1); 546 CPACR cpacrMask = 0; 547 // Only cp10, cp11, and ase are implemented, nothing else should 548 // be readable? (straight copy from the write code) 549 cpacrMask.cp10 = ones; 550 cpacrMask.cp11 = ones; 551 cpacrMask.asedis = ones; 552 553 // Security Extensions may limit the readability of CPACR 554 if (haveSecurity) { 555 scr = readMiscRegNoEffect(MISCREG_SCR); 556 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 557 if (scr.ns && (cpsr.mode != MODE_MON)) { 558 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 559 // NB: Skipping the full loop, here 560 if (!nsacr.cp10) cpacrMask.cp10 = 0; 561 if (!nsacr.cp11) cpacrMask.cp11 = 0; 562 } 563 } 564 MiscReg val = readMiscRegNoEffect(MISCREG_CPACR); 565 val &= cpacrMask; 566 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 567 miscRegName[misc_reg], val); 568 return val; 569 } 570 case MISCREG_MPIDR: 571 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 572 scr = readMiscRegNoEffect(MISCREG_SCR); 573 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 574 return getMPIDR(system, tc); 575 } else { 576 return readMiscReg(MISCREG_VMPIDR, tc); 577 } 578 break; 579 case MISCREG_MPIDR_EL1: 580 // @todo in the absence of v8 virtualization support just return MPIDR_EL1 581 return getMPIDR(system, tc) & 0xffffffff; 582 case MISCREG_VMPIDR: 583 // top bit defined as RES1 584 return readMiscRegNoEffect(misc_reg) | 0x80000000; 585 case MISCREG_ID_AFR0: // not implemented, so alias MIDR 586 case MISCREG_REVIDR: // not implemented, so alias MIDR 587 case MISCREG_MIDR: 588 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 589 scr = readMiscRegNoEffect(MISCREG_SCR); 590 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 591 return readMiscRegNoEffect(misc_reg); 592 } else { 593 return readMiscRegNoEffect(MISCREG_VPIDR); 594 } 595 break; 596 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 597 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 598 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 599 case MISCREG_AIDR: // AUX ID set to 0 600 case MISCREG_TCMTR: // No TCM's 601 return 0; 602 603 case MISCREG_CLIDR: 604 warn_once("The clidr register always reports 0 caches.\n"); 605 warn_once("clidr LoUIS field of 0b001 to match current " 606 "ARM implementations.\n"); 607 return 0x00200000; 608 case MISCREG_CCSIDR: 609 warn_once("The ccsidr register isn't implemented and " 610 "always reads as 0.\n"); 611 break; 612 case MISCREG_CTR: 613 { 614 //all caches have the same line size in gem5 615 //4 byte words in ARM 616 unsigned lineSizeWords = 617 tc->getSystemPtr()->cacheLineSize() / 4; 618 unsigned log2LineSizeWords = 0; 619 620 while (lineSizeWords >>= 1) { 621 ++log2LineSizeWords; 622 } 623 624 CTR ctr = 0; 625 //log2 of minimun i-cache line size (words) 626 ctr.iCacheLineSize = log2LineSizeWords; 627 //b11 - gem5 uses pipt 628 ctr.l1IndexPolicy = 0x3; 629 //log2 of minimum d-cache line size (words) 630 ctr.dCacheLineSize = log2LineSizeWords; 631 //log2 of max reservation size (words) 632 ctr.erg = log2LineSizeWords; 633 //log2 of max writeback size (words) 634 ctr.cwg = log2LineSizeWords; 635 //b100 - gem5 format is ARMv7 636 ctr.format = 0x4; 637 638 return ctr; 639 } 640 case MISCREG_ACTLR: 641 warn("Not doing anything for miscreg ACTLR\n"); 642 break; 643 644 case MISCREG_PMXEVTYPER_PMCCFILTR: 645 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 646 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 647 case MISCREG_PMCR ... MISCREG_PMOVSSET: 648 return pmu->readMiscReg(misc_reg); 649 650 case MISCREG_CPSR_Q: 651 panic("shouldn't be reading this register seperately\n"); 652 case MISCREG_FPSCR_QC: 653 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 654 case MISCREG_FPSCR_EXC: 655 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 656 case MISCREG_FPSR: 657 { 658 const uint32_t ones = (uint32_t)(-1); 659 FPSCR fpscrMask = 0; 660 fpscrMask.ioc = ones; 661 fpscrMask.dzc = ones; 662 fpscrMask.ofc = ones; 663 fpscrMask.ufc = ones; 664 fpscrMask.ixc = ones; 665 fpscrMask.idc = ones; 666 fpscrMask.qc = ones; 667 fpscrMask.v = ones; 668 fpscrMask.c = ones; 669 fpscrMask.z = ones; 670 fpscrMask.n = ones; 671 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 672 } 673 case MISCREG_FPCR: 674 { 675 const uint32_t ones = (uint32_t)(-1); 676 FPSCR fpscrMask = 0; 677 fpscrMask.ioe = ones; 678 fpscrMask.dze = ones; 679 fpscrMask.ofe = ones; 680 fpscrMask.ufe = ones; 681 fpscrMask.ixe = ones; 682 fpscrMask.ide = ones; 683 fpscrMask.len = ones; 684 fpscrMask.stride = ones; 685 fpscrMask.rMode = ones; 686 fpscrMask.fz = ones; 687 fpscrMask.dn = ones; 688 fpscrMask.ahp = ones; 689 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 690 } 691 case MISCREG_NZCV: 692 { 693 CPSR cpsr = 0; 694 cpsr.nz = tc->readCCReg(CCREG_NZ); 695 cpsr.c = tc->readCCReg(CCREG_C); 696 cpsr.v = tc->readCCReg(CCREG_V); 697 return cpsr; 698 } 699 case MISCREG_DAIF: 700 { 701 CPSR cpsr = 0; 702 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 703 return cpsr; 704 } 705 case MISCREG_SP_EL0: 706 { 707 return tc->readIntReg(INTREG_SP0); 708 } 709 case MISCREG_SP_EL1: 710 { 711 return tc->readIntReg(INTREG_SP1); 712 } 713 case MISCREG_SP_EL2: 714 { 715 return tc->readIntReg(INTREG_SP2); 716 } 717 case MISCREG_SPSEL: 718 { 719 return miscRegs[MISCREG_CPSR] & 0x1; 720 } 721 case MISCREG_CURRENTEL: 722 { 723 return miscRegs[MISCREG_CPSR] & 0xc; 724 } 725 case MISCREG_L2CTLR: 726 { 727 // mostly unimplemented, just set NumCPUs field from sim and return 728 L2CTLR l2ctlr = 0; 729 // b00:1CPU to b11:4CPUs 730 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 731 return l2ctlr; 732 } 733 case MISCREG_DBGDIDR: 734 /* For now just implement the version number. 735 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 736 */ 737 return 0x5 << 16; 738 case MISCREG_DBGDSCRint: 739 return 0; 740 case MISCREG_ISR: 741 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 742 readMiscRegNoEffect(MISCREG_HCR), 743 readMiscRegNoEffect(MISCREG_CPSR), 744 readMiscRegNoEffect(MISCREG_SCR)); 745 case MISCREG_ISR_EL1: 746 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 747 readMiscRegNoEffect(MISCREG_HCR_EL2), 748 readMiscRegNoEffect(MISCREG_CPSR), 749 readMiscRegNoEffect(MISCREG_SCR_EL3)); 750 case MISCREG_DCZID_EL0: 751 return 0x04; // DC ZVA clear 64-byte chunks 752 case MISCREG_HCPTR: 753 { 754 MiscReg val = readMiscRegNoEffect(misc_reg); 755 // The trap bit associated with CP14 is defined as RAZ 756 val &= ~(1 << 14); 757 // If a CP bit in NSACR is 0 then the corresponding bit in 758 // HCPTR is RAO/WI 759 bool secure_lookup = haveSecurity && 760 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 761 readMiscRegNoEffect(MISCREG_CPSR)); 762 if (!secure_lookup) { 763 MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR); 764 val |= (mask ^ 0x7FFF) & 0xBFFF; 765 } 766 // Set the bits for unimplemented coprocessors to RAO/WI 767 val |= 0x33FF; 768 return (val); 769 } 770 case MISCREG_HDFAR: // alias for secure DFAR 771 return readMiscRegNoEffect(MISCREG_DFAR_S); 772 case MISCREG_HIFAR: // alias for secure IFAR 773 return readMiscRegNoEffect(MISCREG_IFAR_S); 774 case MISCREG_HVBAR: // bottom bits reserved 775 return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0; 776 case MISCREG_SCTLR: 777 return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818; 778 case MISCREG_SCTLR_EL1: 779 return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800; 780 case MISCREG_SCTLR_EL2: 781 case MISCREG_SCTLR_EL3: 782 case MISCREG_HSCTLR: 783 return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; 784 785 // Generic Timer registers 786 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 787 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 788 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 789 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 790 return getGenericTimer(tc).readMiscReg(misc_reg); 791 792 default: 793 break; 794 795 } 796 return readMiscRegNoEffect(misc_reg); 797} 798 799void 800ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 801{ 802 assert(misc_reg < NumMiscRegs); 803 804 int flat_idx = flattenMiscIndex(misc_reg); // Note: indexes of AArch64 805 // registers are left unchanged 806 807 int flat_idx2 = lookUpMiscReg[flat_idx].upper; 808 809 if (flat_idx2 > 0) { 810 miscRegs[lookUpMiscReg[flat_idx].lower] = bits(val, 31, 0); 811 miscRegs[flat_idx2] = bits(val, 63, 32); 812 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 813 misc_reg, flat_idx, flat_idx2, val); 814 } else { 815 if (flat_idx == MISCREG_SPSR) 816 flat_idx = flattenMiscIndex(MISCREG_SPSR); 817 else 818 flat_idx = (lookUpMiscReg[flat_idx].lower > 0) ? 819 lookUpMiscReg[flat_idx].lower : flat_idx; 820 miscRegs[flat_idx] = val; 821 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 822 misc_reg, flat_idx, val); 823 } 824} 825 826void 827ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 828{ 829 830 MiscReg newVal = val; 831 int x; 832 bool secure_lookup; 833 bool hyp; 834 System *sys; 835 ThreadContext *oc; 836 uint8_t target_el; 837 uint16_t asid; 838 SCR scr; 839 840 if (misc_reg == MISCREG_CPSR) { 841 updateRegMap(val); 842 843 844 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 845 int old_mode = old_cpsr.mode; 846 CPSR cpsr = val; 847 if (old_mode != cpsr.mode) { 848 tc->getITBPtr()->invalidateMiscReg(); 849 tc->getDTBPtr()->invalidateMiscReg(); 850 } 851 852 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 853 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 854 PCState pc = tc->pcState(); 855 pc.nextThumb(cpsr.t); 856 pc.nextJazelle(cpsr.j); 857 858 // Follow slightly different semantics if a CheckerCPU object 859 // is connected 860 CheckerCPU *checker = tc->getCheckerCpuPtr(); 861 if (checker) { 862 tc->pcStateNoRecord(pc); 863 } else { 864 tc->pcState(pc); 865 } 866 } else { 867#ifndef NDEBUG 868 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 869 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 870 warn("Unimplemented system register %s write with %#x.\n", 871 miscRegName[misc_reg], val); 872 else 873 panic("Unimplemented system register %s write with %#x.\n", 874 miscRegName[misc_reg], val); 875 } 876#endif 877 switch (unflattenMiscReg(misc_reg)) { 878 case MISCREG_CPACR: 879 { 880 881 const uint32_t ones = (uint32_t)(-1); 882 CPACR cpacrMask = 0; 883 // Only cp10, cp11, and ase are implemented, nothing else should 884 // be writable 885 cpacrMask.cp10 = ones; 886 cpacrMask.cp11 = ones; 887 cpacrMask.asedis = ones; 888 889 // Security Extensions may limit the writability of CPACR 890 if (haveSecurity) { 891 scr = readMiscRegNoEffect(MISCREG_SCR); 892 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 893 if (scr.ns && (cpsr.mode != MODE_MON)) { 894 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 895 // NB: Skipping the full loop, here 896 if (!nsacr.cp10) cpacrMask.cp10 = 0; 897 if (!nsacr.cp11) cpacrMask.cp11 = 0; 898 } 899 } 900 901 MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR); 902 newVal &= cpacrMask; 903 newVal |= old_val & ~cpacrMask; 904 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 905 miscRegName[misc_reg], newVal); 906 } 907 break; 908 case MISCREG_CPACR_EL1: 909 { 910 const uint32_t ones = (uint32_t)(-1); 911 CPACR cpacrMask = 0; 912 cpacrMask.tta = ones; 913 cpacrMask.fpen = ones; 914 newVal &= cpacrMask; 915 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 916 miscRegName[misc_reg], newVal); 917 } 918 break; 919 case MISCREG_CPTR_EL2: 920 { 921 const uint32_t ones = (uint32_t)(-1); 922 CPTR cptrMask = 0; 923 cptrMask.tcpac = ones; 924 cptrMask.tta = ones; 925 cptrMask.tfp = ones; 926 newVal &= cptrMask; 927 cptrMask = 0; 928 cptrMask.res1_13_12_el2 = ones; 929 cptrMask.res1_9_0_el2 = ones; 930 newVal |= cptrMask; 931 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 932 miscRegName[misc_reg], newVal); 933 } 934 break; 935 case MISCREG_CPTR_EL3: 936 { 937 const uint32_t ones = (uint32_t)(-1); 938 CPTR cptrMask = 0; 939 cptrMask.tcpac = ones; 940 cptrMask.tta = ones; 941 cptrMask.tfp = ones; 942 newVal &= cptrMask; 943 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 944 miscRegName[misc_reg], newVal); 945 } 946 break; 947 case MISCREG_CSSELR: 948 warn_once("The csselr register isn't implemented.\n"); 949 return; 950 951 case MISCREG_DC_ZVA_Xt: 952 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 953 return; 954 955 case MISCREG_FPSCR: 956 { 957 const uint32_t ones = (uint32_t)(-1); 958 FPSCR fpscrMask = 0; 959 fpscrMask.ioc = ones; 960 fpscrMask.dzc = ones; 961 fpscrMask.ofc = ones; 962 fpscrMask.ufc = ones; 963 fpscrMask.ixc = ones; 964 fpscrMask.idc = ones; 965 fpscrMask.ioe = ones; 966 fpscrMask.dze = ones; 967 fpscrMask.ofe = ones; 968 fpscrMask.ufe = ones; 969 fpscrMask.ixe = ones; 970 fpscrMask.ide = ones; 971 fpscrMask.len = ones; 972 fpscrMask.stride = ones; 973 fpscrMask.rMode = ones; 974 fpscrMask.fz = ones; 975 fpscrMask.dn = ones; 976 fpscrMask.ahp = ones; 977 fpscrMask.qc = ones; 978 fpscrMask.v = ones; 979 fpscrMask.c = ones; 980 fpscrMask.z = ones; 981 fpscrMask.n = ones; 982 newVal = (newVal & (uint32_t)fpscrMask) | 983 (readMiscRegNoEffect(MISCREG_FPSCR) & 984 ~(uint32_t)fpscrMask); 985 tc->getDecoderPtr()->setContext(newVal); 986 } 987 break; 988 case MISCREG_FPSR: 989 { 990 const uint32_t ones = (uint32_t)(-1); 991 FPSCR fpscrMask = 0; 992 fpscrMask.ioc = ones; 993 fpscrMask.dzc = ones; 994 fpscrMask.ofc = ones; 995 fpscrMask.ufc = ones; 996 fpscrMask.ixc = ones; 997 fpscrMask.idc = ones; 998 fpscrMask.qc = ones; 999 fpscrMask.v = ones; 1000 fpscrMask.c = ones; 1001 fpscrMask.z = ones; 1002 fpscrMask.n = ones; 1003 newVal = (newVal & (uint32_t)fpscrMask) | 1004 (readMiscRegNoEffect(MISCREG_FPSCR) & 1005 ~(uint32_t)fpscrMask); 1006 misc_reg = MISCREG_FPSCR; 1007 } 1008 break; 1009 case MISCREG_FPCR: 1010 { 1011 const uint32_t ones = (uint32_t)(-1); 1012 FPSCR fpscrMask = 0; 1013 fpscrMask.ioe = ones; 1014 fpscrMask.dze = ones; 1015 fpscrMask.ofe = ones; 1016 fpscrMask.ufe = ones; 1017 fpscrMask.ixe = ones; 1018 fpscrMask.ide = ones; 1019 fpscrMask.len = ones; 1020 fpscrMask.stride = ones; 1021 fpscrMask.rMode = ones; 1022 fpscrMask.fz = ones; 1023 fpscrMask.dn = ones; 1024 fpscrMask.ahp = ones; 1025 newVal = (newVal & (uint32_t)fpscrMask) | 1026 (readMiscRegNoEffect(MISCREG_FPSCR) & 1027 ~(uint32_t)fpscrMask); 1028 misc_reg = MISCREG_FPSCR; 1029 } 1030 break; 1031 case MISCREG_CPSR_Q: 1032 { 1033 assert(!(newVal & ~CpsrMaskQ)); 1034 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 1035 misc_reg = MISCREG_CPSR; 1036 } 1037 break; 1038 case MISCREG_FPSCR_QC: 1039 { 1040 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 1041 (newVal & FpscrQcMask); 1042 misc_reg = MISCREG_FPSCR; 1043 } 1044 break; 1045 case MISCREG_FPSCR_EXC: 1046 { 1047 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 1048 (newVal & FpscrExcMask); 1049 misc_reg = MISCREG_FPSCR; 1050 } 1051 break; 1052 case MISCREG_FPEXC: 1053 { 1054 // vfpv3 architecture, section B.6.1 of DDI04068 1055 // bit 29 - valid only if fpexc[31] is 0 1056 const uint32_t fpexcMask = 0x60000000; 1057 newVal = (newVal & fpexcMask) | 1058 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 1059 } 1060 break; 1061 case MISCREG_HCR: 1062 { 1063 if (!haveVirtualization) 1064 return; 1065 } 1066 break; 1067 case MISCREG_IFSR: 1068 { 1069 // ARM ARM (ARM DDI 0406C.b) B4.1.96 1070 const uint32_t ifsrMask = 1071 mask(31, 13) | mask(11, 11) | mask(8, 6); 1072 newVal = newVal & ~ifsrMask; 1073 } 1074 break; 1075 case MISCREG_DFSR: 1076 { 1077 // ARM ARM (ARM DDI 0406C.b) B4.1.52 1078 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 1079 newVal = newVal & ~dfsrMask; 1080 } 1081 break; 1082 case MISCREG_AMAIR0: 1083 case MISCREG_AMAIR1: 1084 { 1085 // ARM ARM (ARM DDI 0406C.b) B4.1.5 1086 // Valid only with LPAE 1087 if (!haveLPAE) 1088 return; 1089 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 1090 } 1091 break; 1092 case MISCREG_SCR: 1093 tc->getITBPtr()->invalidateMiscReg(); 1094 tc->getDTBPtr()->invalidateMiscReg(); 1095 break; 1096 case MISCREG_SCTLR: 1097 { 1098 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 1099 scr = readMiscRegNoEffect(MISCREG_SCR); 1100 MiscRegIndex sctlr_idx = (haveSecurity && !scr.ns) 1101 ? MISCREG_SCTLR_S : MISCREG_SCTLR_NS; 1102 SCTLR sctlr = miscRegs[sctlr_idx]; 1103 SCTLR new_sctlr = newVal; 1104 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 1105 miscRegs[sctlr_idx] = (MiscReg)new_sctlr; 1106 tc->getITBPtr()->invalidateMiscReg(); 1107 tc->getDTBPtr()->invalidateMiscReg(); 1108 } 1109 case MISCREG_MIDR: 1110 case MISCREG_ID_PFR0: 1111 case MISCREG_ID_PFR1: 1112 case MISCREG_ID_DFR0: 1113 case MISCREG_ID_MMFR0: 1114 case MISCREG_ID_MMFR1: 1115 case MISCREG_ID_MMFR2: 1116 case MISCREG_ID_MMFR3: 1117 case MISCREG_ID_ISAR0: 1118 case MISCREG_ID_ISAR1: 1119 case MISCREG_ID_ISAR2: 1120 case MISCREG_ID_ISAR3: 1121 case MISCREG_ID_ISAR4: 1122 case MISCREG_ID_ISAR5: 1123 1124 case MISCREG_MPIDR: 1125 case MISCREG_FPSID: 1126 case MISCREG_TLBTR: 1127 case MISCREG_MVFR0: 1128 case MISCREG_MVFR1: 1129 1130 case MISCREG_ID_AA64AFR0_EL1: 1131 case MISCREG_ID_AA64AFR1_EL1: 1132 case MISCREG_ID_AA64DFR0_EL1: 1133 case MISCREG_ID_AA64DFR1_EL1: 1134 case MISCREG_ID_AA64ISAR0_EL1: 1135 case MISCREG_ID_AA64ISAR1_EL1: 1136 case MISCREG_ID_AA64MMFR0_EL1: 1137 case MISCREG_ID_AA64MMFR1_EL1: 1138 case MISCREG_ID_AA64PFR0_EL1: 1139 case MISCREG_ID_AA64PFR1_EL1: 1140 // ID registers are constants. 1141 return; 1142 1143 // TLBI all entries, EL0&1 inner sharable (ignored) 1144 case MISCREG_TLBIALLIS: 1145 case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 1146 assert32(tc); 1147 target_el = 1; // el 0 and 1 are handled together 1148 scr = readMiscReg(MISCREG_SCR, tc); 1149 secure_lookup = haveSecurity && !scr.ns; 1150 sys = tc->getSystemPtr(); 1151 for (x = 0; x < sys->numContexts(); x++) { 1152 oc = sys->getThreadContext(x); 1153 assert(oc->getITBPtr() && oc->getDTBPtr()); 1154 oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 1155 oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 1156 1157 // If CheckerCPU is connected, need to notify it of a flush 1158 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1159 if (checker) { 1160 checker->getITBPtr()->flushAllSecurity(secure_lookup, 1161 target_el); 1162 checker->getDTBPtr()->flushAllSecurity(secure_lookup, 1163 target_el); 1164 } 1165 } 1166 return; 1167 // TLBI all entries, EL0&1, instruction side 1168 case MISCREG_ITLBIALL: 1169 assert32(tc); 1170 target_el = 1; // el 0 and 1 are handled together 1171 scr = readMiscReg(MISCREG_SCR, tc); 1172 secure_lookup = haveSecurity && !scr.ns; 1173 tc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 1174 return; 1175 // TLBI all entries, EL0&1, data side 1176 case MISCREG_DTLBIALL: 1177 assert32(tc); 1178 target_el = 1; // el 0 and 1 are handled together 1179 scr = readMiscReg(MISCREG_SCR, tc); 1180 secure_lookup = haveSecurity && !scr.ns; 1181 tc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 1182 return; 1183 // TLBI based on VA, EL0&1 inner sharable (ignored) 1184 case MISCREG_TLBIMVAIS: 1185 case MISCREG_TLBIMVA: 1186 assert32(tc); 1187 target_el = 1; // el 0 and 1 are handled together 1188 scr = readMiscReg(MISCREG_SCR, tc); 1189 secure_lookup = haveSecurity && !scr.ns; 1190 sys = tc->getSystemPtr(); 1191 for (x = 0; x < sys->numContexts(); x++) { 1192 oc = sys->getThreadContext(x); 1193 assert(oc->getITBPtr() && oc->getDTBPtr()); 1194 oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1195 bits(newVal, 7,0), 1196 secure_lookup, target_el); 1197 oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1198 bits(newVal, 7,0), 1199 secure_lookup, target_el); 1200 1201 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1202 if (checker) { 1203 checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1204 bits(newVal, 7,0), secure_lookup, target_el); 1205 checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1206 bits(newVal, 7,0), secure_lookup, target_el); 1207 } 1208 } 1209 return; 1210 // TLBI by ASID, EL0&1, inner sharable 1211 case MISCREG_TLBIASIDIS: 1212 case MISCREG_TLBIASID: 1213 assert32(tc); 1214 target_el = 1; // el 0 and 1 are handled together 1215 scr = readMiscReg(MISCREG_SCR, tc); 1216 secure_lookup = haveSecurity && !scr.ns; 1217 sys = tc->getSystemPtr(); 1218 for (x = 0; x < sys->numContexts(); x++) { 1219 oc = sys->getThreadContext(x); 1220 assert(oc->getITBPtr() && oc->getDTBPtr()); 1221 oc->getITBPtr()->flushAsid(bits(newVal, 7,0), 1222 secure_lookup, target_el); 1223 oc->getDTBPtr()->flushAsid(bits(newVal, 7,0), 1224 secure_lookup, target_el); 1225 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1226 if (checker) { 1227 checker->getITBPtr()->flushAsid(bits(newVal, 7,0), 1228 secure_lookup, target_el); 1229 checker->getDTBPtr()->flushAsid(bits(newVal, 7,0), 1230 secure_lookup, target_el); 1231 } 1232 } 1233 return; 1234 // TLBI by address, EL0&1, inner sharable (ignored) 1235 case MISCREG_TLBIMVAAIS: 1236 case MISCREG_TLBIMVAA: 1237 assert32(tc); 1238 target_el = 1; // el 0 and 1 are handled together 1239 scr = readMiscReg(MISCREG_SCR, tc); 1240 secure_lookup = haveSecurity && !scr.ns; 1241 hyp = 0; 1242 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el); 1243 return; 1244 // TLBI by address, EL2, hypervisor mode 1245 case MISCREG_TLBIMVAH: 1246 case MISCREG_TLBIMVAHIS: 1247 assert32(tc); 1248 target_el = 1; // aarch32, use hyp bit 1249 scr = readMiscReg(MISCREG_SCR, tc); 1250 secure_lookup = haveSecurity && !scr.ns; 1251 hyp = 1; 1252 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el); 1253 return; 1254 // TLBI by address and asid, EL0&1, instruction side only 1255 case MISCREG_ITLBIMVA: 1256 assert32(tc); 1257 target_el = 1; // el 0 and 1 are handled together 1258 scr = readMiscReg(MISCREG_SCR, tc); 1259 secure_lookup = haveSecurity && !scr.ns; 1260 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1261 bits(newVal, 7,0), secure_lookup, target_el); 1262 return; 1263 // TLBI by address and asid, EL0&1, data side only 1264 case MISCREG_DTLBIMVA: 1265 assert32(tc); 1266 target_el = 1; // el 0 and 1 are handled together 1267 scr = readMiscReg(MISCREG_SCR, tc); 1268 secure_lookup = haveSecurity && !scr.ns; 1269 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1270 bits(newVal, 7,0), secure_lookup, target_el); 1271 return; 1272 // TLBI by ASID, EL0&1, instrution side only 1273 case MISCREG_ITLBIASID: 1274 assert32(tc); 1275 target_el = 1; // el 0 and 1 are handled together 1276 scr = readMiscReg(MISCREG_SCR, tc); 1277 secure_lookup = haveSecurity && !scr.ns; 1278 tc->getITBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup, 1279 target_el); 1280 return; 1281 // TLBI by ASID EL0&1 data size only 1282 case MISCREG_DTLBIASID: 1283 assert32(tc); 1284 target_el = 1; // el 0 and 1 are handled together 1285 scr = readMiscReg(MISCREG_SCR, tc); 1286 secure_lookup = haveSecurity && !scr.ns; 1287 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup, 1288 target_el); 1289 return; 1290 // Invalidate entire Non-secure Hyp/Non-Hyp Unified TLB 1291 case MISCREG_TLBIALLNSNH: 1292 case MISCREG_TLBIALLNSNHIS: 1293 assert32(tc); 1294 target_el = 1; // el 0 and 1 are handled together 1295 hyp = 0; 1296 tlbiALLN(tc, hyp, target_el); 1297 return; 1298 // TLBI all entries, EL2, hyp, 1299 case MISCREG_TLBIALLH: 1300 case MISCREG_TLBIALLHIS: 1301 assert32(tc); 1302 target_el = 1; // aarch32, use hyp bit 1303 hyp = 1; 1304 tlbiALLN(tc, hyp, target_el); 1305 return; 1306 // AArch64 TLBI: invalidate all entries EL3 1307 case MISCREG_TLBI_ALLE3IS: 1308 case MISCREG_TLBI_ALLE3: 1309 assert64(tc); 1310 target_el = 3; 1311 secure_lookup = true; 1312 tlbiALL(tc, secure_lookup, target_el); 1313 return; 1314 // @todo: uncomment this to enable Virtualization 1315 // case MISCREG_TLBI_ALLE2IS: 1316 // case MISCREG_TLBI_ALLE2: 1317 // TLBI all entries, EL0&1 1318 case MISCREG_TLBI_ALLE1IS: 1319 case MISCREG_TLBI_ALLE1: 1320 // AArch64 TLBI: invalidate all entries, stage 1, current VMID 1321 case MISCREG_TLBI_VMALLE1IS: 1322 case MISCREG_TLBI_VMALLE1: 1323 // AArch64 TLBI: invalidate all entries, stages 1 & 2, current VMID 1324 case MISCREG_TLBI_VMALLS12E1IS: 1325 case MISCREG_TLBI_VMALLS12E1: 1326 // @todo: handle VMID and stage 2 to enable Virtualization 1327 assert64(tc); 1328 target_el = 1; // el 0 and 1 are handled together 1329 scr = readMiscReg(MISCREG_SCR, tc); 1330 secure_lookup = haveSecurity && !scr.ns; 1331 tlbiALL(tc, secure_lookup, target_el); 1332 return; 1333 // AArch64 TLBI: invalidate by VA and ASID, stage 1, current VMID 1334 // VAEx(IS) and VALEx(IS) are the same because TLBs only store entries 1335 // from the last level of translation table walks 1336 // @todo: handle VMID to enable Virtualization 1337 // TLBI all entries, EL0&1 1338 case MISCREG_TLBI_VAE3IS_Xt: 1339 case MISCREG_TLBI_VAE3_Xt: 1340 // TLBI by VA, EL3 regime stage 1, last level walk 1341 case MISCREG_TLBI_VALE3IS_Xt: 1342 case MISCREG_TLBI_VALE3_Xt: 1343 assert64(tc); 1344 target_el = 3; 1345 asid = 0xbeef; // does not matter, tlbi is global 1346 secure_lookup = true; 1347 tlbiVA(tc, newVal, asid, secure_lookup, target_el); 1348 return; 1349 // TLBI by VA, EL2 1350 case MISCREG_TLBI_VAE2IS_Xt: 1351 case MISCREG_TLBI_VAE2_Xt: 1352 // TLBI by VA, EL2, stage1 last level walk 1353 case MISCREG_TLBI_VALE2IS_Xt: 1354 case MISCREG_TLBI_VALE2_Xt: 1355 assert64(tc); 1356 target_el = 2; 1357 asid = 0xbeef; // does not matter, tlbi is global 1358 scr = readMiscReg(MISCREG_SCR, tc); 1359 secure_lookup = haveSecurity && !scr.ns; 1360 tlbiVA(tc, newVal, asid, secure_lookup, target_el); 1361 return; 1362 // TLBI by VA EL1 & 0, stage1, ASID, current VMID 1363 case MISCREG_TLBI_VAE1IS_Xt: 1364 case MISCREG_TLBI_VAE1_Xt: 1365 case MISCREG_TLBI_VALE1IS_Xt: 1366 case MISCREG_TLBI_VALE1_Xt: 1367 assert64(tc); 1368 asid = bits(newVal, 63, 48); 1369 target_el = 1; // el 0 and 1 are handled together 1370 scr = readMiscReg(MISCREG_SCR, tc); 1371 secure_lookup = haveSecurity && !scr.ns; 1372 tlbiVA(tc, newVal, asid, secure_lookup, target_el); 1373 return; 1374 // AArch64 TLBI: invalidate by ASID, stage 1, current VMID 1375 // @todo: handle VMID to enable Virtualization 1376 case MISCREG_TLBI_ASIDE1IS_Xt: 1377 case MISCREG_TLBI_ASIDE1_Xt: 1378 assert64(tc); 1379 target_el = 1; // el 0 and 1 are handled together 1380 scr = readMiscReg(MISCREG_SCR, tc); 1381 secure_lookup = haveSecurity && !scr.ns; 1382 sys = tc->getSystemPtr(); 1383 for (x = 0; x < sys->numContexts(); x++) { 1384 oc = sys->getThreadContext(x); 1385 assert(oc->getITBPtr() && oc->getDTBPtr()); 1386 asid = bits(newVal, 63, 48); 1387 if (!haveLargeAsid64) 1388 asid &= mask(8); 1389 oc->getITBPtr()->flushAsid(asid, secure_lookup, target_el); 1390 oc->getDTBPtr()->flushAsid(asid, secure_lookup, target_el); 1391 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1392 if (checker) { 1393 checker->getITBPtr()->flushAsid(asid, 1394 secure_lookup, target_el); 1395 checker->getDTBPtr()->flushAsid(asid, 1396 secure_lookup, target_el); 1397 } 1398 } 1399 return; 1400 // AArch64 TLBI: invalidate by VA, ASID, stage 1, current VMID 1401 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 1402 // entries from the last level of translation table walks 1403 // @todo: handle VMID to enable Virtualization 1404 case MISCREG_TLBI_VAAE1IS_Xt: 1405 case MISCREG_TLBI_VAAE1_Xt: 1406 case MISCREG_TLBI_VAALE1IS_Xt: 1407 case MISCREG_TLBI_VAALE1_Xt: 1408 assert64(tc); 1409 target_el = 1; // el 0 and 1 are handled together 1410 scr = readMiscReg(MISCREG_SCR, tc); 1411 secure_lookup = haveSecurity && !scr.ns; 1412 sys = tc->getSystemPtr(); 1413 for (x = 0; x < sys->numContexts(); x++) { 1414 // @todo: extra controls on TLBI broadcast? 1415 oc = sys->getThreadContext(x); 1416 assert(oc->getITBPtr() && oc->getDTBPtr()); 1417 Addr va = ((Addr) bits(newVal, 43, 0)) << 12; 1418 oc->getITBPtr()->flushMva(va, 1419 secure_lookup, false, target_el); 1420 oc->getDTBPtr()->flushMva(va, 1421 secure_lookup, false, target_el); 1422 1423 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1424 if (checker) { 1425 checker->getITBPtr()->flushMva(va, 1426 secure_lookup, false, target_el); 1427 checker->getDTBPtr()->flushMva(va, 1428 secure_lookup, false, target_el); 1429 } 1430 } 1431 return; 1432 // AArch64 TLBI: invalidate by IPA, stage 2, current VMID 1433 case MISCREG_TLBI_IPAS2LE1IS_Xt: 1434 case MISCREG_TLBI_IPAS2LE1_Xt: 1435 case MISCREG_TLBI_IPAS2E1IS_Xt: 1436 case MISCREG_TLBI_IPAS2E1_Xt: 1437 assert64(tc); 1438 target_el = 1; // EL 0 and 1 are handled together 1439 scr = readMiscReg(MISCREG_SCR, tc); 1440 secure_lookup = haveSecurity && !scr.ns; 1441 sys = tc->getSystemPtr(); 1442 for (x = 0; x < sys->numContexts(); x++) { 1443 oc = sys->getThreadContext(x); 1444 assert(oc->getITBPtr() && oc->getDTBPtr()); 1445 Addr ipa = ((Addr) bits(newVal, 35, 0)) << 12; 1446 oc->getITBPtr()->flushIpaVmid(ipa, 1447 secure_lookup, false, target_el); 1448 oc->getDTBPtr()->flushIpaVmid(ipa, 1449 secure_lookup, false, target_el); 1450 1451 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1452 if (checker) { 1453 checker->getITBPtr()->flushIpaVmid(ipa, 1454 secure_lookup, false, target_el); 1455 checker->getDTBPtr()->flushIpaVmid(ipa, 1456 secure_lookup, false, target_el); 1457 } 1458 } 1459 return; 1460 case MISCREG_ACTLR: 1461 warn("Not doing anything for write of miscreg ACTLR\n"); 1462 break; 1463 1464 case MISCREG_PMXEVTYPER_PMCCFILTR: 1465 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 1466 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 1467 case MISCREG_PMCR ... MISCREG_PMOVSSET: 1468 pmu->setMiscReg(misc_reg, newVal); 1469 break; 1470 1471 1472 case MISCREG_HSTR: // TJDBX, now redifined to be RES0 1473 { 1474 HSTR hstrMask = 0; 1475 hstrMask.tjdbx = 1; 1476 newVal &= ~((uint32_t) hstrMask); 1477 break; 1478 } 1479 case MISCREG_HCPTR: 1480 { 1481 // If a CP bit in NSACR is 0 then the corresponding bit in 1482 // HCPTR is RAO/WI. Same applies to NSASEDIS 1483 secure_lookup = haveSecurity && 1484 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 1485 readMiscRegNoEffect(MISCREG_CPSR)); 1486 if (!secure_lookup) { 1487 MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 1488 MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 1489 newVal = (newVal & ~mask) | (oldValue & mask); 1490 } 1491 break; 1492 } 1493 case MISCREG_HDFAR: // alias for secure DFAR 1494 misc_reg = MISCREG_DFAR_S; 1495 break; 1496 case MISCREG_HIFAR: // alias for secure IFAR 1497 misc_reg = MISCREG_IFAR_S; 1498 break; 1499 case MISCREG_ATS1CPR: 1500 case MISCREG_ATS1CPW: 1501 case MISCREG_ATS1CUR: 1502 case MISCREG_ATS1CUW: 1503 case MISCREG_ATS12NSOPR: 1504 case MISCREG_ATS12NSOPW: 1505 case MISCREG_ATS12NSOUR: 1506 case MISCREG_ATS12NSOUW: 1507 case MISCREG_ATS1HR: 1508 case MISCREG_ATS1HW: 1509 { 1510 Request::Flags flags = 0; 1511 BaseTLB::Mode mode = BaseTLB::Read; 1512 TLB::ArmTranslationType tranType = TLB::NormalTran; 1513 Fault fault; 1514 switch(misc_reg) { 1515 case MISCREG_ATS1CPR: 1516 flags = TLB::MustBeOne; 1517 tranType = TLB::S1CTran; 1518 mode = BaseTLB::Read; 1519 break; 1520 case MISCREG_ATS1CPW: 1521 flags = TLB::MustBeOne; 1522 tranType = TLB::S1CTran; 1523 mode = BaseTLB::Write; 1524 break; 1525 case MISCREG_ATS1CUR: 1526 flags = TLB::MustBeOne | TLB::UserMode; 1527 tranType = TLB::S1CTran; 1528 mode = BaseTLB::Read; 1529 break; 1530 case MISCREG_ATS1CUW: 1531 flags = TLB::MustBeOne | TLB::UserMode; 1532 tranType = TLB::S1CTran; 1533 mode = BaseTLB::Write; 1534 break; 1535 case MISCREG_ATS12NSOPR: 1536 if (!haveSecurity) 1537 panic("Security Extensions required for ATS12NSOPR"); 1538 flags = TLB::MustBeOne; 1539 tranType = TLB::S1S2NsTran; 1540 mode = BaseTLB::Read; 1541 break; 1542 case MISCREG_ATS12NSOPW: 1543 if (!haveSecurity) 1544 panic("Security Extensions required for ATS12NSOPW"); 1545 flags = TLB::MustBeOne; 1546 tranType = TLB::S1S2NsTran; 1547 mode = BaseTLB::Write; 1548 break; 1549 case MISCREG_ATS12NSOUR: 1550 if (!haveSecurity) 1551 panic("Security Extensions required for ATS12NSOUR"); 1552 flags = TLB::MustBeOne | TLB::UserMode; 1553 tranType = TLB::S1S2NsTran; 1554 mode = BaseTLB::Read; 1555 break; 1556 case MISCREG_ATS12NSOUW: 1557 if (!haveSecurity) 1558 panic("Security Extensions required for ATS12NSOUW"); 1559 flags = TLB::MustBeOne | TLB::UserMode; 1560 tranType = TLB::S1S2NsTran; 1561 mode = BaseTLB::Write; 1562 break; 1563 case MISCREG_ATS1HR: // only really useful from secure mode. 1564 flags = TLB::MustBeOne; 1565 tranType = TLB::HypMode; 1566 mode = BaseTLB::Read; 1567 break; 1568 case MISCREG_ATS1HW: 1569 flags = TLB::MustBeOne; 1570 tranType = TLB::HypMode; 1571 mode = BaseTLB::Write; 1572 break; 1573 } 1574 // If we're in timing mode then doing the translation in 1575 // functional mode then we're slightly distorting performance 1576 // results obtained from simulations. The translation should be 1577 // done in the same mode the core is running in. NOTE: This 1578 // can't be an atomic translation because that causes problems 1579 // with unexpected atomic snoop requests. 1580 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1581 Request req(0, val, 0, flags, Request::funcMasterId, 1582 tc->pcState().pc(), tc->contextId()); 1583 fault = tc->getDTBPtr()->translateFunctional(&req, tc, mode, tranType); 1584 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1585 HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 1586 1587 MiscReg newVal; 1588 if (fault == NoFault) { 1589 Addr paddr = req.getPaddr(); 1590 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 1591 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 1592 newVal = (paddr & mask(39, 12)) | 1593 (tc->getDTBPtr()->getAttr()); 1594 } else { 1595 newVal = (paddr & 0xfffff000) | 1596 (tc->getDTBPtr()->getAttr()); 1597 } 1598 DPRINTF(MiscRegs, 1599 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 1600 val, newVal); 1601 } else { 1602 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 1603 // Set fault bit and FSR 1604 FSR fsr = armFault->getFsr(tc); 1605 1606 newVal = ((fsr >> 9) & 1) << 11; 1607 if (newVal) { 1608 // LPAE - rearange fault status 1609 newVal |= ((fsr >> 0) & 0x3f) << 1; 1610 } else { 1611 // VMSA - rearange fault status 1612 newVal |= ((fsr >> 0) & 0xf) << 1; 1613 newVal |= ((fsr >> 10) & 0x1) << 5; 1614 newVal |= ((fsr >> 12) & 0x1) << 6; 1615 } 1616 newVal |= 0x1; // F bit 1617 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1618 newVal |= armFault->isStage2() ? 0x200 : 0; 1619 DPRINTF(MiscRegs, 1620 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 1621 val, fsr, newVal); 1622 } 1623 setMiscRegNoEffect(MISCREG_PAR, newVal); 1624 return; 1625 } 1626 case MISCREG_TTBCR: 1627 { 1628 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1629 const uint32_t ones = (uint32_t)(-1); 1630 TTBCR ttbcrMask = 0; 1631 TTBCR ttbcrNew = newVal; 1632 1633 // ARM DDI 0406C.b, ARMv7-32 1634 ttbcrMask.n = ones; // T0SZ 1635 if (haveSecurity) { 1636 ttbcrMask.pd0 = ones; 1637 ttbcrMask.pd1 = ones; 1638 } 1639 ttbcrMask.epd0 = ones; 1640 ttbcrMask.irgn0 = ones; 1641 ttbcrMask.orgn0 = ones; 1642 ttbcrMask.sh0 = ones; 1643 ttbcrMask.ps = ones; // T1SZ 1644 ttbcrMask.a1 = ones; 1645 ttbcrMask.epd1 = ones; 1646 ttbcrMask.irgn1 = ones; 1647 ttbcrMask.orgn1 = ones; 1648 ttbcrMask.sh1 = ones; 1649 if (haveLPAE) 1650 ttbcrMask.eae = ones; 1651 1652 if (haveLPAE && ttbcrNew.eae) { 1653 newVal = newVal & ttbcrMask; 1654 } else { 1655 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 1656 } 1657 } 1658 case MISCREG_TTBR0: 1659 case MISCREG_TTBR1: 1660 { 1661 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1662 if (haveLPAE) { 1663 if (ttbcr.eae) { 1664 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 1665 // ARMv8 AArch32 bit 63-56 only 1666 uint64_t ttbrMask = mask(63,56) | mask(47,40); 1667 newVal = (newVal & (~ttbrMask)); 1668 } 1669 } 1670 } 1671 case MISCREG_SCTLR_EL1: 1672 { 1673 tc->getITBPtr()->invalidateMiscReg(); 1674 tc->getDTBPtr()->invalidateMiscReg(); 1675 setMiscRegNoEffect(misc_reg, newVal); 1676 } 1677 case MISCREG_CONTEXTIDR: 1678 case MISCREG_PRRR: 1679 case MISCREG_NMRR: 1680 case MISCREG_MAIR0: 1681 case MISCREG_MAIR1: 1682 case MISCREG_DACR: 1683 case MISCREG_VTTBR: 1684 case MISCREG_SCR_EL3: 1685 case MISCREG_HCR_EL2: 1686 case MISCREG_TCR_EL1: 1687 case MISCREG_TCR_EL2: 1688 case MISCREG_TCR_EL3: 1689 case MISCREG_SCTLR_EL2: 1690 case MISCREG_SCTLR_EL3: 1691 case MISCREG_HSCTLR: 1692 case MISCREG_TTBR0_EL1: 1693 case MISCREG_TTBR1_EL1: 1694 case MISCREG_TTBR0_EL2: 1695 case MISCREG_TTBR0_EL3: 1696 tc->getITBPtr()->invalidateMiscReg(); 1697 tc->getDTBPtr()->invalidateMiscReg(); 1698 break; 1699 case MISCREG_NZCV: 1700 { 1701 CPSR cpsr = val; 1702 1703 tc->setCCReg(CCREG_NZ, cpsr.nz); 1704 tc->setCCReg(CCREG_C, cpsr.c); 1705 tc->setCCReg(CCREG_V, cpsr.v); 1706 } 1707 break; 1708 case MISCREG_DAIF: 1709 { 1710 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1711 cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 1712 newVal = cpsr; 1713 misc_reg = MISCREG_CPSR; 1714 } 1715 break; 1716 case MISCREG_SP_EL0: 1717 tc->setIntReg(INTREG_SP0, newVal); 1718 break; 1719 case MISCREG_SP_EL1: 1720 tc->setIntReg(INTREG_SP1, newVal); 1721 break; 1722 case MISCREG_SP_EL2: 1723 tc->setIntReg(INTREG_SP2, newVal); 1724 break; 1725 case MISCREG_SPSEL: 1726 { 1727 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1728 cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 1729 newVal = cpsr; 1730 misc_reg = MISCREG_CPSR; 1731 } 1732 break; 1733 case MISCREG_CURRENTEL: 1734 { 1735 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1736 cpsr.el = (uint8_t) ((CPSR) newVal).el; 1737 newVal = cpsr; 1738 misc_reg = MISCREG_CPSR; 1739 } 1740 break; 1741 case MISCREG_AT_S1E1R_Xt: 1742 case MISCREG_AT_S1E1W_Xt: 1743 case MISCREG_AT_S1E0R_Xt: 1744 case MISCREG_AT_S1E0W_Xt: 1745 case MISCREG_AT_S1E2R_Xt: 1746 case MISCREG_AT_S1E2W_Xt: 1747 case MISCREG_AT_S12E1R_Xt: 1748 case MISCREG_AT_S12E1W_Xt: 1749 case MISCREG_AT_S12E0R_Xt: 1750 case MISCREG_AT_S12E0W_Xt: 1751 case MISCREG_AT_S1E3R_Xt: 1752 case MISCREG_AT_S1E3W_Xt: 1753 { 1754 RequestPtr req = new Request; 1755 Request::Flags flags = 0; 1756 BaseTLB::Mode mode = BaseTLB::Read; 1757 TLB::ArmTranslationType tranType = TLB::NormalTran; 1758 Fault fault; 1759 switch(misc_reg) { 1760 case MISCREG_AT_S1E1R_Xt: 1761 flags = TLB::MustBeOne; 1762 tranType = TLB::S1E1Tran; 1763 mode = BaseTLB::Read; 1764 break; 1765 case MISCREG_AT_S1E1W_Xt: 1766 flags = TLB::MustBeOne; 1767 tranType = TLB::S1E1Tran; 1768 mode = BaseTLB::Write; 1769 break; 1770 case MISCREG_AT_S1E0R_Xt: 1771 flags = TLB::MustBeOne | TLB::UserMode; 1772 tranType = TLB::S1E0Tran; 1773 mode = BaseTLB::Read; 1774 break; 1775 case MISCREG_AT_S1E0W_Xt: 1776 flags = TLB::MustBeOne | TLB::UserMode; 1777 tranType = TLB::S1E0Tran; 1778 mode = BaseTLB::Write; 1779 break; 1780 case MISCREG_AT_S1E2R_Xt: 1781 flags = TLB::MustBeOne; 1782 tranType = TLB::S1E2Tran; 1783 mode = BaseTLB::Read; 1784 break; 1785 case MISCREG_AT_S1E2W_Xt: 1786 flags = TLB::MustBeOne; 1787 tranType = TLB::S1E2Tran; 1788 mode = BaseTLB::Write; 1789 break; 1790 case MISCREG_AT_S12E0R_Xt: 1791 flags = TLB::MustBeOne | TLB::UserMode; 1792 tranType = TLB::S12E0Tran; 1793 mode = BaseTLB::Read; 1794 break; 1795 case MISCREG_AT_S12E0W_Xt: 1796 flags = TLB::MustBeOne | TLB::UserMode; 1797 tranType = TLB::S12E0Tran; 1798 mode = BaseTLB::Write; 1799 break; 1800 case MISCREG_AT_S12E1R_Xt: 1801 flags = TLB::MustBeOne; 1802 tranType = TLB::S12E1Tran; 1803 mode = BaseTLB::Read; 1804 break; 1805 case MISCREG_AT_S12E1W_Xt: 1806 flags = TLB::MustBeOne; 1807 tranType = TLB::S12E1Tran; 1808 mode = BaseTLB::Write; 1809 break; 1810 case MISCREG_AT_S1E3R_Xt: 1811 flags = TLB::MustBeOne; 1812 tranType = TLB::S1E3Tran; 1813 mode = BaseTLB::Read; 1814 break; 1815 case MISCREG_AT_S1E3W_Xt: 1816 flags = TLB::MustBeOne; 1817 tranType = TLB::S1E3Tran; 1818 mode = BaseTLB::Write; 1819 break; 1820 } 1821 // If we're in timing mode then doing the translation in 1822 // functional mode then we're slightly distorting performance 1823 // results obtained from simulations. The translation should be 1824 // done in the same mode the core is running in. NOTE: This 1825 // can't be an atomic translation because that causes problems 1826 // with unexpected atomic snoop requests. 1827 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1828 req->setVirt(0, val, 0, flags, Request::funcMasterId, 1829 tc->pcState().pc()); 1830 req->setContext(tc->contextId()); 1831 fault = tc->getDTBPtr()->translateFunctional(req, tc, mode, 1832 tranType); 1833 1834 MiscReg newVal; 1835 if (fault == NoFault) { 1836 Addr paddr = req->getPaddr(); 1837 uint64_t attr = tc->getDTBPtr()->getAttr(); 1838 uint64_t attr1 = attr >> 56; 1839 if (!attr1 || attr1 ==0x44) { 1840 attr |= 0x100; 1841 attr &= ~ uint64_t(0x80); 1842 } 1843 newVal = (paddr & mask(47, 12)) | attr; 1844 DPRINTF(MiscRegs, 1845 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 1846 val, newVal); 1847 } else { 1848 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 1849 // Set fault bit and FSR 1850 FSR fsr = armFault->getFsr(tc); 1851 1852 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1853 if (cpsr.width) { // AArch32 1854 newVal = ((fsr >> 9) & 1) << 11; 1855 // rearrange fault status 1856 newVal |= ((fsr >> 0) & 0x3f) << 1; 1857 newVal |= 0x1; // F bit 1858 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1859 newVal |= armFault->isStage2() ? 0x200 : 0; 1860 } else { // AArch64 1861 newVal = 1; // F bit 1862 newVal |= fsr << 1; // FST 1863 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit. 1864 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 1865 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 1866 newVal |= 1 << 11; // RES1 1867 } 1868 DPRINTF(MiscRegs, 1869 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 1870 val, fsr, newVal); 1871 } 1872 delete req; 1873 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 1874 return; 1875 } 1876 case MISCREG_SPSR_EL3: 1877 case MISCREG_SPSR_EL2: 1878 case MISCREG_SPSR_EL1: 1879 // Force bits 23:21 to 0 1880 newVal = val & ~(0x7 << 21); 1881 break; 1882 case MISCREG_L2CTLR: 1883 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 1884 miscRegName[misc_reg], uint32_t(val)); 1885 break; 1886 1887 // Generic Timer registers 1888 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 1889 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 1890 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 1891 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 1892 getGenericTimer(tc).setMiscReg(misc_reg, newVal); 1893 break; 1894 } 1895 } 1896 setMiscRegNoEffect(misc_reg, newVal); 1897} 1898 1899void 1900ISA::tlbiVA(ThreadContext *tc, MiscReg newVal, uint16_t asid, 1901 bool secure_lookup, uint8_t target_el) 1902{ 1903 if (!haveLargeAsid64) 1904 asid &= mask(8); 1905 Addr va = ((Addr) bits(newVal, 43, 0)) << 12; 1906 System *sys = tc->getSystemPtr(); 1907 for (int x = 0; x < sys->numContexts(); x++) { 1908 ThreadContext *oc = sys->getThreadContext(x); 1909 assert(oc->getITBPtr() && oc->getDTBPtr()); 1910 oc->getITBPtr()->flushMvaAsid(va, asid, 1911 secure_lookup, target_el); 1912 oc->getDTBPtr()->flushMvaAsid(va, asid, 1913 secure_lookup, target_el); 1914 1915 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1916 if (checker) { 1917 checker->getITBPtr()->flushMvaAsid( 1918 va, asid, secure_lookup, target_el); 1919 checker->getDTBPtr()->flushMvaAsid( 1920 va, asid, secure_lookup, target_el); 1921 } 1922 } 1923} 1924 1925void 1926ISA::tlbiALL(ThreadContext *tc, bool secure_lookup, uint8_t target_el) 1927{ 1928 System *sys = tc->getSystemPtr(); 1929 for (int x = 0; x < sys->numContexts(); x++) { 1930 ThreadContext *oc = sys->getThreadContext(x); 1931 assert(oc->getITBPtr() && oc->getDTBPtr()); 1932 oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 1933 oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 1934 1935 // If CheckerCPU is connected, need to notify it of a flush 1936 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1937 if (checker) { 1938 checker->getITBPtr()->flushAllSecurity(secure_lookup, 1939 target_el); 1940 checker->getDTBPtr()->flushAllSecurity(secure_lookup, 1941 target_el); 1942 } 1943 } 1944} 1945 1946void 1947ISA::tlbiALLN(ThreadContext *tc, bool hyp, uint8_t target_el) 1948{ 1949 System *sys = tc->getSystemPtr(); 1950 for (int x = 0; x < sys->numContexts(); x++) { 1951 ThreadContext *oc = sys->getThreadContext(x); 1952 assert(oc->getITBPtr() && oc->getDTBPtr()); 1953 oc->getITBPtr()->flushAllNs(hyp, target_el); 1954 oc->getDTBPtr()->flushAllNs(hyp, target_el); 1955 1956 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1957 if (checker) { 1958 checker->getITBPtr()->flushAllNs(hyp, target_el); 1959 checker->getDTBPtr()->flushAllNs(hyp, target_el); 1960 } 1961 } 1962} 1963 1964void 1965ISA::tlbiMVA(ThreadContext *tc, MiscReg newVal, bool secure_lookup, bool hyp, 1966 uint8_t target_el) 1967{ 1968 System *sys = tc->getSystemPtr(); 1969 for (int x = 0; x < sys->numContexts(); x++) { 1970 ThreadContext *oc = sys->getThreadContext(x); 1971 assert(oc->getITBPtr() && oc->getDTBPtr()); 1972 oc->getITBPtr()->flushMva(mbits(newVal, 31,12), 1973 secure_lookup, hyp, target_el); 1974 oc->getDTBPtr()->flushMva(mbits(newVal, 31,12), 1975 secure_lookup, hyp, target_el); 1976 1977 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1978 if (checker) { 1979 checker->getITBPtr()->flushMva(mbits(newVal, 31,12), 1980 secure_lookup, hyp, target_el); 1981 checker->getDTBPtr()->flushMva(mbits(newVal, 31,12), 1982 secure_lookup, hyp, target_el); 1983 } 1984 } 1985} 1986 1987BaseISADevice & 1988ISA::getGenericTimer(ThreadContext *tc) 1989{ 1990 // We only need to create an ISA interface the first time we try 1991 // to access the timer. 1992 if (timer) 1993 return *timer.get(); 1994 1995 assert(system); 1996 GenericTimer *generic_timer(system->getGenericTimer()); 1997 if (!generic_timer) { 1998 panic("Trying to get a generic timer from a system that hasn't " 1999 "been configured to use a generic timer.\n"); 2000 } 2001 2002 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 2003 return *timer.get(); 2004} 2005 2006} 2007 2008ArmISA::ISA * 2009ArmISAParams::create() 2010{ 2011 return new ArmISA::ISA(this); 2012} 2013