isa.cc revision 11768:5b80960dcf08
1/* 2 * Copyright (c) 2010-2016 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 */ 40 41#include "arch/arm/isa.hh" 42#include "arch/arm/pmu.hh" 43#include "arch/arm/system.hh" 44#include "cpu/checker/cpu.hh" 45#include "cpu/base.hh" 46#include "debug/Arm.hh" 47#include "debug/MiscRegs.hh" 48#include "dev/arm/generic_timer.hh" 49#include "params/ArmISA.hh" 50#include "sim/faults.hh" 51#include "sim/stat_control.hh" 52#include "sim/system.hh" 53 54namespace ArmISA 55{ 56 57 58/** 59 * Some registers alias with others, and therefore need to be translated. 60 * For each entry: 61 * The first value is the misc register that is to be looked up 62 * the second value is the lower part of the translation 63 * the third the upper part 64 * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543 65 */ 66const struct ISA::MiscRegInitializerEntry 67 ISA::MiscRegSwitch[] = { 68 {MISCREG_ACTLR_EL1, {MISCREG_ACTLR_NS, 0}}, 69 {MISCREG_AFSR0_EL1, {MISCREG_ADFSR_NS, 0}}, 70 {MISCREG_AFSR1_EL1, {MISCREG_AIFSR_NS, 0}}, 71 {MISCREG_AMAIR_EL1, {MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS}}, 72 {MISCREG_CONTEXTIDR_EL1, {MISCREG_CONTEXTIDR_NS, 0}}, 73 {MISCREG_CPACR_EL1, {MISCREG_CPACR, 0}}, 74 {MISCREG_CSSELR_EL1, {MISCREG_CSSELR_NS, 0}}, 75 {MISCREG_DACR32_EL2, {MISCREG_DACR_NS, 0}}, 76 {MISCREG_FAR_EL1, {MISCREG_DFAR_NS, MISCREG_IFAR_NS}}, 77 // ESR_EL1 -> DFSR 78 {MISCREG_HACR_EL2, {MISCREG_HACR, 0}}, 79 {MISCREG_ACTLR_EL2, {MISCREG_HACTLR, 0}}, 80 {MISCREG_AFSR0_EL2, {MISCREG_HADFSR, 0}}, 81 {MISCREG_AFSR1_EL2, {MISCREG_HAIFSR, 0}}, 82 {MISCREG_AMAIR_EL2, {MISCREG_HAMAIR0, MISCREG_HAMAIR1}}, 83 {MISCREG_CPTR_EL2, {MISCREG_HCPTR, 0}}, 84 {MISCREG_HCR_EL2, {MISCREG_HCR, 0 /*MISCREG_HCR2*/}}, 85 {MISCREG_MDCR_EL2, {MISCREG_HDCR, 0}}, 86 {MISCREG_FAR_EL2, {MISCREG_HDFAR, MISCREG_HIFAR}}, 87 {MISCREG_MAIR_EL2, {MISCREG_HMAIR0, MISCREG_HMAIR1}}, 88 {MISCREG_HPFAR_EL2, {MISCREG_HPFAR, 0}}, 89 {MISCREG_SCTLR_EL2, {MISCREG_HSCTLR, 0}}, 90 {MISCREG_ESR_EL2, {MISCREG_HSR, 0}}, 91 {MISCREG_HSTR_EL2, {MISCREG_HSTR, 0}}, 92 {MISCREG_TCR_EL2, {MISCREG_HTCR, 0}}, 93 {MISCREG_TPIDR_EL2, {MISCREG_HTPIDR, 0}}, 94 {MISCREG_TTBR0_EL2, {MISCREG_HTTBR, 0}}, 95 {MISCREG_VBAR_EL2, {MISCREG_HVBAR, 0}}, 96 {MISCREG_IFSR32_EL2, {MISCREG_IFSR_NS, 0}}, 97 {MISCREG_MAIR_EL1, {MISCREG_PRRR_NS, MISCREG_NMRR_NS}}, 98 {MISCREG_PAR_EL1, {MISCREG_PAR_NS, 0}}, 99 // RMR_EL1 -> RMR 100 // RMR_EL2 -> HRMR 101 {MISCREG_SCTLR_EL1, {MISCREG_SCTLR_NS, 0}}, 102 {MISCREG_SDER32_EL3, {MISCREG_SDER, 0}}, 103 {MISCREG_TPIDR_EL1, {MISCREG_TPIDRPRW_NS, 0}}, 104 {MISCREG_TPIDRRO_EL0, {MISCREG_TPIDRURO_NS, 0}}, 105 {MISCREG_TPIDR_EL0, {MISCREG_TPIDRURW_NS, 0}}, 106 {MISCREG_TCR_EL1, {MISCREG_TTBCR_NS, 0}}, 107 {MISCREG_TTBR0_EL1, {MISCREG_TTBR0_NS, 0}}, 108 {MISCREG_TTBR1_EL1, {MISCREG_TTBR1_NS, 0}}, 109 {MISCREG_VBAR_EL1, {MISCREG_VBAR_NS, 0}}, 110 {MISCREG_VMPIDR_EL2, {MISCREG_VMPIDR, 0}}, 111 {MISCREG_VPIDR_EL2, {MISCREG_VPIDR, 0}}, 112 {MISCREG_VTCR_EL2, {MISCREG_VTCR, 0}}, 113 {MISCREG_VTTBR_EL2, {MISCREG_VTTBR, 0}}, 114 {MISCREG_CNTFRQ_EL0, {MISCREG_CNTFRQ, 0}}, 115 {MISCREG_CNTHCTL_EL2, {MISCREG_CNTHCTL, 0}}, 116 {MISCREG_CNTHP_CTL_EL2, {MISCREG_CNTHP_CTL, 0}}, 117 {MISCREG_CNTHP_CVAL_EL2, {MISCREG_CNTHP_CVAL, 0}}, /* 64b */ 118 {MISCREG_CNTHP_TVAL_EL2, {MISCREG_CNTHP_TVAL, 0}}, 119 {MISCREG_CNTKCTL_EL1, {MISCREG_CNTKCTL, 0}}, 120 {MISCREG_CNTP_CTL_EL0, {MISCREG_CNTP_CTL_NS, 0}}, 121 {MISCREG_CNTP_CVAL_EL0, {MISCREG_CNTP_CVAL_NS, 0}}, /* 64b */ 122 {MISCREG_CNTP_TVAL_EL0, {MISCREG_CNTP_TVAL_NS, 0}}, 123 {MISCREG_CNTPCT_EL0, {MISCREG_CNTPCT, 0}}, /* 64b */ 124 {MISCREG_CNTV_CTL_EL0, {MISCREG_CNTV_CTL, 0}}, 125 {MISCREG_CNTV_CVAL_EL0, {MISCREG_CNTV_CVAL, 0}}, /* 64b */ 126 {MISCREG_CNTV_TVAL_EL0, {MISCREG_CNTV_TVAL, 0}}, 127 {MISCREG_CNTVCT_EL0, {MISCREG_CNTVCT, 0}}, /* 64b */ 128 {MISCREG_CNTVOFF_EL2, {MISCREG_CNTVOFF, 0}}, /* 64b */ 129 {MISCREG_DBGAUTHSTATUS_EL1, {MISCREG_DBGAUTHSTATUS, 0}}, 130 {MISCREG_DBGBCR0_EL1, {MISCREG_DBGBCR0, 0}}, 131 {MISCREG_DBGBCR1_EL1, {MISCREG_DBGBCR1, 0}}, 132 {MISCREG_DBGBCR2_EL1, {MISCREG_DBGBCR2, 0}}, 133 {MISCREG_DBGBCR3_EL1, {MISCREG_DBGBCR3, 0}}, 134 {MISCREG_DBGBCR4_EL1, {MISCREG_DBGBCR4, 0}}, 135 {MISCREG_DBGBCR5_EL1, {MISCREG_DBGBCR5, 0}}, 136 {MISCREG_DBGBVR0_EL1, {MISCREG_DBGBVR0, 0 /* MISCREG_DBGBXVR0 */}}, 137 {MISCREG_DBGBVR1_EL1, {MISCREG_DBGBVR1, 0 /* MISCREG_DBGBXVR1 */}}, 138 {MISCREG_DBGBVR2_EL1, {MISCREG_DBGBVR2, 0 /* MISCREG_DBGBXVR2 */}}, 139 {MISCREG_DBGBVR3_EL1, {MISCREG_DBGBVR3, 0 /* MISCREG_DBGBXVR3 */}}, 140 {MISCREG_DBGBVR4_EL1, {MISCREG_DBGBVR4, MISCREG_DBGBXVR4}}, 141 {MISCREG_DBGBVR5_EL1, {MISCREG_DBGBVR5, MISCREG_DBGBXVR5}}, 142 {MISCREG_DBGCLAIMSET_EL1, {MISCREG_DBGCLAIMSET, 0}}, 143 {MISCREG_DBGCLAIMCLR_EL1, {MISCREG_DBGCLAIMCLR, 0}}, 144 // DBGDTR_EL0 -> DBGDTR{R or T}Xint 145 // DBGDTRRX_EL0 -> DBGDTRRXint 146 // DBGDTRTX_EL0 -> DBGDTRRXint 147 {MISCREG_DBGPRCR_EL1, {MISCREG_DBGPRCR, 0}}, 148 {MISCREG_DBGVCR32_EL2, {MISCREG_DBGVCR, 0}}, 149 {MISCREG_DBGWCR0_EL1, {MISCREG_DBGWCR0, 0}}, 150 {MISCREG_DBGWCR1_EL1, {MISCREG_DBGWCR1, 0}}, 151 {MISCREG_DBGWCR2_EL1, {MISCREG_DBGWCR2, 0}}, 152 {MISCREG_DBGWCR3_EL1, {MISCREG_DBGWCR3, 0}}, 153 {MISCREG_DBGWVR0_EL1, {MISCREG_DBGWVR0, 0}}, 154 {MISCREG_DBGWVR1_EL1, {MISCREG_DBGWVR1, 0}}, 155 {MISCREG_DBGWVR2_EL1, {MISCREG_DBGWVR2, 0}}, 156 {MISCREG_DBGWVR3_EL1, {MISCREG_DBGWVR3, 0}}, 157 {MISCREG_ID_DFR0_EL1, {MISCREG_ID_DFR0, 0}}, 158 {MISCREG_MDCCSR_EL0, {MISCREG_DBGDSCRint, 0}}, 159 {MISCREG_MDRAR_EL1, {MISCREG_DBGDRAR, 0}}, 160 {MISCREG_MDSCR_EL1, {MISCREG_DBGDSCRext, 0}}, 161 {MISCREG_OSDLR_EL1, {MISCREG_DBGOSDLR, 0}}, 162 {MISCREG_OSDTRRX_EL1, {MISCREG_DBGDTRRXext, 0}}, 163 {MISCREG_OSDTRTX_EL1, {MISCREG_DBGDTRTXext, 0}}, 164 {MISCREG_OSECCR_EL1, {MISCREG_DBGOSECCR, 0}}, 165 {MISCREG_OSLAR_EL1, {MISCREG_DBGOSLAR, 0}}, 166 {MISCREG_OSLSR_EL1, {MISCREG_DBGOSLSR, 0}}, 167 {MISCREG_PMCCNTR_EL0, {MISCREG_PMCCNTR, 0}}, 168 {MISCREG_PMCEID0_EL0, {MISCREG_PMCEID0, 0}}, 169 {MISCREG_PMCEID1_EL0, {MISCREG_PMCEID1, 0}}, 170 {MISCREG_PMCNTENSET_EL0, {MISCREG_PMCNTENSET, 0}}, 171 {MISCREG_PMCNTENCLR_EL0, {MISCREG_PMCNTENCLR, 0}}, 172 {MISCREG_PMCR_EL0, {MISCREG_PMCR, 0}}, 173/* {MISCREG_PMEVCNTR0_EL0, {MISCREG_PMEVCNTR0, 0}}, 174 {MISCREG_PMEVCNTR1_EL0, {MISCREG_PMEVCNTR1, 0}}, 175 {MISCREG_PMEVCNTR2_EL0, {MISCREG_PMEVCNTR2, 0}}, 176 {MISCREG_PMEVCNTR3_EL0, {MISCREG_PMEVCNTR3, 0}}, 177 {MISCREG_PMEVCNTR4_EL0, {MISCREG_PMEVCNTR4, 0}}, 178 {MISCREG_PMEVCNTR5_EL0, {MISCREG_PMEVCNTR5, 0}}, 179 {MISCREG_PMEVTYPER0_EL0, {MISCREG_PMEVTYPER0, 0}}, 180 {MISCREG_PMEVTYPER1_EL0, {MISCREG_PMEVTYPER1, 0}}, 181 {MISCREG_PMEVTYPER2_EL0, {MISCREG_PMEVTYPER2, 0}}, 182 {MISCREG_PMEVTYPER3_EL0, {MISCREG_PMEVTYPER3, 0}}, 183 {MISCREG_PMEVTYPER4_EL0, {MISCREG_PMEVTYPER4, 0}}, 184 {MISCREG_PMEVTYPER5_EL0, {MISCREG_PMEVTYPER5, 0}}, */ 185 {MISCREG_PMINTENCLR_EL1, {MISCREG_PMINTENCLR, 0}}, 186 {MISCREG_PMINTENSET_EL1, {MISCREG_PMINTENSET, 0}}, 187// {MISCREG_PMOVSCLR_EL0, {MISCREG_PMOVSCLR, 0}}, 188 {MISCREG_PMOVSSET_EL0, {MISCREG_PMOVSSET, 0}}, 189 {MISCREG_PMSELR_EL0, {MISCREG_PMSELR, 0}}, 190 {MISCREG_PMSWINC_EL0, {MISCREG_PMSWINC, 0}}, 191 {MISCREG_PMUSERENR_EL0, {MISCREG_PMUSERENR, 0}}, 192 {MISCREG_PMXEVCNTR_EL0, {MISCREG_PMXEVCNTR, 0}}, 193 {MISCREG_PMXEVTYPER_EL0, {MISCREG_PMXEVTYPER, 0}}, 194 195 // from ARM DDI 0487A.i, template text 196 // "AArch64 System register ___ can be mapped to 197 // AArch32 System register ___, but this is not 198 // architecturally mandated." 199 {MISCREG_SCR_EL3, {MISCREG_SCR, 0}}, // D7-2005 200 // MDCR_EL3 -> SDCR, D7-2108 (the latter is unimpl. in gem5) 201 {MISCREG_SPSR_EL1, {MISCREG_SPSR_SVC, 0}}, // C5.2.17 SPSR_EL1 202 {MISCREG_SPSR_EL2, {MISCREG_SPSR_HYP, 0}}, // C5.2.18 SPSR_EL2 203 {MISCREG_SPSR_EL3, {MISCREG_SPSR_MON, 0}}, // C5.2.19 SPSR_EL3 204}; 205 206 207ISA::ISA(Params *p) 208 : SimObject(p), 209 system(NULL), 210 _decoderFlavour(p->decoderFlavour), 211 pmu(p->pmu), 212 lookUpMiscReg(NUM_MISCREGS, {0,0}) 213{ 214 SCTLR sctlr; 215 sctlr = 0; 216 miscRegs[MISCREG_SCTLR_RST] = sctlr; 217 218 // Hook up a dummy device if we haven't been configured with a 219 // real PMU. By using a dummy device, we don't need to check that 220 // the PMU exist every time we try to access a PMU register. 221 if (!pmu) 222 pmu = &dummyDevice; 223 224 // Give all ISA devices a pointer to this ISA 225 pmu->setISA(this); 226 227 system = dynamic_cast<ArmSystem *>(p->system); 228 229 // Cache system-level properties 230 if (FullSystem && system) { 231 haveSecurity = system->haveSecurity(); 232 haveLPAE = system->haveLPAE(); 233 haveVirtualization = system->haveVirtualization(); 234 haveLargeAsid64 = system->haveLargeAsid64(); 235 physAddrRange64 = system->physAddrRange64(); 236 } else { 237 haveSecurity = haveLPAE = haveVirtualization = false; 238 haveLargeAsid64 = false; 239 physAddrRange64 = 32; // dummy value 240 } 241 242 /** Fill in the miscReg translation table */ 243 for (auto sw : MiscRegSwitch) { 244 lookUpMiscReg[sw.index] = sw.entry; 245 } 246 247 preUnflattenMiscReg(); 248 249 clear(); 250} 251 252const ArmISAParams * 253ISA::params() const 254{ 255 return dynamic_cast<const Params *>(_params); 256} 257 258void 259ISA::clear() 260{ 261 const Params *p(params()); 262 263 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 264 memset(miscRegs, 0, sizeof(miscRegs)); 265 266 // Initialize configurable default values 267 miscRegs[MISCREG_MIDR] = p->midr; 268 miscRegs[MISCREG_MIDR_EL1] = p->midr; 269 miscRegs[MISCREG_VPIDR] = p->midr; 270 271 if (FullSystem && system->highestELIs64()) { 272 // Initialize AArch64 state 273 clear64(p); 274 return; 275 } 276 277 // Initialize AArch32 state... 278 279 CPSR cpsr = 0; 280 cpsr.mode = MODE_USER; 281 miscRegs[MISCREG_CPSR] = cpsr; 282 updateRegMap(cpsr); 283 284 SCTLR sctlr = 0; 285 sctlr.te = (bool) sctlr_rst.te; 286 sctlr.nmfi = (bool) sctlr_rst.nmfi; 287 sctlr.v = (bool) sctlr_rst.v; 288 sctlr.u = 1; 289 sctlr.xp = 1; 290 sctlr.rao2 = 1; 291 sctlr.rao3 = 1; 292 sctlr.rao4 = 0xf; // SCTLR[6:3] 293 sctlr.uci = 1; 294 sctlr.dze = 1; 295 miscRegs[MISCREG_SCTLR_NS] = sctlr; 296 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 297 miscRegs[MISCREG_HCPTR] = 0; 298 299 // Start with an event in the mailbox 300 miscRegs[MISCREG_SEV_MAILBOX] = 1; 301 302 // Separate Instruction and Data TLBs 303 miscRegs[MISCREG_TLBTR] = 1; 304 305 MVFR0 mvfr0 = 0; 306 mvfr0.advSimdRegisters = 2; 307 mvfr0.singlePrecision = 2; 308 mvfr0.doublePrecision = 2; 309 mvfr0.vfpExceptionTrapping = 0; 310 mvfr0.divide = 1; 311 mvfr0.squareRoot = 1; 312 mvfr0.shortVectors = 1; 313 mvfr0.roundingModes = 1; 314 miscRegs[MISCREG_MVFR0] = mvfr0; 315 316 MVFR1 mvfr1 = 0; 317 mvfr1.flushToZero = 1; 318 mvfr1.defaultNaN = 1; 319 mvfr1.advSimdLoadStore = 1; 320 mvfr1.advSimdInteger = 1; 321 mvfr1.advSimdSinglePrecision = 1; 322 mvfr1.advSimdHalfPrecision = 1; 323 mvfr1.vfpHalfPrecision = 1; 324 miscRegs[MISCREG_MVFR1] = mvfr1; 325 326 // Reset values of PRRR and NMRR are implementation dependent 327 328 // @todo: PRRR and NMRR in secure state? 329 miscRegs[MISCREG_PRRR_NS] = 330 (1 << 19) | // 19 331 (0 << 18) | // 18 332 (0 << 17) | // 17 333 (1 << 16) | // 16 334 (2 << 14) | // 15:14 335 (0 << 12) | // 13:12 336 (2 << 10) | // 11:10 337 (2 << 8) | // 9:8 338 (2 << 6) | // 7:6 339 (2 << 4) | // 5:4 340 (1 << 2) | // 3:2 341 0; // 1:0 342 miscRegs[MISCREG_NMRR_NS] = 343 (1 << 30) | // 31:30 344 (0 << 26) | // 27:26 345 (0 << 24) | // 25:24 346 (3 << 22) | // 23:22 347 (2 << 20) | // 21:20 348 (0 << 18) | // 19:18 349 (0 << 16) | // 17:16 350 (1 << 14) | // 15:14 351 (0 << 12) | // 13:12 352 (2 << 10) | // 11:10 353 (0 << 8) | // 9:8 354 (3 << 6) | // 7:6 355 (2 << 4) | // 5:4 356 (0 << 2) | // 3:2 357 0; // 1:0 358 359 miscRegs[MISCREG_CPACR] = 0; 360 361 362 miscRegs[MISCREG_ID_PFR0] = p->id_pfr0; 363 miscRegs[MISCREG_ID_PFR1] = p->id_pfr1; 364 365 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 366 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 367 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 368 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 369 370 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 371 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 372 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 373 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 374 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 375 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 376 377 miscRegs[MISCREG_FPSID] = p->fpsid; 378 379 if (haveLPAE) { 380 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 381 ttbcr.eae = 0; 382 miscRegs[MISCREG_TTBCR_NS] = ttbcr; 383 // Enforce consistency with system-level settings 384 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 385 } 386 387 if (haveSecurity) { 388 miscRegs[MISCREG_SCTLR_S] = sctlr; 389 miscRegs[MISCREG_SCR] = 0; 390 miscRegs[MISCREG_VBAR_S] = 0; 391 } else { 392 // we're always non-secure 393 miscRegs[MISCREG_SCR] = 1; 394 } 395 396 //XXX We need to initialize the rest of the state. 397} 398 399void 400ISA::clear64(const ArmISAParams *p) 401{ 402 CPSR cpsr = 0; 403 Addr rvbar = system->resetAddr64(); 404 switch (system->highestEL()) { 405 // Set initial EL to highest implemented EL using associated stack 406 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 407 // value 408 case EL3: 409 cpsr.mode = MODE_EL3H; 410 miscRegs[MISCREG_RVBAR_EL3] = rvbar; 411 break; 412 case EL2: 413 cpsr.mode = MODE_EL2H; 414 miscRegs[MISCREG_RVBAR_EL2] = rvbar; 415 break; 416 case EL1: 417 cpsr.mode = MODE_EL1H; 418 miscRegs[MISCREG_RVBAR_EL1] = rvbar; 419 break; 420 default: 421 panic("Invalid highest implemented exception level"); 422 break; 423 } 424 425 // Initialize rest of CPSR 426 cpsr.daif = 0xf; // Mask all interrupts 427 cpsr.ss = 0; 428 cpsr.il = 0; 429 miscRegs[MISCREG_CPSR] = cpsr; 430 updateRegMap(cpsr); 431 432 // Initialize other control registers 433 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 434 if (haveSecurity) { 435 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50870; 436 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 437 } else if (haveVirtualization) { 438 miscRegs[MISCREG_SCTLR_EL2] = 0x30c50870; 439 } else { 440 miscRegs[MISCREG_SCTLR_EL1] = 0x30c50870; 441 // Always non-secure 442 miscRegs[MISCREG_SCR_EL3] = 1; 443 } 444 445 // Initialize configurable id registers 446 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 447 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 448 miscRegs[MISCREG_ID_AA64DFR0_EL1] = 449 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 450 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 451 452 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 453 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 454 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 455 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 456 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 457 miscRegs[MISCREG_ID_AA64PFR0_EL1] = p->id_aa64pfr0_el1; 458 miscRegs[MISCREG_ID_AA64PFR1_EL1] = p->id_aa64pfr1_el1; 459 460 miscRegs[MISCREG_ID_DFR0_EL1] = 461 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 462 463 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 464 465 // Enforce consistency with system-level settings... 466 467 // EL3 468 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 469 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 470 haveSecurity ? 0x2 : 0x0); 471 // EL2 472 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 473 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 474 haveVirtualization ? 0x2 : 0x0); 475 // Large ASID support 476 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 477 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 478 haveLargeAsid64 ? 0x2 : 0x0); 479 // Physical address size 480 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 481 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 482 encodePhysAddrRange64(physAddrRange64)); 483} 484 485MiscReg 486ISA::readMiscRegNoEffect(int misc_reg) const 487{ 488 assert(misc_reg < NumMiscRegs); 489 490 int flat_idx = flattenMiscIndex(misc_reg); // Note: indexes of AArch64 491 // registers are left unchanged 492 MiscReg val; 493 494 if (lookUpMiscReg[flat_idx].lower == 0 || flat_idx == MISCREG_SPSR 495 || flat_idx == MISCREG_SCTLR_EL1) { 496 if (flat_idx == MISCREG_SPSR) 497 flat_idx = flattenMiscIndex(MISCREG_SPSR); 498 if (flat_idx == MISCREG_SCTLR_EL1) 499 flat_idx = flattenMiscIndex(MISCREG_SCTLR); 500 val = miscRegs[flat_idx]; 501 } else 502 if (lookUpMiscReg[flat_idx].upper > 0) 503 val = ((miscRegs[lookUpMiscReg[flat_idx].lower] & mask(32)) 504 | (miscRegs[lookUpMiscReg[flat_idx].upper] << 32)); 505 else 506 val = miscRegs[lookUpMiscReg[flat_idx].lower]; 507 508 return val; 509} 510 511 512MiscReg 513ISA::readMiscReg(int misc_reg, ThreadContext *tc) 514{ 515 CPSR cpsr = 0; 516 PCState pc = 0; 517 SCR scr = 0; 518 519 if (misc_reg == MISCREG_CPSR) { 520 cpsr = miscRegs[misc_reg]; 521 pc = tc->pcState(); 522 cpsr.j = pc.jazelle() ? 1 : 0; 523 cpsr.t = pc.thumb() ? 1 : 0; 524 return cpsr; 525 } 526 527#ifndef NDEBUG 528 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 529 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 530 warn("Unimplemented system register %s read.\n", 531 miscRegName[misc_reg]); 532 else 533 panic("Unimplemented system register %s read.\n", 534 miscRegName[misc_reg]); 535 } 536#endif 537 538 switch (unflattenMiscReg(misc_reg)) { 539 case MISCREG_HCR: 540 { 541 if (!haveVirtualization) 542 return 0; 543 else 544 return readMiscRegNoEffect(MISCREG_HCR); 545 } 546 case MISCREG_CPACR: 547 { 548 const uint32_t ones = (uint32_t)(-1); 549 CPACR cpacrMask = 0; 550 // Only cp10, cp11, and ase are implemented, nothing else should 551 // be readable? (straight copy from the write code) 552 cpacrMask.cp10 = ones; 553 cpacrMask.cp11 = ones; 554 cpacrMask.asedis = ones; 555 556 // Security Extensions may limit the readability of CPACR 557 if (haveSecurity) { 558 scr = readMiscRegNoEffect(MISCREG_SCR); 559 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 560 if (scr.ns && (cpsr.mode != MODE_MON)) { 561 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 562 // NB: Skipping the full loop, here 563 if (!nsacr.cp10) cpacrMask.cp10 = 0; 564 if (!nsacr.cp11) cpacrMask.cp11 = 0; 565 } 566 } 567 MiscReg val = readMiscRegNoEffect(MISCREG_CPACR); 568 val &= cpacrMask; 569 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 570 miscRegName[misc_reg], val); 571 return val; 572 } 573 case MISCREG_MPIDR: 574 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 575 scr = readMiscRegNoEffect(MISCREG_SCR); 576 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 577 return getMPIDR(system, tc); 578 } else { 579 return readMiscReg(MISCREG_VMPIDR, tc); 580 } 581 break; 582 case MISCREG_MPIDR_EL1: 583 // @todo in the absence of v8 virtualization support just return MPIDR_EL1 584 return getMPIDR(system, tc) & 0xffffffff; 585 case MISCREG_VMPIDR: 586 // top bit defined as RES1 587 return readMiscRegNoEffect(misc_reg) | 0x80000000; 588 case MISCREG_ID_AFR0: // not implemented, so alias MIDR 589 case MISCREG_REVIDR: // not implemented, so alias MIDR 590 case MISCREG_MIDR: 591 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 592 scr = readMiscRegNoEffect(MISCREG_SCR); 593 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 594 return readMiscRegNoEffect(misc_reg); 595 } else { 596 return readMiscRegNoEffect(MISCREG_VPIDR); 597 } 598 break; 599 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 600 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 601 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 602 case MISCREG_AIDR: // AUX ID set to 0 603 case MISCREG_TCMTR: // No TCM's 604 return 0; 605 606 case MISCREG_CLIDR: 607 warn_once("The clidr register always reports 0 caches.\n"); 608 warn_once("clidr LoUIS field of 0b001 to match current " 609 "ARM implementations.\n"); 610 return 0x00200000; 611 case MISCREG_CCSIDR: 612 warn_once("The ccsidr register isn't implemented and " 613 "always reads as 0.\n"); 614 break; 615 case MISCREG_CTR: 616 { 617 //all caches have the same line size in gem5 618 //4 byte words in ARM 619 unsigned lineSizeWords = 620 tc->getSystemPtr()->cacheLineSize() / 4; 621 unsigned log2LineSizeWords = 0; 622 623 while (lineSizeWords >>= 1) { 624 ++log2LineSizeWords; 625 } 626 627 CTR ctr = 0; 628 //log2 of minimun i-cache line size (words) 629 ctr.iCacheLineSize = log2LineSizeWords; 630 //b11 - gem5 uses pipt 631 ctr.l1IndexPolicy = 0x3; 632 //log2 of minimum d-cache line size (words) 633 ctr.dCacheLineSize = log2LineSizeWords; 634 //log2 of max reservation size (words) 635 ctr.erg = log2LineSizeWords; 636 //log2 of max writeback size (words) 637 ctr.cwg = log2LineSizeWords; 638 //b100 - gem5 format is ARMv7 639 ctr.format = 0x4; 640 641 return ctr; 642 } 643 case MISCREG_ACTLR: 644 warn("Not doing anything for miscreg ACTLR\n"); 645 break; 646 647 case MISCREG_PMXEVTYPER_PMCCFILTR: 648 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 649 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 650 case MISCREG_PMCR ... MISCREG_PMOVSSET: 651 return pmu->readMiscReg(misc_reg); 652 653 case MISCREG_CPSR_Q: 654 panic("shouldn't be reading this register seperately\n"); 655 case MISCREG_FPSCR_QC: 656 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 657 case MISCREG_FPSCR_EXC: 658 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 659 case MISCREG_FPSR: 660 { 661 const uint32_t ones = (uint32_t)(-1); 662 FPSCR fpscrMask = 0; 663 fpscrMask.ioc = ones; 664 fpscrMask.dzc = ones; 665 fpscrMask.ofc = ones; 666 fpscrMask.ufc = ones; 667 fpscrMask.ixc = ones; 668 fpscrMask.idc = ones; 669 fpscrMask.qc = ones; 670 fpscrMask.v = ones; 671 fpscrMask.c = ones; 672 fpscrMask.z = ones; 673 fpscrMask.n = ones; 674 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 675 } 676 case MISCREG_FPCR: 677 { 678 const uint32_t ones = (uint32_t)(-1); 679 FPSCR fpscrMask = 0; 680 fpscrMask.ioe = ones; 681 fpscrMask.dze = ones; 682 fpscrMask.ofe = ones; 683 fpscrMask.ufe = ones; 684 fpscrMask.ixe = ones; 685 fpscrMask.ide = ones; 686 fpscrMask.len = ones; 687 fpscrMask.stride = ones; 688 fpscrMask.rMode = ones; 689 fpscrMask.fz = ones; 690 fpscrMask.dn = ones; 691 fpscrMask.ahp = ones; 692 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 693 } 694 case MISCREG_NZCV: 695 { 696 CPSR cpsr = 0; 697 cpsr.nz = tc->readCCReg(CCREG_NZ); 698 cpsr.c = tc->readCCReg(CCREG_C); 699 cpsr.v = tc->readCCReg(CCREG_V); 700 return cpsr; 701 } 702 case MISCREG_DAIF: 703 { 704 CPSR cpsr = 0; 705 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 706 return cpsr; 707 } 708 case MISCREG_SP_EL0: 709 { 710 return tc->readIntReg(INTREG_SP0); 711 } 712 case MISCREG_SP_EL1: 713 { 714 return tc->readIntReg(INTREG_SP1); 715 } 716 case MISCREG_SP_EL2: 717 { 718 return tc->readIntReg(INTREG_SP2); 719 } 720 case MISCREG_SPSEL: 721 { 722 return miscRegs[MISCREG_CPSR] & 0x1; 723 } 724 case MISCREG_CURRENTEL: 725 { 726 return miscRegs[MISCREG_CPSR] & 0xc; 727 } 728 case MISCREG_L2CTLR: 729 { 730 // mostly unimplemented, just set NumCPUs field from sim and return 731 L2CTLR l2ctlr = 0; 732 // b00:1CPU to b11:4CPUs 733 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 734 return l2ctlr; 735 } 736 case MISCREG_DBGDIDR: 737 /* For now just implement the version number. 738 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 739 */ 740 return 0x5 << 16; 741 case MISCREG_DBGDSCRint: 742 return 0; 743 case MISCREG_ISR: 744 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 745 readMiscRegNoEffect(MISCREG_HCR), 746 readMiscRegNoEffect(MISCREG_CPSR), 747 readMiscRegNoEffect(MISCREG_SCR)); 748 case MISCREG_ISR_EL1: 749 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 750 readMiscRegNoEffect(MISCREG_HCR_EL2), 751 readMiscRegNoEffect(MISCREG_CPSR), 752 readMiscRegNoEffect(MISCREG_SCR_EL3)); 753 case MISCREG_DCZID_EL0: 754 return 0x04; // DC ZVA clear 64-byte chunks 755 case MISCREG_HCPTR: 756 { 757 MiscReg val = readMiscRegNoEffect(misc_reg); 758 // The trap bit associated with CP14 is defined as RAZ 759 val &= ~(1 << 14); 760 // If a CP bit in NSACR is 0 then the corresponding bit in 761 // HCPTR is RAO/WI 762 bool secure_lookup = haveSecurity && 763 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 764 readMiscRegNoEffect(MISCREG_CPSR)); 765 if (!secure_lookup) { 766 MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR); 767 val |= (mask ^ 0x7FFF) & 0xBFFF; 768 } 769 // Set the bits for unimplemented coprocessors to RAO/WI 770 val |= 0x33FF; 771 return (val); 772 } 773 case MISCREG_HDFAR: // alias for secure DFAR 774 return readMiscRegNoEffect(MISCREG_DFAR_S); 775 case MISCREG_HIFAR: // alias for secure IFAR 776 return readMiscRegNoEffect(MISCREG_IFAR_S); 777 case MISCREG_HVBAR: // bottom bits reserved 778 return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0; 779 case MISCREG_SCTLR: // Some bits hardwired 780 // The FI field (bit 21) is common between S/NS versions of the register 781 return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21)) | 782 (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818; // V8 SCTLR 783 case MISCREG_SCTLR_EL1: 784 // The FI field (bit 21) is common between S/NS versions of the register 785 return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21)) | 786 (readMiscRegNoEffect(misc_reg) & 0x37DDDBFF) | 0x30D00800; // V8 SCTLR_EL1 787 case MISCREG_SCTLR_EL3: 788 // The FI field (bit 21) is common between S/NS versions of the register 789 return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21)) | 790 (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; // V8 SCTLR_EL3 791 case MISCREG_HSCTLR: // FI comes from SCTLR 792 { 793 uint32_t mask = 1 << 27; 794 return (readMiscRegNoEffect(MISCREG_HSCTLR) & ~mask) | 795 (readMiscRegNoEffect(MISCREG_SCTLR) & mask); 796 } 797 798 // Generic Timer registers 799 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 800 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 801 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 802 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 803 return getGenericTimer(tc).readMiscReg(misc_reg); 804 805 default: 806 break; 807 808 } 809 return readMiscRegNoEffect(misc_reg); 810} 811 812void 813ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 814{ 815 assert(misc_reg < NumMiscRegs); 816 817 int flat_idx = flattenMiscIndex(misc_reg); // Note: indexes of AArch64 818 // registers are left unchanged 819 820 int flat_idx2 = lookUpMiscReg[flat_idx].upper; 821 822 if (flat_idx2 > 0) { 823 miscRegs[lookUpMiscReg[flat_idx].lower] = bits(val, 31, 0); 824 miscRegs[flat_idx2] = bits(val, 63, 32); 825 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 826 misc_reg, flat_idx, flat_idx2, val); 827 } else { 828 if (flat_idx == MISCREG_SPSR) 829 flat_idx = flattenMiscIndex(MISCREG_SPSR); 830 else if (flat_idx == MISCREG_SCTLR_EL1) 831 flat_idx = flattenMiscIndex(MISCREG_SCTLR); 832 else 833 flat_idx = (lookUpMiscReg[flat_idx].lower > 0) ? 834 lookUpMiscReg[flat_idx].lower : flat_idx; 835 miscRegs[flat_idx] = val; 836 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 837 misc_reg, flat_idx, val); 838 } 839} 840 841void 842ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 843{ 844 845 MiscReg newVal = val; 846 int x; 847 bool secure_lookup; 848 bool hyp; 849 System *sys; 850 ThreadContext *oc; 851 uint8_t target_el; 852 uint16_t asid; 853 SCR scr; 854 855 if (misc_reg == MISCREG_CPSR) { 856 updateRegMap(val); 857 858 859 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 860 int old_mode = old_cpsr.mode; 861 CPSR cpsr = val; 862 if (old_mode != cpsr.mode) { 863 tc->getITBPtr()->invalidateMiscReg(); 864 tc->getDTBPtr()->invalidateMiscReg(); 865 } 866 867 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 868 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 869 PCState pc = tc->pcState(); 870 pc.nextThumb(cpsr.t); 871 pc.nextJazelle(cpsr.j); 872 873 // Follow slightly different semantics if a CheckerCPU object 874 // is connected 875 CheckerCPU *checker = tc->getCheckerCpuPtr(); 876 if (checker) { 877 tc->pcStateNoRecord(pc); 878 } else { 879 tc->pcState(pc); 880 } 881 } else { 882#ifndef NDEBUG 883 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 884 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 885 warn("Unimplemented system register %s write with %#x.\n", 886 miscRegName[misc_reg], val); 887 else 888 panic("Unimplemented system register %s write with %#x.\n", 889 miscRegName[misc_reg], val); 890 } 891#endif 892 switch (unflattenMiscReg(misc_reg)) { 893 case MISCREG_CPACR: 894 { 895 896 const uint32_t ones = (uint32_t)(-1); 897 CPACR cpacrMask = 0; 898 // Only cp10, cp11, and ase are implemented, nothing else should 899 // be writable 900 cpacrMask.cp10 = ones; 901 cpacrMask.cp11 = ones; 902 cpacrMask.asedis = ones; 903 904 // Security Extensions may limit the writability of CPACR 905 if (haveSecurity) { 906 scr = readMiscRegNoEffect(MISCREG_SCR); 907 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 908 if (scr.ns && (cpsr.mode != MODE_MON)) { 909 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 910 // NB: Skipping the full loop, here 911 if (!nsacr.cp10) cpacrMask.cp10 = 0; 912 if (!nsacr.cp11) cpacrMask.cp11 = 0; 913 } 914 } 915 916 MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR); 917 newVal &= cpacrMask; 918 newVal |= old_val & ~cpacrMask; 919 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 920 miscRegName[misc_reg], newVal); 921 } 922 break; 923 case MISCREG_CPACR_EL1: 924 { 925 const uint32_t ones = (uint32_t)(-1); 926 CPACR cpacrMask = 0; 927 cpacrMask.tta = ones; 928 cpacrMask.fpen = ones; 929 newVal &= cpacrMask; 930 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 931 miscRegName[misc_reg], newVal); 932 } 933 break; 934 case MISCREG_CPTR_EL2: 935 { 936 const uint32_t ones = (uint32_t)(-1); 937 CPTR cptrMask = 0; 938 cptrMask.tcpac = ones; 939 cptrMask.tta = ones; 940 cptrMask.tfp = ones; 941 newVal &= cptrMask; 942 cptrMask = 0; 943 cptrMask.res1_13_12_el2 = ones; 944 cptrMask.res1_9_0_el2 = ones; 945 newVal |= cptrMask; 946 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 947 miscRegName[misc_reg], newVal); 948 } 949 break; 950 case MISCREG_CPTR_EL3: 951 { 952 const uint32_t ones = (uint32_t)(-1); 953 CPTR cptrMask = 0; 954 cptrMask.tcpac = ones; 955 cptrMask.tta = ones; 956 cptrMask.tfp = ones; 957 newVal &= cptrMask; 958 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 959 miscRegName[misc_reg], newVal); 960 } 961 break; 962 case MISCREG_CSSELR: 963 warn_once("The csselr register isn't implemented.\n"); 964 return; 965 966 case MISCREG_DC_ZVA_Xt: 967 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 968 return; 969 970 case MISCREG_FPSCR: 971 { 972 const uint32_t ones = (uint32_t)(-1); 973 FPSCR fpscrMask = 0; 974 fpscrMask.ioc = ones; 975 fpscrMask.dzc = ones; 976 fpscrMask.ofc = ones; 977 fpscrMask.ufc = ones; 978 fpscrMask.ixc = ones; 979 fpscrMask.idc = ones; 980 fpscrMask.ioe = ones; 981 fpscrMask.dze = ones; 982 fpscrMask.ofe = ones; 983 fpscrMask.ufe = ones; 984 fpscrMask.ixe = ones; 985 fpscrMask.ide = ones; 986 fpscrMask.len = ones; 987 fpscrMask.stride = ones; 988 fpscrMask.rMode = ones; 989 fpscrMask.fz = ones; 990 fpscrMask.dn = ones; 991 fpscrMask.ahp = ones; 992 fpscrMask.qc = ones; 993 fpscrMask.v = ones; 994 fpscrMask.c = ones; 995 fpscrMask.z = ones; 996 fpscrMask.n = ones; 997 newVal = (newVal & (uint32_t)fpscrMask) | 998 (readMiscRegNoEffect(MISCREG_FPSCR) & 999 ~(uint32_t)fpscrMask); 1000 tc->getDecoderPtr()->setContext(newVal); 1001 } 1002 break; 1003 case MISCREG_FPSR: 1004 { 1005 const uint32_t ones = (uint32_t)(-1); 1006 FPSCR fpscrMask = 0; 1007 fpscrMask.ioc = ones; 1008 fpscrMask.dzc = ones; 1009 fpscrMask.ofc = ones; 1010 fpscrMask.ufc = ones; 1011 fpscrMask.ixc = ones; 1012 fpscrMask.idc = ones; 1013 fpscrMask.qc = ones; 1014 fpscrMask.v = ones; 1015 fpscrMask.c = ones; 1016 fpscrMask.z = ones; 1017 fpscrMask.n = ones; 1018 newVal = (newVal & (uint32_t)fpscrMask) | 1019 (readMiscRegNoEffect(MISCREG_FPSCR) & 1020 ~(uint32_t)fpscrMask); 1021 misc_reg = MISCREG_FPSCR; 1022 } 1023 break; 1024 case MISCREG_FPCR: 1025 { 1026 const uint32_t ones = (uint32_t)(-1); 1027 FPSCR fpscrMask = 0; 1028 fpscrMask.ioe = ones; 1029 fpscrMask.dze = ones; 1030 fpscrMask.ofe = ones; 1031 fpscrMask.ufe = ones; 1032 fpscrMask.ixe = ones; 1033 fpscrMask.ide = ones; 1034 fpscrMask.len = ones; 1035 fpscrMask.stride = ones; 1036 fpscrMask.rMode = ones; 1037 fpscrMask.fz = ones; 1038 fpscrMask.dn = ones; 1039 fpscrMask.ahp = ones; 1040 newVal = (newVal & (uint32_t)fpscrMask) | 1041 (readMiscRegNoEffect(MISCREG_FPSCR) & 1042 ~(uint32_t)fpscrMask); 1043 misc_reg = MISCREG_FPSCR; 1044 } 1045 break; 1046 case MISCREG_CPSR_Q: 1047 { 1048 assert(!(newVal & ~CpsrMaskQ)); 1049 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 1050 misc_reg = MISCREG_CPSR; 1051 } 1052 break; 1053 case MISCREG_FPSCR_QC: 1054 { 1055 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 1056 (newVal & FpscrQcMask); 1057 misc_reg = MISCREG_FPSCR; 1058 } 1059 break; 1060 case MISCREG_FPSCR_EXC: 1061 { 1062 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 1063 (newVal & FpscrExcMask); 1064 misc_reg = MISCREG_FPSCR; 1065 } 1066 break; 1067 case MISCREG_FPEXC: 1068 { 1069 // vfpv3 architecture, section B.6.1 of DDI04068 1070 // bit 29 - valid only if fpexc[31] is 0 1071 const uint32_t fpexcMask = 0x60000000; 1072 newVal = (newVal & fpexcMask) | 1073 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 1074 } 1075 break; 1076 case MISCREG_HCR: 1077 { 1078 if (!haveVirtualization) 1079 return; 1080 } 1081 break; 1082 case MISCREG_IFSR: 1083 { 1084 // ARM ARM (ARM DDI 0406C.b) B4.1.96 1085 const uint32_t ifsrMask = 1086 mask(31, 13) | mask(11, 11) | mask(8, 6); 1087 newVal = newVal & ~ifsrMask; 1088 } 1089 break; 1090 case MISCREG_DFSR: 1091 { 1092 // ARM ARM (ARM DDI 0406C.b) B4.1.52 1093 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 1094 newVal = newVal & ~dfsrMask; 1095 } 1096 break; 1097 case MISCREG_AMAIR0: 1098 case MISCREG_AMAIR1: 1099 { 1100 // ARM ARM (ARM DDI 0406C.b) B4.1.5 1101 // Valid only with LPAE 1102 if (!haveLPAE) 1103 return; 1104 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 1105 } 1106 break; 1107 case MISCREG_SCR: 1108 tc->getITBPtr()->invalidateMiscReg(); 1109 tc->getDTBPtr()->invalidateMiscReg(); 1110 break; 1111 case MISCREG_SCTLR: 1112 { 1113 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 1114 MiscRegIndex sctlr_idx; 1115 scr = readMiscRegNoEffect(MISCREG_SCR); 1116 if (haveSecurity && !scr.ns) { 1117 sctlr_idx = MISCREG_SCTLR_S; 1118 } else { 1119 sctlr_idx = MISCREG_SCTLR_NS; 1120 // The FI field (bit 21) is common between S/NS versions 1121 // of the register, we store this in the secure copy of 1122 // the reg 1123 miscRegs[MISCREG_SCTLR_S] &= ~(1 << 21); 1124 miscRegs[MISCREG_SCTLR_S] |= newVal & (1 << 21); 1125 } 1126 SCTLR sctlr = miscRegs[sctlr_idx]; 1127 SCTLR new_sctlr = newVal; 1128 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 1129 miscRegs[sctlr_idx] = (MiscReg)new_sctlr; 1130 tc->getITBPtr()->invalidateMiscReg(); 1131 tc->getDTBPtr()->invalidateMiscReg(); 1132 } 1133 case MISCREG_MIDR: 1134 case MISCREG_ID_PFR0: 1135 case MISCREG_ID_PFR1: 1136 case MISCREG_ID_DFR0: 1137 case MISCREG_ID_MMFR0: 1138 case MISCREG_ID_MMFR1: 1139 case MISCREG_ID_MMFR2: 1140 case MISCREG_ID_MMFR3: 1141 case MISCREG_ID_ISAR0: 1142 case MISCREG_ID_ISAR1: 1143 case MISCREG_ID_ISAR2: 1144 case MISCREG_ID_ISAR3: 1145 case MISCREG_ID_ISAR4: 1146 case MISCREG_ID_ISAR5: 1147 1148 case MISCREG_MPIDR: 1149 case MISCREG_FPSID: 1150 case MISCREG_TLBTR: 1151 case MISCREG_MVFR0: 1152 case MISCREG_MVFR1: 1153 1154 case MISCREG_ID_AA64AFR0_EL1: 1155 case MISCREG_ID_AA64AFR1_EL1: 1156 case MISCREG_ID_AA64DFR0_EL1: 1157 case MISCREG_ID_AA64DFR1_EL1: 1158 case MISCREG_ID_AA64ISAR0_EL1: 1159 case MISCREG_ID_AA64ISAR1_EL1: 1160 case MISCREG_ID_AA64MMFR0_EL1: 1161 case MISCREG_ID_AA64MMFR1_EL1: 1162 case MISCREG_ID_AA64PFR0_EL1: 1163 case MISCREG_ID_AA64PFR1_EL1: 1164 // ID registers are constants. 1165 return; 1166 1167 // TLBI all entries, EL0&1 inner sharable (ignored) 1168 case MISCREG_TLBIALLIS: 1169 case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 1170 assert32(tc); 1171 target_el = 1; // el 0 and 1 are handled together 1172 scr = readMiscReg(MISCREG_SCR, tc); 1173 secure_lookup = haveSecurity && !scr.ns; 1174 sys = tc->getSystemPtr(); 1175 for (x = 0; x < sys->numContexts(); x++) { 1176 oc = sys->getThreadContext(x); 1177 assert(oc->getITBPtr() && oc->getDTBPtr()); 1178 oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 1179 oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 1180 1181 // If CheckerCPU is connected, need to notify it of a flush 1182 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1183 if (checker) { 1184 checker->getITBPtr()->flushAllSecurity(secure_lookup, 1185 target_el); 1186 checker->getDTBPtr()->flushAllSecurity(secure_lookup, 1187 target_el); 1188 } 1189 } 1190 return; 1191 // TLBI all entries, EL0&1, instruction side 1192 case MISCREG_ITLBIALL: 1193 assert32(tc); 1194 target_el = 1; // el 0 and 1 are handled together 1195 scr = readMiscReg(MISCREG_SCR, tc); 1196 secure_lookup = haveSecurity && !scr.ns; 1197 tc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 1198 return; 1199 // TLBI all entries, EL0&1, data side 1200 case MISCREG_DTLBIALL: 1201 assert32(tc); 1202 target_el = 1; // el 0 and 1 are handled together 1203 scr = readMiscReg(MISCREG_SCR, tc); 1204 secure_lookup = haveSecurity && !scr.ns; 1205 tc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 1206 return; 1207 // TLBI based on VA, EL0&1 inner sharable (ignored) 1208 case MISCREG_TLBIMVAIS: 1209 case MISCREG_TLBIMVA: 1210 assert32(tc); 1211 target_el = 1; // el 0 and 1 are handled together 1212 scr = readMiscReg(MISCREG_SCR, tc); 1213 secure_lookup = haveSecurity && !scr.ns; 1214 sys = tc->getSystemPtr(); 1215 for (x = 0; x < sys->numContexts(); x++) { 1216 oc = sys->getThreadContext(x); 1217 assert(oc->getITBPtr() && oc->getDTBPtr()); 1218 oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1219 bits(newVal, 7,0), 1220 secure_lookup, target_el); 1221 oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1222 bits(newVal, 7,0), 1223 secure_lookup, target_el); 1224 1225 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1226 if (checker) { 1227 checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1228 bits(newVal, 7,0), secure_lookup, target_el); 1229 checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1230 bits(newVal, 7,0), secure_lookup, target_el); 1231 } 1232 } 1233 return; 1234 // TLBI by ASID, EL0&1, inner sharable 1235 case MISCREG_TLBIASIDIS: 1236 case MISCREG_TLBIASID: 1237 assert32(tc); 1238 target_el = 1; // el 0 and 1 are handled together 1239 scr = readMiscReg(MISCREG_SCR, tc); 1240 secure_lookup = haveSecurity && !scr.ns; 1241 sys = tc->getSystemPtr(); 1242 for (x = 0; x < sys->numContexts(); x++) { 1243 oc = sys->getThreadContext(x); 1244 assert(oc->getITBPtr() && oc->getDTBPtr()); 1245 oc->getITBPtr()->flushAsid(bits(newVal, 7,0), 1246 secure_lookup, target_el); 1247 oc->getDTBPtr()->flushAsid(bits(newVal, 7,0), 1248 secure_lookup, target_el); 1249 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1250 if (checker) { 1251 checker->getITBPtr()->flushAsid(bits(newVal, 7,0), 1252 secure_lookup, target_el); 1253 checker->getDTBPtr()->flushAsid(bits(newVal, 7,0), 1254 secure_lookup, target_el); 1255 } 1256 } 1257 return; 1258 // TLBI by address, EL0&1, inner sharable (ignored) 1259 case MISCREG_TLBIMVAAIS: 1260 case MISCREG_TLBIMVAA: 1261 assert32(tc); 1262 target_el = 1; // el 0 and 1 are handled together 1263 scr = readMiscReg(MISCREG_SCR, tc); 1264 secure_lookup = haveSecurity && !scr.ns; 1265 hyp = 0; 1266 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el); 1267 return; 1268 // TLBI by address, EL2, hypervisor mode 1269 case MISCREG_TLBIMVAH: 1270 case MISCREG_TLBIMVAHIS: 1271 assert32(tc); 1272 target_el = 1; // aarch32, use hyp bit 1273 scr = readMiscReg(MISCREG_SCR, tc); 1274 secure_lookup = haveSecurity && !scr.ns; 1275 hyp = 1; 1276 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el); 1277 return; 1278 // TLBI by address and asid, EL0&1, instruction side only 1279 case MISCREG_ITLBIMVA: 1280 assert32(tc); 1281 target_el = 1; // el 0 and 1 are handled together 1282 scr = readMiscReg(MISCREG_SCR, tc); 1283 secure_lookup = haveSecurity && !scr.ns; 1284 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1285 bits(newVal, 7,0), secure_lookup, target_el); 1286 return; 1287 // TLBI by address and asid, EL0&1, data side only 1288 case MISCREG_DTLBIMVA: 1289 assert32(tc); 1290 target_el = 1; // el 0 and 1 are handled together 1291 scr = readMiscReg(MISCREG_SCR, tc); 1292 secure_lookup = haveSecurity && !scr.ns; 1293 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1294 bits(newVal, 7,0), secure_lookup, target_el); 1295 return; 1296 // TLBI by ASID, EL0&1, instrution side only 1297 case MISCREG_ITLBIASID: 1298 assert32(tc); 1299 target_el = 1; // el 0 and 1 are handled together 1300 scr = readMiscReg(MISCREG_SCR, tc); 1301 secure_lookup = haveSecurity && !scr.ns; 1302 tc->getITBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup, 1303 target_el); 1304 return; 1305 // TLBI by ASID EL0&1 data size only 1306 case MISCREG_DTLBIASID: 1307 assert32(tc); 1308 target_el = 1; // el 0 and 1 are handled together 1309 scr = readMiscReg(MISCREG_SCR, tc); 1310 secure_lookup = haveSecurity && !scr.ns; 1311 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup, 1312 target_el); 1313 return; 1314 // Invalidate entire Non-secure Hyp/Non-Hyp Unified TLB 1315 case MISCREG_TLBIALLNSNH: 1316 case MISCREG_TLBIALLNSNHIS: 1317 assert32(tc); 1318 target_el = 1; // el 0 and 1 are handled together 1319 hyp = 0; 1320 tlbiALLN(tc, hyp, target_el); 1321 return; 1322 // TLBI all entries, EL2, hyp, 1323 case MISCREG_TLBIALLH: 1324 case MISCREG_TLBIALLHIS: 1325 assert32(tc); 1326 target_el = 1; // aarch32, use hyp bit 1327 hyp = 1; 1328 tlbiALLN(tc, hyp, target_el); 1329 return; 1330 // AArch64 TLBI: invalidate all entries EL3 1331 case MISCREG_TLBI_ALLE3IS: 1332 case MISCREG_TLBI_ALLE3: 1333 assert64(tc); 1334 target_el = 3; 1335 secure_lookup = true; 1336 tlbiALL(tc, secure_lookup, target_el); 1337 return; 1338 // @todo: uncomment this to enable Virtualization 1339 // case MISCREG_TLBI_ALLE2IS: 1340 // case MISCREG_TLBI_ALLE2: 1341 // TLBI all entries, EL0&1 1342 case MISCREG_TLBI_ALLE1IS: 1343 case MISCREG_TLBI_ALLE1: 1344 // AArch64 TLBI: invalidate all entries, stage 1, current VMID 1345 case MISCREG_TLBI_VMALLE1IS: 1346 case MISCREG_TLBI_VMALLE1: 1347 // AArch64 TLBI: invalidate all entries, stages 1 & 2, current VMID 1348 case MISCREG_TLBI_VMALLS12E1IS: 1349 case MISCREG_TLBI_VMALLS12E1: 1350 // @todo: handle VMID and stage 2 to enable Virtualization 1351 assert64(tc); 1352 target_el = 1; // el 0 and 1 are handled together 1353 scr = readMiscReg(MISCREG_SCR, tc); 1354 secure_lookup = haveSecurity && !scr.ns; 1355 tlbiALL(tc, secure_lookup, target_el); 1356 return; 1357 // AArch64 TLBI: invalidate by VA and ASID, stage 1, current VMID 1358 // VAEx(IS) and VALEx(IS) are the same because TLBs only store entries 1359 // from the last level of translation table walks 1360 // @todo: handle VMID to enable Virtualization 1361 // TLBI all entries, EL0&1 1362 case MISCREG_TLBI_VAE3IS_Xt: 1363 case MISCREG_TLBI_VAE3_Xt: 1364 // TLBI by VA, EL3 regime stage 1, last level walk 1365 case MISCREG_TLBI_VALE3IS_Xt: 1366 case MISCREG_TLBI_VALE3_Xt: 1367 assert64(tc); 1368 target_el = 3; 1369 asid = 0xbeef; // does not matter, tlbi is global 1370 secure_lookup = true; 1371 tlbiVA(tc, newVal, asid, secure_lookup, target_el); 1372 return; 1373 // TLBI by VA, EL2 1374 case MISCREG_TLBI_VAE2IS_Xt: 1375 case MISCREG_TLBI_VAE2_Xt: 1376 // TLBI by VA, EL2, stage1 last level walk 1377 case MISCREG_TLBI_VALE2IS_Xt: 1378 case MISCREG_TLBI_VALE2_Xt: 1379 assert64(tc); 1380 target_el = 2; 1381 asid = 0xbeef; // does not matter, tlbi is global 1382 scr = readMiscReg(MISCREG_SCR, tc); 1383 secure_lookup = haveSecurity && !scr.ns; 1384 tlbiVA(tc, newVal, asid, secure_lookup, target_el); 1385 return; 1386 // TLBI by VA EL1 & 0, stage1, ASID, current VMID 1387 case MISCREG_TLBI_VAE1IS_Xt: 1388 case MISCREG_TLBI_VAE1_Xt: 1389 case MISCREG_TLBI_VALE1IS_Xt: 1390 case MISCREG_TLBI_VALE1_Xt: 1391 assert64(tc); 1392 asid = bits(newVal, 63, 48); 1393 target_el = 1; // el 0 and 1 are handled together 1394 scr = readMiscReg(MISCREG_SCR, tc); 1395 secure_lookup = haveSecurity && !scr.ns; 1396 tlbiVA(tc, newVal, asid, secure_lookup, target_el); 1397 return; 1398 // AArch64 TLBI: invalidate by ASID, stage 1, current VMID 1399 // @todo: handle VMID to enable Virtualization 1400 case MISCREG_TLBI_ASIDE1IS_Xt: 1401 case MISCREG_TLBI_ASIDE1_Xt: 1402 assert64(tc); 1403 target_el = 1; // el 0 and 1 are handled together 1404 scr = readMiscReg(MISCREG_SCR, tc); 1405 secure_lookup = haveSecurity && !scr.ns; 1406 sys = tc->getSystemPtr(); 1407 for (x = 0; x < sys->numContexts(); x++) { 1408 oc = sys->getThreadContext(x); 1409 assert(oc->getITBPtr() && oc->getDTBPtr()); 1410 asid = bits(newVal, 63, 48); 1411 if (!haveLargeAsid64) 1412 asid &= mask(8); 1413 oc->getITBPtr()->flushAsid(asid, secure_lookup, target_el); 1414 oc->getDTBPtr()->flushAsid(asid, secure_lookup, target_el); 1415 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1416 if (checker) { 1417 checker->getITBPtr()->flushAsid(asid, 1418 secure_lookup, target_el); 1419 checker->getDTBPtr()->flushAsid(asid, 1420 secure_lookup, target_el); 1421 } 1422 } 1423 return; 1424 // AArch64 TLBI: invalidate by VA, ASID, stage 1, current VMID 1425 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 1426 // entries from the last level of translation table walks 1427 // @todo: handle VMID to enable Virtualization 1428 case MISCREG_TLBI_VAAE1IS_Xt: 1429 case MISCREG_TLBI_VAAE1_Xt: 1430 case MISCREG_TLBI_VAALE1IS_Xt: 1431 case MISCREG_TLBI_VAALE1_Xt: 1432 assert64(tc); 1433 target_el = 1; // el 0 and 1 are handled together 1434 scr = readMiscReg(MISCREG_SCR, tc); 1435 secure_lookup = haveSecurity && !scr.ns; 1436 sys = tc->getSystemPtr(); 1437 for (x = 0; x < sys->numContexts(); x++) { 1438 // @todo: extra controls on TLBI broadcast? 1439 oc = sys->getThreadContext(x); 1440 assert(oc->getITBPtr() && oc->getDTBPtr()); 1441 Addr va = ((Addr) bits(newVal, 43, 0)) << 12; 1442 oc->getITBPtr()->flushMva(va, 1443 secure_lookup, false, target_el); 1444 oc->getDTBPtr()->flushMva(va, 1445 secure_lookup, false, target_el); 1446 1447 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1448 if (checker) { 1449 checker->getITBPtr()->flushMva(va, 1450 secure_lookup, false, target_el); 1451 checker->getDTBPtr()->flushMva(va, 1452 secure_lookup, false, target_el); 1453 } 1454 } 1455 return; 1456 // AArch64 TLBI: invalidate by IPA, stage 2, current VMID 1457 case MISCREG_TLBI_IPAS2LE1IS_Xt: 1458 case MISCREG_TLBI_IPAS2LE1_Xt: 1459 case MISCREG_TLBI_IPAS2E1IS_Xt: 1460 case MISCREG_TLBI_IPAS2E1_Xt: 1461 assert64(tc); 1462 target_el = 1; // EL 0 and 1 are handled together 1463 scr = readMiscReg(MISCREG_SCR, tc); 1464 secure_lookup = haveSecurity && !scr.ns; 1465 sys = tc->getSystemPtr(); 1466 for (x = 0; x < sys->numContexts(); x++) { 1467 oc = sys->getThreadContext(x); 1468 assert(oc->getITBPtr() && oc->getDTBPtr()); 1469 Addr ipa = ((Addr) bits(newVal, 35, 0)) << 12; 1470 oc->getITBPtr()->flushIpaVmid(ipa, 1471 secure_lookup, false, target_el); 1472 oc->getDTBPtr()->flushIpaVmid(ipa, 1473 secure_lookup, false, target_el); 1474 1475 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1476 if (checker) { 1477 checker->getITBPtr()->flushIpaVmid(ipa, 1478 secure_lookup, false, target_el); 1479 checker->getDTBPtr()->flushIpaVmid(ipa, 1480 secure_lookup, false, target_el); 1481 } 1482 } 1483 return; 1484 case MISCREG_ACTLR: 1485 warn("Not doing anything for write of miscreg ACTLR\n"); 1486 break; 1487 1488 case MISCREG_PMXEVTYPER_PMCCFILTR: 1489 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 1490 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 1491 case MISCREG_PMCR ... MISCREG_PMOVSSET: 1492 pmu->setMiscReg(misc_reg, newVal); 1493 break; 1494 1495 1496 case MISCREG_HSTR: // TJDBX, now redifined to be RES0 1497 { 1498 HSTR hstrMask = 0; 1499 hstrMask.tjdbx = 1; 1500 newVal &= ~((uint32_t) hstrMask); 1501 break; 1502 } 1503 case MISCREG_HCPTR: 1504 { 1505 // If a CP bit in NSACR is 0 then the corresponding bit in 1506 // HCPTR is RAO/WI. Same applies to NSASEDIS 1507 secure_lookup = haveSecurity && 1508 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 1509 readMiscRegNoEffect(MISCREG_CPSR)); 1510 if (!secure_lookup) { 1511 MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 1512 MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 1513 newVal = (newVal & ~mask) | (oldValue & mask); 1514 } 1515 break; 1516 } 1517 case MISCREG_HDFAR: // alias for secure DFAR 1518 misc_reg = MISCREG_DFAR_S; 1519 break; 1520 case MISCREG_HIFAR: // alias for secure IFAR 1521 misc_reg = MISCREG_IFAR_S; 1522 break; 1523 case MISCREG_ATS1CPR: 1524 case MISCREG_ATS1CPW: 1525 case MISCREG_ATS1CUR: 1526 case MISCREG_ATS1CUW: 1527 case MISCREG_ATS12NSOPR: 1528 case MISCREG_ATS12NSOPW: 1529 case MISCREG_ATS12NSOUR: 1530 case MISCREG_ATS12NSOUW: 1531 case MISCREG_ATS1HR: 1532 case MISCREG_ATS1HW: 1533 { 1534 Request::Flags flags = 0; 1535 BaseTLB::Mode mode = BaseTLB::Read; 1536 TLB::ArmTranslationType tranType = TLB::NormalTran; 1537 Fault fault; 1538 switch(misc_reg) { 1539 case MISCREG_ATS1CPR: 1540 flags = TLB::MustBeOne; 1541 tranType = TLB::S1CTran; 1542 mode = BaseTLB::Read; 1543 break; 1544 case MISCREG_ATS1CPW: 1545 flags = TLB::MustBeOne; 1546 tranType = TLB::S1CTran; 1547 mode = BaseTLB::Write; 1548 break; 1549 case MISCREG_ATS1CUR: 1550 flags = TLB::MustBeOne | TLB::UserMode; 1551 tranType = TLB::S1CTran; 1552 mode = BaseTLB::Read; 1553 break; 1554 case MISCREG_ATS1CUW: 1555 flags = TLB::MustBeOne | TLB::UserMode; 1556 tranType = TLB::S1CTran; 1557 mode = BaseTLB::Write; 1558 break; 1559 case MISCREG_ATS12NSOPR: 1560 if (!haveSecurity) 1561 panic("Security Extensions required for ATS12NSOPR"); 1562 flags = TLB::MustBeOne; 1563 tranType = TLB::S1S2NsTran; 1564 mode = BaseTLB::Read; 1565 break; 1566 case MISCREG_ATS12NSOPW: 1567 if (!haveSecurity) 1568 panic("Security Extensions required for ATS12NSOPW"); 1569 flags = TLB::MustBeOne; 1570 tranType = TLB::S1S2NsTran; 1571 mode = BaseTLB::Write; 1572 break; 1573 case MISCREG_ATS12NSOUR: 1574 if (!haveSecurity) 1575 panic("Security Extensions required for ATS12NSOUR"); 1576 flags = TLB::MustBeOne | TLB::UserMode; 1577 tranType = TLB::S1S2NsTran; 1578 mode = BaseTLB::Read; 1579 break; 1580 case MISCREG_ATS12NSOUW: 1581 if (!haveSecurity) 1582 panic("Security Extensions required for ATS12NSOUW"); 1583 flags = TLB::MustBeOne | TLB::UserMode; 1584 tranType = TLB::S1S2NsTran; 1585 mode = BaseTLB::Write; 1586 break; 1587 case MISCREG_ATS1HR: // only really useful from secure mode. 1588 flags = TLB::MustBeOne; 1589 tranType = TLB::HypMode; 1590 mode = BaseTLB::Read; 1591 break; 1592 case MISCREG_ATS1HW: 1593 flags = TLB::MustBeOne; 1594 tranType = TLB::HypMode; 1595 mode = BaseTLB::Write; 1596 break; 1597 } 1598 // If we're in timing mode then doing the translation in 1599 // functional mode then we're slightly distorting performance 1600 // results obtained from simulations. The translation should be 1601 // done in the same mode the core is running in. NOTE: This 1602 // can't be an atomic translation because that causes problems 1603 // with unexpected atomic snoop requests. 1604 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1605 Request req(0, val, 0, flags, Request::funcMasterId, 1606 tc->pcState().pc(), tc->contextId()); 1607 fault = tc->getDTBPtr()->translateFunctional(&req, tc, mode, tranType); 1608 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1609 HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 1610 1611 MiscReg newVal; 1612 if (fault == NoFault) { 1613 Addr paddr = req.getPaddr(); 1614 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 1615 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 1616 newVal = (paddr & mask(39, 12)) | 1617 (tc->getDTBPtr()->getAttr()); 1618 } else { 1619 newVal = (paddr & 0xfffff000) | 1620 (tc->getDTBPtr()->getAttr()); 1621 } 1622 DPRINTF(MiscRegs, 1623 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 1624 val, newVal); 1625 } else { 1626 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 1627 // Set fault bit and FSR 1628 FSR fsr = armFault->getFsr(tc); 1629 1630 newVal = ((fsr >> 9) & 1) << 11; 1631 if (newVal) { 1632 // LPAE - rearange fault status 1633 newVal |= ((fsr >> 0) & 0x3f) << 1; 1634 } else { 1635 // VMSA - rearange fault status 1636 newVal |= ((fsr >> 0) & 0xf) << 1; 1637 newVal |= ((fsr >> 10) & 0x1) << 5; 1638 newVal |= ((fsr >> 12) & 0x1) << 6; 1639 } 1640 newVal |= 0x1; // F bit 1641 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1642 newVal |= armFault->isStage2() ? 0x200 : 0; 1643 DPRINTF(MiscRegs, 1644 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 1645 val, fsr, newVal); 1646 } 1647 setMiscRegNoEffect(MISCREG_PAR, newVal); 1648 return; 1649 } 1650 case MISCREG_TTBCR: 1651 { 1652 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1653 const uint32_t ones = (uint32_t)(-1); 1654 TTBCR ttbcrMask = 0; 1655 TTBCR ttbcrNew = newVal; 1656 1657 // ARM DDI 0406C.b, ARMv7-32 1658 ttbcrMask.n = ones; // T0SZ 1659 if (haveSecurity) { 1660 ttbcrMask.pd0 = ones; 1661 ttbcrMask.pd1 = ones; 1662 } 1663 ttbcrMask.epd0 = ones; 1664 ttbcrMask.irgn0 = ones; 1665 ttbcrMask.orgn0 = ones; 1666 ttbcrMask.sh0 = ones; 1667 ttbcrMask.ps = ones; // T1SZ 1668 ttbcrMask.a1 = ones; 1669 ttbcrMask.epd1 = ones; 1670 ttbcrMask.irgn1 = ones; 1671 ttbcrMask.orgn1 = ones; 1672 ttbcrMask.sh1 = ones; 1673 if (haveLPAE) 1674 ttbcrMask.eae = ones; 1675 1676 if (haveLPAE && ttbcrNew.eae) { 1677 newVal = newVal & ttbcrMask; 1678 } else { 1679 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 1680 } 1681 } 1682 case MISCREG_TTBR0: 1683 case MISCREG_TTBR1: 1684 { 1685 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1686 if (haveLPAE) { 1687 if (ttbcr.eae) { 1688 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 1689 // ARMv8 AArch32 bit 63-56 only 1690 uint64_t ttbrMask = mask(63,56) | mask(47,40); 1691 newVal = (newVal & (~ttbrMask)); 1692 } 1693 } 1694 } 1695 case MISCREG_SCTLR_EL1: 1696 { 1697 tc->getITBPtr()->invalidateMiscReg(); 1698 tc->getDTBPtr()->invalidateMiscReg(); 1699 setMiscRegNoEffect(misc_reg, newVal); 1700 } 1701 case MISCREG_CONTEXTIDR: 1702 case MISCREG_PRRR: 1703 case MISCREG_NMRR: 1704 case MISCREG_MAIR0: 1705 case MISCREG_MAIR1: 1706 case MISCREG_DACR: 1707 case MISCREG_VTTBR: 1708 case MISCREG_SCR_EL3: 1709 case MISCREG_HCR_EL2: 1710 case MISCREG_TCR_EL1: 1711 case MISCREG_TCR_EL2: 1712 case MISCREG_TCR_EL3: 1713 case MISCREG_SCTLR_EL2: 1714 case MISCREG_SCTLR_EL3: 1715 case MISCREG_HSCTLR: 1716 case MISCREG_TTBR0_EL1: 1717 case MISCREG_TTBR1_EL1: 1718 case MISCREG_TTBR0_EL2: 1719 case MISCREG_TTBR0_EL3: 1720 tc->getITBPtr()->invalidateMiscReg(); 1721 tc->getDTBPtr()->invalidateMiscReg(); 1722 break; 1723 case MISCREG_NZCV: 1724 { 1725 CPSR cpsr = val; 1726 1727 tc->setCCReg(CCREG_NZ, cpsr.nz); 1728 tc->setCCReg(CCREG_C, cpsr.c); 1729 tc->setCCReg(CCREG_V, cpsr.v); 1730 } 1731 break; 1732 case MISCREG_DAIF: 1733 { 1734 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1735 cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 1736 newVal = cpsr; 1737 misc_reg = MISCREG_CPSR; 1738 } 1739 break; 1740 case MISCREG_SP_EL0: 1741 tc->setIntReg(INTREG_SP0, newVal); 1742 break; 1743 case MISCREG_SP_EL1: 1744 tc->setIntReg(INTREG_SP1, newVal); 1745 break; 1746 case MISCREG_SP_EL2: 1747 tc->setIntReg(INTREG_SP2, newVal); 1748 break; 1749 case MISCREG_SPSEL: 1750 { 1751 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1752 cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 1753 newVal = cpsr; 1754 misc_reg = MISCREG_CPSR; 1755 } 1756 break; 1757 case MISCREG_CURRENTEL: 1758 { 1759 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1760 cpsr.el = (uint8_t) ((CPSR) newVal).el; 1761 newVal = cpsr; 1762 misc_reg = MISCREG_CPSR; 1763 } 1764 break; 1765 case MISCREG_AT_S1E1R_Xt: 1766 case MISCREG_AT_S1E1W_Xt: 1767 case MISCREG_AT_S1E0R_Xt: 1768 case MISCREG_AT_S1E0W_Xt: 1769 case MISCREG_AT_S1E2R_Xt: 1770 case MISCREG_AT_S1E2W_Xt: 1771 case MISCREG_AT_S12E1R_Xt: 1772 case MISCREG_AT_S12E1W_Xt: 1773 case MISCREG_AT_S12E0R_Xt: 1774 case MISCREG_AT_S12E0W_Xt: 1775 case MISCREG_AT_S1E3R_Xt: 1776 case MISCREG_AT_S1E3W_Xt: 1777 { 1778 RequestPtr req = new Request; 1779 Request::Flags flags = 0; 1780 BaseTLB::Mode mode = BaseTLB::Read; 1781 TLB::ArmTranslationType tranType = TLB::NormalTran; 1782 Fault fault; 1783 switch(misc_reg) { 1784 case MISCREG_AT_S1E1R_Xt: 1785 flags = TLB::MustBeOne; 1786 tranType = TLB::S1E1Tran; 1787 mode = BaseTLB::Read; 1788 break; 1789 case MISCREG_AT_S1E1W_Xt: 1790 flags = TLB::MustBeOne; 1791 tranType = TLB::S1E1Tran; 1792 mode = BaseTLB::Write; 1793 break; 1794 case MISCREG_AT_S1E0R_Xt: 1795 flags = TLB::MustBeOne | TLB::UserMode; 1796 tranType = TLB::S1E0Tran; 1797 mode = BaseTLB::Read; 1798 break; 1799 case MISCREG_AT_S1E0W_Xt: 1800 flags = TLB::MustBeOne | TLB::UserMode; 1801 tranType = TLB::S1E0Tran; 1802 mode = BaseTLB::Write; 1803 break; 1804 case MISCREG_AT_S1E2R_Xt: 1805 flags = TLB::MustBeOne; 1806 tranType = TLB::S1E2Tran; 1807 mode = BaseTLB::Read; 1808 break; 1809 case MISCREG_AT_S1E2W_Xt: 1810 flags = TLB::MustBeOne; 1811 tranType = TLB::S1E2Tran; 1812 mode = BaseTLB::Write; 1813 break; 1814 case MISCREG_AT_S12E0R_Xt: 1815 flags = TLB::MustBeOne | TLB::UserMode; 1816 tranType = TLB::S12E0Tran; 1817 mode = BaseTLB::Read; 1818 break; 1819 case MISCREG_AT_S12E0W_Xt: 1820 flags = TLB::MustBeOne | TLB::UserMode; 1821 tranType = TLB::S12E0Tran; 1822 mode = BaseTLB::Write; 1823 break; 1824 case MISCREG_AT_S12E1R_Xt: 1825 flags = TLB::MustBeOne; 1826 tranType = TLB::S12E1Tran; 1827 mode = BaseTLB::Read; 1828 break; 1829 case MISCREG_AT_S12E1W_Xt: 1830 flags = TLB::MustBeOne; 1831 tranType = TLB::S12E1Tran; 1832 mode = BaseTLB::Write; 1833 break; 1834 case MISCREG_AT_S1E3R_Xt: 1835 flags = TLB::MustBeOne; 1836 tranType = TLB::S1E3Tran; 1837 mode = BaseTLB::Read; 1838 break; 1839 case MISCREG_AT_S1E3W_Xt: 1840 flags = TLB::MustBeOne; 1841 tranType = TLB::S1E3Tran; 1842 mode = BaseTLB::Write; 1843 break; 1844 } 1845 // If we're in timing mode then doing the translation in 1846 // functional mode then we're slightly distorting performance 1847 // results obtained from simulations. The translation should be 1848 // done in the same mode the core is running in. NOTE: This 1849 // can't be an atomic translation because that causes problems 1850 // with unexpected atomic snoop requests. 1851 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1852 req->setVirt(0, val, 0, flags, Request::funcMasterId, 1853 tc->pcState().pc()); 1854 req->setContext(tc->contextId()); 1855 fault = tc->getDTBPtr()->translateFunctional(req, tc, mode, 1856 tranType); 1857 1858 MiscReg newVal; 1859 if (fault == NoFault) { 1860 Addr paddr = req->getPaddr(); 1861 uint64_t attr = tc->getDTBPtr()->getAttr(); 1862 uint64_t attr1 = attr >> 56; 1863 if (!attr1 || attr1 ==0x44) { 1864 attr |= 0x100; 1865 attr &= ~ uint64_t(0x80); 1866 } 1867 newVal = (paddr & mask(47, 12)) | attr; 1868 DPRINTF(MiscRegs, 1869 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 1870 val, newVal); 1871 } else { 1872 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 1873 // Set fault bit and FSR 1874 FSR fsr = armFault->getFsr(tc); 1875 1876 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1877 if (cpsr.width) { // AArch32 1878 newVal = ((fsr >> 9) & 1) << 11; 1879 // rearrange fault status 1880 newVal |= ((fsr >> 0) & 0x3f) << 1; 1881 newVal |= 0x1; // F bit 1882 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1883 newVal |= armFault->isStage2() ? 0x200 : 0; 1884 } else { // AArch64 1885 newVal = 1; // F bit 1886 newVal |= fsr << 1; // FST 1887 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit. 1888 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 1889 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 1890 newVal |= 1 << 11; // RES1 1891 } 1892 DPRINTF(MiscRegs, 1893 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 1894 val, fsr, newVal); 1895 } 1896 delete req; 1897 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 1898 return; 1899 } 1900 case MISCREG_SPSR_EL3: 1901 case MISCREG_SPSR_EL2: 1902 case MISCREG_SPSR_EL1: 1903 // Force bits 23:21 to 0 1904 newVal = val & ~(0x7 << 21); 1905 break; 1906 case MISCREG_L2CTLR: 1907 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 1908 miscRegName[misc_reg], uint32_t(val)); 1909 break; 1910 1911 // Generic Timer registers 1912 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 1913 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 1914 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 1915 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 1916 getGenericTimer(tc).setMiscReg(misc_reg, newVal); 1917 break; 1918 } 1919 } 1920 setMiscRegNoEffect(misc_reg, newVal); 1921} 1922 1923void 1924ISA::tlbiVA(ThreadContext *tc, MiscReg newVal, uint16_t asid, 1925 bool secure_lookup, uint8_t target_el) 1926{ 1927 if (!haveLargeAsid64) 1928 asid &= mask(8); 1929 Addr va = ((Addr) bits(newVal, 43, 0)) << 12; 1930 System *sys = tc->getSystemPtr(); 1931 for (int x = 0; x < sys->numContexts(); x++) { 1932 ThreadContext *oc = sys->getThreadContext(x); 1933 assert(oc->getITBPtr() && oc->getDTBPtr()); 1934 oc->getITBPtr()->flushMvaAsid(va, asid, 1935 secure_lookup, target_el); 1936 oc->getDTBPtr()->flushMvaAsid(va, asid, 1937 secure_lookup, target_el); 1938 1939 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1940 if (checker) { 1941 checker->getITBPtr()->flushMvaAsid( 1942 va, asid, secure_lookup, target_el); 1943 checker->getDTBPtr()->flushMvaAsid( 1944 va, asid, secure_lookup, target_el); 1945 } 1946 } 1947} 1948 1949void 1950ISA::tlbiALL(ThreadContext *tc, bool secure_lookup, uint8_t target_el) 1951{ 1952 System *sys = tc->getSystemPtr(); 1953 for (int x = 0; x < sys->numContexts(); x++) { 1954 ThreadContext *oc = sys->getThreadContext(x); 1955 assert(oc->getITBPtr() && oc->getDTBPtr()); 1956 oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 1957 oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 1958 1959 // If CheckerCPU is connected, need to notify it of a flush 1960 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1961 if (checker) { 1962 checker->getITBPtr()->flushAllSecurity(secure_lookup, 1963 target_el); 1964 checker->getDTBPtr()->flushAllSecurity(secure_lookup, 1965 target_el); 1966 } 1967 } 1968} 1969 1970void 1971ISA::tlbiALLN(ThreadContext *tc, bool hyp, uint8_t target_el) 1972{ 1973 System *sys = tc->getSystemPtr(); 1974 for (int x = 0; x < sys->numContexts(); x++) { 1975 ThreadContext *oc = sys->getThreadContext(x); 1976 assert(oc->getITBPtr() && oc->getDTBPtr()); 1977 oc->getITBPtr()->flushAllNs(hyp, target_el); 1978 oc->getDTBPtr()->flushAllNs(hyp, target_el); 1979 1980 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1981 if (checker) { 1982 checker->getITBPtr()->flushAllNs(hyp, target_el); 1983 checker->getDTBPtr()->flushAllNs(hyp, target_el); 1984 } 1985 } 1986} 1987 1988void 1989ISA::tlbiMVA(ThreadContext *tc, MiscReg newVal, bool secure_lookup, bool hyp, 1990 uint8_t target_el) 1991{ 1992 System *sys = tc->getSystemPtr(); 1993 for (int x = 0; x < sys->numContexts(); x++) { 1994 ThreadContext *oc = sys->getThreadContext(x); 1995 assert(oc->getITBPtr() && oc->getDTBPtr()); 1996 oc->getITBPtr()->flushMva(mbits(newVal, 31,12), 1997 secure_lookup, hyp, target_el); 1998 oc->getDTBPtr()->flushMva(mbits(newVal, 31,12), 1999 secure_lookup, hyp, target_el); 2000 2001 CheckerCPU *checker = oc->getCheckerCpuPtr(); 2002 if (checker) { 2003 checker->getITBPtr()->flushMva(mbits(newVal, 31,12), 2004 secure_lookup, hyp, target_el); 2005 checker->getDTBPtr()->flushMva(mbits(newVal, 31,12), 2006 secure_lookup, hyp, target_el); 2007 } 2008 } 2009} 2010 2011BaseISADevice & 2012ISA::getGenericTimer(ThreadContext *tc) 2013{ 2014 // We only need to create an ISA interface the first time we try 2015 // to access the timer. 2016 if (timer) 2017 return *timer.get(); 2018 2019 assert(system); 2020 GenericTimer *generic_timer(system->getGenericTimer()); 2021 if (!generic_timer) { 2022 panic("Trying to get a generic timer from a system that hasn't " 2023 "been configured to use a generic timer.\n"); 2024 } 2025 2026 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 2027 return *timer.get(); 2028} 2029 2030} 2031 2032ArmISA::ISA * 2033ArmISAParams::create() 2034{ 2035 return new ArmISA::ISA(this); 2036} 2037