isa.cc revision 11577
113531Sjairo.balart@metempsy.com/* 214167Sgiacomo.travaglini@arm.com * Copyright (c) 2010-2016 ARM Limited 314167Sgiacomo.travaglini@arm.com * All rights reserved 414167Sgiacomo.travaglini@arm.com * 514167Sgiacomo.travaglini@arm.com * The license below extends only to copyright in the software and shall 614167Sgiacomo.travaglini@arm.com * not be construed as granting a license to any other intellectual 714167Sgiacomo.travaglini@arm.com * property including but not limited to intellectual property relating 814167Sgiacomo.travaglini@arm.com * to a hardware implementation of the functionality of the software 914167Sgiacomo.travaglini@arm.com * licensed hereunder. You may use the software subject to the license 1014167Sgiacomo.travaglini@arm.com * terms below provided that you ensure that this notice is replicated 1114167Sgiacomo.travaglini@arm.com * unmodified and in its entirety in all distributions of the software, 1214167Sgiacomo.travaglini@arm.com * modified or unmodified, in source code or in binary form. 1314167Sgiacomo.travaglini@arm.com * 1413531Sjairo.balart@metempsy.com * Redistribution and use in source and binary forms, with or without 1513531Sjairo.balart@metempsy.com * modification, are permitted provided that the following conditions are 1613531Sjairo.balart@metempsy.com * met: redistributions of source code must retain the above copyright 1713531Sjairo.balart@metempsy.com * notice, this list of conditions and the following disclaimer; 1813531Sjairo.balart@metempsy.com * redistributions in binary form must reproduce the above copyright 1913531Sjairo.balart@metempsy.com * notice, this list of conditions and the following disclaimer in the 2013531Sjairo.balart@metempsy.com * documentation and/or other materials provided with the distribution; 2113531Sjairo.balart@metempsy.com * neither the name of the copyright holders nor the names of its 2213531Sjairo.balart@metempsy.com * contributors may be used to endorse or promote products derived from 2313531Sjairo.balart@metempsy.com * this software without specific prior written permission. 2413531Sjairo.balart@metempsy.com * 2513531Sjairo.balart@metempsy.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2613531Sjairo.balart@metempsy.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2713531Sjairo.balart@metempsy.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2813531Sjairo.balart@metempsy.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2913531Sjairo.balart@metempsy.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3013531Sjairo.balart@metempsy.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3113531Sjairo.balart@metempsy.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3213531Sjairo.balart@metempsy.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3313531Sjairo.balart@metempsy.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3413531Sjairo.balart@metempsy.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3513531Sjairo.balart@metempsy.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3613531Sjairo.balart@metempsy.com * 3713531Sjairo.balart@metempsy.com * Authors: Gabe Black 3813531Sjairo.balart@metempsy.com * Ali Saidi 3913531Sjairo.balart@metempsy.com */ 4013531Sjairo.balart@metempsy.com 4113531Sjairo.balart@metempsy.com#include "arch/arm/isa.hh" 4213756Sjairo.balart@metempsy.com#include "arch/arm/pmu.hh" 4313531Sjairo.balart@metempsy.com#include "arch/arm/system.hh" 4413531Sjairo.balart@metempsy.com#include "cpu/checker/cpu.hh" 4513531Sjairo.balart@metempsy.com#include "cpu/base.hh" 4613531Sjairo.balart@metempsy.com#include "debug/Arm.hh" 4714257Sgiacomo.travaglini@arm.com#include "debug/MiscRegs.hh" 4813531Sjairo.balart@metempsy.com#include "dev/arm/generic_timer.hh" 4913531Sjairo.balart@metempsy.com#include "params/ArmISA.hh" 5013531Sjairo.balart@metempsy.com#include "sim/faults.hh" 5113531Sjairo.balart@metempsy.com#include "sim/stat_control.hh" 5213531Sjairo.balart@metempsy.com#include "sim/system.hh" 5313756Sjairo.balart@metempsy.com 5413756Sjairo.balart@metempsy.comnamespace ArmISA 5513756Sjairo.balart@metempsy.com{ 5613756Sjairo.balart@metempsy.com 5713756Sjairo.balart@metempsy.com 5813756Sjairo.balart@metempsy.com/** 5913756Sjairo.balart@metempsy.com * Some registers aliase with others, and therefore need to be translated. 6013531Sjairo.balart@metempsy.com * For each entry: 6113756Sjairo.balart@metempsy.com * The first value is the misc register that is to be looked up 6213756Sjairo.balart@metempsy.com * the second value is the lower part of the translation 6313756Sjairo.balart@metempsy.com * the third the upper part 6413756Sjairo.balart@metempsy.com */ 6513756Sjairo.balart@metempsy.comconst struct ISA::MiscRegInitializerEntry 6613756Sjairo.balart@metempsy.com ISA::MiscRegSwitch[miscRegTranslateMax] = { 6713756Sjairo.balart@metempsy.com {MISCREG_CSSELR_EL1, {MISCREG_CSSELR, 0}}, 6813531Sjairo.balart@metempsy.com {MISCREG_SCTLR_EL1, {MISCREG_SCTLR, 0}}, 6913531Sjairo.balart@metempsy.com {MISCREG_SCTLR_EL2, {MISCREG_HSCTLR, 0}}, 7013531Sjairo.balart@metempsy.com {MISCREG_ACTLR_EL1, {MISCREG_ACTLR, 0}}, 7113531Sjairo.balart@metempsy.com {MISCREG_ACTLR_EL2, {MISCREG_HACTLR, 0}}, 7213531Sjairo.balart@metempsy.com {MISCREG_CPACR_EL1, {MISCREG_CPACR, 0}}, 7313531Sjairo.balart@metempsy.com {MISCREG_CPTR_EL2, {MISCREG_HCPTR, 0}}, 7413531Sjairo.balart@metempsy.com {MISCREG_HCR_EL2, {MISCREG_HCR, 0}}, 7513531Sjairo.balart@metempsy.com {MISCREG_MDCR_EL2, {MISCREG_HDCR, 0}}, 7613531Sjairo.balart@metempsy.com {MISCREG_HSTR_EL2, {MISCREG_HSTR, 0}}, 7713531Sjairo.balart@metempsy.com {MISCREG_HACR_EL2, {MISCREG_HACR, 0}}, 7813531Sjairo.balart@metempsy.com {MISCREG_TTBR0_EL1, {MISCREG_TTBR0, 0}}, 7913531Sjairo.balart@metempsy.com {MISCREG_TTBR1_EL1, {MISCREG_TTBR1, 0}}, 8014167Sgiacomo.travaglini@arm.com {MISCREG_TTBR0_EL2, {MISCREG_HTTBR, 0}}, 8114257Sgiacomo.travaglini@arm.com {MISCREG_VTTBR_EL2, {MISCREG_VTTBR, 0}}, 8214167Sgiacomo.travaglini@arm.com {MISCREG_TCR_EL1, {MISCREG_TTBCR, 0}}, 8314167Sgiacomo.travaglini@arm.com {MISCREG_TCR_EL2, {MISCREG_HTCR, 0}}, 8414167Sgiacomo.travaglini@arm.com {MISCREG_VTCR_EL2, {MISCREG_VTCR, 0}}, 8514167Sgiacomo.travaglini@arm.com {MISCREG_AFSR0_EL1, {MISCREG_ADFSR, 0}}, 8614167Sgiacomo.travaglini@arm.com {MISCREG_AFSR1_EL1, {MISCREG_AIFSR, 0}}, 8713531Sjairo.balart@metempsy.com {MISCREG_AFSR0_EL2, {MISCREG_HADFSR, 0}}, 8813531Sjairo.balart@metempsy.com {MISCREG_AFSR1_EL2, {MISCREG_HAIFSR, 0}}, 8914257Sgiacomo.travaglini@arm.com {MISCREG_ESR_EL2, {MISCREG_HSR, 0}}, 9014257Sgiacomo.travaglini@arm.com {MISCREG_FAR_EL1, {MISCREG_DFAR, MISCREG_IFAR}}, 9114257Sgiacomo.travaglini@arm.com {MISCREG_FAR_EL2, {MISCREG_HDFAR, MISCREG_HIFAR}}, 9214257Sgiacomo.travaglini@arm.com {MISCREG_HPFAR_EL2, {MISCREG_HPFAR, 0}}, 9314257Sgiacomo.travaglini@arm.com {MISCREG_PAR_EL1, {MISCREG_PAR, 0}}, 9414257Sgiacomo.travaglini@arm.com {MISCREG_MAIR_EL1, {MISCREG_PRRR, MISCREG_NMRR}}, 9514257Sgiacomo.travaglini@arm.com {MISCREG_MAIR_EL2, {MISCREG_HMAIR0, MISCREG_HMAIR1}}, 9614257Sgiacomo.travaglini@arm.com {MISCREG_AMAIR_EL1, {MISCREG_AMAIR0, MISCREG_AMAIR1}}, 9714257Sgiacomo.travaglini@arm.com {MISCREG_VBAR_EL1, {MISCREG_VBAR, 0}}, 9814257Sgiacomo.travaglini@arm.com {MISCREG_VBAR_EL2, {MISCREG_HVBAR, 0}}, 9914257Sgiacomo.travaglini@arm.com {MISCREG_CONTEXTIDR_EL1, {MISCREG_CONTEXTIDR, 0}}, 10014257Sgiacomo.travaglini@arm.com {MISCREG_TPIDR_EL0, {MISCREG_TPIDRURW, 0}}, 10114257Sgiacomo.travaglini@arm.com {MISCREG_TPIDRRO_EL0, {MISCREG_TPIDRURO, 0}}, 10214257Sgiacomo.travaglini@arm.com {MISCREG_TPIDR_EL1, {MISCREG_TPIDRPRW, 0}}, 10314257Sgiacomo.travaglini@arm.com {MISCREG_TPIDR_EL2, {MISCREG_HTPIDR, 0}}, 10414257Sgiacomo.travaglini@arm.com {MISCREG_TEECR32_EL1, {MISCREG_TEECR, 0}}, 10514257Sgiacomo.travaglini@arm.com {MISCREG_CNTFRQ_EL0, {MISCREG_CNTFRQ, 0}}, 10614257Sgiacomo.travaglini@arm.com {MISCREG_CNTPCT_EL0, {MISCREG_CNTPCT, 0}}, 10714257Sgiacomo.travaglini@arm.com {MISCREG_CNTVCT_EL0, {MISCREG_CNTVCT, 0}}, 10814257Sgiacomo.travaglini@arm.com {MISCREG_CNTVOFF_EL2, {MISCREG_CNTVOFF, 0}}, 10914257Sgiacomo.travaglini@arm.com {MISCREG_CNTKCTL_EL1, {MISCREG_CNTKCTL, 0}}, 11014257Sgiacomo.travaglini@arm.com {MISCREG_CNTHCTL_EL2, {MISCREG_CNTHCTL, 0}}, 11114257Sgiacomo.travaglini@arm.com {MISCREG_CNTP_TVAL_EL0, {MISCREG_CNTP_TVAL, 0}}, 11214257Sgiacomo.travaglini@arm.com {MISCREG_CNTP_CTL_EL0, {MISCREG_CNTP_CTL, 0}}, 11314257Sgiacomo.travaglini@arm.com {MISCREG_CNTP_CVAL_EL0, {MISCREG_CNTP_CVAL, 0}}, 11414257Sgiacomo.travaglini@arm.com {MISCREG_CNTV_TVAL_EL0, {MISCREG_CNTV_TVAL, 0}}, 11514257Sgiacomo.travaglini@arm.com {MISCREG_CNTV_CTL_EL0, {MISCREG_CNTV_CTL, 0}}, 11614257Sgiacomo.travaglini@arm.com {MISCREG_CNTV_CVAL_EL0, {MISCREG_CNTV_CVAL, 0}}, 11714257Sgiacomo.travaglini@arm.com {MISCREG_CNTHP_TVAL_EL2, {MISCREG_CNTHP_TVAL, 0}}, 11814257Sgiacomo.travaglini@arm.com {MISCREG_CNTHP_CTL_EL2, {MISCREG_CNTHP_CTL, 0}}, 11914257Sgiacomo.travaglini@arm.com {MISCREG_CNTHP_CVAL_EL2, {MISCREG_CNTHP_CVAL, 0}}, 12013531Sjairo.balart@metempsy.com {MISCREG_DACR32_EL2, {MISCREG_DACR, 0}}, 12113531Sjairo.balart@metempsy.com {MISCREG_IFSR32_EL2, {MISCREG_IFSR, 0}}, 12213531Sjairo.balart@metempsy.com {MISCREG_TEEHBR32_EL1, {MISCREG_TEEHBR, 0}}, 12313531Sjairo.balart@metempsy.com {MISCREG_SDER32_EL3, {MISCREG_SDER, 0}} 12413531Sjairo.balart@metempsy.com}; 12513531Sjairo.balart@metempsy.com 12613531Sjairo.balart@metempsy.com 12713531Sjairo.balart@metempsy.comISA::ISA(Params *p) 12813531Sjairo.balart@metempsy.com : SimObject(p), 12913531Sjairo.balart@metempsy.com system(NULL), 13013531Sjairo.balart@metempsy.com _decoderFlavour(p->decoderFlavour), 13113531Sjairo.balart@metempsy.com pmu(p->pmu), 13213531Sjairo.balart@metempsy.com lookUpMiscReg(NUM_MISCREGS, {0,0}) 13313531Sjairo.balart@metempsy.com{ 13413531Sjairo.balart@metempsy.com SCTLR sctlr; 13513531Sjairo.balart@metempsy.com sctlr = 0; 13613531Sjairo.balart@metempsy.com miscRegs[MISCREG_SCTLR_RST] = sctlr; 13713531Sjairo.balart@metempsy.com 13813531Sjairo.balart@metempsy.com // Hook up a dummy device if we haven't been configured with a 13913531Sjairo.balart@metempsy.com // real PMU. By using a dummy device, we don't need to check that 14013531Sjairo.balart@metempsy.com // the PMU exist every time we try to access a PMU register. 14113531Sjairo.balart@metempsy.com if (!pmu) 14213531Sjairo.balart@metempsy.com pmu = &dummyDevice; 14313531Sjairo.balart@metempsy.com 14413531Sjairo.balart@metempsy.com // Give all ISA devices a pointer to this ISA 14513531Sjairo.balart@metempsy.com pmu->setISA(this); 14613531Sjairo.balart@metempsy.com 14713531Sjairo.balart@metempsy.com system = dynamic_cast<ArmSystem *>(p->system); 14813531Sjairo.balart@metempsy.com 14913531Sjairo.balart@metempsy.com // Cache system-level properties 15013531Sjairo.balart@metempsy.com if (FullSystem && system) { 15113531Sjairo.balart@metempsy.com haveSecurity = system->haveSecurity(); 15213531Sjairo.balart@metempsy.com haveLPAE = system->haveLPAE(); 15313531Sjairo.balart@metempsy.com haveVirtualization = system->haveVirtualization(); 15413531Sjairo.balart@metempsy.com haveLargeAsid64 = system->haveLargeAsid64(); 15513531Sjairo.balart@metempsy.com physAddrRange64 = system->physAddrRange64(); 15613531Sjairo.balart@metempsy.com } else { 15713531Sjairo.balart@metempsy.com haveSecurity = haveLPAE = haveVirtualization = false; 15813531Sjairo.balart@metempsy.com haveLargeAsid64 = false; 15913531Sjairo.balart@metempsy.com physAddrRange64 = 32; // dummy value 16013531Sjairo.balart@metempsy.com } 16113531Sjairo.balart@metempsy.com 16213531Sjairo.balart@metempsy.com /** Fill in the miscReg translation table */ 16313531Sjairo.balart@metempsy.com for (uint32_t i = 0; i < miscRegTranslateMax; i++) { 16413531Sjairo.balart@metempsy.com struct MiscRegLUTEntry new_entry; 16513531Sjairo.balart@metempsy.com 16613531Sjairo.balart@metempsy.com uint32_t select = MiscRegSwitch[i].index; 16713531Sjairo.balart@metempsy.com new_entry = MiscRegSwitch[i].entry; 16813531Sjairo.balart@metempsy.com 16913531Sjairo.balart@metempsy.com lookUpMiscReg[select] = new_entry; 17013531Sjairo.balart@metempsy.com } 17113531Sjairo.balart@metempsy.com 17213531Sjairo.balart@metempsy.com preUnflattenMiscReg(); 17313531Sjairo.balart@metempsy.com 17413531Sjairo.balart@metempsy.com clear(); 17513531Sjairo.balart@metempsy.com} 17613531Sjairo.balart@metempsy.com 17713531Sjairo.balart@metempsy.comconst ArmISAParams * 17813531Sjairo.balart@metempsy.comISA::params() const 17913531Sjairo.balart@metempsy.com{ 18013531Sjairo.balart@metempsy.com return dynamic_cast<const Params *>(_params); 18113531Sjairo.balart@metempsy.com} 18213756Sjairo.balart@metempsy.com 18313531Sjairo.balart@metempsy.comvoid 18413531Sjairo.balart@metempsy.comISA::clear() 18513531Sjairo.balart@metempsy.com{ 18613531Sjairo.balart@metempsy.com const Params *p(params()); 18713756Sjairo.balart@metempsy.com 18813531Sjairo.balart@metempsy.com SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 18913531Sjairo.balart@metempsy.com memset(miscRegs, 0, sizeof(miscRegs)); 19013531Sjairo.balart@metempsy.com 19113531Sjairo.balart@metempsy.com // Initialize configurable default values 19213531Sjairo.balart@metempsy.com miscRegs[MISCREG_MIDR] = p->midr; 19313531Sjairo.balart@metempsy.com miscRegs[MISCREG_MIDR_EL1] = p->midr; 19413531Sjairo.balart@metempsy.com miscRegs[MISCREG_VPIDR] = p->midr; 19513531Sjairo.balart@metempsy.com 19613531Sjairo.balart@metempsy.com if (FullSystem && system->highestELIs64()) { 19713756Sjairo.balart@metempsy.com // Initialize AArch64 state 19813756Sjairo.balart@metempsy.com clear64(p); 19913531Sjairo.balart@metempsy.com return; 20013531Sjairo.balart@metempsy.com } 20113531Sjairo.balart@metempsy.com 20213531Sjairo.balart@metempsy.com // Initialize AArch32 state... 20313531Sjairo.balart@metempsy.com 20413531Sjairo.balart@metempsy.com CPSR cpsr = 0; 20513531Sjairo.balart@metempsy.com cpsr.mode = MODE_USER; 20613531Sjairo.balart@metempsy.com miscRegs[MISCREG_CPSR] = cpsr; 20713531Sjairo.balart@metempsy.com updateRegMap(cpsr); 20813531Sjairo.balart@metempsy.com 20913531Sjairo.balart@metempsy.com SCTLR sctlr = 0; 21013531Sjairo.balart@metempsy.com sctlr.te = (bool) sctlr_rst.te; 21113531Sjairo.balart@metempsy.com sctlr.nmfi = (bool) sctlr_rst.nmfi; 21213531Sjairo.balart@metempsy.com sctlr.v = (bool) sctlr_rst.v; 21313531Sjairo.balart@metempsy.com sctlr.u = 1; 21413531Sjairo.balart@metempsy.com sctlr.xp = 1; 21513531Sjairo.balart@metempsy.com sctlr.rao2 = 1; 21613531Sjairo.balart@metempsy.com sctlr.rao3 = 1; 21713531Sjairo.balart@metempsy.com sctlr.rao4 = 0xf; // SCTLR[6:3] 21813756Sjairo.balart@metempsy.com sctlr.uci = 1; 21913756Sjairo.balart@metempsy.com sctlr.dze = 1; 22013531Sjairo.balart@metempsy.com miscRegs[MISCREG_SCTLR_NS] = sctlr; 22113531Sjairo.balart@metempsy.com miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 22213531Sjairo.balart@metempsy.com miscRegs[MISCREG_HCPTR] = 0; 22313531Sjairo.balart@metempsy.com 22413531Sjairo.balart@metempsy.com // Start with an event in the mailbox 22513531Sjairo.balart@metempsy.com miscRegs[MISCREG_SEV_MAILBOX] = 1; 22613531Sjairo.balart@metempsy.com 22713531Sjairo.balart@metempsy.com // Separate Instruction and Data TLBs 22813531Sjairo.balart@metempsy.com miscRegs[MISCREG_TLBTR] = 1; 22913531Sjairo.balart@metempsy.com 23013756Sjairo.balart@metempsy.com MVFR0 mvfr0 = 0; 23113531Sjairo.balart@metempsy.com mvfr0.advSimdRegisters = 2; 23213531Sjairo.balart@metempsy.com mvfr0.singlePrecision = 2; 23313531Sjairo.balart@metempsy.com mvfr0.doublePrecision = 2; 23413531Sjairo.balart@metempsy.com mvfr0.vfpExceptionTrapping = 0; 23513531Sjairo.balart@metempsy.com mvfr0.divide = 1; 23613531Sjairo.balart@metempsy.com mvfr0.squareRoot = 1; 23713531Sjairo.balart@metempsy.com mvfr0.shortVectors = 1; 23813531Sjairo.balart@metempsy.com mvfr0.roundingModes = 1; 23913756Sjairo.balart@metempsy.com miscRegs[MISCREG_MVFR0] = mvfr0; 24013756Sjairo.balart@metempsy.com 24113531Sjairo.balart@metempsy.com MVFR1 mvfr1 = 0; 24213531Sjairo.balart@metempsy.com mvfr1.flushToZero = 1; 24313531Sjairo.balart@metempsy.com mvfr1.defaultNaN = 1; 24413531Sjairo.balart@metempsy.com mvfr1.advSimdLoadStore = 1; 24513531Sjairo.balart@metempsy.com mvfr1.advSimdInteger = 1; 24613531Sjairo.balart@metempsy.com mvfr1.advSimdSinglePrecision = 1; 24713531Sjairo.balart@metempsy.com mvfr1.advSimdHalfPrecision = 1; 24813531Sjairo.balart@metempsy.com mvfr1.vfpHalfPrecision = 1; 24913531Sjairo.balart@metempsy.com miscRegs[MISCREG_MVFR1] = mvfr1; 25013531Sjairo.balart@metempsy.com 25113531Sjairo.balart@metempsy.com // Reset values of PRRR and NMRR are implementation dependent 25213531Sjairo.balart@metempsy.com 25313531Sjairo.balart@metempsy.com // @todo: PRRR and NMRR in secure state? 25413756Sjairo.balart@metempsy.com miscRegs[MISCREG_PRRR_NS] = 25513531Sjairo.balart@metempsy.com (1 << 19) | // 19 25613531Sjairo.balart@metempsy.com (0 << 18) | // 18 25713531Sjairo.balart@metempsy.com (0 << 17) | // 17 25813531Sjairo.balart@metempsy.com (1 << 16) | // 16 25913531Sjairo.balart@metempsy.com (2 << 14) | // 15:14 26013531Sjairo.balart@metempsy.com (0 << 12) | // 13:12 26113531Sjairo.balart@metempsy.com (2 << 10) | // 11:10 26213531Sjairo.balart@metempsy.com (2 << 8) | // 9:8 26313756Sjairo.balart@metempsy.com (2 << 6) | // 7:6 26413756Sjairo.balart@metempsy.com (2 << 4) | // 5:4 26513531Sjairo.balart@metempsy.com (1 << 2) | // 3:2 26613531Sjairo.balart@metempsy.com 0; // 1:0 26713531Sjairo.balart@metempsy.com miscRegs[MISCREG_NMRR_NS] = 26813531Sjairo.balart@metempsy.com (1 << 30) | // 31:30 26913531Sjairo.balart@metempsy.com (0 << 26) | // 27:26 27013531Sjairo.balart@metempsy.com (0 << 24) | // 25:24 27113531Sjairo.balart@metempsy.com (3 << 22) | // 23:22 27213531Sjairo.balart@metempsy.com (2 << 20) | // 21:20 27313531Sjairo.balart@metempsy.com (0 << 18) | // 19:18 27413531Sjairo.balart@metempsy.com (0 << 16) | // 17:16 27513531Sjairo.balart@metempsy.com (1 << 14) | // 15:14 27613531Sjairo.balart@metempsy.com (0 << 12) | // 13:12 27713756Sjairo.balart@metempsy.com (2 << 10) | // 11:10 27813531Sjairo.balart@metempsy.com (0 << 8) | // 9:8 27913531Sjairo.balart@metempsy.com (3 << 6) | // 7:6 28013531Sjairo.balart@metempsy.com (2 << 4) | // 5:4 28113531Sjairo.balart@metempsy.com (0 << 2) | // 3:2 28213531Sjairo.balart@metempsy.com 0; // 1:0 28313531Sjairo.balart@metempsy.com 28413531Sjairo.balart@metempsy.com miscRegs[MISCREG_CPACR] = 0; 28513531Sjairo.balart@metempsy.com 28613531Sjairo.balart@metempsy.com 28713531Sjairo.balart@metempsy.com miscRegs[MISCREG_ID_PFR0] = p->id_pfr0; 28813756Sjairo.balart@metempsy.com miscRegs[MISCREG_ID_PFR1] = p->id_pfr1; 28913756Sjairo.balart@metempsy.com 29013531Sjairo.balart@metempsy.com miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 29113531Sjairo.balart@metempsy.com miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 29213531Sjairo.balart@metempsy.com miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 29313531Sjairo.balart@metempsy.com miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 29413531Sjairo.balart@metempsy.com 29513531Sjairo.balart@metempsy.com miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 29613531Sjairo.balart@metempsy.com miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 29713531Sjairo.balart@metempsy.com miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 29813531Sjairo.balart@metempsy.com miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 29913531Sjairo.balart@metempsy.com miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 30013531Sjairo.balart@metempsy.com miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 30113531Sjairo.balart@metempsy.com 30213756Sjairo.balart@metempsy.com miscRegs[MISCREG_FPSID] = p->fpsid; 30313531Sjairo.balart@metempsy.com 30413531Sjairo.balart@metempsy.com if (haveLPAE) { 30513531Sjairo.balart@metempsy.com TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 30613531Sjairo.balart@metempsy.com ttbcr.eae = 0; 30713531Sjairo.balart@metempsy.com miscRegs[MISCREG_TTBCR_NS] = ttbcr; 30813531Sjairo.balart@metempsy.com // Enforce consistency with system-level settings 30913531Sjairo.balart@metempsy.com miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 31013531Sjairo.balart@metempsy.com } 31113531Sjairo.balart@metempsy.com 31213531Sjairo.balart@metempsy.com if (haveSecurity) { 31313756Sjairo.balart@metempsy.com miscRegs[MISCREG_SCTLR_S] = sctlr; 31413756Sjairo.balart@metempsy.com miscRegs[MISCREG_SCR] = 0; 31513531Sjairo.balart@metempsy.com miscRegs[MISCREG_VBAR_S] = 0; 31613531Sjairo.balart@metempsy.com } else { 31713531Sjairo.balart@metempsy.com // we're always non-secure 31813531Sjairo.balart@metempsy.com miscRegs[MISCREG_SCR] = 1; 31913531Sjairo.balart@metempsy.com } 32013531Sjairo.balart@metempsy.com 32113531Sjairo.balart@metempsy.com //XXX We need to initialize the rest of the state. 32213531Sjairo.balart@metempsy.com} 32313531Sjairo.balart@metempsy.com 32413531Sjairo.balart@metempsy.comvoid 32513531Sjairo.balart@metempsy.comISA::clear64(const ArmISAParams *p) 32613756Sjairo.balart@metempsy.com{ 32713531Sjairo.balart@metempsy.com CPSR cpsr = 0; 32813531Sjairo.balart@metempsy.com Addr rvbar = system->resetAddr64(); 32913531Sjairo.balart@metempsy.com switch (system->highestEL()) { 33013531Sjairo.balart@metempsy.com // Set initial EL to highest implemented EL using associated stack 33113531Sjairo.balart@metempsy.com // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 33213531Sjairo.balart@metempsy.com // value 33313531Sjairo.balart@metempsy.com case EL3: 33413531Sjairo.balart@metempsy.com cpsr.mode = MODE_EL3H; 33513531Sjairo.balart@metempsy.com miscRegs[MISCREG_RVBAR_EL3] = rvbar; 33613756Sjairo.balart@metempsy.com break; 33713756Sjairo.balart@metempsy.com case EL2: 33813531Sjairo.balart@metempsy.com cpsr.mode = MODE_EL2H; 33913531Sjairo.balart@metempsy.com miscRegs[MISCREG_RVBAR_EL2] = rvbar; 34013531Sjairo.balart@metempsy.com break; 34113531Sjairo.balart@metempsy.com case EL1: 34213531Sjairo.balart@metempsy.com cpsr.mode = MODE_EL1H; 34313531Sjairo.balart@metempsy.com miscRegs[MISCREG_RVBAR_EL1] = rvbar; 34413531Sjairo.balart@metempsy.com break; 34513531Sjairo.balart@metempsy.com default: 34613531Sjairo.balart@metempsy.com panic("Invalid highest implemented exception level"); 34713531Sjairo.balart@metempsy.com break; 34813531Sjairo.balart@metempsy.com } 34913531Sjairo.balart@metempsy.com 35013531Sjairo.balart@metempsy.com // Initialize rest of CPSR 35113531Sjairo.balart@metempsy.com cpsr.daif = 0xf; // Mask all interrupts 35213531Sjairo.balart@metempsy.com cpsr.ss = 0; 35313531Sjairo.balart@metempsy.com cpsr.il = 0; 35413531Sjairo.balart@metempsy.com miscRegs[MISCREG_CPSR] = cpsr; 35513531Sjairo.balart@metempsy.com updateRegMap(cpsr); 35613531Sjairo.balart@metempsy.com 35713531Sjairo.balart@metempsy.com // Initialize other control registers 35813531Sjairo.balart@metempsy.com miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 35913531Sjairo.balart@metempsy.com if (haveSecurity) { 36013756Sjairo.balart@metempsy.com miscRegs[MISCREG_SCTLR_EL3] = 0x30c50870; 36113531Sjairo.balart@metempsy.com miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 36213531Sjairo.balart@metempsy.com } else if (haveVirtualization) { 36313531Sjairo.balart@metempsy.com miscRegs[MISCREG_SCTLR_EL2] = 0x30c50870; 36413531Sjairo.balart@metempsy.com } else { 36513531Sjairo.balart@metempsy.com miscRegs[MISCREG_SCTLR_EL1] = 0x30c50870; 36613531Sjairo.balart@metempsy.com // Always non-secure 36713531Sjairo.balart@metempsy.com miscRegs[MISCREG_SCR_EL3] = 1; 36813531Sjairo.balart@metempsy.com } 36913531Sjairo.balart@metempsy.com 37013531Sjairo.balart@metempsy.com // Initialize configurable id registers 37113756Sjairo.balart@metempsy.com miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 37213756Sjairo.balart@metempsy.com miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 37313531Sjairo.balart@metempsy.com miscRegs[MISCREG_ID_AA64DFR0_EL1] = 37413531Sjairo.balart@metempsy.com (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 37513531Sjairo.balart@metempsy.com (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 37613531Sjairo.balart@metempsy.com 37713531Sjairo.balart@metempsy.com miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 37813531Sjairo.balart@metempsy.com miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 37913531Sjairo.balart@metempsy.com miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 38013531Sjairo.balart@metempsy.com miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 38113531Sjairo.balart@metempsy.com miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 38213531Sjairo.balart@metempsy.com miscRegs[MISCREG_ID_AA64PFR0_EL1] = p->id_aa64pfr0_el1; 38313531Sjairo.balart@metempsy.com miscRegs[MISCREG_ID_AA64PFR1_EL1] = p->id_aa64pfr1_el1; 38413531Sjairo.balart@metempsy.com 38513531Sjairo.balart@metempsy.com miscRegs[MISCREG_ID_DFR0_EL1] = 38613531Sjairo.balart@metempsy.com (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 38713531Sjairo.balart@metempsy.com 38813531Sjairo.balart@metempsy.com miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 38913531Sjairo.balart@metempsy.com 39013531Sjairo.balart@metempsy.com // Enforce consistency with system-level settings... 39113531Sjairo.balart@metempsy.com 39213531Sjairo.balart@metempsy.com // EL3 39313531Sjairo.balart@metempsy.com miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 39413531Sjairo.balart@metempsy.com miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 39513531Sjairo.balart@metempsy.com haveSecurity ? 0x2 : 0x0); 39613531Sjairo.balart@metempsy.com // EL2 39713531Sjairo.balart@metempsy.com miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 39813531Sjairo.balart@metempsy.com miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 39913531Sjairo.balart@metempsy.com haveVirtualization ? 0x2 : 0x0); 40013531Sjairo.balart@metempsy.com // Large ASID support 40113531Sjairo.balart@metempsy.com miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 40213531Sjairo.balart@metempsy.com miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 40313756Sjairo.balart@metempsy.com haveLargeAsid64 ? 0x2 : 0x0); 40413531Sjairo.balart@metempsy.com // Physical address size 40513531Sjairo.balart@metempsy.com miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 40613531Sjairo.balart@metempsy.com miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 40713531Sjairo.balart@metempsy.com encodePhysAddrRange64(physAddrRange64)); 40813531Sjairo.balart@metempsy.com} 40913531Sjairo.balart@metempsy.com 41013756Sjairo.balart@metempsy.comMiscReg 41113531Sjairo.balart@metempsy.comISA::readMiscRegNoEffect(int misc_reg) const 41213531Sjairo.balart@metempsy.com{ 41313531Sjairo.balart@metempsy.com assert(misc_reg < NumMiscRegs); 41413531Sjairo.balart@metempsy.com 41513531Sjairo.balart@metempsy.com int flat_idx = flattenMiscIndex(misc_reg); // Note: indexes of AArch64 41613531Sjairo.balart@metempsy.com // registers are left unchanged 41713531Sjairo.balart@metempsy.com MiscReg val; 41813531Sjairo.balart@metempsy.com 41913531Sjairo.balart@metempsy.com if (lookUpMiscReg[flat_idx].lower == 0 || flat_idx == MISCREG_SPSR 42013531Sjairo.balart@metempsy.com || flat_idx == MISCREG_SCTLR_EL1) { 42113531Sjairo.balart@metempsy.com if (flat_idx == MISCREG_SPSR) 42213531Sjairo.balart@metempsy.com flat_idx = flattenMiscIndex(MISCREG_SPSR); 42313531Sjairo.balart@metempsy.com if (flat_idx == MISCREG_SCTLR_EL1) 42413531Sjairo.balart@metempsy.com flat_idx = flattenMiscIndex(MISCREG_SCTLR); 42513531Sjairo.balart@metempsy.com val = miscRegs[flat_idx]; 42613756Sjairo.balart@metempsy.com } else 42713531Sjairo.balart@metempsy.com if (lookUpMiscReg[flat_idx].upper > 0) 42813531Sjairo.balart@metempsy.com val = ((miscRegs[lookUpMiscReg[flat_idx].lower] & mask(32)) 42913531Sjairo.balart@metempsy.com | (miscRegs[lookUpMiscReg[flat_idx].upper] << 32)); 43013531Sjairo.balart@metempsy.com else 43113531Sjairo.balart@metempsy.com val = miscRegs[lookUpMiscReg[flat_idx].lower]; 43213531Sjairo.balart@metempsy.com 43313531Sjairo.balart@metempsy.com return val; 43413531Sjairo.balart@metempsy.com} 43513531Sjairo.balart@metempsy.com 43613531Sjairo.balart@metempsy.com 43713531Sjairo.balart@metempsy.comMiscReg 43813531Sjairo.balart@metempsy.comISA::readMiscReg(int misc_reg, ThreadContext *tc) 43913531Sjairo.balart@metempsy.com{ 44013531Sjairo.balart@metempsy.com CPSR cpsr = 0; 44113531Sjairo.balart@metempsy.com PCState pc = 0; 44213531Sjairo.balart@metempsy.com SCR scr = 0; 44313531Sjairo.balart@metempsy.com 44413531Sjairo.balart@metempsy.com if (misc_reg == MISCREG_CPSR) { 44513531Sjairo.balart@metempsy.com cpsr = miscRegs[misc_reg]; 44613531Sjairo.balart@metempsy.com pc = tc->pcState(); 44713531Sjairo.balart@metempsy.com cpsr.j = pc.jazelle() ? 1 : 0; 44813531Sjairo.balart@metempsy.com cpsr.t = pc.thumb() ? 1 : 0; 44913531Sjairo.balart@metempsy.com return cpsr; 45013531Sjairo.balart@metempsy.com } 45113531Sjairo.balart@metempsy.com 45213531Sjairo.balart@metempsy.com#ifndef NDEBUG 45313531Sjairo.balart@metempsy.com if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 45413531Sjairo.balart@metempsy.com if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 45513531Sjairo.balart@metempsy.com warn("Unimplemented system register %s read.\n", 45613531Sjairo.balart@metempsy.com miscRegName[misc_reg]); 45713531Sjairo.balart@metempsy.com else 45813531Sjairo.balart@metempsy.com panic("Unimplemented system register %s read.\n", 45913531Sjairo.balart@metempsy.com miscRegName[misc_reg]); 46013531Sjairo.balart@metempsy.com } 46113531Sjairo.balart@metempsy.com#endif 46213531Sjairo.balart@metempsy.com 46313531Sjairo.balart@metempsy.com switch (unflattenMiscReg(misc_reg)) { 46413531Sjairo.balart@metempsy.com case MISCREG_HCR: 46513531Sjairo.balart@metempsy.com { 46613531Sjairo.balart@metempsy.com if (!haveVirtualization) 46713531Sjairo.balart@metempsy.com return 0; 46813531Sjairo.balart@metempsy.com else 46913531Sjairo.balart@metempsy.com return readMiscRegNoEffect(MISCREG_HCR); 47013531Sjairo.balart@metempsy.com } 47113531Sjairo.balart@metempsy.com case MISCREG_CPACR: 47213531Sjairo.balart@metempsy.com { 47313531Sjairo.balart@metempsy.com const uint32_t ones = (uint32_t)(-1); 47413531Sjairo.balart@metempsy.com CPACR cpacrMask = 0; 47513531Sjairo.balart@metempsy.com // Only cp10, cp11, and ase are implemented, nothing else should 47613531Sjairo.balart@metempsy.com // be readable? (straight copy from the write code) 47713531Sjairo.balart@metempsy.com cpacrMask.cp10 = ones; 47813531Sjairo.balart@metempsy.com cpacrMask.cp11 = ones; 47913531Sjairo.balart@metempsy.com cpacrMask.asedis = ones; 48013531Sjairo.balart@metempsy.com 48113531Sjairo.balart@metempsy.com // Security Extensions may limit the readability of CPACR 48213531Sjairo.balart@metempsy.com if (haveSecurity) { 48313531Sjairo.balart@metempsy.com scr = readMiscRegNoEffect(MISCREG_SCR); 48413531Sjairo.balart@metempsy.com cpsr = readMiscRegNoEffect(MISCREG_CPSR); 48513531Sjairo.balart@metempsy.com if (scr.ns && (cpsr.mode != MODE_MON)) { 48613531Sjairo.balart@metempsy.com NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 48713531Sjairo.balart@metempsy.com // NB: Skipping the full loop, here 48813531Sjairo.balart@metempsy.com if (!nsacr.cp10) cpacrMask.cp10 = 0; 48913531Sjairo.balart@metempsy.com if (!nsacr.cp11) cpacrMask.cp11 = 0; 49013531Sjairo.balart@metempsy.com } 49113531Sjairo.balart@metempsy.com } 49213531Sjairo.balart@metempsy.com MiscReg val = readMiscRegNoEffect(MISCREG_CPACR); 49313531Sjairo.balart@metempsy.com val &= cpacrMask; 49413531Sjairo.balart@metempsy.com DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 49513531Sjairo.balart@metempsy.com miscRegName[misc_reg], val); 49613531Sjairo.balart@metempsy.com return val; 49714257Sgiacomo.travaglini@arm.com } 49813531Sjairo.balart@metempsy.com case MISCREG_MPIDR: 49913531Sjairo.balart@metempsy.com cpsr = readMiscRegNoEffect(MISCREG_CPSR); 50013531Sjairo.balart@metempsy.com scr = readMiscRegNoEffect(MISCREG_SCR); 50113531Sjairo.balart@metempsy.com if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 50213531Sjairo.balart@metempsy.com return getMPIDR(system, tc); 50313531Sjairo.balart@metempsy.com } else { 50413531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_VMPIDR, tc); 50513531Sjairo.balart@metempsy.com } 50613531Sjairo.balart@metempsy.com break; 50713756Sjairo.balart@metempsy.com case MISCREG_MPIDR_EL1: 50814167Sgiacomo.travaglini@arm.com // @todo in the absence of v8 virtualization support just return MPIDR_EL1 50913531Sjairo.balart@metempsy.com return getMPIDR(system, tc) & 0xffffffff; 51014167Sgiacomo.travaglini@arm.com case MISCREG_VMPIDR: 51114167Sgiacomo.travaglini@arm.com // top bit defined as RES1 51213531Sjairo.balart@metempsy.com return readMiscRegNoEffect(misc_reg) | 0x80000000; 51314167Sgiacomo.travaglini@arm.com case MISCREG_ID_AFR0: // not implemented, so alias MIDR 51414167Sgiacomo.travaglini@arm.com case MISCREG_REVIDR: // not implemented, so alias MIDR 51513531Sjairo.balart@metempsy.com case MISCREG_MIDR: 51613531Sjairo.balart@metempsy.com cpsr = readMiscRegNoEffect(MISCREG_CPSR); 51714167Sgiacomo.travaglini@arm.com scr = readMiscRegNoEffect(MISCREG_SCR); 51813531Sjairo.balart@metempsy.com if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 51914167Sgiacomo.travaglini@arm.com return readMiscRegNoEffect(misc_reg); 52014167Sgiacomo.travaglini@arm.com } else { 52113531Sjairo.balart@metempsy.com return readMiscRegNoEffect(MISCREG_VPIDR); 52213531Sjairo.balart@metempsy.com } 52313531Sjairo.balart@metempsy.com break; 52413531Sjairo.balart@metempsy.com case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 52513531Sjairo.balart@metempsy.com case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 52613531Sjairo.balart@metempsy.com case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 52713531Sjairo.balart@metempsy.com case MISCREG_AIDR: // AUX ID set to 0 52813531Sjairo.balart@metempsy.com case MISCREG_TCMTR: // No TCM's 52913531Sjairo.balart@metempsy.com return 0; 53013531Sjairo.balart@metempsy.com 53113531Sjairo.balart@metempsy.com case MISCREG_CLIDR: 53213531Sjairo.balart@metempsy.com warn_once("The clidr register always reports 0 caches.\n"); 53313531Sjairo.balart@metempsy.com warn_once("clidr LoUIS field of 0b001 to match current " 53413531Sjairo.balart@metempsy.com "ARM implementations.\n"); 53513531Sjairo.balart@metempsy.com return 0x00200000; 53613531Sjairo.balart@metempsy.com case MISCREG_CCSIDR: 53713531Sjairo.balart@metempsy.com warn_once("The ccsidr register isn't implemented and " 53813531Sjairo.balart@metempsy.com "always reads as 0.\n"); 53913531Sjairo.balart@metempsy.com break; 54013531Sjairo.balart@metempsy.com case MISCREG_CTR: 54113531Sjairo.balart@metempsy.com { 54213531Sjairo.balart@metempsy.com //all caches have the same line size in gem5 54313531Sjairo.balart@metempsy.com //4 byte words in ARM 54413531Sjairo.balart@metempsy.com unsigned lineSizeWords = 54513531Sjairo.balart@metempsy.com tc->getSystemPtr()->cacheLineSize() / 4; 54613531Sjairo.balart@metempsy.com unsigned log2LineSizeWords = 0; 54713531Sjairo.balart@metempsy.com 54813531Sjairo.balart@metempsy.com while (lineSizeWords >>= 1) { 54913531Sjairo.balart@metempsy.com ++log2LineSizeWords; 55013756Sjairo.balart@metempsy.com } 55113531Sjairo.balart@metempsy.com 55213531Sjairo.balart@metempsy.com CTR ctr = 0; 55313531Sjairo.balart@metempsy.com //log2 of minimun i-cache line size (words) 55413531Sjairo.balart@metempsy.com ctr.iCacheLineSize = log2LineSizeWords; 55513531Sjairo.balart@metempsy.com //b11 - gem5 uses pipt 55613531Sjairo.balart@metempsy.com ctr.l1IndexPolicy = 0x3; 55713756Sjairo.balart@metempsy.com //log2 of minimum d-cache line size (words) 55813531Sjairo.balart@metempsy.com ctr.dCacheLineSize = log2LineSizeWords; 55913531Sjairo.balart@metempsy.com //log2 of max reservation size (words) 56013531Sjairo.balart@metempsy.com ctr.erg = log2LineSizeWords; 56113531Sjairo.balart@metempsy.com //log2 of max writeback size (words) 56213531Sjairo.balart@metempsy.com ctr.cwg = log2LineSizeWords; 56313531Sjairo.balart@metempsy.com //b100 - gem5 format is ARMv7 56413531Sjairo.balart@metempsy.com ctr.format = 0x4; 56513531Sjairo.balart@metempsy.com 56613756Sjairo.balart@metempsy.com return ctr; 56713756Sjairo.balart@metempsy.com } 56813531Sjairo.balart@metempsy.com case MISCREG_ACTLR: 56913531Sjairo.balart@metempsy.com warn("Not doing anything for miscreg ACTLR\n"); 57013531Sjairo.balart@metempsy.com break; 57113531Sjairo.balart@metempsy.com 57213531Sjairo.balart@metempsy.com case MISCREG_PMXEVTYPER_PMCCFILTR: 57313531Sjairo.balart@metempsy.com case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 57413531Sjairo.balart@metempsy.com case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 57513531Sjairo.balart@metempsy.com case MISCREG_PMCR ... MISCREG_PMOVSSET: 57613531Sjairo.balart@metempsy.com return pmu->readMiscReg(misc_reg); 57713531Sjairo.balart@metempsy.com 57813531Sjairo.balart@metempsy.com case MISCREG_CPSR_Q: 57913531Sjairo.balart@metempsy.com panic("shouldn't be reading this register seperately\n"); 58013531Sjairo.balart@metempsy.com case MISCREG_FPSCR_QC: 58113531Sjairo.balart@metempsy.com return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 58213531Sjairo.balart@metempsy.com case MISCREG_FPSCR_EXC: 58313531Sjairo.balart@metempsy.com return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 58413531Sjairo.balart@metempsy.com case MISCREG_FPSR: 58513531Sjairo.balart@metempsy.com { 58613531Sjairo.balart@metempsy.com const uint32_t ones = (uint32_t)(-1); 58713531Sjairo.balart@metempsy.com FPSCR fpscrMask = 0; 58813531Sjairo.balart@metempsy.com fpscrMask.ioc = ones; 58913531Sjairo.balart@metempsy.com fpscrMask.dzc = ones; 59013812Sgiacomo.travaglini@arm.com fpscrMask.ofc = ones; 59113812Sgiacomo.travaglini@arm.com fpscrMask.ufc = ones; 59213812Sgiacomo.travaglini@arm.com fpscrMask.ixc = ones; 59313812Sgiacomo.travaglini@arm.com fpscrMask.idc = ones; 59413531Sjairo.balart@metempsy.com fpscrMask.qc = ones; 59513756Sjairo.balart@metempsy.com fpscrMask.v = ones; 59613756Sjairo.balart@metempsy.com fpscrMask.c = ones; 59713531Sjairo.balart@metempsy.com fpscrMask.z = ones; 59813531Sjairo.balart@metempsy.com fpscrMask.n = ones; 59913531Sjairo.balart@metempsy.com return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 60013531Sjairo.balart@metempsy.com } 60113531Sjairo.balart@metempsy.com case MISCREG_FPCR: 60213531Sjairo.balart@metempsy.com { 60313531Sjairo.balart@metempsy.com const uint32_t ones = (uint32_t)(-1); 60413531Sjairo.balart@metempsy.com FPSCR fpscrMask = 0; 60513531Sjairo.balart@metempsy.com fpscrMask.ioe = ones; 60613531Sjairo.balart@metempsy.com fpscrMask.dze = ones; 60713531Sjairo.balart@metempsy.com fpscrMask.ofe = ones; 60813531Sjairo.balart@metempsy.com fpscrMask.ufe = ones; 60913531Sjairo.balart@metempsy.com fpscrMask.ixe = ones; 61013531Sjairo.balart@metempsy.com fpscrMask.ide = ones; 61113531Sjairo.balart@metempsy.com fpscrMask.len = ones; 61213531Sjairo.balart@metempsy.com fpscrMask.stride = ones; 61313531Sjairo.balart@metempsy.com fpscrMask.rMode = ones; 61413531Sjairo.balart@metempsy.com fpscrMask.fz = ones; 61513531Sjairo.balart@metempsy.com fpscrMask.dn = ones; 61613756Sjairo.balart@metempsy.com fpscrMask.ahp = ones; 61713531Sjairo.balart@metempsy.com return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 61813531Sjairo.balart@metempsy.com } 61913531Sjairo.balart@metempsy.com case MISCREG_NZCV: 62013531Sjairo.balart@metempsy.com { 62113531Sjairo.balart@metempsy.com CPSR cpsr = 0; 62213531Sjairo.balart@metempsy.com cpsr.nz = tc->readCCReg(CCREG_NZ); 62313531Sjairo.balart@metempsy.com cpsr.c = tc->readCCReg(CCREG_C); 62413756Sjairo.balart@metempsy.com cpsr.v = tc->readCCReg(CCREG_V); 62513756Sjairo.balart@metempsy.com return cpsr; 62613531Sjairo.balart@metempsy.com } 62713531Sjairo.balart@metempsy.com case MISCREG_DAIF: 62813531Sjairo.balart@metempsy.com { 62913531Sjairo.balart@metempsy.com CPSR cpsr = 0; 63013531Sjairo.balart@metempsy.com cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 63113531Sjairo.balart@metempsy.com return cpsr; 63213531Sjairo.balart@metempsy.com } 63313531Sjairo.balart@metempsy.com case MISCREG_SP_EL0: 63413531Sjairo.balart@metempsy.com { 63513531Sjairo.balart@metempsy.com return tc->readIntReg(INTREG_SP0); 63613531Sjairo.balart@metempsy.com } 63713531Sjairo.balart@metempsy.com case MISCREG_SP_EL1: 63813531Sjairo.balart@metempsy.com { 63913531Sjairo.balart@metempsy.com return tc->readIntReg(INTREG_SP1); 64013531Sjairo.balart@metempsy.com } 64113531Sjairo.balart@metempsy.com case MISCREG_SP_EL2: 64213531Sjairo.balart@metempsy.com { 64314231Sgiacomo.travaglini@arm.com return tc->readIntReg(INTREG_SP2); 64413531Sjairo.balart@metempsy.com } 64513531Sjairo.balart@metempsy.com case MISCREG_SPSEL: 64613756Sjairo.balart@metempsy.com { 64713531Sjairo.balart@metempsy.com return miscRegs[MISCREG_CPSR] & 0x1; 64813531Sjairo.balart@metempsy.com } 64913531Sjairo.balart@metempsy.com case MISCREG_CURRENTEL: 65013531Sjairo.balart@metempsy.com { 65113531Sjairo.balart@metempsy.com return miscRegs[MISCREG_CPSR] & 0xc; 65213531Sjairo.balart@metempsy.com } 65313531Sjairo.balart@metempsy.com case MISCREG_L2CTLR: 65413756Sjairo.balart@metempsy.com { 65513756Sjairo.balart@metempsy.com // mostly unimplemented, just set NumCPUs field from sim and return 65613531Sjairo.balart@metempsy.com L2CTLR l2ctlr = 0; 65713531Sjairo.balart@metempsy.com // b00:1CPU to b11:4CPUs 65813531Sjairo.balart@metempsy.com l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 65913531Sjairo.balart@metempsy.com return l2ctlr; 66013531Sjairo.balart@metempsy.com } 66113531Sjairo.balart@metempsy.com case MISCREG_DBGDIDR: 66213531Sjairo.balart@metempsy.com /* For now just implement the version number. 66313531Sjairo.balart@metempsy.com * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 66413531Sjairo.balart@metempsy.com */ 66513531Sjairo.balart@metempsy.com return 0x5 << 16; 66613531Sjairo.balart@metempsy.com case MISCREG_DBGDSCRint: 66713531Sjairo.balart@metempsy.com return 0; 66814231Sgiacomo.travaglini@arm.com case MISCREG_ISR: 66913531Sjairo.balart@metempsy.com return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 67013531Sjairo.balart@metempsy.com readMiscRegNoEffect(MISCREG_HCR), 67113531Sjairo.balart@metempsy.com readMiscRegNoEffect(MISCREG_CPSR), 67214231Sgiacomo.travaglini@arm.com readMiscRegNoEffect(MISCREG_SCR)); 67313531Sjairo.balart@metempsy.com case MISCREG_ISR_EL1: 67413756Sjairo.balart@metempsy.com return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 67513531Sjairo.balart@metempsy.com readMiscRegNoEffect(MISCREG_HCR_EL2), 67613531Sjairo.balart@metempsy.com readMiscRegNoEffect(MISCREG_CPSR), 67713531Sjairo.balart@metempsy.com readMiscRegNoEffect(MISCREG_SCR_EL3)); 67813531Sjairo.balart@metempsy.com case MISCREG_DCZID_EL0: 67913531Sjairo.balart@metempsy.com return 0x04; // DC ZVA clear 64-byte chunks 68013531Sjairo.balart@metempsy.com case MISCREG_HCPTR: 68113531Sjairo.balart@metempsy.com { 68213531Sjairo.balart@metempsy.com MiscReg val = readMiscRegNoEffect(misc_reg); 68313756Sjairo.balart@metempsy.com // The trap bit associated with CP14 is defined as RAZ 68413756Sjairo.balart@metempsy.com val &= ~(1 << 14); 68513531Sjairo.balart@metempsy.com // If a CP bit in NSACR is 0 then the corresponding bit in 68613531Sjairo.balart@metempsy.com // HCPTR is RAO/WI 68713531Sjairo.balart@metempsy.com bool secure_lookup = haveSecurity && 68813531Sjairo.balart@metempsy.com inSecureState(readMiscRegNoEffect(MISCREG_SCR), 68913531Sjairo.balart@metempsy.com readMiscRegNoEffect(MISCREG_CPSR)); 69013531Sjairo.balart@metempsy.com if (!secure_lookup) { 69113531Sjairo.balart@metempsy.com MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR); 69213531Sjairo.balart@metempsy.com val |= (mask ^ 0x7FFF) & 0xBFFF; 69313531Sjairo.balart@metempsy.com } 69413531Sjairo.balart@metempsy.com // Set the bits for unimplemented coprocessors to RAO/WI 69513531Sjairo.balart@metempsy.com val |= 0x33FF; 69613531Sjairo.balart@metempsy.com return (val); 69713531Sjairo.balart@metempsy.com } 69813531Sjairo.balart@metempsy.com case MISCREG_HDFAR: // alias for secure DFAR 69913531Sjairo.balart@metempsy.com return readMiscRegNoEffect(MISCREG_DFAR_S); 70013531Sjairo.balart@metempsy.com case MISCREG_HIFAR: // alias for secure IFAR 70113531Sjairo.balart@metempsy.com return readMiscRegNoEffect(MISCREG_IFAR_S); 70213531Sjairo.balart@metempsy.com case MISCREG_HVBAR: // bottom bits reserved 70313531Sjairo.balart@metempsy.com return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0; 70413531Sjairo.balart@metempsy.com case MISCREG_SCTLR: // Some bits hardwired 70513531Sjairo.balart@metempsy.com // The FI field (bit 21) is common between S/NS versions of the register 70613531Sjairo.balart@metempsy.com return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21)) | 70713756Sjairo.balart@metempsy.com (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818; // V8 SCTLR 70813756Sjairo.balart@metempsy.com case MISCREG_SCTLR_EL1: 70913531Sjairo.balart@metempsy.com // The FI field (bit 21) is common between S/NS versions of the register 71013531Sjairo.balart@metempsy.com return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21)) | 71113531Sjairo.balart@metempsy.com (readMiscRegNoEffect(misc_reg) & 0x37DDDBFF) | 0x30D00800; // V8 SCTLR_EL1 71213531Sjairo.balart@metempsy.com case MISCREG_SCTLR_EL3: 71313531Sjairo.balart@metempsy.com // The FI field (bit 21) is common between S/NS versions of the register 71413531Sjairo.balart@metempsy.com return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21)) | 71513531Sjairo.balart@metempsy.com (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; // V8 SCTLR_EL3 71613531Sjairo.balart@metempsy.com case MISCREG_HSCTLR: // FI comes from SCTLR 71713531Sjairo.balart@metempsy.com { 71813531Sjairo.balart@metempsy.com uint32_t mask = 1 << 27; 71913531Sjairo.balart@metempsy.com return (readMiscRegNoEffect(MISCREG_HSCTLR) & ~mask) | 72013531Sjairo.balart@metempsy.com (readMiscRegNoEffect(MISCREG_SCTLR) & mask); 72113531Sjairo.balart@metempsy.com } 72213531Sjairo.balart@metempsy.com case MISCREG_SCR: 72313531Sjairo.balart@metempsy.com { 72413531Sjairo.balart@metempsy.com CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 72513531Sjairo.balart@metempsy.com if (cpsr.width) { 72613531Sjairo.balart@metempsy.com return readMiscRegNoEffect(MISCREG_SCR); 72713756Sjairo.balart@metempsy.com } else { 72813531Sjairo.balart@metempsy.com return readMiscRegNoEffect(MISCREG_SCR_EL3); 72913531Sjairo.balart@metempsy.com } 73013531Sjairo.balart@metempsy.com } 73113531Sjairo.balart@metempsy.com 73213531Sjairo.balart@metempsy.com // Generic Timer registers 73313531Sjairo.balart@metempsy.com case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 73413531Sjairo.balart@metempsy.com case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 73513531Sjairo.balart@metempsy.com case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 73613531Sjairo.balart@metempsy.com case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 73713531Sjairo.balart@metempsy.com return getGenericTimer(tc).readMiscReg(misc_reg); 73813531Sjairo.balart@metempsy.com 73913531Sjairo.balart@metempsy.com default: 74013531Sjairo.balart@metempsy.com break; 74113531Sjairo.balart@metempsy.com 74213531Sjairo.balart@metempsy.com } 74313531Sjairo.balart@metempsy.com return readMiscRegNoEffect(misc_reg); 74413531Sjairo.balart@metempsy.com} 74513531Sjairo.balart@metempsy.com 74613531Sjairo.balart@metempsy.comvoid 74713531Sjairo.balart@metempsy.comISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 74813531Sjairo.balart@metempsy.com{ 74913531Sjairo.balart@metempsy.com assert(misc_reg < NumMiscRegs); 75013531Sjairo.balart@metempsy.com 75113531Sjairo.balart@metempsy.com int flat_idx = flattenMiscIndex(misc_reg); // Note: indexes of AArch64 75213531Sjairo.balart@metempsy.com // registers are left unchanged 75313531Sjairo.balart@metempsy.com 75413531Sjairo.balart@metempsy.com int flat_idx2 = lookUpMiscReg[flat_idx].upper; 75513531Sjairo.balart@metempsy.com 75613531Sjairo.balart@metempsy.com if (flat_idx2 > 0) { 75713531Sjairo.balart@metempsy.com miscRegs[lookUpMiscReg[flat_idx].lower] = bits(val, 31, 0); 75813531Sjairo.balart@metempsy.com miscRegs[flat_idx2] = bits(val, 63, 32); 75913531Sjairo.balart@metempsy.com DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 76013756Sjairo.balart@metempsy.com misc_reg, flat_idx, flat_idx2, val); 76113531Sjairo.balart@metempsy.com } else { 76213756Sjairo.balart@metempsy.com if (flat_idx == MISCREG_SPSR) 76313756Sjairo.balart@metempsy.com flat_idx = flattenMiscIndex(MISCREG_SPSR); 76413756Sjairo.balart@metempsy.com else if (flat_idx == MISCREG_SCTLR_EL1) 76513756Sjairo.balart@metempsy.com flat_idx = flattenMiscIndex(MISCREG_SCTLR); 76613756Sjairo.balart@metempsy.com else 76713531Sjairo.balart@metempsy.com flat_idx = (lookUpMiscReg[flat_idx].lower > 0) ? 76813531Sjairo.balart@metempsy.com lookUpMiscReg[flat_idx].lower : flat_idx; 76913531Sjairo.balart@metempsy.com miscRegs[flat_idx] = val; 77013531Sjairo.balart@metempsy.com DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 77113531Sjairo.balart@metempsy.com misc_reg, flat_idx, val); 77213531Sjairo.balart@metempsy.com } 77313531Sjairo.balart@metempsy.com} 77413756Sjairo.balart@metempsy.com 77513531Sjairo.balart@metempsy.comvoid 77613531Sjairo.balart@metempsy.comISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 77713531Sjairo.balart@metempsy.com{ 77813531Sjairo.balart@metempsy.com 77913531Sjairo.balart@metempsy.com MiscReg newVal = val; 78013531Sjairo.balart@metempsy.com int x; 78113531Sjairo.balart@metempsy.com bool secure_lookup; 78213531Sjairo.balart@metempsy.com bool hyp; 78313531Sjairo.balart@metempsy.com System *sys; 78413531Sjairo.balart@metempsy.com ThreadContext *oc; 78513531Sjairo.balart@metempsy.com uint8_t target_el; 78613531Sjairo.balart@metempsy.com uint16_t asid; 78713531Sjairo.balart@metempsy.com SCR scr; 78813531Sjairo.balart@metempsy.com 78913531Sjairo.balart@metempsy.com if (misc_reg == MISCREG_CPSR) { 79013531Sjairo.balart@metempsy.com updateRegMap(val); 79113531Sjairo.balart@metempsy.com 79213531Sjairo.balart@metempsy.com 79313531Sjairo.balart@metempsy.com CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 79413531Sjairo.balart@metempsy.com int old_mode = old_cpsr.mode; 79513531Sjairo.balart@metempsy.com CPSR cpsr = val; 79613531Sjairo.balart@metempsy.com if (old_mode != cpsr.mode) { 79713531Sjairo.balart@metempsy.com tc->getITBPtr()->invalidateMiscReg(); 79813531Sjairo.balart@metempsy.com tc->getDTBPtr()->invalidateMiscReg(); 79913756Sjairo.balart@metempsy.com } 80014230Sgiacomo.travaglini@arm.com 80113531Sjairo.balart@metempsy.com DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 80213531Sjairo.balart@metempsy.com miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 80313531Sjairo.balart@metempsy.com PCState pc = tc->pcState(); 80413531Sjairo.balart@metempsy.com pc.nextThumb(cpsr.t); 80513531Sjairo.balart@metempsy.com pc.nextJazelle(cpsr.j); 80613531Sjairo.balart@metempsy.com 80713756Sjairo.balart@metempsy.com // Follow slightly different semantics if a CheckerCPU object 80813531Sjairo.balart@metempsy.com // is connected 80913531Sjairo.balart@metempsy.com CheckerCPU *checker = tc->getCheckerCpuPtr(); 81013531Sjairo.balart@metempsy.com if (checker) { 81113531Sjairo.balart@metempsy.com tc->pcStateNoRecord(pc); 81213531Sjairo.balart@metempsy.com } else { 81313531Sjairo.balart@metempsy.com tc->pcState(pc); 81413531Sjairo.balart@metempsy.com } 81513531Sjairo.balart@metempsy.com } else { 81613531Sjairo.balart@metempsy.com#ifndef NDEBUG 81713531Sjairo.balart@metempsy.com if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 81813531Sjairo.balart@metempsy.com if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 81913531Sjairo.balart@metempsy.com warn("Unimplemented system register %s write with %#x.\n", 82013531Sjairo.balart@metempsy.com miscRegName[misc_reg], val); 82113756Sjairo.balart@metempsy.com else 82213531Sjairo.balart@metempsy.com panic("Unimplemented system register %s write with %#x.\n", 82313531Sjairo.balart@metempsy.com miscRegName[misc_reg], val); 82413531Sjairo.balart@metempsy.com } 82513531Sjairo.balart@metempsy.com#endif 82613531Sjairo.balart@metempsy.com switch (unflattenMiscReg(misc_reg)) { 82713531Sjairo.balart@metempsy.com case MISCREG_CPACR: 82813531Sjairo.balart@metempsy.com { 82913531Sjairo.balart@metempsy.com 83013531Sjairo.balart@metempsy.com const uint32_t ones = (uint32_t)(-1); 83113531Sjairo.balart@metempsy.com CPACR cpacrMask = 0; 83213531Sjairo.balart@metempsy.com // Only cp10, cp11, and ase are implemented, nothing else should 83313531Sjairo.balart@metempsy.com // be writable 83413531Sjairo.balart@metempsy.com cpacrMask.cp10 = ones; 83513531Sjairo.balart@metempsy.com cpacrMask.cp11 = ones; 83613531Sjairo.balart@metempsy.com cpacrMask.asedis = ones; 83713531Sjairo.balart@metempsy.com 83813531Sjairo.balart@metempsy.com // Security Extensions may limit the writability of CPACR 83913531Sjairo.balart@metempsy.com if (haveSecurity) { 84013531Sjairo.balart@metempsy.com scr = readMiscRegNoEffect(MISCREG_SCR); 84113531Sjairo.balart@metempsy.com CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 84213531Sjairo.balart@metempsy.com if (scr.ns && (cpsr.mode != MODE_MON)) { 84313531Sjairo.balart@metempsy.com NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 84413531Sjairo.balart@metempsy.com // NB: Skipping the full loop, here 84513531Sjairo.balart@metempsy.com if (!nsacr.cp10) cpacrMask.cp10 = 0; 84613531Sjairo.balart@metempsy.com if (!nsacr.cp11) cpacrMask.cp11 = 0; 84713531Sjairo.balart@metempsy.com } 84813531Sjairo.balart@metempsy.com } 84913531Sjairo.balart@metempsy.com 85013531Sjairo.balart@metempsy.com MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR); 85113531Sjairo.balart@metempsy.com newVal &= cpacrMask; 85213531Sjairo.balart@metempsy.com newVal |= old_val & ~cpacrMask; 85313531Sjairo.balart@metempsy.com DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 85413531Sjairo.balart@metempsy.com miscRegName[misc_reg], newVal); 85513531Sjairo.balart@metempsy.com } 85613531Sjairo.balart@metempsy.com break; 85713531Sjairo.balart@metempsy.com case MISCREG_CPACR_EL1: 85813531Sjairo.balart@metempsy.com { 85913531Sjairo.balart@metempsy.com const uint32_t ones = (uint32_t)(-1); 86013531Sjairo.balart@metempsy.com CPACR cpacrMask = 0; 86113531Sjairo.balart@metempsy.com cpacrMask.tta = ones; 86213531Sjairo.balart@metempsy.com cpacrMask.fpen = ones; 86313531Sjairo.balart@metempsy.com newVal &= cpacrMask; 86413531Sjairo.balart@metempsy.com DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 86513531Sjairo.balart@metempsy.com miscRegName[misc_reg], newVal); 86613531Sjairo.balart@metempsy.com } 86713531Sjairo.balart@metempsy.com break; 86813531Sjairo.balart@metempsy.com case MISCREG_CPTR_EL2: 86913531Sjairo.balart@metempsy.com { 87013531Sjairo.balart@metempsy.com const uint32_t ones = (uint32_t)(-1); 87113531Sjairo.balart@metempsy.com CPTR cptrMask = 0; 87213531Sjairo.balart@metempsy.com cptrMask.tcpac = ones; 87313531Sjairo.balart@metempsy.com cptrMask.tta = ones; 87413531Sjairo.balart@metempsy.com cptrMask.tfp = ones; 87513531Sjairo.balart@metempsy.com newVal &= cptrMask; 87613531Sjairo.balart@metempsy.com cptrMask = 0; 87713531Sjairo.balart@metempsy.com cptrMask.res1_13_12_el2 = ones; 87813531Sjairo.balart@metempsy.com cptrMask.res1_9_0_el2 = ones; 87913531Sjairo.balart@metempsy.com newVal |= cptrMask; 88013531Sjairo.balart@metempsy.com DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 88113531Sjairo.balart@metempsy.com miscRegName[misc_reg], newVal); 88213531Sjairo.balart@metempsy.com } 88313531Sjairo.balart@metempsy.com break; 88413531Sjairo.balart@metempsy.com case MISCREG_CPTR_EL3: 88513531Sjairo.balart@metempsy.com { 88613531Sjairo.balart@metempsy.com const uint32_t ones = (uint32_t)(-1); 88713531Sjairo.balart@metempsy.com CPTR cptrMask = 0; 88813531Sjairo.balart@metempsy.com cptrMask.tcpac = ones; 88913531Sjairo.balart@metempsy.com cptrMask.tta = ones; 89013531Sjairo.balart@metempsy.com cptrMask.tfp = ones; 89113531Sjairo.balart@metempsy.com newVal &= cptrMask; 89213531Sjairo.balart@metempsy.com DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 89313531Sjairo.balart@metempsy.com miscRegName[misc_reg], newVal); 89413531Sjairo.balart@metempsy.com } 89513531Sjairo.balart@metempsy.com break; 89613531Sjairo.balart@metempsy.com case MISCREG_CSSELR: 89713531Sjairo.balart@metempsy.com warn_once("The csselr register isn't implemented.\n"); 89813531Sjairo.balart@metempsy.com return; 89913531Sjairo.balart@metempsy.com 90013531Sjairo.balart@metempsy.com case MISCREG_DC_ZVA_Xt: 90113531Sjairo.balart@metempsy.com warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 90213531Sjairo.balart@metempsy.com return; 90313531Sjairo.balart@metempsy.com 90413531Sjairo.balart@metempsy.com case MISCREG_FPSCR: 90513531Sjairo.balart@metempsy.com { 90613531Sjairo.balart@metempsy.com const uint32_t ones = (uint32_t)(-1); 90713531Sjairo.balart@metempsy.com FPSCR fpscrMask = 0; 90813531Sjairo.balart@metempsy.com fpscrMask.ioc = ones; 90913531Sjairo.balart@metempsy.com fpscrMask.dzc = ones; 91013531Sjairo.balart@metempsy.com fpscrMask.ofc = ones; 91113531Sjairo.balart@metempsy.com fpscrMask.ufc = ones; 91213531Sjairo.balart@metempsy.com fpscrMask.ixc = ones; 91313531Sjairo.balart@metempsy.com fpscrMask.idc = ones; 91413531Sjairo.balart@metempsy.com fpscrMask.ioe = ones; 91513531Sjairo.balart@metempsy.com fpscrMask.dze = ones; 91613531Sjairo.balart@metempsy.com fpscrMask.ofe = ones; 91713531Sjairo.balart@metempsy.com fpscrMask.ufe = ones; 91813531Sjairo.balart@metempsy.com fpscrMask.ixe = ones; 91913531Sjairo.balart@metempsy.com fpscrMask.ide = ones; 92013531Sjairo.balart@metempsy.com fpscrMask.len = ones; 92113531Sjairo.balart@metempsy.com fpscrMask.stride = ones; 92213531Sjairo.balart@metempsy.com fpscrMask.rMode = ones; 92313531Sjairo.balart@metempsy.com fpscrMask.fz = ones; 92413531Sjairo.balart@metempsy.com fpscrMask.dn = ones; 92513531Sjairo.balart@metempsy.com fpscrMask.ahp = ones; 92613531Sjairo.balart@metempsy.com fpscrMask.qc = ones; 92713531Sjairo.balart@metempsy.com fpscrMask.v = ones; 92813531Sjairo.balart@metempsy.com fpscrMask.c = ones; 92913531Sjairo.balart@metempsy.com fpscrMask.z = ones; 93013531Sjairo.balart@metempsy.com fpscrMask.n = ones; 93113531Sjairo.balart@metempsy.com newVal = (newVal & (uint32_t)fpscrMask) | 93213531Sjairo.balart@metempsy.com (readMiscRegNoEffect(MISCREG_FPSCR) & 93313531Sjairo.balart@metempsy.com ~(uint32_t)fpscrMask); 93413531Sjairo.balart@metempsy.com tc->getDecoderPtr()->setContext(newVal); 93513531Sjairo.balart@metempsy.com } 93613531Sjairo.balart@metempsy.com break; 93714232Sgiacomo.travaglini@arm.com case MISCREG_FPSR: 93814232Sgiacomo.travaglini@arm.com { 93913531Sjairo.balart@metempsy.com const uint32_t ones = (uint32_t)(-1); 94013531Sjairo.balart@metempsy.com FPSCR fpscrMask = 0; 94114251Sgiacomo.travaglini@arm.com fpscrMask.ioc = ones; 94214251Sgiacomo.travaglini@arm.com fpscrMask.dzc = ones; 94314251Sgiacomo.travaglini@arm.com fpscrMask.ofc = ones; 94414251Sgiacomo.travaglini@arm.com fpscrMask.ufc = ones; 94514253Sgiacomo.travaglini@arm.com fpscrMask.ixc = ones; 94614253Sgiacomo.travaglini@arm.com fpscrMask.idc = ones; 94714253Sgiacomo.travaglini@arm.com fpscrMask.qc = ones; 94814253Sgiacomo.travaglini@arm.com fpscrMask.v = ones; 94914253Sgiacomo.travaglini@arm.com fpscrMask.c = ones; 95014253Sgiacomo.travaglini@arm.com fpscrMask.z = ones; 95114253Sgiacomo.travaglini@arm.com fpscrMask.n = ones; 95214253Sgiacomo.travaglini@arm.com newVal = (newVal & (uint32_t)fpscrMask) | 95314253Sgiacomo.travaglini@arm.com (readMiscRegNoEffect(MISCREG_FPSCR) & 95414253Sgiacomo.travaglini@arm.com ~(uint32_t)fpscrMask); 95514253Sgiacomo.travaglini@arm.com misc_reg = MISCREG_FPSCR; 95614253Sgiacomo.travaglini@arm.com } 95714253Sgiacomo.travaglini@arm.com break; 95814253Sgiacomo.travaglini@arm.com case MISCREG_FPCR: 95914253Sgiacomo.travaglini@arm.com { 96014253Sgiacomo.travaglini@arm.com const uint32_t ones = (uint32_t)(-1); 96114253Sgiacomo.travaglini@arm.com FPSCR fpscrMask = 0; 96214253Sgiacomo.travaglini@arm.com fpscrMask.ioe = ones; 96314253Sgiacomo.travaglini@arm.com fpscrMask.dze = ones; 96414253Sgiacomo.travaglini@arm.com fpscrMask.ofe = ones; 96514253Sgiacomo.travaglini@arm.com fpscrMask.ufe = ones; 96614253Sgiacomo.travaglini@arm.com fpscrMask.ixe = ones; 96714253Sgiacomo.travaglini@arm.com fpscrMask.ide = ones; 96814253Sgiacomo.travaglini@arm.com fpscrMask.len = ones; 96914253Sgiacomo.travaglini@arm.com fpscrMask.stride = ones; 97014253Sgiacomo.travaglini@arm.com fpscrMask.rMode = ones; 97114253Sgiacomo.travaglini@arm.com fpscrMask.fz = ones; 97214253Sgiacomo.travaglini@arm.com fpscrMask.dn = ones; 97314253Sgiacomo.travaglini@arm.com fpscrMask.ahp = ones; 97414253Sgiacomo.travaglini@arm.com newVal = (newVal & (uint32_t)fpscrMask) | 97514253Sgiacomo.travaglini@arm.com (readMiscRegNoEffect(MISCREG_FPSCR) & 97614253Sgiacomo.travaglini@arm.com ~(uint32_t)fpscrMask); 97714253Sgiacomo.travaglini@arm.com misc_reg = MISCREG_FPSCR; 97814253Sgiacomo.travaglini@arm.com } 97914253Sgiacomo.travaglini@arm.com break; 98014253Sgiacomo.travaglini@arm.com case MISCREG_CPSR_Q: 98114253Sgiacomo.travaglini@arm.com { 98214253Sgiacomo.travaglini@arm.com assert(!(newVal & ~CpsrMaskQ)); 98314253Sgiacomo.travaglini@arm.com newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 98414253Sgiacomo.travaglini@arm.com misc_reg = MISCREG_CPSR; 98514253Sgiacomo.travaglini@arm.com } 98614253Sgiacomo.travaglini@arm.com break; 98714253Sgiacomo.travaglini@arm.com case MISCREG_FPSCR_QC: 98814253Sgiacomo.travaglini@arm.com { 98914253Sgiacomo.travaglini@arm.com newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 99014253Sgiacomo.travaglini@arm.com (newVal & FpscrQcMask); 99114253Sgiacomo.travaglini@arm.com misc_reg = MISCREG_FPSCR; 99214253Sgiacomo.travaglini@arm.com } 99314253Sgiacomo.travaglini@arm.com break; 99414253Sgiacomo.travaglini@arm.com case MISCREG_FPSCR_EXC: 99514253Sgiacomo.travaglini@arm.com { 99614253Sgiacomo.travaglini@arm.com newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 99714253Sgiacomo.travaglini@arm.com (newVal & FpscrExcMask); 99814253Sgiacomo.travaglini@arm.com misc_reg = MISCREG_FPSCR; 99914253Sgiacomo.travaglini@arm.com } 100014253Sgiacomo.travaglini@arm.com break; 100114253Sgiacomo.travaglini@arm.com case MISCREG_FPEXC: 100214253Sgiacomo.travaglini@arm.com { 100314253Sgiacomo.travaglini@arm.com // vfpv3 architecture, section B.6.1 of DDI04068 100414253Sgiacomo.travaglini@arm.com // bit 29 - valid only if fpexc[31] is 0 100514253Sgiacomo.travaglini@arm.com const uint32_t fpexcMask = 0x60000000; 100614253Sgiacomo.travaglini@arm.com newVal = (newVal & fpexcMask) | 100714253Sgiacomo.travaglini@arm.com (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 100814253Sgiacomo.travaglini@arm.com } 100914253Sgiacomo.travaglini@arm.com break; 101014253Sgiacomo.travaglini@arm.com case MISCREG_HCR: 101114253Sgiacomo.travaglini@arm.com { 101214253Sgiacomo.travaglini@arm.com if (!haveVirtualization) 101314253Sgiacomo.travaglini@arm.com return; 101414253Sgiacomo.travaglini@arm.com } 101513531Sjairo.balart@metempsy.com break; 101613531Sjairo.balart@metempsy.com case MISCREG_IFSR: 101713531Sjairo.balart@metempsy.com { 101813531Sjairo.balart@metempsy.com // ARM ARM (ARM DDI 0406C.b) B4.1.96 101913531Sjairo.balart@metempsy.com const uint32_t ifsrMask = 102013531Sjairo.balart@metempsy.com mask(31, 13) | mask(11, 11) | mask(8, 6); 102113531Sjairo.balart@metempsy.com newVal = newVal & ~ifsrMask; 102213531Sjairo.balart@metempsy.com } 102313531Sjairo.balart@metempsy.com break; 102413531Sjairo.balart@metempsy.com case MISCREG_DFSR: 102513531Sjairo.balart@metempsy.com { 102613531Sjairo.balart@metempsy.com // ARM ARM (ARM DDI 0406C.b) B4.1.52 102713531Sjairo.balart@metempsy.com const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 102813531Sjairo.balart@metempsy.com newVal = newVal & ~dfsrMask; 102914231Sgiacomo.travaglini@arm.com } 103013531Sjairo.balart@metempsy.com break; 103113531Sjairo.balart@metempsy.com case MISCREG_AMAIR0: 103213531Sjairo.balart@metempsy.com case MISCREG_AMAIR1: 103313756Sjairo.balart@metempsy.com { 103413531Sjairo.balart@metempsy.com // ARM ARM (ARM DDI 0406C.b) B4.1.5 103513531Sjairo.balart@metempsy.com // Valid only with LPAE 103613531Sjairo.balart@metempsy.com if (!haveLPAE) 103713531Sjairo.balart@metempsy.com return; 103814231Sgiacomo.travaglini@arm.com DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 103914231Sgiacomo.travaglini@arm.com } 104014231Sgiacomo.travaglini@arm.com break; 104113531Sjairo.balart@metempsy.com case MISCREG_SCR: 104213531Sjairo.balart@metempsy.com tc->getITBPtr()->invalidateMiscReg(); 104314231Sgiacomo.travaglini@arm.com tc->getDTBPtr()->invalidateMiscReg(); 104414231Sgiacomo.travaglini@arm.com break; 104513531Sjairo.balart@metempsy.com case MISCREG_SCTLR: 104614231Sgiacomo.travaglini@arm.com { 104714231Sgiacomo.travaglini@arm.com DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 104813531Sjairo.balart@metempsy.com MiscRegIndex sctlr_idx; 104914231Sgiacomo.travaglini@arm.com scr = readMiscRegNoEffect(MISCREG_SCR); 105014231Sgiacomo.travaglini@arm.com if (haveSecurity && !scr.ns) { 105114231Sgiacomo.travaglini@arm.com sctlr_idx = MISCREG_SCTLR_S; 105214231Sgiacomo.travaglini@arm.com } else { 105314231Sgiacomo.travaglini@arm.com sctlr_idx = MISCREG_SCTLR_NS; 105414231Sgiacomo.travaglini@arm.com // The FI field (bit 21) is common between S/NS versions 105514231Sgiacomo.travaglini@arm.com // of the register, we store this in the secure copy of 105614231Sgiacomo.travaglini@arm.com // the reg 105714231Sgiacomo.travaglini@arm.com miscRegs[MISCREG_SCTLR_S] &= ~(1 << 21); 105814231Sgiacomo.travaglini@arm.com miscRegs[MISCREG_SCTLR_S] |= newVal & (1 << 21); 105914231Sgiacomo.travaglini@arm.com } 106014231Sgiacomo.travaglini@arm.com SCTLR sctlr = miscRegs[sctlr_idx]; 106114231Sgiacomo.travaglini@arm.com SCTLR new_sctlr = newVal; 106214231Sgiacomo.travaglini@arm.com new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 106314231Sgiacomo.travaglini@arm.com miscRegs[sctlr_idx] = (MiscReg)new_sctlr; 106414231Sgiacomo.travaglini@arm.com tc->getITBPtr()->invalidateMiscReg(); 106514231Sgiacomo.travaglini@arm.com tc->getDTBPtr()->invalidateMiscReg(); 106614231Sgiacomo.travaglini@arm.com } 106714231Sgiacomo.travaglini@arm.com case MISCREG_MIDR: 106814231Sgiacomo.travaglini@arm.com case MISCREG_ID_PFR0: 106914231Sgiacomo.travaglini@arm.com case MISCREG_ID_PFR1: 107014231Sgiacomo.travaglini@arm.com case MISCREG_ID_DFR0: 107114231Sgiacomo.travaglini@arm.com case MISCREG_ID_MMFR0: 107214231Sgiacomo.travaglini@arm.com case MISCREG_ID_MMFR1: 107314231Sgiacomo.travaglini@arm.com case MISCREG_ID_MMFR2: 107414231Sgiacomo.travaglini@arm.com case MISCREG_ID_MMFR3: 107514231Sgiacomo.travaglini@arm.com case MISCREG_ID_ISAR0: 107614231Sgiacomo.travaglini@arm.com case MISCREG_ID_ISAR1: 107713531Sjairo.balart@metempsy.com case MISCREG_ID_ISAR2: 107813531Sjairo.balart@metempsy.com case MISCREG_ID_ISAR3: 107913531Sjairo.balart@metempsy.com case MISCREG_ID_ISAR4: 108013531Sjairo.balart@metempsy.com case MISCREG_ID_ISAR5: 108114231Sgiacomo.travaglini@arm.com 108213531Sjairo.balart@metempsy.com case MISCREG_MPIDR: 108314231Sgiacomo.travaglini@arm.com case MISCREG_FPSID: 108414231Sgiacomo.travaglini@arm.com case MISCREG_TLBTR: 108514231Sgiacomo.travaglini@arm.com case MISCREG_MVFR0: 108613531Sjairo.balart@metempsy.com case MISCREG_MVFR1: 108713531Sjairo.balart@metempsy.com 108813531Sjairo.balart@metempsy.com case MISCREG_ID_AA64AFR0_EL1: 108913531Sjairo.balart@metempsy.com case MISCREG_ID_AA64AFR1_EL1: 109013531Sjairo.balart@metempsy.com case MISCREG_ID_AA64DFR0_EL1: 109113531Sjairo.balart@metempsy.com case MISCREG_ID_AA64DFR1_EL1: 109213531Sjairo.balart@metempsy.com case MISCREG_ID_AA64ISAR0_EL1: 109313756Sjairo.balart@metempsy.com case MISCREG_ID_AA64ISAR1_EL1: 109413531Sjairo.balart@metempsy.com case MISCREG_ID_AA64MMFR0_EL1: 109513531Sjairo.balart@metempsy.com case MISCREG_ID_AA64MMFR1_EL1: 109613531Sjairo.balart@metempsy.com case MISCREG_ID_AA64PFR0_EL1: 109713531Sjairo.balart@metempsy.com case MISCREG_ID_AA64PFR1_EL1: 109813756Sjairo.balart@metempsy.com // ID registers are constants. 109913531Sjairo.balart@metempsy.com return; 110014231Sgiacomo.travaglini@arm.com 110114231Sgiacomo.travaglini@arm.com // TLBI all entries, EL0&1 inner sharable (ignored) 110213531Sjairo.balart@metempsy.com case MISCREG_TLBIALLIS: 110314231Sgiacomo.travaglini@arm.com case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 110414231Sgiacomo.travaglini@arm.com assert32(tc); 110513531Sjairo.balart@metempsy.com target_el = 1; // el 0 and 1 are handled together 110613531Sjairo.balart@metempsy.com scr = readMiscReg(MISCREG_SCR, tc); 110713756Sjairo.balart@metempsy.com secure_lookup = haveSecurity && !scr.ns; 110813756Sjairo.balart@metempsy.com sys = tc->getSystemPtr(); 110914231Sgiacomo.travaglini@arm.com for (x = 0; x < sys->numContexts(); x++) { 111013531Sjairo.balart@metempsy.com oc = sys->getThreadContext(x); 111113531Sjairo.balart@metempsy.com assert(oc->getITBPtr() && oc->getDTBPtr()); 111213531Sjairo.balart@metempsy.com oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 111313531Sjairo.balart@metempsy.com oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 111413531Sjairo.balart@metempsy.com 111513531Sjairo.balart@metempsy.com // If CheckerCPU is connected, need to notify it of a flush 111613531Sjairo.balart@metempsy.com CheckerCPU *checker = oc->getCheckerCpuPtr(); 111714231Sgiacomo.travaglini@arm.com if (checker) { 111813531Sjairo.balart@metempsy.com checker->getITBPtr()->flushAllSecurity(secure_lookup, 111914231Sgiacomo.travaglini@arm.com target_el); 112013531Sjairo.balart@metempsy.com checker->getDTBPtr()->flushAllSecurity(secure_lookup, 112113531Sjairo.balart@metempsy.com target_el); 112213531Sjairo.balart@metempsy.com } 112313531Sjairo.balart@metempsy.com } 112413756Sjairo.balart@metempsy.com return; 112513531Sjairo.balart@metempsy.com // TLBI all entries, EL0&1, instruction side 112613531Sjairo.balart@metempsy.com case MISCREG_ITLBIALL: 112713531Sjairo.balart@metempsy.com assert32(tc); 112813531Sjairo.balart@metempsy.com target_el = 1; // el 0 and 1 are handled together 112913531Sjairo.balart@metempsy.com scr = readMiscReg(MISCREG_SCR, tc); 113013531Sjairo.balart@metempsy.com secure_lookup = haveSecurity && !scr.ns; 113113531Sjairo.balart@metempsy.com tc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 113213531Sjairo.balart@metempsy.com return; 113313531Sjairo.balart@metempsy.com // TLBI all entries, EL0&1, data side 113413531Sjairo.balart@metempsy.com case MISCREG_DTLBIALL: 113513531Sjairo.balart@metempsy.com assert32(tc); 113613531Sjairo.balart@metempsy.com target_el = 1; // el 0 and 1 are handled together 113713531Sjairo.balart@metempsy.com scr = readMiscReg(MISCREG_SCR, tc); 113813531Sjairo.balart@metempsy.com secure_lookup = haveSecurity && !scr.ns; 113913531Sjairo.balart@metempsy.com tc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 114013531Sjairo.balart@metempsy.com return; 114113531Sjairo.balart@metempsy.com // TLBI based on VA, EL0&1 inner sharable (ignored) 114213531Sjairo.balart@metempsy.com case MISCREG_TLBIMVAIS: 114313756Sjairo.balart@metempsy.com case MISCREG_TLBIMVA: 114413531Sjairo.balart@metempsy.com assert32(tc); 114513531Sjairo.balart@metempsy.com target_el = 1; // el 0 and 1 are handled together 114613531Sjairo.balart@metempsy.com scr = readMiscReg(MISCREG_SCR, tc); 114713531Sjairo.balart@metempsy.com secure_lookup = haveSecurity && !scr.ns; 114813531Sjairo.balart@metempsy.com sys = tc->getSystemPtr(); 114913531Sjairo.balart@metempsy.com for (x = 0; x < sys->numContexts(); x++) { 115013531Sjairo.balart@metempsy.com oc = sys->getThreadContext(x); 115113531Sjairo.balart@metempsy.com assert(oc->getITBPtr() && oc->getDTBPtr()); 115213531Sjairo.balart@metempsy.com oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 115313531Sjairo.balart@metempsy.com bits(newVal, 7,0), 115413531Sjairo.balart@metempsy.com secure_lookup, target_el); 115513531Sjairo.balart@metempsy.com oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 115613531Sjairo.balart@metempsy.com bits(newVal, 7,0), 115713531Sjairo.balart@metempsy.com secure_lookup, target_el); 115813531Sjairo.balart@metempsy.com 115913531Sjairo.balart@metempsy.com CheckerCPU *checker = oc->getCheckerCpuPtr(); 116013531Sjairo.balart@metempsy.com if (checker) { 116113531Sjairo.balart@metempsy.com checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 116213531Sjairo.balart@metempsy.com bits(newVal, 7,0), secure_lookup, target_el); 116313531Sjairo.balart@metempsy.com checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 116413531Sjairo.balart@metempsy.com bits(newVal, 7,0), secure_lookup, target_el); 116513531Sjairo.balart@metempsy.com } 116613531Sjairo.balart@metempsy.com } 116713531Sjairo.balart@metempsy.com return; 116813531Sjairo.balart@metempsy.com // TLBI by ASID, EL0&1, inner sharable 116913531Sjairo.balart@metempsy.com case MISCREG_TLBIASIDIS: 117013531Sjairo.balart@metempsy.com case MISCREG_TLBIASID: 117113531Sjairo.balart@metempsy.com assert32(tc); 117213531Sjairo.balart@metempsy.com target_el = 1; // el 0 and 1 are handled together 117313531Sjairo.balart@metempsy.com scr = readMiscReg(MISCREG_SCR, tc); 117413531Sjairo.balart@metempsy.com secure_lookup = haveSecurity && !scr.ns; 117513531Sjairo.balart@metempsy.com sys = tc->getSystemPtr(); 117613531Sjairo.balart@metempsy.com for (x = 0; x < sys->numContexts(); x++) { 117713531Sjairo.balart@metempsy.com oc = sys->getThreadContext(x); 117813531Sjairo.balart@metempsy.com assert(oc->getITBPtr() && oc->getDTBPtr()); 117913531Sjairo.balart@metempsy.com oc->getITBPtr()->flushAsid(bits(newVal, 7,0), 118013531Sjairo.balart@metempsy.com secure_lookup, target_el); 118113531Sjairo.balart@metempsy.com oc->getDTBPtr()->flushAsid(bits(newVal, 7,0), 118213531Sjairo.balart@metempsy.com secure_lookup, target_el); 118313531Sjairo.balart@metempsy.com CheckerCPU *checker = oc->getCheckerCpuPtr(); 118413531Sjairo.balart@metempsy.com if (checker) { 118513531Sjairo.balart@metempsy.com checker->getITBPtr()->flushAsid(bits(newVal, 7,0), 118613531Sjairo.balart@metempsy.com secure_lookup, target_el); 118713531Sjairo.balart@metempsy.com checker->getDTBPtr()->flushAsid(bits(newVal, 7,0), 118813531Sjairo.balart@metempsy.com secure_lookup, target_el); 118913531Sjairo.balart@metempsy.com } 119013531Sjairo.balart@metempsy.com } 119113531Sjairo.balart@metempsy.com return; 119213531Sjairo.balart@metempsy.com // TLBI by address, EL0&1, inner sharable (ignored) 119313531Sjairo.balart@metempsy.com case MISCREG_TLBIMVAAIS: 119413531Sjairo.balart@metempsy.com case MISCREG_TLBIMVAA: 119513531Sjairo.balart@metempsy.com assert32(tc); 119613531Sjairo.balart@metempsy.com target_el = 1; // el 0 and 1 are handled together 119713531Sjairo.balart@metempsy.com scr = readMiscReg(MISCREG_SCR, tc); 119813531Sjairo.balart@metempsy.com secure_lookup = haveSecurity && !scr.ns; 119913531Sjairo.balart@metempsy.com hyp = 0; 120013531Sjairo.balart@metempsy.com tlbiMVA(tc, newVal, secure_lookup, hyp, target_el); 120113531Sjairo.balart@metempsy.com return; 120213531Sjairo.balart@metempsy.com // TLBI by address, EL2, hypervisor mode 120313531Sjairo.balart@metempsy.com case MISCREG_TLBIMVAH: 120413531Sjairo.balart@metempsy.com case MISCREG_TLBIMVAHIS: 120513531Sjairo.balart@metempsy.com assert32(tc); 120613531Sjairo.balart@metempsy.com target_el = 1; // aarch32, use hyp bit 120713531Sjairo.balart@metempsy.com scr = readMiscReg(MISCREG_SCR, tc); 120813531Sjairo.balart@metempsy.com secure_lookup = haveSecurity && !scr.ns; 120913531Sjairo.balart@metempsy.com hyp = 1; 121013531Sjairo.balart@metempsy.com tlbiMVA(tc, newVal, secure_lookup, hyp, target_el); 121113531Sjairo.balart@metempsy.com return; 121213531Sjairo.balart@metempsy.com // TLBI by address and asid, EL0&1, instruction side only 121313531Sjairo.balart@metempsy.com case MISCREG_ITLBIMVA: 121413531Sjairo.balart@metempsy.com assert32(tc); 121513531Sjairo.balart@metempsy.com target_el = 1; // el 0 and 1 are handled together 121613531Sjairo.balart@metempsy.com scr = readMiscReg(MISCREG_SCR, tc); 121713531Sjairo.balart@metempsy.com secure_lookup = haveSecurity && !scr.ns; 121813531Sjairo.balart@metempsy.com tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1219 bits(newVal, 7,0), secure_lookup, target_el); 1220 return; 1221 // TLBI by address and asid, EL0&1, data side only 1222 case MISCREG_DTLBIMVA: 1223 assert32(tc); 1224 target_el = 1; // el 0 and 1 are handled together 1225 scr = readMiscReg(MISCREG_SCR, tc); 1226 secure_lookup = haveSecurity && !scr.ns; 1227 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1228 bits(newVal, 7,0), secure_lookup, target_el); 1229 return; 1230 // TLBI by ASID, EL0&1, instrution side only 1231 case MISCREG_ITLBIASID: 1232 assert32(tc); 1233 target_el = 1; // el 0 and 1 are handled together 1234 scr = readMiscReg(MISCREG_SCR, tc); 1235 secure_lookup = haveSecurity && !scr.ns; 1236 tc->getITBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup, 1237 target_el); 1238 return; 1239 // TLBI by ASID EL0&1 data size only 1240 case MISCREG_DTLBIASID: 1241 assert32(tc); 1242 target_el = 1; // el 0 and 1 are handled together 1243 scr = readMiscReg(MISCREG_SCR, tc); 1244 secure_lookup = haveSecurity && !scr.ns; 1245 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup, 1246 target_el); 1247 return; 1248 // Invalidate entire Non-secure Hyp/Non-Hyp Unified TLB 1249 case MISCREG_TLBIALLNSNH: 1250 case MISCREG_TLBIALLNSNHIS: 1251 assert32(tc); 1252 target_el = 1; // el 0 and 1 are handled together 1253 hyp = 0; 1254 tlbiALLN(tc, hyp, target_el); 1255 return; 1256 // TLBI all entries, EL2, hyp, 1257 case MISCREG_TLBIALLH: 1258 case MISCREG_TLBIALLHIS: 1259 assert32(tc); 1260 target_el = 1; // aarch32, use hyp bit 1261 hyp = 1; 1262 tlbiALLN(tc, hyp, target_el); 1263 return; 1264 // AArch64 TLBI: invalidate all entries EL3 1265 case MISCREG_TLBI_ALLE3IS: 1266 case MISCREG_TLBI_ALLE3: 1267 assert64(tc); 1268 target_el = 3; 1269 secure_lookup = true; 1270 tlbiALL(tc, secure_lookup, target_el); 1271 return; 1272 // @todo: uncomment this to enable Virtualization 1273 // case MISCREG_TLBI_ALLE2IS: 1274 // case MISCREG_TLBI_ALLE2: 1275 // TLBI all entries, EL0&1 1276 case MISCREG_TLBI_ALLE1IS: 1277 case MISCREG_TLBI_ALLE1: 1278 // AArch64 TLBI: invalidate all entries, stage 1, current VMID 1279 case MISCREG_TLBI_VMALLE1IS: 1280 case MISCREG_TLBI_VMALLE1: 1281 // AArch64 TLBI: invalidate all entries, stages 1 & 2, current VMID 1282 case MISCREG_TLBI_VMALLS12E1IS: 1283 case MISCREG_TLBI_VMALLS12E1: 1284 // @todo: handle VMID and stage 2 to enable Virtualization 1285 assert64(tc); 1286 target_el = 1; // el 0 and 1 are handled together 1287 scr = readMiscReg(MISCREG_SCR, tc); 1288 secure_lookup = haveSecurity && !scr.ns; 1289 tlbiALL(tc, secure_lookup, target_el); 1290 return; 1291 // AArch64 TLBI: invalidate by VA and ASID, stage 1, current VMID 1292 // VAEx(IS) and VALEx(IS) are the same because TLBs only store entries 1293 // from the last level of translation table walks 1294 // @todo: handle VMID to enable Virtualization 1295 // TLBI all entries, EL0&1 1296 case MISCREG_TLBI_VAE3IS_Xt: 1297 case MISCREG_TLBI_VAE3_Xt: 1298 // TLBI by VA, EL3 regime stage 1, last level walk 1299 case MISCREG_TLBI_VALE3IS_Xt: 1300 case MISCREG_TLBI_VALE3_Xt: 1301 assert64(tc); 1302 target_el = 3; 1303 asid = 0xbeef; // does not matter, tlbi is global 1304 secure_lookup = true; 1305 tlbiVA(tc, newVal, asid, secure_lookup, target_el); 1306 return; 1307 // TLBI by VA, EL2 1308 case MISCREG_TLBI_VAE2IS_Xt: 1309 case MISCREG_TLBI_VAE2_Xt: 1310 // TLBI by VA, EL2, stage1 last level walk 1311 case MISCREG_TLBI_VALE2IS_Xt: 1312 case MISCREG_TLBI_VALE2_Xt: 1313 assert64(tc); 1314 target_el = 2; 1315 asid = 0xbeef; // does not matter, tlbi is global 1316 scr = readMiscReg(MISCREG_SCR, tc); 1317 secure_lookup = haveSecurity && !scr.ns; 1318 tlbiVA(tc, newVal, asid, secure_lookup, target_el); 1319 return; 1320 // TLBI by VA EL1 & 0, stage1, ASID, current VMID 1321 case MISCREG_TLBI_VAE1IS_Xt: 1322 case MISCREG_TLBI_VAE1_Xt: 1323 case MISCREG_TLBI_VALE1IS_Xt: 1324 case MISCREG_TLBI_VALE1_Xt: 1325 assert64(tc); 1326 asid = bits(newVal, 63, 48); 1327 target_el = 1; // el 0 and 1 are handled together 1328 scr = readMiscReg(MISCREG_SCR, tc); 1329 secure_lookup = haveSecurity && !scr.ns; 1330 tlbiVA(tc, newVal, asid, secure_lookup, target_el); 1331 return; 1332 // AArch64 TLBI: invalidate by ASID, stage 1, current VMID 1333 // @todo: handle VMID to enable Virtualization 1334 case MISCREG_TLBI_ASIDE1IS_Xt: 1335 case MISCREG_TLBI_ASIDE1_Xt: 1336 assert64(tc); 1337 target_el = 1; // el 0 and 1 are handled together 1338 scr = readMiscReg(MISCREG_SCR, tc); 1339 secure_lookup = haveSecurity && !scr.ns; 1340 sys = tc->getSystemPtr(); 1341 for (x = 0; x < sys->numContexts(); x++) { 1342 oc = sys->getThreadContext(x); 1343 assert(oc->getITBPtr() && oc->getDTBPtr()); 1344 asid = bits(newVal, 63, 48); 1345 if (!haveLargeAsid64) 1346 asid &= mask(8); 1347 oc->getITBPtr()->flushAsid(asid, secure_lookup, target_el); 1348 oc->getDTBPtr()->flushAsid(asid, secure_lookup, target_el); 1349 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1350 if (checker) { 1351 checker->getITBPtr()->flushAsid(asid, 1352 secure_lookup, target_el); 1353 checker->getDTBPtr()->flushAsid(asid, 1354 secure_lookup, target_el); 1355 } 1356 } 1357 return; 1358 // AArch64 TLBI: invalidate by VA, ASID, stage 1, current VMID 1359 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 1360 // entries from the last level of translation table walks 1361 // @todo: handle VMID to enable Virtualization 1362 case MISCREG_TLBI_VAAE1IS_Xt: 1363 case MISCREG_TLBI_VAAE1_Xt: 1364 case MISCREG_TLBI_VAALE1IS_Xt: 1365 case MISCREG_TLBI_VAALE1_Xt: 1366 assert64(tc); 1367 target_el = 1; // el 0 and 1 are handled together 1368 scr = readMiscReg(MISCREG_SCR, tc); 1369 secure_lookup = haveSecurity && !scr.ns; 1370 sys = tc->getSystemPtr(); 1371 for (x = 0; x < sys->numContexts(); x++) { 1372 // @todo: extra controls on TLBI broadcast? 1373 oc = sys->getThreadContext(x); 1374 assert(oc->getITBPtr() && oc->getDTBPtr()); 1375 Addr va = ((Addr) bits(newVal, 43, 0)) << 12; 1376 oc->getITBPtr()->flushMva(va, 1377 secure_lookup, false, target_el); 1378 oc->getDTBPtr()->flushMva(va, 1379 secure_lookup, false, target_el); 1380 1381 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1382 if (checker) { 1383 checker->getITBPtr()->flushMva(va, 1384 secure_lookup, false, target_el); 1385 checker->getDTBPtr()->flushMva(va, 1386 secure_lookup, false, target_el); 1387 } 1388 } 1389 return; 1390 // AArch64 TLBI: invalidate by IPA, stage 2, current VMID 1391 case MISCREG_TLBI_IPAS2LE1IS_Xt: 1392 case MISCREG_TLBI_IPAS2LE1_Xt: 1393 case MISCREG_TLBI_IPAS2E1IS_Xt: 1394 case MISCREG_TLBI_IPAS2E1_Xt: 1395 assert64(tc); 1396 // @todo: implement these as part of Virtualization 1397 warn("Not doing anything for write of miscreg ITLB_IPAS2\n"); 1398 return; 1399 case MISCREG_ACTLR: 1400 warn("Not doing anything for write of miscreg ACTLR\n"); 1401 break; 1402 1403 case MISCREG_PMXEVTYPER_PMCCFILTR: 1404 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 1405 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 1406 case MISCREG_PMCR ... MISCREG_PMOVSSET: 1407 pmu->setMiscReg(misc_reg, newVal); 1408 break; 1409 1410 1411 case MISCREG_HSTR: // TJDBX, now redifined to be RES0 1412 { 1413 HSTR hstrMask = 0; 1414 hstrMask.tjdbx = 1; 1415 newVal &= ~((uint32_t) hstrMask); 1416 break; 1417 } 1418 case MISCREG_HCPTR: 1419 { 1420 // If a CP bit in NSACR is 0 then the corresponding bit in 1421 // HCPTR is RAO/WI. Same applies to NSASEDIS 1422 secure_lookup = haveSecurity && 1423 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 1424 readMiscRegNoEffect(MISCREG_CPSR)); 1425 if (!secure_lookup) { 1426 MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 1427 MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 1428 newVal = (newVal & ~mask) | (oldValue & mask); 1429 } 1430 break; 1431 } 1432 case MISCREG_HDFAR: // alias for secure DFAR 1433 misc_reg = MISCREG_DFAR_S; 1434 break; 1435 case MISCREG_HIFAR: // alias for secure IFAR 1436 misc_reg = MISCREG_IFAR_S; 1437 break; 1438 case MISCREG_ATS1CPR: 1439 case MISCREG_ATS1CPW: 1440 case MISCREG_ATS1CUR: 1441 case MISCREG_ATS1CUW: 1442 case MISCREG_ATS12NSOPR: 1443 case MISCREG_ATS12NSOPW: 1444 case MISCREG_ATS12NSOUR: 1445 case MISCREG_ATS12NSOUW: 1446 case MISCREG_ATS1HR: 1447 case MISCREG_ATS1HW: 1448 { 1449 unsigned flags = 0; 1450 BaseTLB::Mode mode = BaseTLB::Read; 1451 TLB::ArmTranslationType tranType = TLB::NormalTran; 1452 Fault fault; 1453 switch(misc_reg) { 1454 case MISCREG_ATS1CPR: 1455 flags = TLB::MustBeOne; 1456 tranType = TLB::S1CTran; 1457 mode = BaseTLB::Read; 1458 break; 1459 case MISCREG_ATS1CPW: 1460 flags = TLB::MustBeOne; 1461 tranType = TLB::S1CTran; 1462 mode = BaseTLB::Write; 1463 break; 1464 case MISCREG_ATS1CUR: 1465 flags = TLB::MustBeOne | TLB::UserMode; 1466 tranType = TLB::S1CTran; 1467 mode = BaseTLB::Read; 1468 break; 1469 case MISCREG_ATS1CUW: 1470 flags = TLB::MustBeOne | TLB::UserMode; 1471 tranType = TLB::S1CTran; 1472 mode = BaseTLB::Write; 1473 break; 1474 case MISCREG_ATS12NSOPR: 1475 if (!haveSecurity) 1476 panic("Security Extensions required for ATS12NSOPR"); 1477 flags = TLB::MustBeOne; 1478 tranType = TLB::S1S2NsTran; 1479 mode = BaseTLB::Read; 1480 break; 1481 case MISCREG_ATS12NSOPW: 1482 if (!haveSecurity) 1483 panic("Security Extensions required for ATS12NSOPW"); 1484 flags = TLB::MustBeOne; 1485 tranType = TLB::S1S2NsTran; 1486 mode = BaseTLB::Write; 1487 break; 1488 case MISCREG_ATS12NSOUR: 1489 if (!haveSecurity) 1490 panic("Security Extensions required for ATS12NSOUR"); 1491 flags = TLB::MustBeOne | TLB::UserMode; 1492 tranType = TLB::S1S2NsTran; 1493 mode = BaseTLB::Read; 1494 break; 1495 case MISCREG_ATS12NSOUW: 1496 if (!haveSecurity) 1497 panic("Security Extensions required for ATS12NSOUW"); 1498 flags = TLB::MustBeOne | TLB::UserMode; 1499 tranType = TLB::S1S2NsTran; 1500 mode = BaseTLB::Write; 1501 break; 1502 case MISCREG_ATS1HR: // only really useful from secure mode. 1503 flags = TLB::MustBeOne; 1504 tranType = TLB::HypMode; 1505 mode = BaseTLB::Read; 1506 break; 1507 case MISCREG_ATS1HW: 1508 flags = TLB::MustBeOne; 1509 tranType = TLB::HypMode; 1510 mode = BaseTLB::Write; 1511 break; 1512 } 1513 // If we're in timing mode then doing the translation in 1514 // functional mode then we're slightly distorting performance 1515 // results obtained from simulations. The translation should be 1516 // done in the same mode the core is running in. NOTE: This 1517 // can't be an atomic translation because that causes problems 1518 // with unexpected atomic snoop requests. 1519 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1520 Request req(0, val, 0, flags, Request::funcMasterId, 1521 tc->pcState().pc(), tc->contextId()); 1522 fault = tc->getDTBPtr()->translateFunctional(&req, tc, mode, tranType); 1523 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1524 HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 1525 1526 MiscReg newVal; 1527 if (fault == NoFault) { 1528 Addr paddr = req.getPaddr(); 1529 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 1530 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 1531 newVal = (paddr & mask(39, 12)) | 1532 (tc->getDTBPtr()->getAttr()); 1533 } else { 1534 newVal = (paddr & 0xfffff000) | 1535 (tc->getDTBPtr()->getAttr()); 1536 } 1537 DPRINTF(MiscRegs, 1538 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 1539 val, newVal); 1540 } else { 1541 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 1542 // Set fault bit and FSR 1543 FSR fsr = armFault->getFsr(tc); 1544 1545 newVal = ((fsr >> 9) & 1) << 11; 1546 if (newVal) { 1547 // LPAE - rearange fault status 1548 newVal |= ((fsr >> 0) & 0x3f) << 1; 1549 } else { 1550 // VMSA - rearange fault status 1551 newVal |= ((fsr >> 0) & 0xf) << 1; 1552 newVal |= ((fsr >> 10) & 0x1) << 5; 1553 newVal |= ((fsr >> 12) & 0x1) << 6; 1554 } 1555 newVal |= 0x1; // F bit 1556 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1557 newVal |= armFault->isStage2() ? 0x200 : 0; 1558 DPRINTF(MiscRegs, 1559 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 1560 val, fsr, newVal); 1561 } 1562 setMiscRegNoEffect(MISCREG_PAR, newVal); 1563 return; 1564 } 1565 case MISCREG_TTBCR: 1566 { 1567 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1568 const uint32_t ones = (uint32_t)(-1); 1569 TTBCR ttbcrMask = 0; 1570 TTBCR ttbcrNew = newVal; 1571 1572 // ARM DDI 0406C.b, ARMv7-32 1573 ttbcrMask.n = ones; // T0SZ 1574 if (haveSecurity) { 1575 ttbcrMask.pd0 = ones; 1576 ttbcrMask.pd1 = ones; 1577 } 1578 ttbcrMask.epd0 = ones; 1579 ttbcrMask.irgn0 = ones; 1580 ttbcrMask.orgn0 = ones; 1581 ttbcrMask.sh0 = ones; 1582 ttbcrMask.ps = ones; // T1SZ 1583 ttbcrMask.a1 = ones; 1584 ttbcrMask.epd1 = ones; 1585 ttbcrMask.irgn1 = ones; 1586 ttbcrMask.orgn1 = ones; 1587 ttbcrMask.sh1 = ones; 1588 if (haveLPAE) 1589 ttbcrMask.eae = ones; 1590 1591 if (haveLPAE && ttbcrNew.eae) { 1592 newVal = newVal & ttbcrMask; 1593 } else { 1594 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 1595 } 1596 } 1597 case MISCREG_TTBR0: 1598 case MISCREG_TTBR1: 1599 { 1600 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1601 if (haveLPAE) { 1602 if (ttbcr.eae) { 1603 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 1604 // ARMv8 AArch32 bit 63-56 only 1605 uint64_t ttbrMask = mask(63,56) | mask(47,40); 1606 newVal = (newVal & (~ttbrMask)); 1607 } 1608 } 1609 } 1610 case MISCREG_SCTLR_EL1: 1611 { 1612 tc->getITBPtr()->invalidateMiscReg(); 1613 tc->getDTBPtr()->invalidateMiscReg(); 1614 setMiscRegNoEffect(misc_reg, newVal); 1615 } 1616 case MISCREG_CONTEXTIDR: 1617 case MISCREG_PRRR: 1618 case MISCREG_NMRR: 1619 case MISCREG_MAIR0: 1620 case MISCREG_MAIR1: 1621 case MISCREG_DACR: 1622 case MISCREG_VTTBR: 1623 case MISCREG_SCR_EL3: 1624 case MISCREG_HCR_EL2: 1625 case MISCREG_TCR_EL1: 1626 case MISCREG_TCR_EL2: 1627 case MISCREG_TCR_EL3: 1628 case MISCREG_SCTLR_EL2: 1629 case MISCREG_SCTLR_EL3: 1630 case MISCREG_HSCTLR: 1631 case MISCREG_TTBR0_EL1: 1632 case MISCREG_TTBR1_EL1: 1633 case MISCREG_TTBR0_EL2: 1634 case MISCREG_TTBR0_EL3: 1635 tc->getITBPtr()->invalidateMiscReg(); 1636 tc->getDTBPtr()->invalidateMiscReg(); 1637 break; 1638 case MISCREG_NZCV: 1639 { 1640 CPSR cpsr = val; 1641 1642 tc->setCCReg(CCREG_NZ, cpsr.nz); 1643 tc->setCCReg(CCREG_C, cpsr.c); 1644 tc->setCCReg(CCREG_V, cpsr.v); 1645 } 1646 break; 1647 case MISCREG_DAIF: 1648 { 1649 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1650 cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 1651 newVal = cpsr; 1652 misc_reg = MISCREG_CPSR; 1653 } 1654 break; 1655 case MISCREG_SP_EL0: 1656 tc->setIntReg(INTREG_SP0, newVal); 1657 break; 1658 case MISCREG_SP_EL1: 1659 tc->setIntReg(INTREG_SP1, newVal); 1660 break; 1661 case MISCREG_SP_EL2: 1662 tc->setIntReg(INTREG_SP2, newVal); 1663 break; 1664 case MISCREG_SPSEL: 1665 { 1666 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1667 cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 1668 newVal = cpsr; 1669 misc_reg = MISCREG_CPSR; 1670 } 1671 break; 1672 case MISCREG_CURRENTEL: 1673 { 1674 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1675 cpsr.el = (uint8_t) ((CPSR) newVal).el; 1676 newVal = cpsr; 1677 misc_reg = MISCREG_CPSR; 1678 } 1679 break; 1680 case MISCREG_AT_S1E1R_Xt: 1681 case MISCREG_AT_S1E1W_Xt: 1682 case MISCREG_AT_S1E0R_Xt: 1683 case MISCREG_AT_S1E0W_Xt: 1684 case MISCREG_AT_S1E2R_Xt: 1685 case MISCREG_AT_S1E2W_Xt: 1686 case MISCREG_AT_S12E1R_Xt: 1687 case MISCREG_AT_S12E1W_Xt: 1688 case MISCREG_AT_S12E0R_Xt: 1689 case MISCREG_AT_S12E0W_Xt: 1690 case MISCREG_AT_S1E3R_Xt: 1691 case MISCREG_AT_S1E3W_Xt: 1692 { 1693 RequestPtr req = new Request; 1694 unsigned flags = 0; 1695 BaseTLB::Mode mode = BaseTLB::Read; 1696 TLB::ArmTranslationType tranType = TLB::NormalTran; 1697 Fault fault; 1698 switch(misc_reg) { 1699 case MISCREG_AT_S1E1R_Xt: 1700 flags = TLB::MustBeOne; 1701 tranType = TLB::S1E1Tran; 1702 mode = BaseTLB::Read; 1703 break; 1704 case MISCREG_AT_S1E1W_Xt: 1705 flags = TLB::MustBeOne; 1706 tranType = TLB::S1E1Tran; 1707 mode = BaseTLB::Write; 1708 break; 1709 case MISCREG_AT_S1E0R_Xt: 1710 flags = TLB::MustBeOne | TLB::UserMode; 1711 tranType = TLB::S1E0Tran; 1712 mode = BaseTLB::Read; 1713 break; 1714 case MISCREG_AT_S1E0W_Xt: 1715 flags = TLB::MustBeOne | TLB::UserMode; 1716 tranType = TLB::S1E0Tran; 1717 mode = BaseTLB::Write; 1718 break; 1719 case MISCREG_AT_S1E2R_Xt: 1720 flags = TLB::MustBeOne; 1721 tranType = TLB::S1E2Tran; 1722 mode = BaseTLB::Read; 1723 break; 1724 case MISCREG_AT_S1E2W_Xt: 1725 flags = TLB::MustBeOne; 1726 tranType = TLB::S1E2Tran; 1727 mode = BaseTLB::Write; 1728 break; 1729 case MISCREG_AT_S12E0R_Xt: 1730 flags = TLB::MustBeOne | TLB::UserMode; 1731 tranType = TLB::S12E0Tran; 1732 mode = BaseTLB::Read; 1733 break; 1734 case MISCREG_AT_S12E0W_Xt: 1735 flags = TLB::MustBeOne | TLB::UserMode; 1736 tranType = TLB::S12E0Tran; 1737 mode = BaseTLB::Write; 1738 break; 1739 case MISCREG_AT_S12E1R_Xt: 1740 flags = TLB::MustBeOne; 1741 tranType = TLB::S12E1Tran; 1742 mode = BaseTLB::Read; 1743 break; 1744 case MISCREG_AT_S12E1W_Xt: 1745 flags = TLB::MustBeOne; 1746 tranType = TLB::S12E1Tran; 1747 mode = BaseTLB::Write; 1748 break; 1749 case MISCREG_AT_S1E3R_Xt: 1750 flags = TLB::MustBeOne; 1751 tranType = TLB::S1E3Tran; 1752 mode = BaseTLB::Read; 1753 break; 1754 case MISCREG_AT_S1E3W_Xt: 1755 flags = TLB::MustBeOne; 1756 tranType = TLB::S1E3Tran; 1757 mode = BaseTLB::Write; 1758 break; 1759 } 1760 // If we're in timing mode then doing the translation in 1761 // functional mode then we're slightly distorting performance 1762 // results obtained from simulations. The translation should be 1763 // done in the same mode the core is running in. NOTE: This 1764 // can't be an atomic translation because that causes problems 1765 // with unexpected atomic snoop requests. 1766 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1767 req->setVirt(0, val, 0, flags, Request::funcMasterId, 1768 tc->pcState().pc()); 1769 req->setContext(tc->contextId()); 1770 fault = tc->getDTBPtr()->translateFunctional(req, tc, mode, 1771 tranType); 1772 1773 MiscReg newVal; 1774 if (fault == NoFault) { 1775 Addr paddr = req->getPaddr(); 1776 uint64_t attr = tc->getDTBPtr()->getAttr(); 1777 uint64_t attr1 = attr >> 56; 1778 if (!attr1 || attr1 ==0x44) { 1779 attr |= 0x100; 1780 attr &= ~ uint64_t(0x80); 1781 } 1782 newVal = (paddr & mask(47, 12)) | attr; 1783 DPRINTF(MiscRegs, 1784 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 1785 val, newVal); 1786 } else { 1787 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 1788 // Set fault bit and FSR 1789 FSR fsr = armFault->getFsr(tc); 1790 1791 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1792 if (cpsr.width) { // AArch32 1793 newVal = ((fsr >> 9) & 1) << 11; 1794 // rearrange fault status 1795 newVal |= ((fsr >> 0) & 0x3f) << 1; 1796 newVal |= 0x1; // F bit 1797 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1798 newVal |= armFault->isStage2() ? 0x200 : 0; 1799 } else { // AArch64 1800 newVal = 1; // F bit 1801 newVal |= fsr << 1; // FST 1802 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit. 1803 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 1804 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 1805 newVal |= 1 << 11; // RES1 1806 } 1807 DPRINTF(MiscRegs, 1808 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 1809 val, fsr, newVal); 1810 } 1811 delete req; 1812 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 1813 return; 1814 } 1815 case MISCREG_SPSR_EL3: 1816 case MISCREG_SPSR_EL2: 1817 case MISCREG_SPSR_EL1: 1818 // Force bits 23:21 to 0 1819 newVal = val & ~(0x7 << 21); 1820 break; 1821 case MISCREG_L2CTLR: 1822 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 1823 miscRegName[misc_reg], uint32_t(val)); 1824 break; 1825 1826 // Generic Timer registers 1827 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 1828 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 1829 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 1830 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 1831 getGenericTimer(tc).setMiscReg(misc_reg, newVal); 1832 break; 1833 } 1834 } 1835 setMiscRegNoEffect(misc_reg, newVal); 1836} 1837 1838void 1839ISA::tlbiVA(ThreadContext *tc, MiscReg newVal, uint16_t asid, 1840 bool secure_lookup, uint8_t target_el) 1841{ 1842 if (!haveLargeAsid64) 1843 asid &= mask(8); 1844 Addr va = ((Addr) bits(newVal, 43, 0)) << 12; 1845 System *sys = tc->getSystemPtr(); 1846 for (int x = 0; x < sys->numContexts(); x++) { 1847 ThreadContext *oc = sys->getThreadContext(x); 1848 assert(oc->getITBPtr() && oc->getDTBPtr()); 1849 oc->getITBPtr()->flushMvaAsid(va, asid, 1850 secure_lookup, target_el); 1851 oc->getDTBPtr()->flushMvaAsid(va, asid, 1852 secure_lookup, target_el); 1853 1854 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1855 if (checker) { 1856 checker->getITBPtr()->flushMvaAsid( 1857 va, asid, secure_lookup, target_el); 1858 checker->getDTBPtr()->flushMvaAsid( 1859 va, asid, secure_lookup, target_el); 1860 } 1861 } 1862} 1863 1864void 1865ISA::tlbiALL(ThreadContext *tc, bool secure_lookup, uint8_t target_el) 1866{ 1867 System *sys = tc->getSystemPtr(); 1868 for (int x = 0; x < sys->numContexts(); x++) { 1869 ThreadContext *oc = sys->getThreadContext(x); 1870 assert(oc->getITBPtr() && oc->getDTBPtr()); 1871 oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 1872 oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 1873 1874 // If CheckerCPU is connected, need to notify it of a flush 1875 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1876 if (checker) { 1877 checker->getITBPtr()->flushAllSecurity(secure_lookup, 1878 target_el); 1879 checker->getDTBPtr()->flushAllSecurity(secure_lookup, 1880 target_el); 1881 } 1882 } 1883} 1884 1885void 1886ISA::tlbiALLN(ThreadContext *tc, bool hyp, uint8_t target_el) 1887{ 1888 System *sys = tc->getSystemPtr(); 1889 for (int x = 0; x < sys->numContexts(); x++) { 1890 ThreadContext *oc = sys->getThreadContext(x); 1891 assert(oc->getITBPtr() && oc->getDTBPtr()); 1892 oc->getITBPtr()->flushAllNs(hyp, target_el); 1893 oc->getDTBPtr()->flushAllNs(hyp, target_el); 1894 1895 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1896 if (checker) { 1897 checker->getITBPtr()->flushAllNs(hyp, target_el); 1898 checker->getDTBPtr()->flushAllNs(hyp, target_el); 1899 } 1900 } 1901} 1902 1903void 1904ISA::tlbiMVA(ThreadContext *tc, MiscReg newVal, bool secure_lookup, bool hyp, 1905 uint8_t target_el) 1906{ 1907 System *sys = tc->getSystemPtr(); 1908 for (int x = 0; x < sys->numContexts(); x++) { 1909 ThreadContext *oc = sys->getThreadContext(x); 1910 assert(oc->getITBPtr() && oc->getDTBPtr()); 1911 oc->getITBPtr()->flushMva(mbits(newVal, 31,12), 1912 secure_lookup, hyp, target_el); 1913 oc->getDTBPtr()->flushMva(mbits(newVal, 31,12), 1914 secure_lookup, hyp, target_el); 1915 1916 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1917 if (checker) { 1918 checker->getITBPtr()->flushMva(mbits(newVal, 31,12), 1919 secure_lookup, hyp, target_el); 1920 checker->getDTBPtr()->flushMva(mbits(newVal, 31,12), 1921 secure_lookup, hyp, target_el); 1922 } 1923 } 1924} 1925 1926BaseISADevice & 1927ISA::getGenericTimer(ThreadContext *tc) 1928{ 1929 // We only need to create an ISA interface the first time we try 1930 // to access the timer. 1931 if (timer) 1932 return *timer.get(); 1933 1934 assert(system); 1935 GenericTimer *generic_timer(system->getGenericTimer()); 1936 if (!generic_timer) { 1937 panic("Trying to get a generic timer from a system that hasn't " 1938 "been configured to use a generic timer.\n"); 1939 } 1940 1941 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 1942 return *timer.get(); 1943} 1944 1945} 1946 1947ArmISA::ISA * 1948ArmISAParams::create() 1949{ 1950 return new ArmISA::ISA(this); 1951} 1952