isa.cc revision 11574:868c31fcca24
1/* 2 * Copyright (c) 2010-2016 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 */ 40 41#include "arch/arm/isa.hh" 42#include "arch/arm/pmu.hh" 43#include "arch/arm/system.hh" 44#include "cpu/checker/cpu.hh" 45#include "cpu/base.hh" 46#include "debug/Arm.hh" 47#include "debug/MiscRegs.hh" 48#include "dev/arm/generic_timer.hh" 49#include "params/ArmISA.hh" 50#include "sim/faults.hh" 51#include "sim/stat_control.hh" 52#include "sim/system.hh" 53 54namespace ArmISA 55{ 56 57 58/** 59 * Some registers aliase with others, and therefore need to be translated. 60 * For each entry: 61 * The first value is the misc register that is to be looked up 62 * the second value is the lower part of the translation 63 * the third the upper part 64 */ 65const struct ISA::MiscRegInitializerEntry 66 ISA::MiscRegSwitch[miscRegTranslateMax] = { 67 {MISCREG_CSSELR_EL1, {MISCREG_CSSELR, 0}}, 68 {MISCREG_SCTLR_EL1, {MISCREG_SCTLR, 0}}, 69 {MISCREG_SCTLR_EL2, {MISCREG_HSCTLR, 0}}, 70 {MISCREG_ACTLR_EL1, {MISCREG_ACTLR, 0}}, 71 {MISCREG_ACTLR_EL2, {MISCREG_HACTLR, 0}}, 72 {MISCREG_CPACR_EL1, {MISCREG_CPACR, 0}}, 73 {MISCREG_CPTR_EL2, {MISCREG_HCPTR, 0}}, 74 {MISCREG_HCR_EL2, {MISCREG_HCR, 0}}, 75 {MISCREG_MDCR_EL2, {MISCREG_HDCR, 0}}, 76 {MISCREG_HSTR_EL2, {MISCREG_HSTR, 0}}, 77 {MISCREG_HACR_EL2, {MISCREG_HACR, 0}}, 78 {MISCREG_TTBR0_EL1, {MISCREG_TTBR0, 0}}, 79 {MISCREG_TTBR1_EL1, {MISCREG_TTBR1, 0}}, 80 {MISCREG_TTBR0_EL2, {MISCREG_HTTBR, 0}}, 81 {MISCREG_VTTBR_EL2, {MISCREG_VTTBR, 0}}, 82 {MISCREG_TCR_EL1, {MISCREG_TTBCR, 0}}, 83 {MISCREG_TCR_EL2, {MISCREG_HTCR, 0}}, 84 {MISCREG_VTCR_EL2, {MISCREG_VTCR, 0}}, 85 {MISCREG_AFSR0_EL1, {MISCREG_ADFSR, 0}}, 86 {MISCREG_AFSR1_EL1, {MISCREG_AIFSR, 0}}, 87 {MISCREG_AFSR0_EL2, {MISCREG_HADFSR, 0}}, 88 {MISCREG_AFSR1_EL2, {MISCREG_HAIFSR, 0}}, 89 {MISCREG_ESR_EL2, {MISCREG_HSR, 0}}, 90 {MISCREG_FAR_EL1, {MISCREG_DFAR, MISCREG_IFAR}}, 91 {MISCREG_FAR_EL2, {MISCREG_HDFAR, MISCREG_HIFAR}}, 92 {MISCREG_HPFAR_EL2, {MISCREG_HPFAR, 0}}, 93 {MISCREG_PAR_EL1, {MISCREG_PAR, 0}}, 94 {MISCREG_MAIR_EL1, {MISCREG_PRRR, MISCREG_NMRR}}, 95 {MISCREG_MAIR_EL2, {MISCREG_HMAIR0, MISCREG_HMAIR1}}, 96 {MISCREG_AMAIR_EL1, {MISCREG_AMAIR0, MISCREG_AMAIR1}}, 97 {MISCREG_VBAR_EL1, {MISCREG_VBAR, 0}}, 98 {MISCREG_VBAR_EL2, {MISCREG_HVBAR, 0}}, 99 {MISCREG_CONTEXTIDR_EL1, {MISCREG_CONTEXTIDR, 0}}, 100 {MISCREG_TPIDR_EL0, {MISCREG_TPIDRURW, 0}}, 101 {MISCREG_TPIDRRO_EL0, {MISCREG_TPIDRURO, 0}}, 102 {MISCREG_TPIDR_EL1, {MISCREG_TPIDRPRW, 0}}, 103 {MISCREG_TPIDR_EL2, {MISCREG_HTPIDR, 0}}, 104 {MISCREG_TEECR32_EL1, {MISCREG_TEECR, 0}}, 105 {MISCREG_CNTFRQ_EL0, {MISCREG_CNTFRQ, 0}}, 106 {MISCREG_CNTPCT_EL0, {MISCREG_CNTPCT, 0}}, 107 {MISCREG_CNTVCT_EL0, {MISCREG_CNTVCT, 0}}, 108 {MISCREG_CNTVOFF_EL2, {MISCREG_CNTVOFF, 0}}, 109 {MISCREG_CNTKCTL_EL1, {MISCREG_CNTKCTL, 0}}, 110 {MISCREG_CNTHCTL_EL2, {MISCREG_CNTHCTL, 0}}, 111 {MISCREG_CNTP_TVAL_EL0, {MISCREG_CNTP_TVAL, 0}}, 112 {MISCREG_CNTP_CTL_EL0, {MISCREG_CNTP_CTL, 0}}, 113 {MISCREG_CNTP_CVAL_EL0, {MISCREG_CNTP_CVAL, 0}}, 114 {MISCREG_CNTV_TVAL_EL0, {MISCREG_CNTV_TVAL, 0}}, 115 {MISCREG_CNTV_CTL_EL0, {MISCREG_CNTV_CTL, 0}}, 116 {MISCREG_CNTV_CVAL_EL0, {MISCREG_CNTV_CVAL, 0}}, 117 {MISCREG_CNTHP_TVAL_EL2, {MISCREG_CNTHP_TVAL, 0}}, 118 {MISCREG_CNTHP_CTL_EL2, {MISCREG_CNTHP_CTL, 0}}, 119 {MISCREG_CNTHP_CVAL_EL2, {MISCREG_CNTHP_CVAL, 0}}, 120 {MISCREG_DACR32_EL2, {MISCREG_DACR, 0}}, 121 {MISCREG_IFSR32_EL2, {MISCREG_IFSR, 0}}, 122 {MISCREG_TEEHBR32_EL1, {MISCREG_TEEHBR, 0}}, 123 {MISCREG_SDER32_EL3, {MISCREG_SDER, 0}} 124}; 125 126 127ISA::ISA(Params *p) 128 : SimObject(p), 129 system(NULL), 130 _decoderFlavour(p->decoderFlavour), 131 pmu(p->pmu), 132 lookUpMiscReg(NUM_MISCREGS, {0,0}) 133{ 134 SCTLR sctlr; 135 sctlr = 0; 136 miscRegs[MISCREG_SCTLR_RST] = sctlr; 137 138 // Hook up a dummy device if we haven't been configured with a 139 // real PMU. By using a dummy device, we don't need to check that 140 // the PMU exist every time we try to access a PMU register. 141 if (!pmu) 142 pmu = &dummyDevice; 143 144 // Give all ISA devices a pointer to this ISA 145 pmu->setISA(this); 146 147 system = dynamic_cast<ArmSystem *>(p->system); 148 149 // Cache system-level properties 150 if (FullSystem && system) { 151 haveSecurity = system->haveSecurity(); 152 haveLPAE = system->haveLPAE(); 153 haveVirtualization = system->haveVirtualization(); 154 haveLargeAsid64 = system->haveLargeAsid64(); 155 physAddrRange64 = system->physAddrRange64(); 156 } else { 157 haveSecurity = haveLPAE = haveVirtualization = false; 158 haveLargeAsid64 = false; 159 physAddrRange64 = 32; // dummy value 160 } 161 162 /** Fill in the miscReg translation table */ 163 for (uint32_t i = 0; i < miscRegTranslateMax; i++) { 164 struct MiscRegLUTEntry new_entry; 165 166 uint32_t select = MiscRegSwitch[i].index; 167 new_entry = MiscRegSwitch[i].entry; 168 169 lookUpMiscReg[select] = new_entry; 170 } 171 172 preUnflattenMiscReg(); 173 174 clear(); 175} 176 177const ArmISAParams * 178ISA::params() const 179{ 180 return dynamic_cast<const Params *>(_params); 181} 182 183void 184ISA::clear() 185{ 186 const Params *p(params()); 187 188 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 189 memset(miscRegs, 0, sizeof(miscRegs)); 190 191 // Initialize configurable default values 192 miscRegs[MISCREG_MIDR] = p->midr; 193 miscRegs[MISCREG_MIDR_EL1] = p->midr; 194 miscRegs[MISCREG_VPIDR] = p->midr; 195 196 if (FullSystem && system->highestELIs64()) { 197 // Initialize AArch64 state 198 clear64(p); 199 return; 200 } 201 202 // Initialize AArch32 state... 203 204 CPSR cpsr = 0; 205 cpsr.mode = MODE_USER; 206 miscRegs[MISCREG_CPSR] = cpsr; 207 updateRegMap(cpsr); 208 209 SCTLR sctlr = 0; 210 sctlr.te = (bool) sctlr_rst.te; 211 sctlr.nmfi = (bool) sctlr_rst.nmfi; 212 sctlr.v = (bool) sctlr_rst.v; 213 sctlr.u = 1; 214 sctlr.xp = 1; 215 sctlr.rao2 = 1; 216 sctlr.rao3 = 1; 217 sctlr.rao4 = 0xf; // SCTLR[6:3] 218 sctlr.uci = 1; 219 sctlr.dze = 1; 220 miscRegs[MISCREG_SCTLR_NS] = sctlr; 221 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 222 miscRegs[MISCREG_HCPTR] = 0; 223 224 // Start with an event in the mailbox 225 miscRegs[MISCREG_SEV_MAILBOX] = 1; 226 227 // Separate Instruction and Data TLBs 228 miscRegs[MISCREG_TLBTR] = 1; 229 230 MVFR0 mvfr0 = 0; 231 mvfr0.advSimdRegisters = 2; 232 mvfr0.singlePrecision = 2; 233 mvfr0.doublePrecision = 2; 234 mvfr0.vfpExceptionTrapping = 0; 235 mvfr0.divide = 1; 236 mvfr0.squareRoot = 1; 237 mvfr0.shortVectors = 1; 238 mvfr0.roundingModes = 1; 239 miscRegs[MISCREG_MVFR0] = mvfr0; 240 241 MVFR1 mvfr1 = 0; 242 mvfr1.flushToZero = 1; 243 mvfr1.defaultNaN = 1; 244 mvfr1.advSimdLoadStore = 1; 245 mvfr1.advSimdInteger = 1; 246 mvfr1.advSimdSinglePrecision = 1; 247 mvfr1.advSimdHalfPrecision = 1; 248 mvfr1.vfpHalfPrecision = 1; 249 miscRegs[MISCREG_MVFR1] = mvfr1; 250 251 // Reset values of PRRR and NMRR are implementation dependent 252 253 // @todo: PRRR and NMRR in secure state? 254 miscRegs[MISCREG_PRRR_NS] = 255 (1 << 19) | // 19 256 (0 << 18) | // 18 257 (0 << 17) | // 17 258 (1 << 16) | // 16 259 (2 << 14) | // 15:14 260 (0 << 12) | // 13:12 261 (2 << 10) | // 11:10 262 (2 << 8) | // 9:8 263 (2 << 6) | // 7:6 264 (2 << 4) | // 5:4 265 (1 << 2) | // 3:2 266 0; // 1:0 267 miscRegs[MISCREG_NMRR_NS] = 268 (1 << 30) | // 31:30 269 (0 << 26) | // 27:26 270 (0 << 24) | // 25:24 271 (3 << 22) | // 23:22 272 (2 << 20) | // 21:20 273 (0 << 18) | // 19:18 274 (0 << 16) | // 17:16 275 (1 << 14) | // 15:14 276 (0 << 12) | // 13:12 277 (2 << 10) | // 11:10 278 (0 << 8) | // 9:8 279 (3 << 6) | // 7:6 280 (2 << 4) | // 5:4 281 (0 << 2) | // 3:2 282 0; // 1:0 283 284 miscRegs[MISCREG_CPACR] = 0; 285 286 287 miscRegs[MISCREG_ID_PFR0] = p->id_pfr0; 288 miscRegs[MISCREG_ID_PFR1] = p->id_pfr1; 289 290 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 291 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 292 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 293 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 294 295 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 296 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 297 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 298 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 299 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 300 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 301 302 miscRegs[MISCREG_FPSID] = p->fpsid; 303 304 if (haveLPAE) { 305 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 306 ttbcr.eae = 0; 307 miscRegs[MISCREG_TTBCR_NS] = ttbcr; 308 // Enforce consistency with system-level settings 309 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 310 } 311 312 if (haveSecurity) { 313 miscRegs[MISCREG_SCTLR_S] = sctlr; 314 miscRegs[MISCREG_SCR] = 0; 315 miscRegs[MISCREG_VBAR_S] = 0; 316 } else { 317 // we're always non-secure 318 miscRegs[MISCREG_SCR] = 1; 319 } 320 321 //XXX We need to initialize the rest of the state. 322} 323 324void 325ISA::clear64(const ArmISAParams *p) 326{ 327 CPSR cpsr = 0; 328 Addr rvbar = system->resetAddr64(); 329 switch (system->highestEL()) { 330 // Set initial EL to highest implemented EL using associated stack 331 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 332 // value 333 case EL3: 334 cpsr.mode = MODE_EL3H; 335 miscRegs[MISCREG_RVBAR_EL3] = rvbar; 336 break; 337 case EL2: 338 cpsr.mode = MODE_EL2H; 339 miscRegs[MISCREG_RVBAR_EL2] = rvbar; 340 break; 341 case EL1: 342 cpsr.mode = MODE_EL1H; 343 miscRegs[MISCREG_RVBAR_EL1] = rvbar; 344 break; 345 default: 346 panic("Invalid highest implemented exception level"); 347 break; 348 } 349 350 // Initialize rest of CPSR 351 cpsr.daif = 0xf; // Mask all interrupts 352 cpsr.ss = 0; 353 cpsr.il = 0; 354 miscRegs[MISCREG_CPSR] = cpsr; 355 updateRegMap(cpsr); 356 357 // Initialize other control registers 358 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 359 if (haveSecurity) { 360 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50870; 361 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 362 } else if (haveVirtualization) { 363 miscRegs[MISCREG_SCTLR_EL2] = 0x30c50870; 364 } else { 365 miscRegs[MISCREG_SCTLR_EL1] = 0x30c50870; 366 // Always non-secure 367 miscRegs[MISCREG_SCR_EL3] = 1; 368 } 369 370 // Initialize configurable id registers 371 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 372 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 373 miscRegs[MISCREG_ID_AA64DFR0_EL1] = 374 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 375 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 376 377 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 378 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 379 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 380 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 381 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 382 miscRegs[MISCREG_ID_AA64PFR0_EL1] = p->id_aa64pfr0_el1; 383 miscRegs[MISCREG_ID_AA64PFR1_EL1] = p->id_aa64pfr1_el1; 384 385 miscRegs[MISCREG_ID_DFR0_EL1] = 386 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 387 388 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 389 390 // Enforce consistency with system-level settings... 391 392 // EL3 393 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 394 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 395 haveSecurity ? 0x2 : 0x0); 396 // EL2 397 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 398 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 399 haveVirtualization ? 0x2 : 0x0); 400 // Large ASID support 401 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 402 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 403 haveLargeAsid64 ? 0x2 : 0x0); 404 // Physical address size 405 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 406 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 407 encodePhysAddrRange64(physAddrRange64)); 408} 409 410MiscReg 411ISA::readMiscRegNoEffect(int misc_reg) const 412{ 413 assert(misc_reg < NumMiscRegs); 414 415 int flat_idx = flattenMiscIndex(misc_reg); // Note: indexes of AArch64 416 // registers are left unchanged 417 MiscReg val; 418 419 if (lookUpMiscReg[flat_idx].lower == 0 || flat_idx == MISCREG_SPSR 420 || flat_idx == MISCREG_SCTLR_EL1) { 421 if (flat_idx == MISCREG_SPSR) 422 flat_idx = flattenMiscIndex(MISCREG_SPSR); 423 if (flat_idx == MISCREG_SCTLR_EL1) 424 flat_idx = flattenMiscIndex(MISCREG_SCTLR); 425 val = miscRegs[flat_idx]; 426 } else 427 if (lookUpMiscReg[flat_idx].upper > 0) 428 val = ((miscRegs[lookUpMiscReg[flat_idx].lower] & mask(32)) 429 | (miscRegs[lookUpMiscReg[flat_idx].upper] << 32)); 430 else 431 val = miscRegs[lookUpMiscReg[flat_idx].lower]; 432 433 return val; 434} 435 436 437MiscReg 438ISA::readMiscReg(int misc_reg, ThreadContext *tc) 439{ 440 CPSR cpsr = 0; 441 PCState pc = 0; 442 SCR scr = 0; 443 444 if (misc_reg == MISCREG_CPSR) { 445 cpsr = miscRegs[misc_reg]; 446 pc = tc->pcState(); 447 cpsr.j = pc.jazelle() ? 1 : 0; 448 cpsr.t = pc.thumb() ? 1 : 0; 449 return cpsr; 450 } 451 452#ifndef NDEBUG 453 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 454 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 455 warn("Unimplemented system register %s read.\n", 456 miscRegName[misc_reg]); 457 else 458 panic("Unimplemented system register %s read.\n", 459 miscRegName[misc_reg]); 460 } 461#endif 462 463 switch (unflattenMiscReg(misc_reg)) { 464 case MISCREG_HCR: 465 { 466 if (!haveVirtualization) 467 return 0; 468 else 469 return readMiscRegNoEffect(MISCREG_HCR); 470 } 471 case MISCREG_CPACR: 472 { 473 const uint32_t ones = (uint32_t)(-1); 474 CPACR cpacrMask = 0; 475 // Only cp10, cp11, and ase are implemented, nothing else should 476 // be readable? (straight copy from the write code) 477 cpacrMask.cp10 = ones; 478 cpacrMask.cp11 = ones; 479 cpacrMask.asedis = ones; 480 481 // Security Extensions may limit the readability of CPACR 482 if (haveSecurity) { 483 scr = readMiscRegNoEffect(MISCREG_SCR); 484 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 485 if (scr.ns && (cpsr.mode != MODE_MON)) { 486 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 487 // NB: Skipping the full loop, here 488 if (!nsacr.cp10) cpacrMask.cp10 = 0; 489 if (!nsacr.cp11) cpacrMask.cp11 = 0; 490 } 491 } 492 MiscReg val = readMiscRegNoEffect(MISCREG_CPACR); 493 val &= cpacrMask; 494 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 495 miscRegName[misc_reg], val); 496 return val; 497 } 498 case MISCREG_MPIDR: 499 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 500 scr = readMiscRegNoEffect(MISCREG_SCR); 501 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 502 return getMPIDR(system, tc); 503 } else { 504 return readMiscReg(MISCREG_VMPIDR, tc); 505 } 506 break; 507 case MISCREG_MPIDR_EL1: 508 // @todo in the absence of v8 virtualization support just return MPIDR_EL1 509 return getMPIDR(system, tc) & 0xffffffff; 510 case MISCREG_VMPIDR: 511 // top bit defined as RES1 512 return readMiscRegNoEffect(misc_reg) | 0x80000000; 513 case MISCREG_ID_AFR0: // not implemented, so alias MIDR 514 case MISCREG_REVIDR: // not implemented, so alias MIDR 515 case MISCREG_MIDR: 516 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 517 scr = readMiscRegNoEffect(MISCREG_SCR); 518 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 519 return readMiscRegNoEffect(misc_reg); 520 } else { 521 return readMiscRegNoEffect(MISCREG_VPIDR); 522 } 523 break; 524 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 525 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 526 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 527 case MISCREG_AIDR: // AUX ID set to 0 528 case MISCREG_TCMTR: // No TCM's 529 return 0; 530 531 case MISCREG_CLIDR: 532 warn_once("The clidr register always reports 0 caches.\n"); 533 warn_once("clidr LoUIS field of 0b001 to match current " 534 "ARM implementations.\n"); 535 return 0x00200000; 536 case MISCREG_CCSIDR: 537 warn_once("The ccsidr register isn't implemented and " 538 "always reads as 0.\n"); 539 break; 540 case MISCREG_CTR: 541 { 542 //all caches have the same line size in gem5 543 //4 byte words in ARM 544 unsigned lineSizeWords = 545 tc->getSystemPtr()->cacheLineSize() / 4; 546 unsigned log2LineSizeWords = 0; 547 548 while (lineSizeWords >>= 1) { 549 ++log2LineSizeWords; 550 } 551 552 CTR ctr = 0; 553 //log2 of minimun i-cache line size (words) 554 ctr.iCacheLineSize = log2LineSizeWords; 555 //b11 - gem5 uses pipt 556 ctr.l1IndexPolicy = 0x3; 557 //log2 of minimum d-cache line size (words) 558 ctr.dCacheLineSize = log2LineSizeWords; 559 //log2 of max reservation size (words) 560 ctr.erg = log2LineSizeWords; 561 //log2 of max writeback size (words) 562 ctr.cwg = log2LineSizeWords; 563 //b100 - gem5 format is ARMv7 564 ctr.format = 0x4; 565 566 return ctr; 567 } 568 case MISCREG_ACTLR: 569 warn("Not doing anything for miscreg ACTLR\n"); 570 break; 571 572 case MISCREG_PMXEVTYPER_PMCCFILTR: 573 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 574 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 575 case MISCREG_PMCR ... MISCREG_PMOVSSET: 576 return pmu->readMiscReg(misc_reg); 577 578 case MISCREG_CPSR_Q: 579 panic("shouldn't be reading this register seperately\n"); 580 case MISCREG_FPSCR_QC: 581 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 582 case MISCREG_FPSCR_EXC: 583 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 584 case MISCREG_FPSR: 585 { 586 const uint32_t ones = (uint32_t)(-1); 587 FPSCR fpscrMask = 0; 588 fpscrMask.ioc = ones; 589 fpscrMask.dzc = ones; 590 fpscrMask.ofc = ones; 591 fpscrMask.ufc = ones; 592 fpscrMask.ixc = ones; 593 fpscrMask.idc = ones; 594 fpscrMask.qc = ones; 595 fpscrMask.v = ones; 596 fpscrMask.c = ones; 597 fpscrMask.z = ones; 598 fpscrMask.n = ones; 599 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 600 } 601 case MISCREG_FPCR: 602 { 603 const uint32_t ones = (uint32_t)(-1); 604 FPSCR fpscrMask = 0; 605 fpscrMask.ioe = ones; 606 fpscrMask.dze = ones; 607 fpscrMask.ofe = ones; 608 fpscrMask.ufe = ones; 609 fpscrMask.ixe = ones; 610 fpscrMask.ide = ones; 611 fpscrMask.len = ones; 612 fpscrMask.stride = ones; 613 fpscrMask.rMode = ones; 614 fpscrMask.fz = ones; 615 fpscrMask.dn = ones; 616 fpscrMask.ahp = ones; 617 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 618 } 619 case MISCREG_NZCV: 620 { 621 CPSR cpsr = 0; 622 cpsr.nz = tc->readCCReg(CCREG_NZ); 623 cpsr.c = tc->readCCReg(CCREG_C); 624 cpsr.v = tc->readCCReg(CCREG_V); 625 return cpsr; 626 } 627 case MISCREG_DAIF: 628 { 629 CPSR cpsr = 0; 630 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 631 return cpsr; 632 } 633 case MISCREG_SP_EL0: 634 { 635 return tc->readIntReg(INTREG_SP0); 636 } 637 case MISCREG_SP_EL1: 638 { 639 return tc->readIntReg(INTREG_SP1); 640 } 641 case MISCREG_SP_EL2: 642 { 643 return tc->readIntReg(INTREG_SP2); 644 } 645 case MISCREG_SPSEL: 646 { 647 return miscRegs[MISCREG_CPSR] & 0x1; 648 } 649 case MISCREG_CURRENTEL: 650 { 651 return miscRegs[MISCREG_CPSR] & 0xc; 652 } 653 case MISCREG_L2CTLR: 654 { 655 // mostly unimplemented, just set NumCPUs field from sim and return 656 L2CTLR l2ctlr = 0; 657 // b00:1CPU to b11:4CPUs 658 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 659 return l2ctlr; 660 } 661 case MISCREG_DBGDIDR: 662 /* For now just implement the version number. 663 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 664 */ 665 return 0x5 << 16; 666 case MISCREG_DBGDSCRint: 667 return 0; 668 case MISCREG_ISR: 669 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 670 readMiscRegNoEffect(MISCREG_HCR), 671 readMiscRegNoEffect(MISCREG_CPSR), 672 readMiscRegNoEffect(MISCREG_SCR)); 673 case MISCREG_ISR_EL1: 674 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 675 readMiscRegNoEffect(MISCREG_HCR_EL2), 676 readMiscRegNoEffect(MISCREG_CPSR), 677 readMiscRegNoEffect(MISCREG_SCR_EL3)); 678 case MISCREG_DCZID_EL0: 679 return 0x04; // DC ZVA clear 64-byte chunks 680 case MISCREG_HCPTR: 681 { 682 MiscReg val = readMiscRegNoEffect(misc_reg); 683 // The trap bit associated with CP14 is defined as RAZ 684 val &= ~(1 << 14); 685 // If a CP bit in NSACR is 0 then the corresponding bit in 686 // HCPTR is RAO/WI 687 bool secure_lookup = haveSecurity && 688 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 689 readMiscRegNoEffect(MISCREG_CPSR)); 690 if (!secure_lookup) { 691 MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR); 692 val |= (mask ^ 0x7FFF) & 0xBFFF; 693 } 694 // Set the bits for unimplemented coprocessors to RAO/WI 695 val |= 0x33FF; 696 return (val); 697 } 698 case MISCREG_HDFAR: // alias for secure DFAR 699 return readMiscRegNoEffect(MISCREG_DFAR_S); 700 case MISCREG_HIFAR: // alias for secure IFAR 701 return readMiscRegNoEffect(MISCREG_IFAR_S); 702 case MISCREG_HVBAR: // bottom bits reserved 703 return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0; 704 case MISCREG_SCTLR: // Some bits hardwired 705 // The FI field (bit 21) is common between S/NS versions of the register 706 return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21)) | 707 (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818; // V8 SCTLR 708 case MISCREG_SCTLR_EL1: 709 // The FI field (bit 21) is common between S/NS versions of the register 710 return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21)) | 711 (readMiscRegNoEffect(misc_reg) & 0x37DDDBFF) | 0x30D00800; // V8 SCTLR_EL1 712 case MISCREG_SCTLR_EL3: 713 // The FI field (bit 21) is common between S/NS versions of the register 714 return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21)) | 715 (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; // V8 SCTLR_EL3 716 case MISCREG_HSCTLR: // FI comes from SCTLR 717 { 718 uint32_t mask = 1 << 27; 719 return (readMiscRegNoEffect(MISCREG_HSCTLR) & ~mask) | 720 (readMiscRegNoEffect(MISCREG_SCTLR) & mask); 721 } 722 case MISCREG_SCR: 723 { 724 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 725 if (cpsr.width) { 726 return readMiscRegNoEffect(MISCREG_SCR); 727 } else { 728 return readMiscRegNoEffect(MISCREG_SCR_EL3); 729 } 730 } 731 732 // Generic Timer registers 733 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 734 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 735 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 736 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 737 return getGenericTimer(tc).readMiscReg(misc_reg); 738 739 default: 740 break; 741 742 } 743 return readMiscRegNoEffect(misc_reg); 744} 745 746void 747ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 748{ 749 assert(misc_reg < NumMiscRegs); 750 751 int flat_idx = flattenMiscIndex(misc_reg); // Note: indexes of AArch64 752 // registers are left unchanged 753 754 int flat_idx2 = lookUpMiscReg[flat_idx].upper; 755 756 if (flat_idx2 > 0) { 757 miscRegs[lookUpMiscReg[flat_idx].lower] = bits(val, 31, 0); 758 miscRegs[flat_idx2] = bits(val, 63, 32); 759 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 760 misc_reg, flat_idx, flat_idx2, val); 761 } else { 762 if (flat_idx == MISCREG_SPSR) 763 flat_idx = flattenMiscIndex(MISCREG_SPSR); 764 else if (flat_idx == MISCREG_SCTLR_EL1) 765 flat_idx = flattenMiscIndex(MISCREG_SCTLR); 766 else 767 flat_idx = (lookUpMiscReg[flat_idx].lower > 0) ? 768 lookUpMiscReg[flat_idx].lower : flat_idx; 769 miscRegs[flat_idx] = val; 770 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 771 misc_reg, flat_idx, val); 772 } 773} 774 775void 776ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 777{ 778 779 MiscReg newVal = val; 780 int x; 781 bool secure_lookup; 782 bool hyp; 783 System *sys; 784 ThreadContext *oc; 785 uint8_t target_el; 786 uint16_t asid; 787 SCR scr; 788 789 if (misc_reg == MISCREG_CPSR) { 790 updateRegMap(val); 791 792 793 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 794 int old_mode = old_cpsr.mode; 795 CPSR cpsr = val; 796 if (old_mode != cpsr.mode) { 797 tc->getITBPtr()->invalidateMiscReg(); 798 tc->getDTBPtr()->invalidateMiscReg(); 799 } 800 801 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 802 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 803 PCState pc = tc->pcState(); 804 pc.nextThumb(cpsr.t); 805 pc.nextJazelle(cpsr.j); 806 807 // Follow slightly different semantics if a CheckerCPU object 808 // is connected 809 CheckerCPU *checker = tc->getCheckerCpuPtr(); 810 if (checker) { 811 tc->pcStateNoRecord(pc); 812 } else { 813 tc->pcState(pc); 814 } 815 } else { 816#ifndef NDEBUG 817 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 818 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 819 warn("Unimplemented system register %s write with %#x.\n", 820 miscRegName[misc_reg], val); 821 else 822 panic("Unimplemented system register %s write with %#x.\n", 823 miscRegName[misc_reg], val); 824 } 825#endif 826 switch (unflattenMiscReg(misc_reg)) { 827 case MISCREG_CPACR: 828 { 829 830 const uint32_t ones = (uint32_t)(-1); 831 CPACR cpacrMask = 0; 832 // Only cp10, cp11, and ase are implemented, nothing else should 833 // be writable 834 cpacrMask.cp10 = ones; 835 cpacrMask.cp11 = ones; 836 cpacrMask.asedis = ones; 837 838 // Security Extensions may limit the writability of CPACR 839 if (haveSecurity) { 840 scr = readMiscRegNoEffect(MISCREG_SCR); 841 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 842 if (scr.ns && (cpsr.mode != MODE_MON)) { 843 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 844 // NB: Skipping the full loop, here 845 if (!nsacr.cp10) cpacrMask.cp10 = 0; 846 if (!nsacr.cp11) cpacrMask.cp11 = 0; 847 } 848 } 849 850 MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR); 851 newVal &= cpacrMask; 852 newVal |= old_val & ~cpacrMask; 853 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 854 miscRegName[misc_reg], newVal); 855 } 856 break; 857 case MISCREG_CPACR_EL1: 858 { 859 const uint32_t ones = (uint32_t)(-1); 860 CPACR cpacrMask = 0; 861 cpacrMask.tta = ones; 862 cpacrMask.fpen = ones; 863 newVal &= cpacrMask; 864 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 865 miscRegName[misc_reg], newVal); 866 } 867 break; 868 case MISCREG_CPTR_EL2: 869 { 870 const uint32_t ones = (uint32_t)(-1); 871 CPTR cptrMask = 0; 872 cptrMask.tcpac = ones; 873 cptrMask.tta = ones; 874 cptrMask.tfp = ones; 875 newVal &= cptrMask; 876 cptrMask = 0; 877 cptrMask.res1_13_12_el2 = ones; 878 cptrMask.res1_9_0_el2 = ones; 879 newVal |= cptrMask; 880 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 881 miscRegName[misc_reg], newVal); 882 } 883 break; 884 case MISCREG_CPTR_EL3: 885 { 886 const uint32_t ones = (uint32_t)(-1); 887 CPTR cptrMask = 0; 888 cptrMask.tcpac = ones; 889 cptrMask.tta = ones; 890 cptrMask.tfp = ones; 891 newVal &= cptrMask; 892 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 893 miscRegName[misc_reg], newVal); 894 } 895 break; 896 case MISCREG_CSSELR: 897 warn_once("The csselr register isn't implemented.\n"); 898 return; 899 900 case MISCREG_DC_ZVA_Xt: 901 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 902 return; 903 904 case MISCREG_FPSCR: 905 { 906 const uint32_t ones = (uint32_t)(-1); 907 FPSCR fpscrMask = 0; 908 fpscrMask.ioc = ones; 909 fpscrMask.dzc = ones; 910 fpscrMask.ofc = ones; 911 fpscrMask.ufc = ones; 912 fpscrMask.ixc = ones; 913 fpscrMask.idc = ones; 914 fpscrMask.ioe = ones; 915 fpscrMask.dze = ones; 916 fpscrMask.ofe = ones; 917 fpscrMask.ufe = ones; 918 fpscrMask.ixe = ones; 919 fpscrMask.ide = ones; 920 fpscrMask.len = ones; 921 fpscrMask.stride = ones; 922 fpscrMask.rMode = ones; 923 fpscrMask.fz = ones; 924 fpscrMask.dn = ones; 925 fpscrMask.ahp = ones; 926 fpscrMask.qc = ones; 927 fpscrMask.v = ones; 928 fpscrMask.c = ones; 929 fpscrMask.z = ones; 930 fpscrMask.n = ones; 931 newVal = (newVal & (uint32_t)fpscrMask) | 932 (readMiscRegNoEffect(MISCREG_FPSCR) & 933 ~(uint32_t)fpscrMask); 934 tc->getDecoderPtr()->setContext(newVal); 935 } 936 break; 937 case MISCREG_FPSR: 938 { 939 const uint32_t ones = (uint32_t)(-1); 940 FPSCR fpscrMask = 0; 941 fpscrMask.ioc = ones; 942 fpscrMask.dzc = ones; 943 fpscrMask.ofc = ones; 944 fpscrMask.ufc = ones; 945 fpscrMask.ixc = ones; 946 fpscrMask.idc = ones; 947 fpscrMask.qc = ones; 948 fpscrMask.v = ones; 949 fpscrMask.c = ones; 950 fpscrMask.z = ones; 951 fpscrMask.n = ones; 952 newVal = (newVal & (uint32_t)fpscrMask) | 953 (readMiscRegNoEffect(MISCREG_FPSCR) & 954 ~(uint32_t)fpscrMask); 955 misc_reg = MISCREG_FPSCR; 956 } 957 break; 958 case MISCREG_FPCR: 959 { 960 const uint32_t ones = (uint32_t)(-1); 961 FPSCR fpscrMask = 0; 962 fpscrMask.ioe = ones; 963 fpscrMask.dze = ones; 964 fpscrMask.ofe = ones; 965 fpscrMask.ufe = ones; 966 fpscrMask.ixe = ones; 967 fpscrMask.ide = ones; 968 fpscrMask.len = ones; 969 fpscrMask.stride = ones; 970 fpscrMask.rMode = ones; 971 fpscrMask.fz = ones; 972 fpscrMask.dn = ones; 973 fpscrMask.ahp = ones; 974 newVal = (newVal & (uint32_t)fpscrMask) | 975 (readMiscRegNoEffect(MISCREG_FPSCR) & 976 ~(uint32_t)fpscrMask); 977 misc_reg = MISCREG_FPSCR; 978 } 979 break; 980 case MISCREG_CPSR_Q: 981 { 982 assert(!(newVal & ~CpsrMaskQ)); 983 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 984 misc_reg = MISCREG_CPSR; 985 } 986 break; 987 case MISCREG_FPSCR_QC: 988 { 989 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 990 (newVal & FpscrQcMask); 991 misc_reg = MISCREG_FPSCR; 992 } 993 break; 994 case MISCREG_FPSCR_EXC: 995 { 996 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 997 (newVal & FpscrExcMask); 998 misc_reg = MISCREG_FPSCR; 999 } 1000 break; 1001 case MISCREG_FPEXC: 1002 { 1003 // vfpv3 architecture, section B.6.1 of DDI04068 1004 // bit 29 - valid only if fpexc[31] is 0 1005 const uint32_t fpexcMask = 0x60000000; 1006 newVal = (newVal & fpexcMask) | 1007 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 1008 } 1009 break; 1010 case MISCREG_HCR: 1011 { 1012 if (!haveVirtualization) 1013 return; 1014 } 1015 break; 1016 case MISCREG_IFSR: 1017 { 1018 // ARM ARM (ARM DDI 0406C.b) B4.1.96 1019 const uint32_t ifsrMask = 1020 mask(31, 13) | mask(11, 11) | mask(8, 6); 1021 newVal = newVal & ~ifsrMask; 1022 } 1023 break; 1024 case MISCREG_DFSR: 1025 { 1026 // ARM ARM (ARM DDI 0406C.b) B4.1.52 1027 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 1028 newVal = newVal & ~dfsrMask; 1029 } 1030 break; 1031 case MISCREG_AMAIR0: 1032 case MISCREG_AMAIR1: 1033 { 1034 // ARM ARM (ARM DDI 0406C.b) B4.1.5 1035 // Valid only with LPAE 1036 if (!haveLPAE) 1037 return; 1038 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 1039 } 1040 break; 1041 case MISCREG_SCR: 1042 tc->getITBPtr()->invalidateMiscReg(); 1043 tc->getDTBPtr()->invalidateMiscReg(); 1044 break; 1045 case MISCREG_SCTLR: 1046 { 1047 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 1048 MiscRegIndex sctlr_idx; 1049 scr = readMiscRegNoEffect(MISCREG_SCR); 1050 if (haveSecurity && !scr.ns) { 1051 sctlr_idx = MISCREG_SCTLR_S; 1052 } else { 1053 sctlr_idx = MISCREG_SCTLR_NS; 1054 // The FI field (bit 21) is common between S/NS versions 1055 // of the register, we store this in the secure copy of 1056 // the reg 1057 miscRegs[MISCREG_SCTLR_S] &= ~(1 << 21); 1058 miscRegs[MISCREG_SCTLR_S] |= newVal & (1 << 21); 1059 } 1060 SCTLR sctlr = miscRegs[sctlr_idx]; 1061 SCTLR new_sctlr = newVal; 1062 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 1063 miscRegs[sctlr_idx] = (MiscReg)new_sctlr; 1064 tc->getITBPtr()->invalidateMiscReg(); 1065 tc->getDTBPtr()->invalidateMiscReg(); 1066 } 1067 case MISCREG_MIDR: 1068 case MISCREG_ID_PFR0: 1069 case MISCREG_ID_PFR1: 1070 case MISCREG_ID_DFR0: 1071 case MISCREG_ID_MMFR0: 1072 case MISCREG_ID_MMFR1: 1073 case MISCREG_ID_MMFR2: 1074 case MISCREG_ID_MMFR3: 1075 case MISCREG_ID_ISAR0: 1076 case MISCREG_ID_ISAR1: 1077 case MISCREG_ID_ISAR2: 1078 case MISCREG_ID_ISAR3: 1079 case MISCREG_ID_ISAR4: 1080 case MISCREG_ID_ISAR5: 1081 1082 case MISCREG_MPIDR: 1083 case MISCREG_FPSID: 1084 case MISCREG_TLBTR: 1085 case MISCREG_MVFR0: 1086 case MISCREG_MVFR1: 1087 1088 case MISCREG_ID_AA64AFR0_EL1: 1089 case MISCREG_ID_AA64AFR1_EL1: 1090 case MISCREG_ID_AA64DFR0_EL1: 1091 case MISCREG_ID_AA64DFR1_EL1: 1092 case MISCREG_ID_AA64ISAR0_EL1: 1093 case MISCREG_ID_AA64ISAR1_EL1: 1094 case MISCREG_ID_AA64MMFR0_EL1: 1095 case MISCREG_ID_AA64MMFR1_EL1: 1096 case MISCREG_ID_AA64PFR0_EL1: 1097 case MISCREG_ID_AA64PFR1_EL1: 1098 // ID registers are constants. 1099 return; 1100 1101 // TLBI all entries, EL0&1 inner sharable (ignored) 1102 case MISCREG_TLBIALLIS: 1103 case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 1104 assert32(tc); 1105 target_el = 1; // el 0 and 1 are handled together 1106 scr = readMiscReg(MISCREG_SCR, tc); 1107 secure_lookup = haveSecurity && !scr.ns; 1108 sys = tc->getSystemPtr(); 1109 for (x = 0; x < sys->numContexts(); x++) { 1110 oc = sys->getThreadContext(x); 1111 assert(oc->getITBPtr() && oc->getDTBPtr()); 1112 oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 1113 oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 1114 1115 // If CheckerCPU is connected, need to notify it of a flush 1116 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1117 if (checker) { 1118 checker->getITBPtr()->flushAllSecurity(secure_lookup, 1119 target_el); 1120 checker->getDTBPtr()->flushAllSecurity(secure_lookup, 1121 target_el); 1122 } 1123 } 1124 return; 1125 // TLBI all entries, EL0&1, instruction side 1126 case MISCREG_ITLBIALL: 1127 assert32(tc); 1128 target_el = 1; // el 0 and 1 are handled together 1129 scr = readMiscReg(MISCREG_SCR, tc); 1130 secure_lookup = haveSecurity && !scr.ns; 1131 tc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 1132 return; 1133 // TLBI all entries, EL0&1, data side 1134 case MISCREG_DTLBIALL: 1135 assert32(tc); 1136 target_el = 1; // el 0 and 1 are handled together 1137 scr = readMiscReg(MISCREG_SCR, tc); 1138 secure_lookup = haveSecurity && !scr.ns; 1139 tc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 1140 return; 1141 // TLBI based on VA, EL0&1 inner sharable (ignored) 1142 case MISCREG_TLBIMVAIS: 1143 case MISCREG_TLBIMVA: 1144 assert32(tc); 1145 target_el = 1; // el 0 and 1 are handled together 1146 scr = readMiscReg(MISCREG_SCR, tc); 1147 secure_lookup = haveSecurity && !scr.ns; 1148 sys = tc->getSystemPtr(); 1149 for (x = 0; x < sys->numContexts(); x++) { 1150 oc = sys->getThreadContext(x); 1151 assert(oc->getITBPtr() && oc->getDTBPtr()); 1152 oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1153 bits(newVal, 7,0), 1154 secure_lookup, target_el); 1155 oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1156 bits(newVal, 7,0), 1157 secure_lookup, target_el); 1158 1159 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1160 if (checker) { 1161 checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1162 bits(newVal, 7,0), secure_lookup, target_el); 1163 checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1164 bits(newVal, 7,0), secure_lookup, target_el); 1165 } 1166 } 1167 return; 1168 // TLBI by ASID, EL0&1, inner sharable 1169 case MISCREG_TLBIASIDIS: 1170 case MISCREG_TLBIASID: 1171 assert32(tc); 1172 target_el = 1; // el 0 and 1 are handled together 1173 scr = readMiscReg(MISCREG_SCR, tc); 1174 secure_lookup = haveSecurity && !scr.ns; 1175 sys = tc->getSystemPtr(); 1176 for (x = 0; x < sys->numContexts(); x++) { 1177 oc = sys->getThreadContext(x); 1178 assert(oc->getITBPtr() && oc->getDTBPtr()); 1179 oc->getITBPtr()->flushAsid(bits(newVal, 7,0), 1180 secure_lookup, target_el); 1181 oc->getDTBPtr()->flushAsid(bits(newVal, 7,0), 1182 secure_lookup, target_el); 1183 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1184 if (checker) { 1185 checker->getITBPtr()->flushAsid(bits(newVal, 7,0), 1186 secure_lookup, target_el); 1187 checker->getDTBPtr()->flushAsid(bits(newVal, 7,0), 1188 secure_lookup, target_el); 1189 } 1190 } 1191 return; 1192 // TLBI by address, EL0&1, inner sharable (ignored) 1193 case MISCREG_TLBIMVAAIS: 1194 case MISCREG_TLBIMVAA: 1195 assert32(tc); 1196 target_el = 1; // el 0 and 1 are handled together 1197 scr = readMiscReg(MISCREG_SCR, tc); 1198 secure_lookup = haveSecurity && !scr.ns; 1199 hyp = 0; 1200 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el); 1201 return; 1202 // TLBI by address, EL2, hypervisor mode 1203 case MISCREG_TLBIMVAH: 1204 case MISCREG_TLBIMVAHIS: 1205 assert32(tc); 1206 target_el = 1; // aarch32, use hyp bit 1207 scr = readMiscReg(MISCREG_SCR, tc); 1208 secure_lookup = haveSecurity && !scr.ns; 1209 hyp = 1; 1210 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el); 1211 return; 1212 // TLBI by address and asid, EL0&1, instruction side only 1213 case MISCREG_ITLBIMVA: 1214 assert32(tc); 1215 target_el = 1; // el 0 and 1 are handled together 1216 scr = readMiscReg(MISCREG_SCR, tc); 1217 secure_lookup = haveSecurity && !scr.ns; 1218 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1219 bits(newVal, 7,0), secure_lookup, target_el); 1220 return; 1221 // TLBI by address and asid, EL0&1, data side only 1222 case MISCREG_DTLBIMVA: 1223 assert32(tc); 1224 target_el = 1; // el 0 and 1 are handled together 1225 scr = readMiscReg(MISCREG_SCR, tc); 1226 secure_lookup = haveSecurity && !scr.ns; 1227 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1228 bits(newVal, 7,0), secure_lookup, target_el); 1229 return; 1230 // TLBI by ASID, EL0&1, instrution side only 1231 case MISCREG_ITLBIASID: 1232 assert32(tc); 1233 target_el = 1; // el 0 and 1 are handled together 1234 scr = readMiscReg(MISCREG_SCR, tc); 1235 secure_lookup = haveSecurity && !scr.ns; 1236 tc->getITBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup, 1237 target_el); 1238 return; 1239 // TLBI by ASID EL0&1 data size only 1240 case MISCREG_DTLBIASID: 1241 assert32(tc); 1242 target_el = 1; // el 0 and 1 are handled together 1243 scr = readMiscReg(MISCREG_SCR, tc); 1244 secure_lookup = haveSecurity && !scr.ns; 1245 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup, 1246 target_el); 1247 return; 1248 // Invalidate entire Non-secure Hyp/Non-Hyp Unified TLB 1249 case MISCREG_TLBIALLNSNH: 1250 case MISCREG_TLBIALLNSNHIS: 1251 assert32(tc); 1252 target_el = 1; // el 0 and 1 are handled together 1253 hyp = 0; 1254 tlbiALLN(tc, hyp, target_el); 1255 return; 1256 // TLBI all entries, EL2, hyp, 1257 case MISCREG_TLBIALLH: 1258 case MISCREG_TLBIALLHIS: 1259 assert32(tc); 1260 target_el = 1; // aarch32, use hyp bit 1261 hyp = 1; 1262 tlbiALLN(tc, hyp, target_el); 1263 return; 1264 // AArch64 TLBI: invalidate all entries EL3 1265 case MISCREG_TLBI_ALLE3IS: 1266 case MISCREG_TLBI_ALLE3: 1267 assert64(tc); 1268 target_el = 3; 1269 secure_lookup = true; 1270 tlbiALL(tc, secure_lookup, target_el); 1271 return; 1272 // @todo: uncomment this to enable Virtualization 1273 // case MISCREG_TLBI_ALLE2IS: 1274 // case MISCREG_TLBI_ALLE2: 1275 // TLBI all entries, EL0&1 1276 case MISCREG_TLBI_ALLE1IS: 1277 case MISCREG_TLBI_ALLE1: 1278 // AArch64 TLBI: invalidate all entries, stage 1, current VMID 1279 case MISCREG_TLBI_VMALLE1IS: 1280 case MISCREG_TLBI_VMALLE1: 1281 // AArch64 TLBI: invalidate all entries, stages 1 & 2, current VMID 1282 case MISCREG_TLBI_VMALLS12E1IS: 1283 case MISCREG_TLBI_VMALLS12E1: 1284 // @todo: handle VMID and stage 2 to enable Virtualization 1285 assert64(tc); 1286 target_el = 1; // el 0 and 1 are handled together 1287 scr = readMiscReg(MISCREG_SCR, tc); 1288 secure_lookup = haveSecurity && !scr.ns; 1289 tlbiALL(tc, secure_lookup, target_el); 1290 return; 1291 // AArch64 TLBI: invalidate by VA and ASID, stage 1, current VMID 1292 // VAEx(IS) and VALEx(IS) are the same because TLBs only store entries 1293 // from the last level of translation table walks 1294 // @todo: handle VMID to enable Virtualization 1295 // TLBI all entries, EL0&1 1296 case MISCREG_TLBI_VAE3IS_Xt: 1297 case MISCREG_TLBI_VAE3_Xt: 1298 // TLBI by VA, EL3 regime stage 1, last level walk 1299 case MISCREG_TLBI_VALE3IS_Xt: 1300 case MISCREG_TLBI_VALE3_Xt: 1301 assert64(tc); 1302 target_el = 3; 1303 asid = 0xbeef; // does not matter, tlbi is global 1304 secure_lookup = true; 1305 tlbiVA(tc, newVal, asid, secure_lookup, target_el); 1306 return; 1307 // TLBI by VA, EL2 1308 case MISCREG_TLBI_VAE2IS_Xt: 1309 case MISCREG_TLBI_VAE2_Xt: 1310 // TLBI by VA, EL2, stage1 last level walk 1311 case MISCREG_TLBI_VALE2IS_Xt: 1312 case MISCREG_TLBI_VALE2_Xt: 1313 assert64(tc); 1314 target_el = 2; 1315 asid = 0xbeef; // does not matter, tlbi is global 1316 scr = readMiscReg(MISCREG_SCR, tc); 1317 secure_lookup = haveSecurity && !scr.ns; 1318 tlbiVA(tc, newVal, asid, secure_lookup, target_el); 1319 return; 1320 // TLBI by VA EL1 & 0, stage1, ASID, current VMID 1321 case MISCREG_TLBI_VAE1IS_Xt: 1322 case MISCREG_TLBI_VAE1_Xt: 1323 case MISCREG_TLBI_VALE1IS_Xt: 1324 case MISCREG_TLBI_VALE1_Xt: 1325 assert64(tc); 1326 asid = bits(newVal, 63, 48); 1327 target_el = 1; // el 0 and 1 are handled together 1328 scr = readMiscReg(MISCREG_SCR, tc); 1329 secure_lookup = haveSecurity && !scr.ns; 1330 tlbiVA(tc, newVal, asid, secure_lookup, target_el); 1331 return; 1332 // AArch64 TLBI: invalidate by ASID, stage 1, current VMID 1333 // @todo: handle VMID to enable Virtualization 1334 case MISCREG_TLBI_ASIDE1IS_Xt: 1335 case MISCREG_TLBI_ASIDE1_Xt: 1336 assert64(tc); 1337 target_el = 1; // el 0 and 1 are handled together 1338 scr = readMiscReg(MISCREG_SCR, tc); 1339 secure_lookup = haveSecurity && !scr.ns; 1340 sys = tc->getSystemPtr(); 1341 for (x = 0; x < sys->numContexts(); x++) { 1342 oc = sys->getThreadContext(x); 1343 assert(oc->getITBPtr() && oc->getDTBPtr()); 1344 asid = bits(newVal, 63, 48); 1345 if (!haveLargeAsid64) 1346 asid &= mask(8); 1347 oc->getITBPtr()->flushAsid(asid, secure_lookup, target_el); 1348 oc->getDTBPtr()->flushAsid(asid, secure_lookup, target_el); 1349 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1350 if (checker) { 1351 checker->getITBPtr()->flushAsid(asid, 1352 secure_lookup, target_el); 1353 checker->getDTBPtr()->flushAsid(asid, 1354 secure_lookup, target_el); 1355 } 1356 } 1357 return; 1358 // AArch64 TLBI: invalidate by VA, ASID, stage 1, current VMID 1359 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 1360 // entries from the last level of translation table walks 1361 // @todo: handle VMID to enable Virtualization 1362 case MISCREG_TLBI_VAAE1IS_Xt: 1363 case MISCREG_TLBI_VAAE1_Xt: 1364 case MISCREG_TLBI_VAALE1IS_Xt: 1365 case MISCREG_TLBI_VAALE1_Xt: 1366 assert64(tc); 1367 target_el = 1; // el 0 and 1 are handled together 1368 scr = readMiscReg(MISCREG_SCR, tc); 1369 secure_lookup = haveSecurity && !scr.ns; 1370 sys = tc->getSystemPtr(); 1371 for (x = 0; x < sys->numContexts(); x++) { 1372 // @todo: extra controls on TLBI broadcast? 1373 oc = sys->getThreadContext(x); 1374 assert(oc->getITBPtr() && oc->getDTBPtr()); 1375 Addr va = ((Addr) bits(newVal, 43, 0)) << 12; 1376 oc->getITBPtr()->flushMva(va, 1377 secure_lookup, false, target_el); 1378 oc->getDTBPtr()->flushMva(va, 1379 secure_lookup, false, target_el); 1380 1381 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1382 if (checker) { 1383 checker->getITBPtr()->flushMva(va, 1384 secure_lookup, false, target_el); 1385 checker->getDTBPtr()->flushMva(va, 1386 secure_lookup, false, target_el); 1387 } 1388 } 1389 return; 1390 // AArch64 TLBI: invalidate by IPA, stage 2, current VMID 1391 case MISCREG_TLBI_IPAS2LE1IS_Xt: 1392 case MISCREG_TLBI_IPAS2LE1_Xt: 1393 case MISCREG_TLBI_IPAS2E1IS_Xt: 1394 case MISCREG_TLBI_IPAS2E1_Xt: 1395 assert64(tc); 1396 // @todo: implement these as part of Virtualization 1397 warn("Not doing anything for write of miscreg ITLB_IPAS2\n"); 1398 return; 1399 case MISCREG_ACTLR: 1400 warn("Not doing anything for write of miscreg ACTLR\n"); 1401 break; 1402 1403 case MISCREG_PMXEVTYPER_PMCCFILTR: 1404 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 1405 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 1406 case MISCREG_PMCR ... MISCREG_PMOVSSET: 1407 pmu->setMiscReg(misc_reg, newVal); 1408 break; 1409 1410 1411 case MISCREG_HSTR: // TJDBX, now redifined to be RES0 1412 { 1413 HSTR hstrMask = 0; 1414 hstrMask.tjdbx = 1; 1415 newVal &= ~((uint32_t) hstrMask); 1416 break; 1417 } 1418 case MISCREG_HCPTR: 1419 { 1420 // If a CP bit in NSACR is 0 then the corresponding bit in 1421 // HCPTR is RAO/WI. Same applies to NSASEDIS 1422 secure_lookup = haveSecurity && 1423 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 1424 readMiscRegNoEffect(MISCREG_CPSR)); 1425 if (!secure_lookup) { 1426 MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 1427 MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 1428 newVal = (newVal & ~mask) | (oldValue & mask); 1429 } 1430 break; 1431 } 1432 case MISCREG_HDFAR: // alias for secure DFAR 1433 misc_reg = MISCREG_DFAR_S; 1434 break; 1435 case MISCREG_HIFAR: // alias for secure IFAR 1436 misc_reg = MISCREG_IFAR_S; 1437 break; 1438 case MISCREG_ATS1CPR: 1439 case MISCREG_ATS1CPW: 1440 case MISCREG_ATS1CUR: 1441 case MISCREG_ATS1CUW: 1442 case MISCREG_ATS12NSOPR: 1443 case MISCREG_ATS12NSOPW: 1444 case MISCREG_ATS12NSOUR: 1445 case MISCREG_ATS12NSOUW: 1446 case MISCREG_ATS1HR: 1447 case MISCREG_ATS1HW: 1448 { 1449 unsigned flags = 0; 1450 BaseTLB::Mode mode = BaseTLB::Read; 1451 TLB::ArmTranslationType tranType = TLB::NormalTran; 1452 Fault fault; 1453 switch(misc_reg) { 1454 case MISCREG_ATS1CPR: 1455 flags = TLB::MustBeOne; 1456 tranType = TLB::S1CTran; 1457 mode = BaseTLB::Read; 1458 break; 1459 case MISCREG_ATS1CPW: 1460 flags = TLB::MustBeOne; 1461 tranType = TLB::S1CTran; 1462 mode = BaseTLB::Write; 1463 break; 1464 case MISCREG_ATS1CUR: 1465 flags = TLB::MustBeOne | TLB::UserMode; 1466 tranType = TLB::S1CTran; 1467 mode = BaseTLB::Read; 1468 break; 1469 case MISCREG_ATS1CUW: 1470 flags = TLB::MustBeOne | TLB::UserMode; 1471 tranType = TLB::S1CTran; 1472 mode = BaseTLB::Write; 1473 break; 1474 case MISCREG_ATS12NSOPR: 1475 if (!haveSecurity) 1476 panic("Security Extensions required for ATS12NSOPR"); 1477 flags = TLB::MustBeOne; 1478 tranType = TLB::S1S2NsTran; 1479 mode = BaseTLB::Read; 1480 break; 1481 case MISCREG_ATS12NSOPW: 1482 if (!haveSecurity) 1483 panic("Security Extensions required for ATS12NSOPW"); 1484 flags = TLB::MustBeOne; 1485 tranType = TLB::S1S2NsTran; 1486 mode = BaseTLB::Write; 1487 break; 1488 case MISCREG_ATS12NSOUR: 1489 if (!haveSecurity) 1490 panic("Security Extensions required for ATS12NSOUR"); 1491 flags = TLB::MustBeOne | TLB::UserMode; 1492 tranType = TLB::S1S2NsTran; 1493 mode = BaseTLB::Read; 1494 break; 1495 case MISCREG_ATS12NSOUW: 1496 if (!haveSecurity) 1497 panic("Security Extensions required for ATS12NSOUW"); 1498 flags = TLB::MustBeOne | TLB::UserMode; 1499 tranType = TLB::S1S2NsTran; 1500 mode = BaseTLB::Write; 1501 break; 1502 case MISCREG_ATS1HR: // only really useful from secure mode. 1503 flags = TLB::MustBeOne; 1504 tranType = TLB::HypMode; 1505 mode = BaseTLB::Read; 1506 break; 1507 case MISCREG_ATS1HW: 1508 flags = TLB::MustBeOne; 1509 tranType = TLB::HypMode; 1510 mode = BaseTLB::Write; 1511 break; 1512 } 1513 // If we're in timing mode then doing the translation in 1514 // functional mode then we're slightly distorting performance 1515 // results obtained from simulations. The translation should be 1516 // done in the same mode the core is running in. NOTE: This 1517 // can't be an atomic translation because that causes problems 1518 // with unexpected atomic snoop requests. 1519 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1520 Request req(0, val, 0, flags, Request::funcMasterId, 1521 tc->pcState().pc(), tc->contextId()); 1522 fault = tc->getDTBPtr()->translateFunctional(&req, tc, mode, tranType); 1523 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1524 HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 1525 1526 MiscReg newVal; 1527 if (fault == NoFault) { 1528 Addr paddr = req.getPaddr(); 1529 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 1530 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 1531 newVal = (paddr & mask(39, 12)) | 1532 (tc->getDTBPtr()->getAttr()); 1533 } else { 1534 newVal = (paddr & 0xfffff000) | 1535 (tc->getDTBPtr()->getAttr()); 1536 } 1537 DPRINTF(MiscRegs, 1538 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 1539 val, newVal); 1540 } else { 1541 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 1542 // Set fault bit and FSR 1543 FSR fsr = armFault->getFsr(tc); 1544 1545 newVal = ((fsr >> 9) & 1) << 11; 1546 if (newVal) { 1547 // LPAE - rearange fault status 1548 newVal |= ((fsr >> 0) & 0x3f) << 1; 1549 } else { 1550 // VMSA - rearange fault status 1551 newVal |= ((fsr >> 0) & 0xf) << 1; 1552 newVal |= ((fsr >> 10) & 0x1) << 5; 1553 newVal |= ((fsr >> 12) & 0x1) << 6; 1554 } 1555 newVal |= 0x1; // F bit 1556 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1557 newVal |= armFault->isStage2() ? 0x200 : 0; 1558 DPRINTF(MiscRegs, 1559 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 1560 val, fsr, newVal); 1561 } 1562 setMiscRegNoEffect(MISCREG_PAR, newVal); 1563 return; 1564 } 1565 case MISCREG_TTBCR: 1566 { 1567 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1568 const uint32_t ones = (uint32_t)(-1); 1569 TTBCR ttbcrMask = 0; 1570 TTBCR ttbcrNew = newVal; 1571 1572 // ARM DDI 0406C.b, ARMv7-32 1573 ttbcrMask.n = ones; // T0SZ 1574 if (haveSecurity) { 1575 ttbcrMask.pd0 = ones; 1576 ttbcrMask.pd1 = ones; 1577 } 1578 ttbcrMask.epd0 = ones; 1579 ttbcrMask.irgn0 = ones; 1580 ttbcrMask.orgn0 = ones; 1581 ttbcrMask.sh0 = ones; 1582 ttbcrMask.ps = ones; // T1SZ 1583 ttbcrMask.a1 = ones; 1584 ttbcrMask.epd1 = ones; 1585 ttbcrMask.irgn1 = ones; 1586 ttbcrMask.orgn1 = ones; 1587 ttbcrMask.sh1 = ones; 1588 if (haveLPAE) 1589 ttbcrMask.eae = ones; 1590 1591 if (haveLPAE && ttbcrNew.eae) { 1592 newVal = newVal & ttbcrMask; 1593 } else { 1594 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 1595 } 1596 } 1597 case MISCREG_TTBR0: 1598 case MISCREG_TTBR1: 1599 { 1600 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1601 if (haveLPAE) { 1602 if (ttbcr.eae) { 1603 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 1604 // ARMv8 AArch32 bit 63-56 only 1605 uint64_t ttbrMask = mask(63,56) | mask(47,40); 1606 newVal = (newVal & (~ttbrMask)); 1607 } 1608 } 1609 } 1610 case MISCREG_SCTLR_EL1: 1611 { 1612 tc->getITBPtr()->invalidateMiscReg(); 1613 tc->getDTBPtr()->invalidateMiscReg(); 1614 setMiscRegNoEffect(misc_reg, newVal); 1615 } 1616 case MISCREG_CONTEXTIDR: 1617 case MISCREG_PRRR: 1618 case MISCREG_NMRR: 1619 case MISCREG_MAIR0: 1620 case MISCREG_MAIR1: 1621 case MISCREG_DACR: 1622 case MISCREG_VTTBR: 1623 case MISCREG_SCR_EL3: 1624 case MISCREG_TCR_EL1: 1625 case MISCREG_TCR_EL2: 1626 case MISCREG_TCR_EL3: 1627 case MISCREG_SCTLR_EL2: 1628 case MISCREG_SCTLR_EL3: 1629 case MISCREG_HSCTLR: 1630 case MISCREG_TTBR0_EL1: 1631 case MISCREG_TTBR1_EL1: 1632 case MISCREG_TTBR0_EL2: 1633 case MISCREG_TTBR0_EL3: 1634 tc->getITBPtr()->invalidateMiscReg(); 1635 tc->getDTBPtr()->invalidateMiscReg(); 1636 break; 1637 case MISCREG_NZCV: 1638 { 1639 CPSR cpsr = val; 1640 1641 tc->setCCReg(CCREG_NZ, cpsr.nz); 1642 tc->setCCReg(CCREG_C, cpsr.c); 1643 tc->setCCReg(CCREG_V, cpsr.v); 1644 } 1645 break; 1646 case MISCREG_DAIF: 1647 { 1648 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1649 cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 1650 newVal = cpsr; 1651 misc_reg = MISCREG_CPSR; 1652 } 1653 break; 1654 case MISCREG_SP_EL0: 1655 tc->setIntReg(INTREG_SP0, newVal); 1656 break; 1657 case MISCREG_SP_EL1: 1658 tc->setIntReg(INTREG_SP1, newVal); 1659 break; 1660 case MISCREG_SP_EL2: 1661 tc->setIntReg(INTREG_SP2, newVal); 1662 break; 1663 case MISCREG_SPSEL: 1664 { 1665 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1666 cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 1667 newVal = cpsr; 1668 misc_reg = MISCREG_CPSR; 1669 } 1670 break; 1671 case MISCREG_CURRENTEL: 1672 { 1673 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1674 cpsr.el = (uint8_t) ((CPSR) newVal).el; 1675 newVal = cpsr; 1676 misc_reg = MISCREG_CPSR; 1677 } 1678 break; 1679 case MISCREG_AT_S1E1R_Xt: 1680 case MISCREG_AT_S1E1W_Xt: 1681 case MISCREG_AT_S1E0R_Xt: 1682 case MISCREG_AT_S1E0W_Xt: 1683 case MISCREG_AT_S1E2R_Xt: 1684 case MISCREG_AT_S1E2W_Xt: 1685 case MISCREG_AT_S12E1R_Xt: 1686 case MISCREG_AT_S12E1W_Xt: 1687 case MISCREG_AT_S12E0R_Xt: 1688 case MISCREG_AT_S12E0W_Xt: 1689 case MISCREG_AT_S1E3R_Xt: 1690 case MISCREG_AT_S1E3W_Xt: 1691 { 1692 RequestPtr req = new Request; 1693 unsigned flags = 0; 1694 BaseTLB::Mode mode = BaseTLB::Read; 1695 TLB::ArmTranslationType tranType = TLB::NormalTran; 1696 Fault fault; 1697 switch(misc_reg) { 1698 case MISCREG_AT_S1E1R_Xt: 1699 flags = TLB::MustBeOne; 1700 tranType = TLB::S1CTran; 1701 mode = BaseTLB::Read; 1702 break; 1703 case MISCREG_AT_S1E1W_Xt: 1704 flags = TLB::MustBeOne; 1705 tranType = TLB::S1CTran; 1706 mode = BaseTLB::Write; 1707 break; 1708 case MISCREG_AT_S1E0R_Xt: 1709 flags = TLB::MustBeOne | TLB::UserMode; 1710 tranType = TLB::S1CTran; 1711 mode = BaseTLB::Read; 1712 break; 1713 case MISCREG_AT_S1E0W_Xt: 1714 flags = TLB::MustBeOne | TLB::UserMode; 1715 tranType = TLB::S1CTran; 1716 mode = BaseTLB::Write; 1717 break; 1718 case MISCREG_AT_S1E2R_Xt: 1719 flags = TLB::MustBeOne; 1720 tranType = TLB::HypMode; 1721 mode = BaseTLB::Read; 1722 break; 1723 case MISCREG_AT_S1E2W_Xt: 1724 flags = TLB::MustBeOne; 1725 tranType = TLB::HypMode; 1726 mode = BaseTLB::Write; 1727 break; 1728 case MISCREG_AT_S12E0R_Xt: 1729 flags = TLB::MustBeOne | TLB::UserMode; 1730 tranType = TLB::S1S2NsTran; 1731 mode = BaseTLB::Read; 1732 break; 1733 case MISCREG_AT_S12E0W_Xt: 1734 flags = TLB::MustBeOne | TLB::UserMode; 1735 tranType = TLB::S1S2NsTran; 1736 mode = BaseTLB::Write; 1737 break; 1738 case MISCREG_AT_S12E1R_Xt: 1739 flags = TLB::MustBeOne; 1740 tranType = TLB::S1S2NsTran; 1741 mode = BaseTLB::Read; 1742 break; 1743 case MISCREG_AT_S12E1W_Xt: 1744 flags = TLB::MustBeOne; 1745 tranType = TLB::S1S2NsTran; 1746 mode = BaseTLB::Write; 1747 break; 1748 case MISCREG_AT_S1E3R_Xt: 1749 flags = TLB::MustBeOne; 1750 tranType = TLB::HypMode; // There is no TZ mode defined. 1751 mode = BaseTLB::Read; 1752 break; 1753 case MISCREG_AT_S1E3W_Xt: 1754 flags = TLB::MustBeOne; 1755 tranType = TLB::HypMode; // There is no TZ mode defined. 1756 mode = BaseTLB::Write; 1757 break; 1758 } 1759 // If we're in timing mode then doing the translation in 1760 // functional mode then we're slightly distorting performance 1761 // results obtained from simulations. The translation should be 1762 // done in the same mode the core is running in. NOTE: This 1763 // can't be an atomic translation because that causes problems 1764 // with unexpected atomic snoop requests. 1765 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1766 req->setVirt(0, val, 0, flags, Request::funcMasterId, 1767 tc->pcState().pc()); 1768 req->setContext(tc->contextId()); 1769 fault = tc->getDTBPtr()->translateFunctional(req, tc, mode, 1770 tranType); 1771 1772 MiscReg newVal; 1773 if (fault == NoFault) { 1774 Addr paddr = req->getPaddr(); 1775 uint64_t attr = tc->getDTBPtr()->getAttr(); 1776 uint64_t attr1 = attr >> 56; 1777 if (!attr1 || attr1 ==0x44) { 1778 attr |= 0x100; 1779 attr &= ~ uint64_t(0x80); 1780 } 1781 newVal = (paddr & mask(47, 12)) | attr; 1782 DPRINTF(MiscRegs, 1783 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 1784 val, newVal); 1785 } else { 1786 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 1787 // Set fault bit and FSR 1788 FSR fsr = armFault->getFsr(tc); 1789 1790 newVal = ((fsr >> 9) & 1) << 11; 1791 // rearange fault status 1792 newVal |= ((fsr >> 0) & 0x3f) << 1; 1793 newVal |= 0x1; // F bit 1794 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1795 newVal |= armFault->isStage2() ? 0x200 : 0; 1796 DPRINTF(MiscRegs, 1797 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 1798 val, fsr, newVal); 1799 } 1800 delete req; 1801 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 1802 return; 1803 } 1804 case MISCREG_SPSR_EL3: 1805 case MISCREG_SPSR_EL2: 1806 case MISCREG_SPSR_EL1: 1807 // Force bits 23:21 to 0 1808 newVal = val & ~(0x7 << 21); 1809 break; 1810 case MISCREG_L2CTLR: 1811 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 1812 miscRegName[misc_reg], uint32_t(val)); 1813 break; 1814 1815 // Generic Timer registers 1816 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 1817 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 1818 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 1819 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 1820 getGenericTimer(tc).setMiscReg(misc_reg, newVal); 1821 break; 1822 } 1823 } 1824 setMiscRegNoEffect(misc_reg, newVal); 1825} 1826 1827void 1828ISA::tlbiVA(ThreadContext *tc, MiscReg newVal, uint16_t asid, 1829 bool secure_lookup, uint8_t target_el) 1830{ 1831 if (!haveLargeAsid64) 1832 asid &= mask(8); 1833 Addr va = ((Addr) bits(newVal, 43, 0)) << 12; 1834 System *sys = tc->getSystemPtr(); 1835 for (int x = 0; x < sys->numContexts(); x++) { 1836 ThreadContext *oc = sys->getThreadContext(x); 1837 assert(oc->getITBPtr() && oc->getDTBPtr()); 1838 oc->getITBPtr()->flushMvaAsid(va, asid, 1839 secure_lookup, target_el); 1840 oc->getDTBPtr()->flushMvaAsid(va, asid, 1841 secure_lookup, target_el); 1842 1843 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1844 if (checker) { 1845 checker->getITBPtr()->flushMvaAsid( 1846 va, asid, secure_lookup, target_el); 1847 checker->getDTBPtr()->flushMvaAsid( 1848 va, asid, secure_lookup, target_el); 1849 } 1850 } 1851} 1852 1853void 1854ISA::tlbiALL(ThreadContext *tc, bool secure_lookup, uint8_t target_el) 1855{ 1856 System *sys = tc->getSystemPtr(); 1857 for (int x = 0; x < sys->numContexts(); x++) { 1858 ThreadContext *oc = sys->getThreadContext(x); 1859 assert(oc->getITBPtr() && oc->getDTBPtr()); 1860 oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 1861 oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 1862 1863 // If CheckerCPU is connected, need to notify it of a flush 1864 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1865 if (checker) { 1866 checker->getITBPtr()->flushAllSecurity(secure_lookup, 1867 target_el); 1868 checker->getDTBPtr()->flushAllSecurity(secure_lookup, 1869 target_el); 1870 } 1871 } 1872} 1873 1874void 1875ISA::tlbiALLN(ThreadContext *tc, bool hyp, uint8_t target_el) 1876{ 1877 System *sys = tc->getSystemPtr(); 1878 for (int x = 0; x < sys->numContexts(); x++) { 1879 ThreadContext *oc = sys->getThreadContext(x); 1880 assert(oc->getITBPtr() && oc->getDTBPtr()); 1881 oc->getITBPtr()->flushAllNs(hyp, target_el); 1882 oc->getDTBPtr()->flushAllNs(hyp, target_el); 1883 1884 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1885 if (checker) { 1886 checker->getITBPtr()->flushAllNs(hyp, target_el); 1887 checker->getDTBPtr()->flushAllNs(hyp, target_el); 1888 } 1889 } 1890} 1891 1892void 1893ISA::tlbiMVA(ThreadContext *tc, MiscReg newVal, bool secure_lookup, bool hyp, 1894 uint8_t target_el) 1895{ 1896 System *sys = tc->getSystemPtr(); 1897 for (int x = 0; x < sys->numContexts(); x++) { 1898 ThreadContext *oc = sys->getThreadContext(x); 1899 assert(oc->getITBPtr() && oc->getDTBPtr()); 1900 oc->getITBPtr()->flushMva(mbits(newVal, 31,12), 1901 secure_lookup, hyp, target_el); 1902 oc->getDTBPtr()->flushMva(mbits(newVal, 31,12), 1903 secure_lookup, hyp, target_el); 1904 1905 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1906 if (checker) { 1907 checker->getITBPtr()->flushMva(mbits(newVal, 31,12), 1908 secure_lookup, hyp, target_el); 1909 checker->getDTBPtr()->flushMva(mbits(newVal, 31,12), 1910 secure_lookup, hyp, target_el); 1911 } 1912 } 1913} 1914 1915BaseISADevice & 1916ISA::getGenericTimer(ThreadContext *tc) 1917{ 1918 // We only need to create an ISA interface the first time we try 1919 // to access the timer. 1920 if (timer) 1921 return *timer.get(); 1922 1923 assert(system); 1924 GenericTimer *generic_timer(system->getGenericTimer()); 1925 if (!generic_timer) { 1926 panic("Trying to get a generic timer from a system that hasn't " 1927 "been configured to use a generic timer.\n"); 1928 } 1929 1930 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 1931 return *timer.get(); 1932} 1933 1934} 1935 1936ArmISA::ISA * 1937ArmISAParams::create() 1938{ 1939 return new ArmISA::ISA(this); 1940} 1941