isa.cc revision 11428:20264eb69fbf
1/* 2 * Copyright (c) 2010-2015 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 */ 40 41#include "arch/arm/isa.hh" 42#include "arch/arm/pmu.hh" 43#include "arch/arm/system.hh" 44#include "cpu/checker/cpu.hh" 45#include "cpu/base.hh" 46#include "debug/Arm.hh" 47#include "debug/MiscRegs.hh" 48#include "dev/arm/generic_timer.hh" 49#include "params/ArmISA.hh" 50#include "sim/faults.hh" 51#include "sim/stat_control.hh" 52#include "sim/system.hh" 53 54namespace ArmISA 55{ 56 57 58/** 59 * Some registers aliase with others, and therefore need to be translated. 60 * For each entry: 61 * The first value is the misc register that is to be looked up 62 * the second value is the lower part of the translation 63 * the third the upper part 64 */ 65const struct ISA::MiscRegInitializerEntry 66 ISA::MiscRegSwitch[miscRegTranslateMax] = { 67 {MISCREG_CSSELR_EL1, {MISCREG_CSSELR, 0}}, 68 {MISCREG_SCTLR_EL1, {MISCREG_SCTLR, 0}}, 69 {MISCREG_SCTLR_EL2, {MISCREG_HSCTLR, 0}}, 70 {MISCREG_ACTLR_EL1, {MISCREG_ACTLR, 0}}, 71 {MISCREG_ACTLR_EL2, {MISCREG_HACTLR, 0}}, 72 {MISCREG_CPACR_EL1, {MISCREG_CPACR, 0}}, 73 {MISCREG_CPTR_EL2, {MISCREG_HCPTR, 0}}, 74 {MISCREG_HCR_EL2, {MISCREG_HCR, 0}}, 75 {MISCREG_MDCR_EL2, {MISCREG_HDCR, 0}}, 76 {MISCREG_HSTR_EL2, {MISCREG_HSTR, 0}}, 77 {MISCREG_HACR_EL2, {MISCREG_HACR, 0}}, 78 {MISCREG_TTBR0_EL1, {MISCREG_TTBR0, 0}}, 79 {MISCREG_TTBR1_EL1, {MISCREG_TTBR1, 0}}, 80 {MISCREG_TTBR0_EL2, {MISCREG_HTTBR, 0}}, 81 {MISCREG_VTTBR_EL2, {MISCREG_VTTBR, 0}}, 82 {MISCREG_TCR_EL1, {MISCREG_TTBCR, 0}}, 83 {MISCREG_TCR_EL2, {MISCREG_HTCR, 0}}, 84 {MISCREG_VTCR_EL2, {MISCREG_VTCR, 0}}, 85 {MISCREG_AFSR0_EL1, {MISCREG_ADFSR, 0}}, 86 {MISCREG_AFSR1_EL1, {MISCREG_AIFSR, 0}}, 87 {MISCREG_AFSR0_EL2, {MISCREG_HADFSR, 0}}, 88 {MISCREG_AFSR1_EL2, {MISCREG_HAIFSR, 0}}, 89 {MISCREG_ESR_EL2, {MISCREG_HSR, 0}}, 90 {MISCREG_FAR_EL1, {MISCREG_DFAR, MISCREG_IFAR}}, 91 {MISCREG_FAR_EL2, {MISCREG_HDFAR, MISCREG_HIFAR}}, 92 {MISCREG_HPFAR_EL2, {MISCREG_HPFAR, 0}}, 93 {MISCREG_PAR_EL1, {MISCREG_PAR, 0}}, 94 {MISCREG_MAIR_EL1, {MISCREG_PRRR, MISCREG_NMRR}}, 95 {MISCREG_MAIR_EL2, {MISCREG_HMAIR0, MISCREG_HMAIR1}}, 96 {MISCREG_AMAIR_EL1, {MISCREG_AMAIR0, MISCREG_AMAIR1}}, 97 {MISCREG_VBAR_EL1, {MISCREG_VBAR, 0}}, 98 {MISCREG_VBAR_EL2, {MISCREG_HVBAR, 0}}, 99 {MISCREG_CONTEXTIDR_EL1, {MISCREG_CONTEXTIDR, 0}}, 100 {MISCREG_TPIDR_EL0, {MISCREG_TPIDRURW, 0}}, 101 {MISCREG_TPIDRRO_EL0, {MISCREG_TPIDRURO, 0}}, 102 {MISCREG_TPIDR_EL1, {MISCREG_TPIDRPRW, 0}}, 103 {MISCREG_TPIDR_EL2, {MISCREG_HTPIDR, 0}}, 104 {MISCREG_TEECR32_EL1, {MISCREG_TEECR, 0}}, 105 {MISCREG_CNTFRQ_EL0, {MISCREG_CNTFRQ, 0}}, 106 {MISCREG_CNTPCT_EL0, {MISCREG_CNTPCT, 0}}, 107 {MISCREG_CNTVCT_EL0, {MISCREG_CNTVCT, 0}}, 108 {MISCREG_CNTVOFF_EL2, {MISCREG_CNTVOFF, 0}}, 109 {MISCREG_CNTKCTL_EL1, {MISCREG_CNTKCTL, 0}}, 110 {MISCREG_CNTHCTL_EL2, {MISCREG_CNTHCTL, 0}}, 111 {MISCREG_CNTP_TVAL_EL0, {MISCREG_CNTP_TVAL, 0}}, 112 {MISCREG_CNTP_CTL_EL0, {MISCREG_CNTP_CTL, 0}}, 113 {MISCREG_CNTP_CVAL_EL0, {MISCREG_CNTP_CVAL, 0}}, 114 {MISCREG_CNTV_TVAL_EL0, {MISCREG_CNTV_TVAL, 0}}, 115 {MISCREG_CNTV_CTL_EL0, {MISCREG_CNTV_CTL, 0}}, 116 {MISCREG_CNTV_CVAL_EL0, {MISCREG_CNTV_CVAL, 0}}, 117 {MISCREG_CNTHP_TVAL_EL2, {MISCREG_CNTHP_TVAL, 0}}, 118 {MISCREG_CNTHP_CTL_EL2, {MISCREG_CNTHP_CTL, 0}}, 119 {MISCREG_CNTHP_CVAL_EL2, {MISCREG_CNTHP_CVAL, 0}}, 120 {MISCREG_DACR32_EL2, {MISCREG_DACR, 0}}, 121 {MISCREG_IFSR32_EL2, {MISCREG_IFSR, 0}}, 122 {MISCREG_TEEHBR32_EL1, {MISCREG_TEEHBR, 0}}, 123 {MISCREG_SDER32_EL3, {MISCREG_SDER, 0}} 124}; 125 126 127ISA::ISA(Params *p) 128 : SimObject(p), 129 system(NULL), 130 _decoderFlavour(p->decoderFlavour), 131 pmu(p->pmu), 132 lookUpMiscReg(NUM_MISCREGS, {0,0}) 133{ 134 SCTLR sctlr; 135 sctlr = 0; 136 miscRegs[MISCREG_SCTLR_RST] = sctlr; 137 138 // Hook up a dummy device if we haven't been configured with a 139 // real PMU. By using a dummy device, we don't need to check that 140 // the PMU exist every time we try to access a PMU register. 141 if (!pmu) 142 pmu = &dummyDevice; 143 144 // Give all ISA devices a pointer to this ISA 145 pmu->setISA(this); 146 147 system = dynamic_cast<ArmSystem *>(p->system); 148 149 // Cache system-level properties 150 if (FullSystem && system) { 151 haveSecurity = system->haveSecurity(); 152 haveLPAE = system->haveLPAE(); 153 haveVirtualization = system->haveVirtualization(); 154 haveLargeAsid64 = system->haveLargeAsid64(); 155 physAddrRange64 = system->physAddrRange64(); 156 } else { 157 haveSecurity = haveLPAE = haveVirtualization = false; 158 haveLargeAsid64 = false; 159 physAddrRange64 = 32; // dummy value 160 } 161 162 /** Fill in the miscReg translation table */ 163 for (uint32_t i = 0; i < miscRegTranslateMax; i++) { 164 struct MiscRegLUTEntry new_entry; 165 166 uint32_t select = MiscRegSwitch[i].index; 167 new_entry = MiscRegSwitch[i].entry; 168 169 lookUpMiscReg[select] = new_entry; 170 } 171 172 preUnflattenMiscReg(); 173 174 clear(); 175} 176 177const ArmISAParams * 178ISA::params() const 179{ 180 return dynamic_cast<const Params *>(_params); 181} 182 183void 184ISA::clear() 185{ 186 const Params *p(params()); 187 188 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 189 memset(miscRegs, 0, sizeof(miscRegs)); 190 191 // Initialize configurable default values 192 miscRegs[MISCREG_MIDR] = p->midr; 193 miscRegs[MISCREG_MIDR_EL1] = p->midr; 194 miscRegs[MISCREG_VPIDR] = p->midr; 195 196 if (FullSystem && system->highestELIs64()) { 197 // Initialize AArch64 state 198 clear64(p); 199 return; 200 } 201 202 // Initialize AArch32 state... 203 204 CPSR cpsr = 0; 205 cpsr.mode = MODE_USER; 206 miscRegs[MISCREG_CPSR] = cpsr; 207 updateRegMap(cpsr); 208 209 SCTLR sctlr = 0; 210 sctlr.te = (bool) sctlr_rst.te; 211 sctlr.nmfi = (bool) sctlr_rst.nmfi; 212 sctlr.v = (bool) sctlr_rst.v; 213 sctlr.u = 1; 214 sctlr.xp = 1; 215 sctlr.rao2 = 1; 216 sctlr.rao3 = 1; 217 sctlr.rao4 = 0xf; // SCTLR[6:3] 218 sctlr.uci = 1; 219 sctlr.dze = 1; 220 miscRegs[MISCREG_SCTLR_NS] = sctlr; 221 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 222 miscRegs[MISCREG_HCPTR] = 0; 223 224 // Start with an event in the mailbox 225 miscRegs[MISCREG_SEV_MAILBOX] = 1; 226 227 // Separate Instruction and Data TLBs 228 miscRegs[MISCREG_TLBTR] = 1; 229 230 MVFR0 mvfr0 = 0; 231 mvfr0.advSimdRegisters = 2; 232 mvfr0.singlePrecision = 2; 233 mvfr0.doublePrecision = 2; 234 mvfr0.vfpExceptionTrapping = 0; 235 mvfr0.divide = 1; 236 mvfr0.squareRoot = 1; 237 mvfr0.shortVectors = 1; 238 mvfr0.roundingModes = 1; 239 miscRegs[MISCREG_MVFR0] = mvfr0; 240 241 MVFR1 mvfr1 = 0; 242 mvfr1.flushToZero = 1; 243 mvfr1.defaultNaN = 1; 244 mvfr1.advSimdLoadStore = 1; 245 mvfr1.advSimdInteger = 1; 246 mvfr1.advSimdSinglePrecision = 1; 247 mvfr1.advSimdHalfPrecision = 1; 248 mvfr1.vfpHalfPrecision = 1; 249 miscRegs[MISCREG_MVFR1] = mvfr1; 250 251 // Reset values of PRRR and NMRR are implementation dependent 252 253 // @todo: PRRR and NMRR in secure state? 254 miscRegs[MISCREG_PRRR_NS] = 255 (1 << 19) | // 19 256 (0 << 18) | // 18 257 (0 << 17) | // 17 258 (1 << 16) | // 16 259 (2 << 14) | // 15:14 260 (0 << 12) | // 13:12 261 (2 << 10) | // 11:10 262 (2 << 8) | // 9:8 263 (2 << 6) | // 7:6 264 (2 << 4) | // 5:4 265 (1 << 2) | // 3:2 266 0; // 1:0 267 miscRegs[MISCREG_NMRR_NS] = 268 (1 << 30) | // 31:30 269 (0 << 26) | // 27:26 270 (0 << 24) | // 25:24 271 (3 << 22) | // 23:22 272 (2 << 20) | // 21:20 273 (0 << 18) | // 19:18 274 (0 << 16) | // 17:16 275 (1 << 14) | // 15:14 276 (0 << 12) | // 13:12 277 (2 << 10) | // 11:10 278 (0 << 8) | // 9:8 279 (3 << 6) | // 7:6 280 (2 << 4) | // 5:4 281 (0 << 2) | // 3:2 282 0; // 1:0 283 284 miscRegs[MISCREG_CPACR] = 0; 285 286 287 miscRegs[MISCREG_ID_PFR0] = p->id_pfr0; 288 miscRegs[MISCREG_ID_PFR1] = p->id_pfr1; 289 290 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 291 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 292 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 293 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 294 295 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 296 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 297 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 298 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 299 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 300 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 301 302 miscRegs[MISCREG_FPSID] = p->fpsid; 303 304 if (haveLPAE) { 305 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 306 ttbcr.eae = 0; 307 miscRegs[MISCREG_TTBCR_NS] = ttbcr; 308 // Enforce consistency with system-level settings 309 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 310 } 311 312 if (haveSecurity) { 313 miscRegs[MISCREG_SCTLR_S] = sctlr; 314 miscRegs[MISCREG_SCR] = 0; 315 miscRegs[MISCREG_VBAR_S] = 0; 316 } else { 317 // we're always non-secure 318 miscRegs[MISCREG_SCR] = 1; 319 } 320 321 //XXX We need to initialize the rest of the state. 322} 323 324void 325ISA::clear64(const ArmISAParams *p) 326{ 327 CPSR cpsr = 0; 328 Addr rvbar = system->resetAddr64(); 329 switch (system->highestEL()) { 330 // Set initial EL to highest implemented EL using associated stack 331 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 332 // value 333 case EL3: 334 cpsr.mode = MODE_EL3H; 335 miscRegs[MISCREG_RVBAR_EL3] = rvbar; 336 break; 337 case EL2: 338 cpsr.mode = MODE_EL2H; 339 miscRegs[MISCREG_RVBAR_EL2] = rvbar; 340 break; 341 case EL1: 342 cpsr.mode = MODE_EL1H; 343 miscRegs[MISCREG_RVBAR_EL1] = rvbar; 344 break; 345 default: 346 panic("Invalid highest implemented exception level"); 347 break; 348 } 349 350 // Initialize rest of CPSR 351 cpsr.daif = 0xf; // Mask all interrupts 352 cpsr.ss = 0; 353 cpsr.il = 0; 354 miscRegs[MISCREG_CPSR] = cpsr; 355 updateRegMap(cpsr); 356 357 // Initialize other control registers 358 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 359 if (haveSecurity) { 360 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50870; 361 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 362 // @todo: uncomment this to enable Virtualization 363 // } else if (haveVirtualization) { 364 // miscRegs[MISCREG_SCTLR_EL2] = 0x30c50870; 365 } else { 366 miscRegs[MISCREG_SCTLR_EL1] = 0x30c50870; 367 // Always non-secure 368 miscRegs[MISCREG_SCR_EL3] = 1; 369 } 370 371 // Initialize configurable id registers 372 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 373 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 374 miscRegs[MISCREG_ID_AA64DFR0_EL1] = 375 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 376 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 377 378 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 379 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 380 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 381 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 382 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 383 miscRegs[MISCREG_ID_AA64PFR0_EL1] = p->id_aa64pfr0_el1; 384 miscRegs[MISCREG_ID_AA64PFR1_EL1] = p->id_aa64pfr1_el1; 385 386 miscRegs[MISCREG_ID_DFR0_EL1] = 387 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 388 389 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 390 391 // Enforce consistency with system-level settings... 392 393 // EL3 394 // (no AArch32/64 interprocessing support for now) 395 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 396 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 397 haveSecurity ? 0x1 : 0x0); 398 // EL2 399 // (no AArch32/64 interprocessing support for now) 400 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 401 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 402 haveVirtualization ? 0x1 : 0x0); 403 // Large ASID support 404 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 405 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 406 haveLargeAsid64 ? 0x2 : 0x0); 407 // Physical address size 408 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 409 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 410 encodePhysAddrRange64(physAddrRange64)); 411} 412 413MiscReg 414ISA::readMiscRegNoEffect(int misc_reg) const 415{ 416 assert(misc_reg < NumMiscRegs); 417 418 int flat_idx = flattenMiscIndex(misc_reg); // Note: indexes of AArch64 419 // registers are left unchanged 420 MiscReg val; 421 422 if (lookUpMiscReg[flat_idx].lower == 0 || flat_idx == MISCREG_SPSR 423 || flat_idx == MISCREG_SCTLR_EL1) { 424 if (flat_idx == MISCREG_SPSR) 425 flat_idx = flattenMiscIndex(MISCREG_SPSR); 426 if (flat_idx == MISCREG_SCTLR_EL1) 427 flat_idx = flattenMiscIndex(MISCREG_SCTLR); 428 val = miscRegs[flat_idx]; 429 } else 430 if (lookUpMiscReg[flat_idx].upper > 0) 431 val = ((miscRegs[lookUpMiscReg[flat_idx].lower] & mask(32)) 432 | (miscRegs[lookUpMiscReg[flat_idx].upper] << 32)); 433 else 434 val = miscRegs[lookUpMiscReg[flat_idx].lower]; 435 436 return val; 437} 438 439 440MiscReg 441ISA::readMiscReg(int misc_reg, ThreadContext *tc) 442{ 443 CPSR cpsr = 0; 444 PCState pc = 0; 445 SCR scr = 0; 446 447 if (misc_reg == MISCREG_CPSR) { 448 cpsr = miscRegs[misc_reg]; 449 pc = tc->pcState(); 450 cpsr.j = pc.jazelle() ? 1 : 0; 451 cpsr.t = pc.thumb() ? 1 : 0; 452 return cpsr; 453 } 454 455#ifndef NDEBUG 456 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 457 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 458 warn("Unimplemented system register %s read.\n", 459 miscRegName[misc_reg]); 460 else 461 panic("Unimplemented system register %s read.\n", 462 miscRegName[misc_reg]); 463 } 464#endif 465 466 switch (unflattenMiscReg(misc_reg)) { 467 case MISCREG_HCR: 468 { 469 if (!haveVirtualization) 470 return 0; 471 else 472 return readMiscRegNoEffect(MISCREG_HCR); 473 } 474 case MISCREG_CPACR: 475 { 476 const uint32_t ones = (uint32_t)(-1); 477 CPACR cpacrMask = 0; 478 // Only cp10, cp11, and ase are implemented, nothing else should 479 // be readable? (straight copy from the write code) 480 cpacrMask.cp10 = ones; 481 cpacrMask.cp11 = ones; 482 cpacrMask.asedis = ones; 483 484 // Security Extensions may limit the readability of CPACR 485 if (haveSecurity) { 486 scr = readMiscRegNoEffect(MISCREG_SCR); 487 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 488 if (scr.ns && (cpsr.mode != MODE_MON)) { 489 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 490 // NB: Skipping the full loop, here 491 if (!nsacr.cp10) cpacrMask.cp10 = 0; 492 if (!nsacr.cp11) cpacrMask.cp11 = 0; 493 } 494 } 495 MiscReg val = readMiscRegNoEffect(MISCREG_CPACR); 496 val &= cpacrMask; 497 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 498 miscRegName[misc_reg], val); 499 return val; 500 } 501 case MISCREG_MPIDR: 502 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 503 scr = readMiscRegNoEffect(MISCREG_SCR); 504 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 505 return getMPIDR(system, tc); 506 } else { 507 return readMiscReg(MISCREG_VMPIDR, tc); 508 } 509 break; 510 case MISCREG_MPIDR_EL1: 511 // @todo in the absence of v8 virtualization support just return MPIDR_EL1 512 return getMPIDR(system, tc) & 0xffffffff; 513 case MISCREG_VMPIDR: 514 // top bit defined as RES1 515 return readMiscRegNoEffect(misc_reg) | 0x80000000; 516 case MISCREG_ID_AFR0: // not implemented, so alias MIDR 517 case MISCREG_REVIDR: // not implemented, so alias MIDR 518 case MISCREG_MIDR: 519 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 520 scr = readMiscRegNoEffect(MISCREG_SCR); 521 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 522 return readMiscRegNoEffect(misc_reg); 523 } else { 524 return readMiscRegNoEffect(MISCREG_VPIDR); 525 } 526 break; 527 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 528 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 529 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 530 case MISCREG_AIDR: // AUX ID set to 0 531 case MISCREG_TCMTR: // No TCM's 532 return 0; 533 534 case MISCREG_CLIDR: 535 warn_once("The clidr register always reports 0 caches.\n"); 536 warn_once("clidr LoUIS field of 0b001 to match current " 537 "ARM implementations.\n"); 538 return 0x00200000; 539 case MISCREG_CCSIDR: 540 warn_once("The ccsidr register isn't implemented and " 541 "always reads as 0.\n"); 542 break; 543 case MISCREG_CTR: 544 { 545 //all caches have the same line size in gem5 546 //4 byte words in ARM 547 unsigned lineSizeWords = 548 tc->getSystemPtr()->cacheLineSize() / 4; 549 unsigned log2LineSizeWords = 0; 550 551 while (lineSizeWords >>= 1) { 552 ++log2LineSizeWords; 553 } 554 555 CTR ctr = 0; 556 //log2 of minimun i-cache line size (words) 557 ctr.iCacheLineSize = log2LineSizeWords; 558 //b11 - gem5 uses pipt 559 ctr.l1IndexPolicy = 0x3; 560 //log2 of minimum d-cache line size (words) 561 ctr.dCacheLineSize = log2LineSizeWords; 562 //log2 of max reservation size (words) 563 ctr.erg = log2LineSizeWords; 564 //log2 of max writeback size (words) 565 ctr.cwg = log2LineSizeWords; 566 //b100 - gem5 format is ARMv7 567 ctr.format = 0x4; 568 569 return ctr; 570 } 571 case MISCREG_ACTLR: 572 warn("Not doing anything for miscreg ACTLR\n"); 573 break; 574 575 case MISCREG_PMXEVTYPER_PMCCFILTR: 576 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 577 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 578 case MISCREG_PMCR ... MISCREG_PMOVSSET: 579 return pmu->readMiscReg(misc_reg); 580 581 case MISCREG_CPSR_Q: 582 panic("shouldn't be reading this register seperately\n"); 583 case MISCREG_FPSCR_QC: 584 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 585 case MISCREG_FPSCR_EXC: 586 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 587 case MISCREG_FPSR: 588 { 589 const uint32_t ones = (uint32_t)(-1); 590 FPSCR fpscrMask = 0; 591 fpscrMask.ioc = ones; 592 fpscrMask.dzc = ones; 593 fpscrMask.ofc = ones; 594 fpscrMask.ufc = ones; 595 fpscrMask.ixc = ones; 596 fpscrMask.idc = ones; 597 fpscrMask.qc = ones; 598 fpscrMask.v = ones; 599 fpscrMask.c = ones; 600 fpscrMask.z = ones; 601 fpscrMask.n = ones; 602 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 603 } 604 case MISCREG_FPCR: 605 { 606 const uint32_t ones = (uint32_t)(-1); 607 FPSCR fpscrMask = 0; 608 fpscrMask.ioe = ones; 609 fpscrMask.dze = ones; 610 fpscrMask.ofe = ones; 611 fpscrMask.ufe = ones; 612 fpscrMask.ixe = ones; 613 fpscrMask.ide = ones; 614 fpscrMask.len = ones; 615 fpscrMask.stride = ones; 616 fpscrMask.rMode = ones; 617 fpscrMask.fz = ones; 618 fpscrMask.dn = ones; 619 fpscrMask.ahp = ones; 620 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 621 } 622 case MISCREG_NZCV: 623 { 624 CPSR cpsr = 0; 625 cpsr.nz = tc->readCCReg(CCREG_NZ); 626 cpsr.c = tc->readCCReg(CCREG_C); 627 cpsr.v = tc->readCCReg(CCREG_V); 628 return cpsr; 629 } 630 case MISCREG_DAIF: 631 { 632 CPSR cpsr = 0; 633 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 634 return cpsr; 635 } 636 case MISCREG_SP_EL0: 637 { 638 return tc->readIntReg(INTREG_SP0); 639 } 640 case MISCREG_SP_EL1: 641 { 642 return tc->readIntReg(INTREG_SP1); 643 } 644 case MISCREG_SP_EL2: 645 { 646 return tc->readIntReg(INTREG_SP2); 647 } 648 case MISCREG_SPSEL: 649 { 650 return miscRegs[MISCREG_CPSR] & 0x1; 651 } 652 case MISCREG_CURRENTEL: 653 { 654 return miscRegs[MISCREG_CPSR] & 0xc; 655 } 656 case MISCREG_L2CTLR: 657 { 658 // mostly unimplemented, just set NumCPUs field from sim and return 659 L2CTLR l2ctlr = 0; 660 // b00:1CPU to b11:4CPUs 661 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 662 return l2ctlr; 663 } 664 case MISCREG_DBGDIDR: 665 /* For now just implement the version number. 666 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 667 */ 668 return 0x5 << 16; 669 case MISCREG_DBGDSCRint: 670 return 0; 671 case MISCREG_ISR: 672 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 673 readMiscRegNoEffect(MISCREG_HCR), 674 readMiscRegNoEffect(MISCREG_CPSR), 675 readMiscRegNoEffect(MISCREG_SCR)); 676 case MISCREG_ISR_EL1: 677 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 678 readMiscRegNoEffect(MISCREG_HCR_EL2), 679 readMiscRegNoEffect(MISCREG_CPSR), 680 readMiscRegNoEffect(MISCREG_SCR_EL3)); 681 case MISCREG_DCZID_EL0: 682 return 0x04; // DC ZVA clear 64-byte chunks 683 case MISCREG_HCPTR: 684 { 685 MiscReg val = readMiscRegNoEffect(misc_reg); 686 // The trap bit associated with CP14 is defined as RAZ 687 val &= ~(1 << 14); 688 // If a CP bit in NSACR is 0 then the corresponding bit in 689 // HCPTR is RAO/WI 690 bool secure_lookup = haveSecurity && 691 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 692 readMiscRegNoEffect(MISCREG_CPSR)); 693 if (!secure_lookup) { 694 MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR); 695 val |= (mask ^ 0x7FFF) & 0xBFFF; 696 } 697 // Set the bits for unimplemented coprocessors to RAO/WI 698 val |= 0x33FF; 699 return (val); 700 } 701 case MISCREG_HDFAR: // alias for secure DFAR 702 return readMiscRegNoEffect(MISCREG_DFAR_S); 703 case MISCREG_HIFAR: // alias for secure IFAR 704 return readMiscRegNoEffect(MISCREG_IFAR_S); 705 case MISCREG_HVBAR: // bottom bits reserved 706 return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0; 707 case MISCREG_SCTLR: // Some bits hardwired 708 // The FI field (bit 21) is common between S/NS versions of the register 709 return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21)) | 710 (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818; // V8 SCTLR 711 case MISCREG_SCTLR_EL1: 712 // The FI field (bit 21) is common between S/NS versions of the register 713 return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21)) | 714 (readMiscRegNoEffect(misc_reg) & 0x37DDDBFF) | 0x30D00800; // V8 SCTLR_EL1 715 case MISCREG_SCTLR_EL3: 716 // The FI field (bit 21) is common between S/NS versions of the register 717 return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21)) | 718 (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; // V8 SCTLR_EL3 719 case MISCREG_HSCTLR: // FI comes from SCTLR 720 { 721 uint32_t mask = 1 << 27; 722 return (readMiscRegNoEffect(MISCREG_HSCTLR) & ~mask) | 723 (readMiscRegNoEffect(MISCREG_SCTLR) & mask); 724 } 725 case MISCREG_SCR: 726 { 727 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 728 if (cpsr.width) { 729 return readMiscRegNoEffect(MISCREG_SCR); 730 } else { 731 return readMiscRegNoEffect(MISCREG_SCR_EL3); 732 } 733 } 734 735 // Generic Timer registers 736 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 737 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 738 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 739 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 740 return getGenericTimer(tc).readMiscReg(misc_reg); 741 742 default: 743 break; 744 745 } 746 return readMiscRegNoEffect(misc_reg); 747} 748 749void 750ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 751{ 752 assert(misc_reg < NumMiscRegs); 753 754 int flat_idx = flattenMiscIndex(misc_reg); // Note: indexes of AArch64 755 // registers are left unchanged 756 757 int flat_idx2 = lookUpMiscReg[flat_idx].upper; 758 759 if (flat_idx2 > 0) { 760 miscRegs[lookUpMiscReg[flat_idx].lower] = bits(val, 31, 0); 761 miscRegs[flat_idx2] = bits(val, 63, 32); 762 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 763 misc_reg, flat_idx, flat_idx2, val); 764 } else { 765 if (flat_idx == MISCREG_SPSR) 766 flat_idx = flattenMiscIndex(MISCREG_SPSR); 767 else if (flat_idx == MISCREG_SCTLR_EL1) 768 flat_idx = flattenMiscIndex(MISCREG_SCTLR); 769 else 770 flat_idx = (lookUpMiscReg[flat_idx].lower > 0) ? 771 lookUpMiscReg[flat_idx].lower : flat_idx; 772 miscRegs[flat_idx] = val; 773 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 774 misc_reg, flat_idx, val); 775 } 776} 777 778void 779ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 780{ 781 782 MiscReg newVal = val; 783 int x; 784 bool secure_lookup; 785 bool hyp; 786 System *sys; 787 ThreadContext *oc; 788 uint8_t target_el; 789 uint16_t asid; 790 SCR scr; 791 792 if (misc_reg == MISCREG_CPSR) { 793 updateRegMap(val); 794 795 796 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 797 int old_mode = old_cpsr.mode; 798 CPSR cpsr = val; 799 if (old_mode != cpsr.mode) { 800 tc->getITBPtr()->invalidateMiscReg(); 801 tc->getDTBPtr()->invalidateMiscReg(); 802 } 803 804 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 805 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 806 PCState pc = tc->pcState(); 807 pc.nextThumb(cpsr.t); 808 pc.nextJazelle(cpsr.j); 809 810 // Follow slightly different semantics if a CheckerCPU object 811 // is connected 812 CheckerCPU *checker = tc->getCheckerCpuPtr(); 813 if (checker) { 814 tc->pcStateNoRecord(pc); 815 } else { 816 tc->pcState(pc); 817 } 818 } else { 819#ifndef NDEBUG 820 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 821 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 822 warn("Unimplemented system register %s write with %#x.\n", 823 miscRegName[misc_reg], val); 824 else 825 panic("Unimplemented system register %s write with %#x.\n", 826 miscRegName[misc_reg], val); 827 } 828#endif 829 switch (unflattenMiscReg(misc_reg)) { 830 case MISCREG_CPACR: 831 { 832 833 const uint32_t ones = (uint32_t)(-1); 834 CPACR cpacrMask = 0; 835 // Only cp10, cp11, and ase are implemented, nothing else should 836 // be writable 837 cpacrMask.cp10 = ones; 838 cpacrMask.cp11 = ones; 839 cpacrMask.asedis = ones; 840 841 // Security Extensions may limit the writability of CPACR 842 if (haveSecurity) { 843 scr = readMiscRegNoEffect(MISCREG_SCR); 844 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 845 if (scr.ns && (cpsr.mode != MODE_MON)) { 846 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 847 // NB: Skipping the full loop, here 848 if (!nsacr.cp10) cpacrMask.cp10 = 0; 849 if (!nsacr.cp11) cpacrMask.cp11 = 0; 850 } 851 } 852 853 MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR); 854 newVal &= cpacrMask; 855 newVal |= old_val & ~cpacrMask; 856 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 857 miscRegName[misc_reg], newVal); 858 } 859 break; 860 case MISCREG_CPACR_EL1: 861 { 862 const uint32_t ones = (uint32_t)(-1); 863 CPACR cpacrMask = 0; 864 cpacrMask.tta = ones; 865 cpacrMask.fpen = ones; 866 newVal &= cpacrMask; 867 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 868 miscRegName[misc_reg], newVal); 869 } 870 break; 871 case MISCREG_CPTR_EL2: 872 { 873 const uint32_t ones = (uint32_t)(-1); 874 CPTR cptrMask = 0; 875 cptrMask.tcpac = ones; 876 cptrMask.tta = ones; 877 cptrMask.tfp = ones; 878 newVal &= cptrMask; 879 cptrMask = 0; 880 cptrMask.res1_13_12_el2 = ones; 881 cptrMask.res1_9_0_el2 = ones; 882 newVal |= cptrMask; 883 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 884 miscRegName[misc_reg], newVal); 885 } 886 break; 887 case MISCREG_CPTR_EL3: 888 { 889 const uint32_t ones = (uint32_t)(-1); 890 CPTR cptrMask = 0; 891 cptrMask.tcpac = ones; 892 cptrMask.tta = ones; 893 cptrMask.tfp = ones; 894 newVal &= cptrMask; 895 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 896 miscRegName[misc_reg], newVal); 897 } 898 break; 899 case MISCREG_CSSELR: 900 warn_once("The csselr register isn't implemented.\n"); 901 return; 902 903 case MISCREG_DC_ZVA_Xt: 904 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 905 return; 906 907 case MISCREG_FPSCR: 908 { 909 const uint32_t ones = (uint32_t)(-1); 910 FPSCR fpscrMask = 0; 911 fpscrMask.ioc = ones; 912 fpscrMask.dzc = ones; 913 fpscrMask.ofc = ones; 914 fpscrMask.ufc = ones; 915 fpscrMask.ixc = ones; 916 fpscrMask.idc = ones; 917 fpscrMask.ioe = ones; 918 fpscrMask.dze = ones; 919 fpscrMask.ofe = ones; 920 fpscrMask.ufe = ones; 921 fpscrMask.ixe = ones; 922 fpscrMask.ide = ones; 923 fpscrMask.len = ones; 924 fpscrMask.stride = ones; 925 fpscrMask.rMode = ones; 926 fpscrMask.fz = ones; 927 fpscrMask.dn = ones; 928 fpscrMask.ahp = ones; 929 fpscrMask.qc = ones; 930 fpscrMask.v = ones; 931 fpscrMask.c = ones; 932 fpscrMask.z = ones; 933 fpscrMask.n = ones; 934 newVal = (newVal & (uint32_t)fpscrMask) | 935 (readMiscRegNoEffect(MISCREG_FPSCR) & 936 ~(uint32_t)fpscrMask); 937 tc->getDecoderPtr()->setContext(newVal); 938 } 939 break; 940 case MISCREG_FPSR: 941 { 942 const uint32_t ones = (uint32_t)(-1); 943 FPSCR fpscrMask = 0; 944 fpscrMask.ioc = ones; 945 fpscrMask.dzc = ones; 946 fpscrMask.ofc = ones; 947 fpscrMask.ufc = ones; 948 fpscrMask.ixc = ones; 949 fpscrMask.idc = ones; 950 fpscrMask.qc = ones; 951 fpscrMask.v = ones; 952 fpscrMask.c = ones; 953 fpscrMask.z = ones; 954 fpscrMask.n = ones; 955 newVal = (newVal & (uint32_t)fpscrMask) | 956 (readMiscRegNoEffect(MISCREG_FPSCR) & 957 ~(uint32_t)fpscrMask); 958 misc_reg = MISCREG_FPSCR; 959 } 960 break; 961 case MISCREG_FPCR: 962 { 963 const uint32_t ones = (uint32_t)(-1); 964 FPSCR fpscrMask = 0; 965 fpscrMask.ioe = ones; 966 fpscrMask.dze = ones; 967 fpscrMask.ofe = ones; 968 fpscrMask.ufe = ones; 969 fpscrMask.ixe = ones; 970 fpscrMask.ide = ones; 971 fpscrMask.len = ones; 972 fpscrMask.stride = ones; 973 fpscrMask.rMode = ones; 974 fpscrMask.fz = ones; 975 fpscrMask.dn = ones; 976 fpscrMask.ahp = ones; 977 newVal = (newVal & (uint32_t)fpscrMask) | 978 (readMiscRegNoEffect(MISCREG_FPSCR) & 979 ~(uint32_t)fpscrMask); 980 misc_reg = MISCREG_FPSCR; 981 } 982 break; 983 case MISCREG_CPSR_Q: 984 { 985 assert(!(newVal & ~CpsrMaskQ)); 986 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 987 misc_reg = MISCREG_CPSR; 988 } 989 break; 990 case MISCREG_FPSCR_QC: 991 { 992 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 993 (newVal & FpscrQcMask); 994 misc_reg = MISCREG_FPSCR; 995 } 996 break; 997 case MISCREG_FPSCR_EXC: 998 { 999 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 1000 (newVal & FpscrExcMask); 1001 misc_reg = MISCREG_FPSCR; 1002 } 1003 break; 1004 case MISCREG_FPEXC: 1005 { 1006 // vfpv3 architecture, section B.6.1 of DDI04068 1007 // bit 29 - valid only if fpexc[31] is 0 1008 const uint32_t fpexcMask = 0x60000000; 1009 newVal = (newVal & fpexcMask) | 1010 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 1011 } 1012 break; 1013 case MISCREG_HCR: 1014 { 1015 if (!haveVirtualization) 1016 return; 1017 } 1018 break; 1019 case MISCREG_IFSR: 1020 { 1021 // ARM ARM (ARM DDI 0406C.b) B4.1.96 1022 const uint32_t ifsrMask = 1023 mask(31, 13) | mask(11, 11) | mask(8, 6); 1024 newVal = newVal & ~ifsrMask; 1025 } 1026 break; 1027 case MISCREG_DFSR: 1028 { 1029 // ARM ARM (ARM DDI 0406C.b) B4.1.52 1030 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 1031 newVal = newVal & ~dfsrMask; 1032 } 1033 break; 1034 case MISCREG_AMAIR0: 1035 case MISCREG_AMAIR1: 1036 { 1037 // ARM ARM (ARM DDI 0406C.b) B4.1.5 1038 // Valid only with LPAE 1039 if (!haveLPAE) 1040 return; 1041 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 1042 } 1043 break; 1044 case MISCREG_SCR: 1045 tc->getITBPtr()->invalidateMiscReg(); 1046 tc->getDTBPtr()->invalidateMiscReg(); 1047 break; 1048 case MISCREG_SCTLR: 1049 { 1050 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 1051 MiscRegIndex sctlr_idx; 1052 scr = readMiscRegNoEffect(MISCREG_SCR); 1053 if (haveSecurity && !scr.ns) { 1054 sctlr_idx = MISCREG_SCTLR_S; 1055 } else { 1056 sctlr_idx = MISCREG_SCTLR_NS; 1057 // The FI field (bit 21) is common between S/NS versions 1058 // of the register, we store this in the secure copy of 1059 // the reg 1060 miscRegs[MISCREG_SCTLR_S] &= ~(1 << 21); 1061 miscRegs[MISCREG_SCTLR_S] |= newVal & (1 << 21); 1062 } 1063 SCTLR sctlr = miscRegs[sctlr_idx]; 1064 SCTLR new_sctlr = newVal; 1065 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 1066 miscRegs[sctlr_idx] = (MiscReg)new_sctlr; 1067 tc->getITBPtr()->invalidateMiscReg(); 1068 tc->getDTBPtr()->invalidateMiscReg(); 1069 } 1070 case MISCREG_MIDR: 1071 case MISCREG_ID_PFR0: 1072 case MISCREG_ID_PFR1: 1073 case MISCREG_ID_DFR0: 1074 case MISCREG_ID_MMFR0: 1075 case MISCREG_ID_MMFR1: 1076 case MISCREG_ID_MMFR2: 1077 case MISCREG_ID_MMFR3: 1078 case MISCREG_ID_ISAR0: 1079 case MISCREG_ID_ISAR1: 1080 case MISCREG_ID_ISAR2: 1081 case MISCREG_ID_ISAR3: 1082 case MISCREG_ID_ISAR4: 1083 case MISCREG_ID_ISAR5: 1084 1085 case MISCREG_MPIDR: 1086 case MISCREG_FPSID: 1087 case MISCREG_TLBTR: 1088 case MISCREG_MVFR0: 1089 case MISCREG_MVFR1: 1090 1091 case MISCREG_ID_AA64AFR0_EL1: 1092 case MISCREG_ID_AA64AFR1_EL1: 1093 case MISCREG_ID_AA64DFR0_EL1: 1094 case MISCREG_ID_AA64DFR1_EL1: 1095 case MISCREG_ID_AA64ISAR0_EL1: 1096 case MISCREG_ID_AA64ISAR1_EL1: 1097 case MISCREG_ID_AA64MMFR0_EL1: 1098 case MISCREG_ID_AA64MMFR1_EL1: 1099 case MISCREG_ID_AA64PFR0_EL1: 1100 case MISCREG_ID_AA64PFR1_EL1: 1101 // ID registers are constants. 1102 return; 1103 1104 // TLBI all entries, EL0&1 inner sharable (ignored) 1105 case MISCREG_TLBIALLIS: 1106 case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 1107 assert32(tc); 1108 target_el = 1; // el 0 and 1 are handled together 1109 scr = readMiscReg(MISCREG_SCR, tc); 1110 secure_lookup = haveSecurity && !scr.ns; 1111 sys = tc->getSystemPtr(); 1112 for (x = 0; x < sys->numContexts(); x++) { 1113 oc = sys->getThreadContext(x); 1114 assert(oc->getITBPtr() && oc->getDTBPtr()); 1115 oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 1116 oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 1117 1118 // If CheckerCPU is connected, need to notify it of a flush 1119 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1120 if (checker) { 1121 checker->getITBPtr()->flushAllSecurity(secure_lookup, 1122 target_el); 1123 checker->getDTBPtr()->flushAllSecurity(secure_lookup, 1124 target_el); 1125 } 1126 } 1127 return; 1128 // TLBI all entries, EL0&1, instruction side 1129 case MISCREG_ITLBIALL: 1130 assert32(tc); 1131 target_el = 1; // el 0 and 1 are handled together 1132 scr = readMiscReg(MISCREG_SCR, tc); 1133 secure_lookup = haveSecurity && !scr.ns; 1134 tc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 1135 return; 1136 // TLBI all entries, EL0&1, data side 1137 case MISCREG_DTLBIALL: 1138 assert32(tc); 1139 target_el = 1; // el 0 and 1 are handled together 1140 scr = readMiscReg(MISCREG_SCR, tc); 1141 secure_lookup = haveSecurity && !scr.ns; 1142 tc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 1143 return; 1144 // TLBI based on VA, EL0&1 inner sharable (ignored) 1145 case MISCREG_TLBIMVAIS: 1146 case MISCREG_TLBIMVA: 1147 assert32(tc); 1148 target_el = 1; // el 0 and 1 are handled together 1149 scr = readMiscReg(MISCREG_SCR, tc); 1150 secure_lookup = haveSecurity && !scr.ns; 1151 sys = tc->getSystemPtr(); 1152 for (x = 0; x < sys->numContexts(); x++) { 1153 oc = sys->getThreadContext(x); 1154 assert(oc->getITBPtr() && oc->getDTBPtr()); 1155 oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1156 bits(newVal, 7,0), 1157 secure_lookup, target_el); 1158 oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1159 bits(newVal, 7,0), 1160 secure_lookup, target_el); 1161 1162 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1163 if (checker) { 1164 checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1165 bits(newVal, 7,0), secure_lookup, target_el); 1166 checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1167 bits(newVal, 7,0), secure_lookup, target_el); 1168 } 1169 } 1170 return; 1171 // TLBI by ASID, EL0&1, inner sharable 1172 case MISCREG_TLBIASIDIS: 1173 case MISCREG_TLBIASID: 1174 assert32(tc); 1175 target_el = 1; // el 0 and 1 are handled together 1176 scr = readMiscReg(MISCREG_SCR, tc); 1177 secure_lookup = haveSecurity && !scr.ns; 1178 sys = tc->getSystemPtr(); 1179 for (x = 0; x < sys->numContexts(); x++) { 1180 oc = sys->getThreadContext(x); 1181 assert(oc->getITBPtr() && oc->getDTBPtr()); 1182 oc->getITBPtr()->flushAsid(bits(newVal, 7,0), 1183 secure_lookup, target_el); 1184 oc->getDTBPtr()->flushAsid(bits(newVal, 7,0), 1185 secure_lookup, target_el); 1186 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1187 if (checker) { 1188 checker->getITBPtr()->flushAsid(bits(newVal, 7,0), 1189 secure_lookup, target_el); 1190 checker->getDTBPtr()->flushAsid(bits(newVal, 7,0), 1191 secure_lookup, target_el); 1192 } 1193 } 1194 return; 1195 // TLBI by address, EL0&1, inner sharable (ignored) 1196 case MISCREG_TLBIMVAAIS: 1197 case MISCREG_TLBIMVAA: 1198 assert32(tc); 1199 target_el = 1; // el 0 and 1 are handled together 1200 scr = readMiscReg(MISCREG_SCR, tc); 1201 secure_lookup = haveSecurity && !scr.ns; 1202 hyp = 0; 1203 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el); 1204 return; 1205 // TLBI by address, EL2, hypervisor mode 1206 case MISCREG_TLBIMVAH: 1207 case MISCREG_TLBIMVAHIS: 1208 assert32(tc); 1209 target_el = 1; // aarch32, use hyp bit 1210 scr = readMiscReg(MISCREG_SCR, tc); 1211 secure_lookup = haveSecurity && !scr.ns; 1212 hyp = 1; 1213 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el); 1214 return; 1215 // TLBI by address and asid, EL0&1, instruction side only 1216 case MISCREG_ITLBIMVA: 1217 assert32(tc); 1218 target_el = 1; // el 0 and 1 are handled together 1219 scr = readMiscReg(MISCREG_SCR, tc); 1220 secure_lookup = haveSecurity && !scr.ns; 1221 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1222 bits(newVal, 7,0), secure_lookup, target_el); 1223 return; 1224 // TLBI by address and asid, EL0&1, data side only 1225 case MISCREG_DTLBIMVA: 1226 assert32(tc); 1227 target_el = 1; // el 0 and 1 are handled together 1228 scr = readMiscReg(MISCREG_SCR, tc); 1229 secure_lookup = haveSecurity && !scr.ns; 1230 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1231 bits(newVal, 7,0), secure_lookup, target_el); 1232 return; 1233 // TLBI by ASID, EL0&1, instrution side only 1234 case MISCREG_ITLBIASID: 1235 assert32(tc); 1236 target_el = 1; // el 0 and 1 are handled together 1237 scr = readMiscReg(MISCREG_SCR, tc); 1238 secure_lookup = haveSecurity && !scr.ns; 1239 tc->getITBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup, 1240 target_el); 1241 return; 1242 // TLBI by ASID EL0&1 data size only 1243 case MISCREG_DTLBIASID: 1244 assert32(tc); 1245 target_el = 1; // el 0 and 1 are handled together 1246 scr = readMiscReg(MISCREG_SCR, tc); 1247 secure_lookup = haveSecurity && !scr.ns; 1248 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup, 1249 target_el); 1250 return; 1251 // Invalidate entire Non-secure Hyp/Non-Hyp Unified TLB 1252 case MISCREG_TLBIALLNSNH: 1253 case MISCREG_TLBIALLNSNHIS: 1254 assert32(tc); 1255 target_el = 1; // el 0 and 1 are handled together 1256 hyp = 0; 1257 tlbiALLN(tc, hyp, target_el); 1258 return; 1259 // TLBI all entries, EL2, hyp, 1260 case MISCREG_TLBIALLH: 1261 case MISCREG_TLBIALLHIS: 1262 assert32(tc); 1263 target_el = 1; // aarch32, use hyp bit 1264 hyp = 1; 1265 tlbiALLN(tc, hyp, target_el); 1266 return; 1267 // AArch64 TLBI: invalidate all entries EL3 1268 case MISCREG_TLBI_ALLE3IS: 1269 case MISCREG_TLBI_ALLE3: 1270 assert64(tc); 1271 target_el = 3; 1272 secure_lookup = true; 1273 tlbiALL(tc, secure_lookup, target_el); 1274 return; 1275 // @todo: uncomment this to enable Virtualization 1276 // case MISCREG_TLBI_ALLE2IS: 1277 // case MISCREG_TLBI_ALLE2: 1278 // TLBI all entries, EL0&1 1279 case MISCREG_TLBI_ALLE1IS: 1280 case MISCREG_TLBI_ALLE1: 1281 // AArch64 TLBI: invalidate all entries, stage 1, current VMID 1282 case MISCREG_TLBI_VMALLE1IS: 1283 case MISCREG_TLBI_VMALLE1: 1284 // AArch64 TLBI: invalidate all entries, stages 1 & 2, current VMID 1285 case MISCREG_TLBI_VMALLS12E1IS: 1286 case MISCREG_TLBI_VMALLS12E1: 1287 // @todo: handle VMID and stage 2 to enable Virtualization 1288 assert64(tc); 1289 target_el = 1; // el 0 and 1 are handled together 1290 scr = readMiscReg(MISCREG_SCR, tc); 1291 secure_lookup = haveSecurity && !scr.ns; 1292 tlbiALL(tc, secure_lookup, target_el); 1293 return; 1294 // AArch64 TLBI: invalidate by VA and ASID, stage 1, current VMID 1295 // VAEx(IS) and VALEx(IS) are the same because TLBs only store entries 1296 // from the last level of translation table walks 1297 // @todo: handle VMID to enable Virtualization 1298 // TLBI all entries, EL0&1 1299 case MISCREG_TLBI_VAE3IS_Xt: 1300 case MISCREG_TLBI_VAE3_Xt: 1301 // TLBI by VA, EL3 regime stage 1, last level walk 1302 case MISCREG_TLBI_VALE3IS_Xt: 1303 case MISCREG_TLBI_VALE3_Xt: 1304 assert64(tc); 1305 target_el = 3; 1306 asid = 0xbeef; // does not matter, tlbi is global 1307 secure_lookup = true; 1308 tlbiVA(tc, newVal, asid, secure_lookup, target_el); 1309 return; 1310 // TLBI by VA, EL2 1311 case MISCREG_TLBI_VAE2IS_Xt: 1312 case MISCREG_TLBI_VAE2_Xt: 1313 // TLBI by VA, EL2, stage1 last level walk 1314 case MISCREG_TLBI_VALE2IS_Xt: 1315 case MISCREG_TLBI_VALE2_Xt: 1316 assert64(tc); 1317 target_el = 2; 1318 asid = 0xbeef; // does not matter, tlbi is global 1319 scr = readMiscReg(MISCREG_SCR, tc); 1320 secure_lookup = haveSecurity && !scr.ns; 1321 tlbiVA(tc, newVal, asid, secure_lookup, target_el); 1322 return; 1323 // TLBI by VA EL1 & 0, stage1, ASID, current VMID 1324 case MISCREG_TLBI_VAE1IS_Xt: 1325 case MISCREG_TLBI_VAE1_Xt: 1326 case MISCREG_TLBI_VALE1IS_Xt: 1327 case MISCREG_TLBI_VALE1_Xt: 1328 assert64(tc); 1329 asid = bits(newVal, 63, 48); 1330 target_el = 1; // el 0 and 1 are handled together 1331 scr = readMiscReg(MISCREG_SCR, tc); 1332 secure_lookup = haveSecurity && !scr.ns; 1333 tlbiVA(tc, newVal, asid, secure_lookup, target_el); 1334 return; 1335 // AArch64 TLBI: invalidate by ASID, stage 1, current VMID 1336 // @todo: handle VMID to enable Virtualization 1337 case MISCREG_TLBI_ASIDE1IS_Xt: 1338 case MISCREG_TLBI_ASIDE1_Xt: 1339 assert64(tc); 1340 target_el = 1; // el 0 and 1 are handled together 1341 scr = readMiscReg(MISCREG_SCR, tc); 1342 secure_lookup = haveSecurity && !scr.ns; 1343 sys = tc->getSystemPtr(); 1344 for (x = 0; x < sys->numContexts(); x++) { 1345 oc = sys->getThreadContext(x); 1346 assert(oc->getITBPtr() && oc->getDTBPtr()); 1347 asid = bits(newVal, 63, 48); 1348 if (!haveLargeAsid64) 1349 asid &= mask(8); 1350 oc->getITBPtr()->flushAsid(asid, secure_lookup, target_el); 1351 oc->getDTBPtr()->flushAsid(asid, secure_lookup, target_el); 1352 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1353 if (checker) { 1354 checker->getITBPtr()->flushAsid(asid, 1355 secure_lookup, target_el); 1356 checker->getDTBPtr()->flushAsid(asid, 1357 secure_lookup, target_el); 1358 } 1359 } 1360 return; 1361 // AArch64 TLBI: invalidate by VA, ASID, stage 1, current VMID 1362 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 1363 // entries from the last level of translation table walks 1364 // @todo: handle VMID to enable Virtualization 1365 case MISCREG_TLBI_VAAE1IS_Xt: 1366 case MISCREG_TLBI_VAAE1_Xt: 1367 case MISCREG_TLBI_VAALE1IS_Xt: 1368 case MISCREG_TLBI_VAALE1_Xt: 1369 assert64(tc); 1370 target_el = 1; // el 0 and 1 are handled together 1371 scr = readMiscReg(MISCREG_SCR, tc); 1372 secure_lookup = haveSecurity && !scr.ns; 1373 sys = tc->getSystemPtr(); 1374 for (x = 0; x < sys->numContexts(); x++) { 1375 // @todo: extra controls on TLBI broadcast? 1376 oc = sys->getThreadContext(x); 1377 assert(oc->getITBPtr() && oc->getDTBPtr()); 1378 Addr va = ((Addr) bits(newVal, 43, 0)) << 12; 1379 oc->getITBPtr()->flushMva(va, 1380 secure_lookup, false, target_el); 1381 oc->getDTBPtr()->flushMva(va, 1382 secure_lookup, false, target_el); 1383 1384 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1385 if (checker) { 1386 checker->getITBPtr()->flushMva(va, 1387 secure_lookup, false, target_el); 1388 checker->getDTBPtr()->flushMva(va, 1389 secure_lookup, false, target_el); 1390 } 1391 } 1392 return; 1393 // AArch64 TLBI: invalidate by IPA, stage 2, current VMID 1394 case MISCREG_TLBI_IPAS2LE1IS_Xt: 1395 case MISCREG_TLBI_IPAS2LE1_Xt: 1396 case MISCREG_TLBI_IPAS2E1IS_Xt: 1397 case MISCREG_TLBI_IPAS2E1_Xt: 1398 assert64(tc); 1399 // @todo: implement these as part of Virtualization 1400 warn("Not doing anything for write of miscreg ITLB_IPAS2\n"); 1401 return; 1402 case MISCREG_ACTLR: 1403 warn("Not doing anything for write of miscreg ACTLR\n"); 1404 break; 1405 1406 case MISCREG_PMXEVTYPER_PMCCFILTR: 1407 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 1408 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 1409 case MISCREG_PMCR ... MISCREG_PMOVSSET: 1410 pmu->setMiscReg(misc_reg, newVal); 1411 break; 1412 1413 1414 case MISCREG_HSTR: // TJDBX, now redifined to be RES0 1415 { 1416 HSTR hstrMask = 0; 1417 hstrMask.tjdbx = 1; 1418 newVal &= ~((uint32_t) hstrMask); 1419 break; 1420 } 1421 case MISCREG_HCPTR: 1422 { 1423 // If a CP bit in NSACR is 0 then the corresponding bit in 1424 // HCPTR is RAO/WI. Same applies to NSASEDIS 1425 secure_lookup = haveSecurity && 1426 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 1427 readMiscRegNoEffect(MISCREG_CPSR)); 1428 if (!secure_lookup) { 1429 MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 1430 MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 1431 newVal = (newVal & ~mask) | (oldValue & mask); 1432 } 1433 break; 1434 } 1435 case MISCREG_HDFAR: // alias for secure DFAR 1436 misc_reg = MISCREG_DFAR_S; 1437 break; 1438 case MISCREG_HIFAR: // alias for secure IFAR 1439 misc_reg = MISCREG_IFAR_S; 1440 break; 1441 case MISCREG_ATS1CPR: 1442 case MISCREG_ATS1CPW: 1443 case MISCREG_ATS1CUR: 1444 case MISCREG_ATS1CUW: 1445 case MISCREG_ATS12NSOPR: 1446 case MISCREG_ATS12NSOPW: 1447 case MISCREG_ATS12NSOUR: 1448 case MISCREG_ATS12NSOUW: 1449 case MISCREG_ATS1HR: 1450 case MISCREG_ATS1HW: 1451 { 1452 unsigned flags = 0; 1453 BaseTLB::Mode mode = BaseTLB::Read; 1454 TLB::ArmTranslationType tranType = TLB::NormalTran; 1455 Fault fault; 1456 switch(misc_reg) { 1457 case MISCREG_ATS1CPR: 1458 flags = TLB::MustBeOne; 1459 tranType = TLB::S1CTran; 1460 mode = BaseTLB::Read; 1461 break; 1462 case MISCREG_ATS1CPW: 1463 flags = TLB::MustBeOne; 1464 tranType = TLB::S1CTran; 1465 mode = BaseTLB::Write; 1466 break; 1467 case MISCREG_ATS1CUR: 1468 flags = TLB::MustBeOne | TLB::UserMode; 1469 tranType = TLB::S1CTran; 1470 mode = BaseTLB::Read; 1471 break; 1472 case MISCREG_ATS1CUW: 1473 flags = TLB::MustBeOne | TLB::UserMode; 1474 tranType = TLB::S1CTran; 1475 mode = BaseTLB::Write; 1476 break; 1477 case MISCREG_ATS12NSOPR: 1478 if (!haveSecurity) 1479 panic("Security Extensions required for ATS12NSOPR"); 1480 flags = TLB::MustBeOne; 1481 tranType = TLB::S1S2NsTran; 1482 mode = BaseTLB::Read; 1483 break; 1484 case MISCREG_ATS12NSOPW: 1485 if (!haveSecurity) 1486 panic("Security Extensions required for ATS12NSOPW"); 1487 flags = TLB::MustBeOne; 1488 tranType = TLB::S1S2NsTran; 1489 mode = BaseTLB::Write; 1490 break; 1491 case MISCREG_ATS12NSOUR: 1492 if (!haveSecurity) 1493 panic("Security Extensions required for ATS12NSOUR"); 1494 flags = TLB::MustBeOne | TLB::UserMode; 1495 tranType = TLB::S1S2NsTran; 1496 mode = BaseTLB::Read; 1497 break; 1498 case MISCREG_ATS12NSOUW: 1499 if (!haveSecurity) 1500 panic("Security Extensions required for ATS12NSOUW"); 1501 flags = TLB::MustBeOne | TLB::UserMode; 1502 tranType = TLB::S1S2NsTran; 1503 mode = BaseTLB::Write; 1504 break; 1505 case MISCREG_ATS1HR: // only really useful from secure mode. 1506 flags = TLB::MustBeOne; 1507 tranType = TLB::HypMode; 1508 mode = BaseTLB::Read; 1509 break; 1510 case MISCREG_ATS1HW: 1511 flags = TLB::MustBeOne; 1512 tranType = TLB::HypMode; 1513 mode = BaseTLB::Write; 1514 break; 1515 } 1516 // If we're in timing mode then doing the translation in 1517 // functional mode then we're slightly distorting performance 1518 // results obtained from simulations. The translation should be 1519 // done in the same mode the core is running in. NOTE: This 1520 // can't be an atomic translation because that causes problems 1521 // with unexpected atomic snoop requests. 1522 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1523 Request req(0, val, 1, flags, Request::funcMasterId, 1524 tc->pcState().pc(), tc->contextId()); 1525 fault = tc->getDTBPtr()->translateFunctional(&req, tc, mode, tranType); 1526 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1527 HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 1528 1529 MiscReg newVal; 1530 if (fault == NoFault) { 1531 Addr paddr = req.getPaddr(); 1532 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 1533 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 1534 newVal = (paddr & mask(39, 12)) | 1535 (tc->getDTBPtr()->getAttr()); 1536 } else { 1537 newVal = (paddr & 0xfffff000) | 1538 (tc->getDTBPtr()->getAttr()); 1539 } 1540 DPRINTF(MiscRegs, 1541 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 1542 val, newVal); 1543 } else { 1544 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 1545 // Set fault bit and FSR 1546 FSR fsr = armFault->getFsr(tc); 1547 1548 newVal = ((fsr >> 9) & 1) << 11; 1549 if (newVal) { 1550 // LPAE - rearange fault status 1551 newVal |= ((fsr >> 0) & 0x3f) << 1; 1552 } else { 1553 // VMSA - rearange fault status 1554 newVal |= ((fsr >> 0) & 0xf) << 1; 1555 newVal |= ((fsr >> 10) & 0x1) << 5; 1556 newVal |= ((fsr >> 12) & 0x1) << 6; 1557 } 1558 newVal |= 0x1; // F bit 1559 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1560 newVal |= armFault->isStage2() ? 0x200 : 0; 1561 DPRINTF(MiscRegs, 1562 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 1563 val, fsr, newVal); 1564 } 1565 setMiscRegNoEffect(MISCREG_PAR, newVal); 1566 return; 1567 } 1568 case MISCREG_TTBCR: 1569 { 1570 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1571 const uint32_t ones = (uint32_t)(-1); 1572 TTBCR ttbcrMask = 0; 1573 TTBCR ttbcrNew = newVal; 1574 1575 // ARM DDI 0406C.b, ARMv7-32 1576 ttbcrMask.n = ones; // T0SZ 1577 if (haveSecurity) { 1578 ttbcrMask.pd0 = ones; 1579 ttbcrMask.pd1 = ones; 1580 } 1581 ttbcrMask.epd0 = ones; 1582 ttbcrMask.irgn0 = ones; 1583 ttbcrMask.orgn0 = ones; 1584 ttbcrMask.sh0 = ones; 1585 ttbcrMask.ps = ones; // T1SZ 1586 ttbcrMask.a1 = ones; 1587 ttbcrMask.epd1 = ones; 1588 ttbcrMask.irgn1 = ones; 1589 ttbcrMask.orgn1 = ones; 1590 ttbcrMask.sh1 = ones; 1591 if (haveLPAE) 1592 ttbcrMask.eae = ones; 1593 1594 if (haveLPAE && ttbcrNew.eae) { 1595 newVal = newVal & ttbcrMask; 1596 } else { 1597 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 1598 } 1599 } 1600 case MISCREG_TTBR0: 1601 case MISCREG_TTBR1: 1602 { 1603 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1604 if (haveLPAE) { 1605 if (ttbcr.eae) { 1606 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 1607 // ARMv8 AArch32 bit 63-56 only 1608 uint64_t ttbrMask = mask(63,56) | mask(47,40); 1609 newVal = (newVal & (~ttbrMask)); 1610 } 1611 } 1612 } 1613 case MISCREG_SCTLR_EL1: 1614 { 1615 tc->getITBPtr()->invalidateMiscReg(); 1616 tc->getDTBPtr()->invalidateMiscReg(); 1617 setMiscRegNoEffect(misc_reg, newVal); 1618 } 1619 case MISCREG_CONTEXTIDR: 1620 case MISCREG_PRRR: 1621 case MISCREG_NMRR: 1622 case MISCREG_MAIR0: 1623 case MISCREG_MAIR1: 1624 case MISCREG_DACR: 1625 case MISCREG_VTTBR: 1626 case MISCREG_SCR_EL3: 1627 case MISCREG_TCR_EL1: 1628 case MISCREG_TCR_EL2: 1629 case MISCREG_TCR_EL3: 1630 case MISCREG_SCTLR_EL2: 1631 case MISCREG_SCTLR_EL3: 1632 case MISCREG_TTBR0_EL1: 1633 case MISCREG_TTBR1_EL1: 1634 case MISCREG_TTBR0_EL2: 1635 case MISCREG_TTBR0_EL3: 1636 tc->getITBPtr()->invalidateMiscReg(); 1637 tc->getDTBPtr()->invalidateMiscReg(); 1638 break; 1639 case MISCREG_NZCV: 1640 { 1641 CPSR cpsr = val; 1642 1643 tc->setCCReg(CCREG_NZ, cpsr.nz); 1644 tc->setCCReg(CCREG_C, cpsr.c); 1645 tc->setCCReg(CCREG_V, cpsr.v); 1646 } 1647 break; 1648 case MISCREG_DAIF: 1649 { 1650 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1651 cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 1652 newVal = cpsr; 1653 misc_reg = MISCREG_CPSR; 1654 } 1655 break; 1656 case MISCREG_SP_EL0: 1657 tc->setIntReg(INTREG_SP0, newVal); 1658 break; 1659 case MISCREG_SP_EL1: 1660 tc->setIntReg(INTREG_SP1, newVal); 1661 break; 1662 case MISCREG_SP_EL2: 1663 tc->setIntReg(INTREG_SP2, newVal); 1664 break; 1665 case MISCREG_SPSEL: 1666 { 1667 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1668 cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 1669 newVal = cpsr; 1670 misc_reg = MISCREG_CPSR; 1671 } 1672 break; 1673 case MISCREG_CURRENTEL: 1674 { 1675 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1676 cpsr.el = (uint8_t) ((CPSR) newVal).el; 1677 newVal = cpsr; 1678 misc_reg = MISCREG_CPSR; 1679 } 1680 break; 1681 case MISCREG_AT_S1E1R_Xt: 1682 case MISCREG_AT_S1E1W_Xt: 1683 case MISCREG_AT_S1E0R_Xt: 1684 case MISCREG_AT_S1E0W_Xt: 1685 case MISCREG_AT_S1E2R_Xt: 1686 case MISCREG_AT_S1E2W_Xt: 1687 case MISCREG_AT_S12E1R_Xt: 1688 case MISCREG_AT_S12E1W_Xt: 1689 case MISCREG_AT_S12E0R_Xt: 1690 case MISCREG_AT_S12E0W_Xt: 1691 case MISCREG_AT_S1E3R_Xt: 1692 case MISCREG_AT_S1E3W_Xt: 1693 { 1694 RequestPtr req = new Request; 1695 unsigned flags = 0; 1696 BaseTLB::Mode mode = BaseTLB::Read; 1697 TLB::ArmTranslationType tranType = TLB::NormalTran; 1698 Fault fault; 1699 switch(misc_reg) { 1700 case MISCREG_AT_S1E1R_Xt: 1701 flags = TLB::MustBeOne; 1702 tranType = TLB::S1CTran; 1703 mode = BaseTLB::Read; 1704 break; 1705 case MISCREG_AT_S1E1W_Xt: 1706 flags = TLB::MustBeOne; 1707 tranType = TLB::S1CTran; 1708 mode = BaseTLB::Write; 1709 break; 1710 case MISCREG_AT_S1E0R_Xt: 1711 flags = TLB::MustBeOne | TLB::UserMode; 1712 tranType = TLB::S1CTran; 1713 mode = BaseTLB::Read; 1714 break; 1715 case MISCREG_AT_S1E0W_Xt: 1716 flags = TLB::MustBeOne | TLB::UserMode; 1717 tranType = TLB::S1CTran; 1718 mode = BaseTLB::Write; 1719 break; 1720 case MISCREG_AT_S1E2R_Xt: 1721 flags = TLB::MustBeOne; 1722 tranType = TLB::HypMode; 1723 mode = BaseTLB::Read; 1724 break; 1725 case MISCREG_AT_S1E2W_Xt: 1726 flags = TLB::MustBeOne; 1727 tranType = TLB::HypMode; 1728 mode = BaseTLB::Write; 1729 break; 1730 case MISCREG_AT_S12E0R_Xt: 1731 flags = TLB::MustBeOne | TLB::UserMode; 1732 tranType = TLB::S1S2NsTran; 1733 mode = BaseTLB::Read; 1734 break; 1735 case MISCREG_AT_S12E0W_Xt: 1736 flags = TLB::MustBeOne | TLB::UserMode; 1737 tranType = TLB::S1S2NsTran; 1738 mode = BaseTLB::Write; 1739 break; 1740 case MISCREG_AT_S12E1R_Xt: 1741 flags = TLB::MustBeOne; 1742 tranType = TLB::S1S2NsTran; 1743 mode = BaseTLB::Read; 1744 break; 1745 case MISCREG_AT_S12E1W_Xt: 1746 flags = TLB::MustBeOne; 1747 tranType = TLB::S1S2NsTran; 1748 mode = BaseTLB::Write; 1749 break; 1750 case MISCREG_AT_S1E3R_Xt: 1751 flags = TLB::MustBeOne; 1752 tranType = TLB::HypMode; // There is no TZ mode defined. 1753 mode = BaseTLB::Read; 1754 break; 1755 case MISCREG_AT_S1E3W_Xt: 1756 flags = TLB::MustBeOne; 1757 tranType = TLB::HypMode; // There is no TZ mode defined. 1758 mode = BaseTLB::Write; 1759 break; 1760 } 1761 // If we're in timing mode then doing the translation in 1762 // functional mode then we're slightly distorting performance 1763 // results obtained from simulations. The translation should be 1764 // done in the same mode the core is running in. NOTE: This 1765 // can't be an atomic translation because that causes problems 1766 // with unexpected atomic snoop requests. 1767 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1768 req->setVirt(0, val, 1, flags, Request::funcMasterId, 1769 tc->pcState().pc()); 1770 req->setContext(tc->contextId()); 1771 fault = tc->getDTBPtr()->translateFunctional(req, tc, mode, 1772 tranType); 1773 1774 MiscReg newVal; 1775 if (fault == NoFault) { 1776 Addr paddr = req->getPaddr(); 1777 uint64_t attr = tc->getDTBPtr()->getAttr(); 1778 uint64_t attr1 = attr >> 56; 1779 if (!attr1 || attr1 ==0x44) { 1780 attr |= 0x100; 1781 attr &= ~ uint64_t(0x80); 1782 } 1783 newVal = (paddr & mask(47, 12)) | attr; 1784 DPRINTF(MiscRegs, 1785 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 1786 val, newVal); 1787 } else { 1788 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 1789 // Set fault bit and FSR 1790 FSR fsr = armFault->getFsr(tc); 1791 1792 newVal = ((fsr >> 9) & 1) << 11; 1793 // rearange fault status 1794 newVal |= ((fsr >> 0) & 0x3f) << 1; 1795 newVal |= 0x1; // F bit 1796 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1797 newVal |= armFault->isStage2() ? 0x200 : 0; 1798 DPRINTF(MiscRegs, 1799 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 1800 val, fsr, newVal); 1801 } 1802 delete req; 1803 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 1804 return; 1805 } 1806 case MISCREG_SPSR_EL3: 1807 case MISCREG_SPSR_EL2: 1808 case MISCREG_SPSR_EL1: 1809 // Force bits 23:21 to 0 1810 newVal = val & ~(0x7 << 21); 1811 break; 1812 case MISCREG_L2CTLR: 1813 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 1814 miscRegName[misc_reg], uint32_t(val)); 1815 break; 1816 1817 // Generic Timer registers 1818 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 1819 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 1820 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 1821 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 1822 getGenericTimer(tc).setMiscReg(misc_reg, newVal); 1823 break; 1824 } 1825 } 1826 setMiscRegNoEffect(misc_reg, newVal); 1827} 1828 1829void 1830ISA::tlbiVA(ThreadContext *tc, MiscReg newVal, uint16_t asid, 1831 bool secure_lookup, uint8_t target_el) 1832{ 1833 if (!haveLargeAsid64) 1834 asid &= mask(8); 1835 Addr va = ((Addr) bits(newVal, 43, 0)) << 12; 1836 System *sys = tc->getSystemPtr(); 1837 for (int x = 0; x < sys->numContexts(); x++) { 1838 ThreadContext *oc = sys->getThreadContext(x); 1839 assert(oc->getITBPtr() && oc->getDTBPtr()); 1840 oc->getITBPtr()->flushMvaAsid(va, asid, 1841 secure_lookup, target_el); 1842 oc->getDTBPtr()->flushMvaAsid(va, asid, 1843 secure_lookup, target_el); 1844 1845 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1846 if (checker) { 1847 checker->getITBPtr()->flushMvaAsid( 1848 va, asid, secure_lookup, target_el); 1849 checker->getDTBPtr()->flushMvaAsid( 1850 va, asid, secure_lookup, target_el); 1851 } 1852 } 1853} 1854 1855void 1856ISA::tlbiALL(ThreadContext *tc, bool secure_lookup, uint8_t target_el) 1857{ 1858 System *sys = tc->getSystemPtr(); 1859 for (int x = 0; x < sys->numContexts(); x++) { 1860 ThreadContext *oc = sys->getThreadContext(x); 1861 assert(oc->getITBPtr() && oc->getDTBPtr()); 1862 oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 1863 oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 1864 1865 // If CheckerCPU is connected, need to notify it of a flush 1866 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1867 if (checker) { 1868 checker->getITBPtr()->flushAllSecurity(secure_lookup, 1869 target_el); 1870 checker->getDTBPtr()->flushAllSecurity(secure_lookup, 1871 target_el); 1872 } 1873 } 1874} 1875 1876void 1877ISA::tlbiALLN(ThreadContext *tc, bool hyp, uint8_t target_el) 1878{ 1879 System *sys = tc->getSystemPtr(); 1880 for (int x = 0; x < sys->numContexts(); x++) { 1881 ThreadContext *oc = sys->getThreadContext(x); 1882 assert(oc->getITBPtr() && oc->getDTBPtr()); 1883 oc->getITBPtr()->flushAllNs(hyp, target_el); 1884 oc->getDTBPtr()->flushAllNs(hyp, target_el); 1885 1886 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1887 if (checker) { 1888 checker->getITBPtr()->flushAllNs(hyp, target_el); 1889 checker->getDTBPtr()->flushAllNs(hyp, target_el); 1890 } 1891 } 1892} 1893 1894void 1895ISA::tlbiMVA(ThreadContext *tc, MiscReg newVal, bool secure_lookup, bool hyp, 1896 uint8_t target_el) 1897{ 1898 System *sys = tc->getSystemPtr(); 1899 for (int x = 0; x < sys->numContexts(); x++) { 1900 ThreadContext *oc = sys->getThreadContext(x); 1901 assert(oc->getITBPtr() && oc->getDTBPtr()); 1902 oc->getITBPtr()->flushMva(mbits(newVal, 31,12), 1903 secure_lookup, hyp, target_el); 1904 oc->getDTBPtr()->flushMva(mbits(newVal, 31,12), 1905 secure_lookup, hyp, target_el); 1906 1907 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1908 if (checker) { 1909 checker->getITBPtr()->flushMva(mbits(newVal, 31,12), 1910 secure_lookup, hyp, target_el); 1911 checker->getDTBPtr()->flushMva(mbits(newVal, 31,12), 1912 secure_lookup, hyp, target_el); 1913 } 1914 } 1915} 1916 1917BaseISADevice & 1918ISA::getGenericTimer(ThreadContext *tc) 1919{ 1920 // We only need to create an ISA interface the first time we try 1921 // to access the timer. 1922 if (timer) 1923 return *timer.get(); 1924 1925 assert(system); 1926 GenericTimer *generic_timer(system->getGenericTimer()); 1927 if (!generic_timer) { 1928 panic("Trying to get a generic timer from a system that hasn't " 1929 "been configured to use a generic timer.\n"); 1930 } 1931 1932 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 1933 return *timer.get(); 1934} 1935 1936} 1937 1938ArmISA::ISA * 1939ArmISAParams::create() 1940{ 1941 return new ArmISA::ISA(this); 1942} 1943